Array substrate and its fabrication method, display panel

Abstract

This application provides an array substrate and its fabrication method, as well as a display panel. The array substrate includes a substrate; a first conductive layer located on one side of the substrate, including multiple data lines arranged in an array; and a second conductive layer located on the side of the first conductive layer away from the substrate, and in direct contact with a portion of the first conductive layer, including pixel electrodes and compensation electrodes. The orthographic projection of the compensation electrodes on the substrate is located within the orthographic projection of the data lines on the substrate. The array substrate provided by the embodiments of this application has low cost, high fabrication yield, and good reliability.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and its fabrication method, and a display panel. Background Technology

[0002] With the rapid development of display technology, people have increasingly higher requirements for the quality of display products. During the manufacturing process of display products, process fluctuations can easily lead to the breakage of traces in the display panel. In subsequent manufacturing processes or during use, the broken traces can easily expand further, causing open circuits and display abnormalities. Summary of the Invention

[0003] In a first aspect, embodiments of this application provide an array substrate, comprising:

[0004] Substrate;

[0005] The first conductive layer, located on one side of the substrate, includes multiple data lines arranged in an array;

[0006] The second conductive layer is located on the side of the first conductive layer away from the substrate and is in direct contact with a portion of the first conductive layer, including a pixel electrode and a compensation electrode.

[0007] The orthogonal projection of the compensation electrode on the substrate is located within the orthogonal projection of the data line on the substrate.

[0008] In some embodiments of this application, the extension direction of the compensation electrode is the same as the extension direction of the data line, and the length of the compensation electrode is less than or equal to the length of the data line in the extension direction of the data line.

[0009] In some embodiments of this application, in the extension direction perpendicular to the data line, the size of the orthographic projection pattern of the data line on the substrate is greater than or equal to the size of the orthographic projection pattern of the compensation electrode on the substrate.

[0010] In some embodiments of this application, the array substrate further includes a third conductive layer located between the first conductive layer and the substrate; the third conductive layer includes a plurality of gate lines arranged in an array, the gate lines intersecting with and being insulated from the data lines;

[0011] The portion of the data line located between two adjacent gate lines includes a first segment, a bend, and a second segment connected in sequence; the compensation electrode covers at least a portion of the first segment and the second segment.

[0012] In some embodiments of this application, the data line further includes a third segment and a fourth segment. The third segment is connected to the end of the first segment away from the bend, and the fourth segment is connected to the end of the second segment away from the bend. The orthographic projections of the third segment and the fourth segment on the substrate overlap with the orthographic projections of the gate line on the substrate.

[0013] The compensation electrode covers at least a portion of the third segment and the fourth segment.

[0014] In some embodiments of this application, the compensation electrode covers the first line segment, the second line segment, the third line segment, and the fourth line segment.

[0015] In some embodiments of this application, the width of the third line segment along the direction perpendicular to the extension of the third line segment is greater than the width of the first line segment along the direction perpendicular to the extension of the first line segment; the width of the fourth line segment along the direction perpendicular to the extension of the fourth line segment is greater than the width of the second line segment along the direction perpendicular to the extension of the second line segment.

[0016] In some embodiments of this application, the width of the portion of the compensation electrode covering the third line segment along the direction perpendicular to the extension of the third line segment is greater than the width of the portion of the compensation electrode covering the main structure of the first line segment along the direction perpendicular to the extension of the first line segment.

[0017] The width of the portion of the compensation electrode covering the fourth line segment along the direction perpendicular to the extension of the fourth line segment is greater than the width of the portion of the main structure of the compensation electrode covering the second line segment along the direction perpendicular to the extension of the second line segment.

[0018] In some embodiments of this application, the pixel electrode is located at a position defined by two adjacent data lines and two adjacent gate lines, and the minimum distance between the pixel electrode and the compensation electrode is greater than or equal to 5 μm.

[0019] In some embodiments of this application, the array substrate further includes a transistor, the first conductive layer further includes a first electrode and a second electrode of the transistor, the pixel electrode is in direct contact with a portion of the first electrode of the transistor, and the data line is connected to the second electrode of the transistor.

[0020] In some embodiments of this application, the first electrode of the transistor includes a first portion parallel to the extension direction of the gate line, a second portion parallel to the extension direction of the gate line, and a connection portion connecting the first portion and the second portion;

[0021] The minimum distance between the second part and the gate line is greater than or equal to the minimum distance between the first part and the gate line, and the pixel electrode covers the second part.

[0022] In some embodiments of this application, the minimum distance between the second part and the gate line is greater than the minimum distance between the first part and the gate line, and the pixel electrode covers the second part and part of the connection part.

[0023] In some embodiments of this application, the array substrate further includes a semiconductor layer located between the first conductive layer and the third conductive layer, and a portion of the semiconductor layer is in direct contact with the first conductive layer;

[0024] The semiconductor layer includes a first active portion, the orthographic projection of the compensation electrode on the substrate is located within the orthographic projection of the first active portion on the substrate, and the orthographic projection of the data line on the substrate is located within the orthographic projection of the first active portion on the substrate.

[0025] In some embodiments of this application, the semiconductor layer further includes a second active portion, the first active portion and the second active portion are connected, and the orthographic projection of the first electrode of the transistor on the substrate and the orthographic projection of the second electrode of the transistor on the substrate are respectively located within the orthographic projection of the second active portion on the substrate;

[0026] The pixel electrode also covers the side of the second active portion away from the second electrode of the transistor, and the pixel electrode is in direct contact with the side.

[0027] In some embodiments of this application, the array substrate further includes a fourth conductive layer, which is located on the side of the second conductive layer away from the substrate and is insulated from the second conductive layer;

[0028] The orthographic projection of the fourth conductive layer on the substrate overlaps with the orthographic projections of the pixel electrode, the data line, and the gate line on the substrate, respectively.

[0029] The fourth conductive layer has multiple slits, and the orthographic projection of the region where the slits are located on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate.

[0030] In some embodiments of this application, the third conductive layer further includes a storage electrode line disposed parallel to the gate line, and the storage electrode line is electrically connected to the fourth conductive layer through a via;

[0031] The orthographic projection of the storage electrode line on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the storage electrode line on the substrate also overlaps with the orthographic projection of the fourth conductive layer on the substrate.

[0032] Secondly, embodiments of this application provide a display panel including the array substrate described above.

[0033] Thirdly, embodiments of this application provide a method for fabricating an array substrate, applied to the fabrication of the array substrate described above, the method comprising:

[0034] Provide substrate;

[0035] Forming semiconductor thin films;

[0036] Forming a first conductive thin film;

[0037] Simultaneously, the semiconductor thin film and the first conductive thin film are patterned to obtain a semiconductor layer and a first conductive layer; wherein, the first conductive layer includes multiple data lines arranged in an array;

[0038] A second conductive layer is formed; the second conductive layer is in direct contact with a portion of the first conductive layer and includes a pixel electrode and a compensation electrode; the orthogonal projection of the compensation electrode on the substrate is located within the orthogonal projection of the data line on the substrate.

[0039] In some embodiments of this application, the simultaneous patterning of the semiconductor thin film and the first conductive thin film to obtain the semiconductor layer and the first conductive layer includes:

[0040] A photoresist film is formed on the first conductive film;

[0041] The photoresist film is patterned using a halftone mask to obtain a first photoresist pattern.

[0042] Using the first photoresist pattern as a mask, the semiconductor thin film and the first conductive thin film are patterned to obtain the first semiconductor pattern and the first conductive pattern.

[0043] The first photoresist pattern is etched to obtain the second photoresist pattern;

[0044] Using the second photoresist pattern as a mask, the first semiconductor pattern and the first conductive pattern are patterned to obtain the semiconductor layer and the first conductive layer.

[0045] Remove the second photoresist pattern.

[0046] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A top view of an array substrate provided in an embodiment of this application;

[0049] Figure 2 and Figure 4 A schematic diagram of the structure of an array substrate in a related art provided for an embodiment of this application;

[0050] Figure 3 A schematic diagram of the structure of a display panel in a related art provided for an embodiment of this application;

[0051] Figures 5-9 Schematic diagrams of the structures of five array substrates provided for embodiments of this application;

[0052] Figure 10 A schematic diagram of the structure of a display panel provided for an embodiment of this application;

[0053] Figure 11 for Figure 1 Enlarged view of a portion of the transistor structure;

[0054] Figures 12-18 An intermediate structural diagram of the fabrication process of an array substrate provided for an embodiment of this application. Detailed Implementation

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] In the figures, for clarity, the thickness of regions and layers may be exaggerated. The same reference numerals in the figures denote the same or similar structures, and therefore their detailed descriptions are omitted. Furthermore, the figures are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0057] In the embodiments of this application, unless otherwise stated, "a plurality of" means two or more; the orientation or positional relationship indicated by the term "above" is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, and is not intended to indicate or imply that the structure or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0058] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0059] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0060] Embodiments of this application provide an array substrate, combined with Figure 1 and Figure 6 As shown, it includes:

[0061] Substrate 1;

[0062] The first conductive layer 5 is located on one side of the substrate 1 and includes multiple data lines 53 arranged in an array.

[0063] The second conductive layer 6 is located on the side of the first conductive layer 5 away from the substrate 1 and is in direct contact with a portion of the first conductive layer 5. The second conductive layer 6 includes a pixel electrode 61 and a compensation electrode 62.

[0064] The orthogonal projection of the compensation electrode 62 on the substrate 1 is located within the orthogonal projection of the data line 53 on the substrate 1.

[0065] It should be noted that, Figure 6 yes Figure 1 Cross-sectional view along the A1A2 direction.

[0066] The specific material of the substrate 1 described above is not limited. For example, the substrate can be a rigid substrate, such as glass.

[0067] In an exemplary embodiment, the material of the first conductive layer 5 can be a metallic material, such as copper.

[0068] For example, the first conductive layer 5 is used to prepare the data line 53, the source of the transistor TFT, and the drain of the transistor TFT in the conductive pattern.

[0069] In some embodiments, the first conductive layer 5 is also referred to as the SD layer. Figure 1 The SD layer in the diagram represents the first conductive layer 5.

[0070] The specific structure of the data line 53 described above is not limited here. For example, the data line 53 may include a straight line segment; or, the data line 53 may include a broken line segment composed of multiple straight line segments. The specific design can be determined according to the actual design.

[0071] In an exemplary embodiment, the material of the second conductive layer 6 can be a light-transmitting conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0072] In some embodiments, the second conductive layer 6 is also referred to as the Pixel ITO layer. Figure 1 The Pixel ITO layer in the diagram represents the second conductive layer 6.

[0073] The second conductive layer 6 includes a pixel electrode 61 and a compensation electrode 62, wherein the pixel electrode 61 is located in the area between two adjacent data lines 53, and the pixel electrode 61 and the compensation electrode 62 are disposed separately.

[0074] The number of the aforementioned compensation electrodes 62 is not specified here; it can be determined based on the actual situation.

[0075] For example, only one of the multiple data lines 53 may have a compensation electrode 62; or, one data line 53 may have a compensation electrode 62; or, multiple disconnected compensation electrodes 62 may be provided on one data line 53.

[0076] In an exemplary embodiment, direct contact between the second conductive layer 6 and a portion of the first conductive layer 5 includes, but is not limited to, the following situations:

[0077] In the first case, the pixel electrode 61 in the second conductive layer 6 is in direct contact with the drain of the transistor TFT in the first conductive layer 5.

[0078] In the second case, the compensation electrode 62 in the second conductive layer 6 is in direct contact with the data line 53 in the first conductive layer 5, and the compensation electrode 62 covers a portion of the data line 53.

[0079] In an exemplary embodiment, the orthographic projection of the compensation electrode 62 on the substrate 1 being within the orthographic projection of the data line 53 on the substrate 1 means that the outer contour of the orthographic projection of the compensation electrode 62 on the substrate 1 is within the outer contour of the orthographic projection of the data line 53 on the substrate 1; or, the outer contour of the orthographic projection of the compensation electrode 62 on the substrate 1 overlaps with the outer contour of the orthographic projection of the data line 53 on the substrate 1.

[0080] In related technologies, for array substrates fabricated using the 6Mask process, refer to Figure 2 and Figure 3 As shown, the second conductive layer 6 is located between the first conductive layer 5 and the substrate 1, and the first conductive layer 5 covers a portion of the second conductive layer 6. However, in order to reduce costs and optimize the process, when using the 5Mask process to fabricate the array substrate, since the orthographic projection of the first conductive layer 5 on the substrate 1 of the 5Mask process array substrate is within the orthographic projection of the semiconductor layer 4 on the substrate 1, in order to avoid a short circuit between the second conductive layer 6 and the semiconductor layer 4, the array substrate provided in the embodiments of this application places the second conductive layer 6 on the side of the first conductive layer 5 away from the substrate 1. The second conductive layer 6 includes a pixel electrode 61 and a compensation electrode 62, and makes a portion of the second conductive layer 6 directly contact the first conductive layer 5. Furthermore, the orthographic projection of the compensation electrode 62 on the substrate 1 is located within the orthographic projection of the data line 53 on the substrate 1. In this way, while saving one mask and reducing fabrication costs, as... Figure 6 As shown, the compensation electrode 62, which is fabricated in the same layer as the pixel electrode 61, covers at least a portion of the data line 53. If the data line 53 has cracks or gaps during the fabrication of the array substrate, the compensation electrode 62 can repair the data line 53, preventing the data line 53 from being open-circuited, thereby improving the fabrication yield of the array substrate and increasing product efficiency.

[0081] It should be noted that the array substrates provided in the embodiments of this application are all fabricated using a 5-mask process. The 5-mask process refers to the use of 5 masks in the fabrication process of the array substrate; the 6-mask process refers to the use of 6 masks in the fabrication process of the array substrate. Since the masks have high precision and high fabrication requirements, the design and manufacturing of the masks account for an important part of the cost of display products. Saving one mask can greatly reduce the manufacturing cost of the array substrate.

[0082] In some embodiments of this application, the extension direction of the compensation electrode 62 is the same as the extension direction of the data line 53, and the length of the compensation electrode 62 is less than or equal to the length of the data line 53 in the extension direction of the data line 53.

[0083] In an exemplary embodiment, in the extension direction of the data line 53, the length of the compensation electrode 62 is less than or equal to the length of the data line 53, including but not limited to the following cases:

[0084] First, in the extension direction of the data line 53, the length of the compensation electrode 62 is less than the length of the data line 53; that is, only a portion of the data line 53 is covered with the compensation electrode 62, while another portion of the data line 53 is not covered with the compensation electrode 62. Thus, in the extension direction of the data line 53, the total length of the compensation electrode 62 is less than the total length of the data line 53. Or, for each data line 53, a portion of the data line 53 is covered with the compensation electrode 62, while a portion of the data line 53 is not covered with the compensation electrode 62. Thus, the length of the compensation electrode 62 on the data line 53 is less than the length of the data line 53.

[0085] Second, in the extension direction of the data line 53, the length of the compensation electrode 62 is equal to the length of the data line 53; for all data lines 53, each data line 53 is provided with a compensation electrode 62, and the total length of the compensation electrode 62 is equal to the total length of the data line 53; for one data line 53, if a compensation electrode 62 is provided along its extension direction, then the length of the compensation electrode 62 is equal to the length of the data line 53.

[0086] Where design permits, a compensation electrode 62 can be provided on each data line 53, with the length of the compensation electrode 62 equal to the length of the data line 53 in its extension direction. This maximizes the ability of the compensation electrode 62 to repair cracks and gaps in the data line 53, preventing defects caused by open circuits in the data line 53 and improving the fabrication yield of the array substrate.

[0087] In some embodiments of this application, in the extension direction perpendicular to the data line 53, the size of the orthographic projection pattern of the data line 53 on the substrate 1 is greater than or equal to the size of the orthographic projection pattern of the compensation electrode 62 on the substrate 1.

[0088] In an exemplary embodiment, reference is made to Figure 6 As shown, in the direction perpendicular to the extension of the data line 53, the size of the orthographic projection pattern of the data line 53 on the substrate 1 is larger than the size of the orthographic projection pattern of the compensation electrode 62 on the substrate 1.

[0089] It is understandable that, without considering the length of the compensation electrode 62, the reference... Figure 6 As shown, the outer contour of the orthogonal projection of the compensation electrode 62 on the substrate 1 is located within the outer contour of the orthogonal projection of the data line 53 on the substrate 1.

[0090] In an exemplary embodiment, reference is made to Figure 7 As shown, in the direction perpendicular to the extension of the data line 53, the size of the orthographic projection pattern of the data line 53 on the substrate 1 is equal to the size of the orthographic projection pattern of the compensation electrode 62 on the substrate 1.

[0091] It is understandable that, without considering the length of the compensation electrode 62, the reference... Figure 7 As shown, the outer contour of the orthogonal projection of the compensation electrode 62 on the substrate 1 overlaps with the outer contour of the orthogonal projection of the data line 53 on the substrate 1.

[0092] In practical applications, the compensation electrode 62 is positioned in the middle region of the data line 53. This ensures that even with fluctuations in the manufacturing process, the edge of the compensation electrode 62 will not extend beyond the edge of the data line 53. This prevents short circuits between the compensation electrode 62 and the pixel electrode 61 in the same layer due to insufficient distance, thereby improving the fabrication yield of the array substrate.

[0093] In some embodiments of this application, reference is made to Figure 1 As shown, the array substrate also includes a third conductive layer 2 located between the first conductive layer 5 and the substrate 1; the third conductive layer 2 includes multiple gate lines GL arranged in an array, the gate lines GL intersect with the data lines 53 and are insulated from them;

[0094] The portion of data line 53 located between two adjacent gate lines GL includes a first segment A, a bend E, and a second segment B connected in sequence; the compensation electrode 62 covers at least a portion of the first segment A and the second segment B.

[0095] In an exemplary embodiment, a gate insulation layer 3 is provided between the gate line GL and the data line 53.

[0096] In an exemplary embodiment, the structural pattern of the bend E is relatively complex during the fabrication of the array substrate, making its fabrication process more difficult. When fabricating the compensation electrode 62 on the bend E, the fabrication precision requirements are even higher; otherwise, a short circuit can easily occur between the compensation electrode 62 on the bend E and the adjacent pixel electrode 61, causing abnormal use of the array substrate. Given the limitations of the fabrication process, the compensation electrode 62 is configured to cover at least a portion of the first line segment A and the second line segment B.

[0097] It should be noted that the compensation electrode 62 covers at least a portion of the area of ​​the first segment A and the second segment B, including but not limited to the following:

[0098] The compensation electrode 62 covers a portion of the first line segment A;

[0099] Alternatively, the compensation electrode 62 may cover a portion of the second line segment B;

[0100] Alternatively, the compensation electrode 62 may cover the entire area of ​​the first line segment A;

[0101] Alternatively, the compensation electrode 62 may cover the entire area of ​​the second line segment B;

[0102] Alternatively, the compensation electrode 62 covers a portion of the first line segment A, and the compensation electrode 62 also covers a portion of the second line segment B.

[0103] Alternatively, the compensation electrode 62 covers the entire area of ​​the first line segment A, and the compensation electrode 62 also covers the entire area of ​​the second line segment B.

[0104] In the embodiments of this application, by setting the compensation electrode 62 to cover at least a portion of the first line segment A and the second line segment B, and setting the non-compensation electrode 62 not to cover the bend E, while ensuring that no short circuit occurs between the compensation electrode 62 and the adjacent pixel electrode 61, the compensation electrode 62 can be used to repair cracks and gaps in the data line 53 to the greatest extent possible, thereby avoiding defects caused by the data line 53 being broken and improving the fabrication yield of the array substrate.

[0105] In some embodiments of this application, reference is made to Figure 1 As shown, the data line 53 also includes a third segment C and a fourth segment D. The third segment C is connected to the end of the first segment A away from the bend E, and the fourth segment D is connected to the end of the second segment B away from the bend E. The orthographic projection of the third segment C on the substrate 1 and the orthographic projection of the fourth segment D on the substrate 1 overlap with the orthographic projection of the gate line GL on the substrate 1.

[0106] The compensation electrode 62 covers at least a portion of the third segment C and the fourth segment D.

[0107] In an exemplary embodiment, the overlap between the orthographic projection of the third line segment C on the substrate 1 and the orthographic projection of the fourth line segment D on the substrate 1 and the orthographic projection of the gate line GL on the substrate 1 includes: the orthographic projection of the third line segment C on the substrate 1 overlaps with the orthographic projection of the gate line GL on the substrate 1, and the orthographic projection of the fourth line segment D on the substrate 1 overlaps with the orthographic projection of the gate line GL on the substrate 1. The overlap refers to at least a partial overlap.

[0108] In exemplary embodiments, the compensation electrode 62 covers at least a portion of the third segment C and the fourth segment D, including but not limited to the following situations: the compensation electrode 62 covers a portion of the third segment C; or, the compensation electrode 62 covers the third segment C; or, the compensation electrode 62 covers a portion of the fourth segment D; or, the compensation electrode 62 covers a portion of the third segment C and a portion of the fourth segment D; or, the compensation electrode 62 covers the third segment C and also covers the fourth segment D.

[0109] In the array substrate provided in the embodiments of this application, since the projection of the third line segment C overlaps with the projection of the gate line GL, and the projection of the fourth line segment D overlaps with the projection of the sector GL, that is, during the fabrication of the data line 53, the third line segment C and the fourth line segment D of the data line 53 need to climb up the gate line GL. Due to the concentration of storage stress near the climbing position, the data line 53 is prone to cracks or gaps. In the array substrate improved by the embodiments of this application, a compensation electrode 62 is provided to cover at least a portion of the third line segment C and the fourth line segment D. Thus, it can be ensured that when cracks and gaps appear in the data line 53, the compensation electrode 62 can repair them, avoid the occurrence of defects caused by the data line 53 being open-circuited, and improve the fabrication yield of the array substrate.

[0110] In some embodiments of this application, the compensation electrode 62 covers the first segment A, the second segment B, the third segment C, and the fourth segment D.

[0111] In the embodiments of this application, the compensation electrode 62 covers the area of ​​the data line except for the bend portion E. While ensuring that no short circuit occurs between the compensation electrode 62 and the adjacent pixel electrode 61, the compensation electrode 62 can maximize the repair function when cracks and gaps appear in the data line 53, thereby avoiding defects caused by the data line 53 being broken and improving the fabrication yield of the array substrate.

[0112] In some embodiments of this application, reference is made to Figure 1 As shown, the width W1 of the third line segment C along the direction perpendicular to the extension of the third line segment C is greater than the width W2 of the first line segment A along the direction perpendicular to the extension of the first line segment A; the width W3 of the fourth line segment D along the direction perpendicular to the extension of the fourth line segment D is greater than the width W4 of the second line segment B along the direction perpendicular to the extension of the second line segment B.

[0113] In the embodiments of this application, the third segment C and the fourth segment D of the data line 53 need to climb up the gate line GL. Due to the concentration of storage stress near the climbing position, the data line 53 is prone to cracks or gaps. In order to avoid large local stress in the third segment C and the fourth segment D, the width W1 of the third segment C is set to be greater than the width W2 of the first segment A, and the width W3 of the fourth segment D is set to be greater than the width W4 of the second segment B. This makes the stress more dispersed in the third segment C and the fourth segment D, reducing the probability of local cracks or gaps and improving the fabrication yield of the array substrate.

[0114] In some embodiments of this application, the width of the portion of the compensation electrode 62 covering the third line segment C along the direction perpendicular to the extension of the third line segment C, for example W1, is greater than the width of the portion of the compensation electrode 62 covering the main structure of the first line segment A along the direction perpendicular to the extension of the first line segment A, for example W2; the width of the portion of the compensation electrode 62 covering the fourth line segment D along the direction perpendicular to the extension of the fourth line segment D, for example W3, is greater than the width of the portion of the compensation electrode 62 covering the main structure of the second line segment B along the direction perpendicular to the extension of the second line segment B, for example W4.

[0115] It should be noted that, Figure 1 The illustrated structure is drawn with the width of the portion of the compensation electrode 62 covering the third line segment C along the direction perpendicular to the extension of the third line segment C being equal to the width of the third line segment C along the direction perpendicular to the extension of the third line segment C. Therefore, the width of the portion of the compensation electrode 62 covering the third line segment C along the direction perpendicular to the extension of the third line segment C can be marked as W1, and the width of the third line segment C along the direction perpendicular to the extension of the third line segment C can also be marked as W1. The markings of W2, W3 and W4 are similar to W1, and will not be repeated here.

[0116] In an exemplary embodiment, the first line segment A includes an end connected to the third line segment C, an end connected to the bent portion E, and a main structural portion. When the widths of the first line segment A and the third line segment C are different, the width of the end of the first line segment A connected to the third line segment C is between the main structural portion of the first line segment A and the third line segment C. Here, in order to more accurately describe the dimensional relationship between the portion of the compensation electrode 62 covering the third line segment C and the portion of the compensation electrode 62 covering the first line segment A, we take the main structural portion of the first line segment A with a relatively uniform width as an example to illustrate that the width of the portion of the compensation electrode 62 covering the third line segment C along the direction perpendicular to the extension of the third line segment C, for example W1, is greater than the width of the portion of the compensation electrode 62 covering the main structural portion of the first line segment A along the direction perpendicular to the extension of the first line segment A, for example W2.

[0117] In some embodiments of this application, the pixel electrode 61 is located at a position defined by two adjacent data lines 53 and two adjacent gate lines GL, and the minimum distance W5 between the pixel electrode 61 and the compensation electrode 62 is greater than or equal to 5 μm.

[0118] In the array substrate provided in the embodiments of this application, since the pixel electrode 61 and the compensation electrode 62 are located in the same layer, for example... Figure 1 In the Pixel ITO layer shown, to avoid short circuits between the pixel electrode 61 and the compensation electrode 62, the minimum distance W5 between the pixel electrode 61 and the compensation electrode 62 is set to be greater than or equal to 5μm, thereby ensuring a safe distance between them and improving the quality of the array substrate.

[0119] In some embodiments of this application, combined with Figure 1 and Figure 5 As shown, the array substrate also includes a transistor TFT, the first conductive layer 5 also includes a first electrode 51 of the transistor TFT and a second electrode 52 of the transistor TFT, the pixel electrode 61 is in direct contact with a portion of the first electrode 51 of the transistor TFT, and the data line 53 is connected to the second electrode 52 of the transistor TFT.

[0120] in, Figure 5 yes Figure 1 Cross-sectional view along the B1B2 direction.

[0121] The aforementioned transistor can be a thin-film transistor (TFT transistor) or a complementary metal-oxide-semiconductor transistor (CMOS transistor). Furthermore, the transistor can be an N-type transistor or a P-type transistor, depending on the specific circumstances. The embodiments in this application are illustrated using a thin-film transistor as an example.

[0122] In an exemplary embodiment, reference is made to Figure 1 or Figure 5 As shown, the pixel electrode 51 partially covers the first electrode 51 of the transistor TFT, and the two are in direct contact and connected.

[0123] In an exemplary embodiment, the third conductive layer 2 further includes the gate GA of the transistor TFT.

[0124] In some embodiments of this application, the first electrode 51 of the transistor TFT includes a first part 51A parallel to the extension direction of the gate line GL, a second part 51B parallel to the extension direction of the gate line GL, and a connecting part 51C connecting the first part 51A and the second part 51B.

[0125] The minimum distance h1 between the second part 51B and the gate line GL is greater than or equal to the minimum distance h2 between the first part 51A and the gate line GL, and the pixel electrode 61 covers the second part 51B.

[0126] In some embodiments of this application, reference is made to Figure 11 As shown, the minimum distance h1 between the second part 51B and the gate line GL is greater than the minimum distance h2 between the first part 51A and the gate line GL, and the pixel electrode 61 covers the second part 51B and part of the connecting part 51C.

[0127] In the embodiments of this application, the minimum distance h1 between the second part 51B and the gate line GL is set to be greater than or equal to the minimum distance h2 between the first part 51A and the gate line GL, and the pixel electrode 61 covers the second part 51B and part of the connecting part 51C, but does not cover the first part 51A. In this way, there is a certain safe distance between the pixel electrode 61 and the gate line GL, avoiding signal crosstalk caused by the small distance between the pixel electrode 61 and the gate line GL.

[0128] In the embodiments of this application, reference is made to Figure 5 As shown, since there is a slope at the position where the pixel electrode 61 covers the first electrode 51 of the transistor, the pixel electrode 61 near the slope position is prone to cracks or gaps due to stress concentration. In order to reduce the probability of cracks and gaps, the first electrode 51 is configured to include a first part 51A, a second part 51B and a connecting part 51C, and the minimum distance h1 between the second part 51B and the gate line GL is greater than or equal to the minimum distance h2 between the first part 51A and the gate line GL. The pixel electrode 61 covers the second part 51B and also extends to cover the connecting part 51C, which increases the contact area between the pixel electrode 61 and the first electrode 51, disperses the internal stress received by the pixel electrode 61 near the slope position, thereby reducing the probability of cracks or gaps in the pixel electrode 61 near the slope position and improving the reliability of the array substrate.

[0129] In some embodiments of this application, participants Figure 1 and Figure 6 As shown, the array substrate also includes a semiconductor layer 4 located between the first conductive layer 5 and the third conductive layer 2, and a portion of the semiconductor layer 4 is in direct contact with the first conductive layer 5; the semiconductor layer 4 includes a first active portion 41, the orthographic projection of the compensation electrode 62 on the substrate 1 is located within the orthographic projection of the first active portion 41 on the substrate 1, and the orthographic projection of the data line 53 on the substrate 1 is located within the orthographic projection of the first active portion 41 on the substrate 1.

[0130] In an exemplary embodiment, the data line 53 is located between the first active part 41 and the compensation electrode 62, and the data line 53 is in direct contact with the first active part 41 and the compensation electrode 62 respectively.

[0131] In an exemplary embodiment, the orthographic projection of the compensation electrode 62 on the substrate 1 is located within the orthographic projection of the first active portion 41 on the substrate 1, and the orthographic projection of the data line 53 on the substrate 1 is located within the orthographic projection of the first active portion 41 on the substrate 1, including the following cases:

[0132] For example, refer to Figure 6 As shown, the outer contour of the orthogonal projection of the compensation electrode 62 on the substrate 1 is located within the outer contour of the orthogonal projection of the data line 53 on the substrate 1, and the outer contour of the orthogonal projection of the data line 53 on the substrate 1 is located within the outer contour of the orthogonal projection of the first active part 41 on the substrate 1.

[0133] For example, refer to Figure 7 As shown, the outer contour of the orthogonal projection of the compensation electrode 62 on the substrate 1 overlaps with the outer contour of the orthogonal projection of the data line 53 on the substrate 1, and the outer contour of the orthogonal projection of the data line 53 on the substrate 1 is located within the outer contour of the orthogonal projection of the first active part 41 on the substrate 1.

[0134] For example, refer to Figure 8 As shown, the outer contour of the orthogonal projection of the compensation electrode 62 on the substrate 1 overlaps with the outer contour of the orthogonal projection of the data line 53 on the substrate 1, and the outer contour of the orthogonal projection of the data line 53 on the substrate 1 overlaps with the outer contour of the orthogonal projection of the first active part 41 on the substrate 1.

[0135] In some embodiments, the material of the first active portion 41 may include a semiconductor material.

[0136] In some embodiments, the material of the first active portion 41 may include a semiconductor material and a doped semiconductor material. The doped semiconductor material is located on the surface of the first active portion 41 away from the substrate 1, which can improve the conductivity of the first active portion 41 and make it conductive. In this case, even if cracks or gaps appear in the data line 53 during the fabrication process, the first active portion 41 can also repair the data line 53 to a certain extent, thereby preventing the data line 53 from being open-circuited.

[0137] For example, in Figure 6 In the array substrate shown, the first active part 41 is not conductive, and the distances d1 and d2 between the data line 52 and the pixel electrodes 61 on both sides are greater than or equal to 5μm, so as to avoid short circuits or signal interference between the data line 52 and the pixel electrodes 61.

[0138] For example, in Figure 7 In the array substrate shown, the first active portion 41 is conductive, and the distances d3 and d4 between the first active portion 41 and the pixel electrodes 61 on both sides are greater than or equal to 5μm, so as to avoid short circuit between the first active portion 41 and the pixel electrodes 61.

[0139] For example, in Figure 8 In the array substrate shown, the first active portion 41 is conductive, and the distances d5 and d6 between the first active portion 41 and the pixel electrodes 61 on both sides are greater than or equal to 5μm, so as to avoid short circuit between the first active portion 41 and the pixel electrodes 61.

[0140] Figure 4 It is a cross-sectional view of the data line location along the extension direction of the data line in related technologies. Figure 9 This is a cross-sectional view of the array substrate along the extension direction of the data line in an embodiment of this application, showing the location of the data line. As can be seen from the comparison, when the data line is broken or has a gap in the related technology, the conductive layer located below the data line repairs the data line. However, in this application, a first active part 41 is provided below the data line 53, and a compensation electrode 62, which is fabricated in the same layer as the pixel electrode 61, is provided above the data line 53. The first active part 41 and the compensation electrode 62 can simultaneously repair the data line 53, preventing it from being open-circuited. This greatly improves the fabrication yield of the data line 53 and enhances the quality of the array substrate.

[0141] In some embodiments of this application, reference is made to Figure 5 As shown, the semiconductor layer 4 also includes a second active portion 42, the first active portion 41 and the second active portion 42 are connected, the orthographic projection of the first electrode 51 of the transistor TFT on the substrate 1 and the orthographic projection of the second electrode 52 of the transistor TFT on the substrate 1 are respectively located within the orthographic projection of the second active portion 42 on the substrate 1; the pixel electrode 61 also covers the side 42M of the second active portion 42 that is far away from the second electrode 52 of the transistor TFT, and the pixel electrode 61 is in direct contact with the side 42M.

[0142] It should be noted that, in the embodiments of this application, since the array substrate is fabricated using a 5Mask process, the semiconductor layer 4 and the first conductive layer 5 are fabricated in a single patterning process, and the outer contour of the orthographic projection of the first conductive layer 5 on the substrate 1 is located within the outer contour of the orthographic projection of the semiconductor layer 4 on the substrate 1. The single patterning process includes processes such as exposure, development, and etching.

[0143] In some embodiments of this application, combined with Figure 1 and Figure 5As shown, the array substrate further includes a fourth conductive layer 8, which is located on the side of the second conductive layer 6 away from the substrate 1 and is insulated from the second conductive layer 6; an interlayer dielectric layer 7 is disposed between the fourth conductive layer 8 and the second conductive layer 6; wherein, the orthographic projection of the fourth conductive layer 8 on the substrate 1 overlaps with the orthographic projection of the pixel electrode 61 on the substrate 1, the orthographic projection of the data line 53 on the substrate 1 and the orthographic projection of the gate line GL on the substrate 1; the fourth conductive layer 8 has a plurality of slits 8S, and the orthographic projection of the area where the slits 8S are located on the substrate 1 overlaps with the orthographic projection of the pixel electrode 61 on the substrate 1.

[0144] In an exemplary embodiment, the material of the fourth conductive layer 8 is a light-transmitting conductive material, such as indium tin oxide or zinc tin oxide.

[0145] For example, in Figure 1 In the diagram, the film layer marked Common ITO represents the fourth conductive layer 8.

[0146] In some embodiments of this application, the third conductive layer 2 further includes a storage electrode line CS disposed parallel to the gate line GL, and the storage electrode line CS is connected to the fourth conductive layer 8 through a via ( Figure 1 (Not shown in the figure) Electrical connection; The orthographic projection of the storage electrode line CS on the substrate 1 overlaps with the orthographic projection of the pixel electrode 61 on the substrate 1, and the orthographic projection of the storage electrode line CS on the substrate 1 also overlaps with the orthographic projection of the fourth conductive layer 8 on the substrate 1.

[0147] In the array substrate provided in the embodiments of this application, by providing a storage electrode line CS, the orthographic projection of the storage electrode line CS on the substrate 1 overlaps with the orthographic projection of the pixel electrode 61 on the substrate 1, and the storage electrode line CS and the fourth conductive layer 8 are connected by a via ( Figure 1 (Not shown in the diagram) Electrical connection, which is equivalent to connecting another capacitor in parallel with the storage capacitor formed by the pixel electrode 61 and the fourth conductive layer 8, greatly increases the capacitance of the storage capacitor, which is beneficial to improving the charging rate of the pixels in the array substrate and improving the display effect of the display panel formed by the array substrate.

[0148] An embodiment of this application provides a display panel including the array substrate described above.

[0149] The specific structure of the array substrate included in the display panel will not be described in detail here; please refer to the embodiments mentioned above.

[0150] In an exemplary embodiment, the display panel further includes, for example, Figure 10 The second substrate 10 shown, and the black matrix layer 11 located on the second substrate 10, wherein the orthographic projection of the black matrix layer 11 on the substrate 1 overlaps with the orthographic projection of the data line 53 on the substrate 1.

[0151] The display panel provided in the embodiments of this application is a liquid crystal display (LCD). Alternatively, the display panel can be an LCD monitor or other display device, as well as any product or component with display function, such as a television, digital camera, mobile phone, or tablet computer that includes such display devices.

[0152] For example, the above-mentioned display panel is a liquid crystal display panel with ADS (Advanced Super Dimension Switch) display mode, where ADS is a general term for core technologies represented by wide viewing angle technology.

[0153] When fabricating the array substrate of a display panel using the 5Mask process, since the orthographic projection of the first conductive layer 5 on the substrate 1 of the 5Mask array substrate lies within the orthographic projection of the semiconductor layer 4 on the substrate 1, to avoid a short circuit between the second conductive layer 6 and the semiconductor layer 4, the array substrate provided in this application has the second conductive layer 6 disposed on the side of the first conductive layer 5 away from the substrate 1. The second conductive layer 6 includes a pixel electrode 61 and a compensation electrode 62, and a portion of the second conductive layer 6 is in direct contact with the first conductive layer 5. Furthermore, the orthographic projection of the compensation electrode 62 on the substrate 1 is positioned within the orthographic projection of the data line 53 on the substrate 1. This saves on mask printing and reduces fabrication costs. Figure 6 As shown, the compensation electrode 62, which is fabricated in the same layer as the pixel electrode 61, covers at least a portion of the data line 53. If the data line 53 has cracks or gaps during the fabrication of the array substrate, the compensation electrode 62 can repair the data line 53, preventing the data line 53 from being open-circuited, thereby improving the fabrication yield of the array substrate and increasing product efficiency.

[0154] Embodiments of this application provide a method for fabricating an array substrate, applicable to the fabrication of the array substrate described above, the method comprising:

[0155] S01, providing such Figure 12 Substrate 1 shown;

[0156] SO2, forming a semiconductor thin film (e.g., including 4A and 4N);

[0157] For example, the semiconductor thin film includes a semiconductor thin film 4A and a conductive thin film 4N located on the semiconductor thin film 4A.

[0158] In some embodiments, a semiconductor thin film can be conductiveized by doping to obtain a conductive thin film.

[0159] S03, Forming the first conductive thin film 50;

[0160] S04. Simultaneously, the semiconductor thin film (e.g., including 4A and 4N) and the first conductive thin film 50 are patterned to obtain the semiconductor layer 4 and the first conductive layer 5; wherein, the first conductive layer 5 includes multiple data lines 53 arranged in an array;

[0161] S05, Forming a second conductive layer 6; The second conductive layer 6 is in direct contact with a portion of the first conductive layer 5, and includes a pixel electrode 61 and a compensation electrode 62; The orthogonal projection of the compensation electrode 62 on the substrate 1 is located within the orthogonal projection of the data line 53 on the substrate.

[0162] In related technologies, for array substrates fabricated using the 6Mask process, refer to Figure 2 and Figure 3 As shown, the second conductive layer 6 is located between the first conductive layer 5 and the substrate 1, and the first conductive layer 5 covers a portion of the second conductive layer 6. However, in order to reduce costs and optimize the process, when using the 5Mask process to fabricate the array substrate, since the orthographic projection of the first conductive layer 5 on the substrate 1 of the 5Mask process array substrate is within the orthographic projection of the semiconductor layer 4 on the substrate 1, in order to avoid a short circuit between the second conductive layer 6 and the semiconductor layer 4, the array substrate provided in the embodiments of this application places the second conductive layer 6 on the side of the first conductive layer 5 away from the substrate 1. The second conductive layer 6 includes a pixel electrode 61 and a compensation electrode 62, and makes a portion of the second conductive layer 6 directly contact the first conductive layer 5. Furthermore, the orthographic projection of the compensation electrode 62 on the substrate 1 is located within the orthographic projection of the data line 53 on the substrate 1. In this way, while saving one mask and reducing fabrication costs, as... Figure 6 As shown, the compensation electrode 62, which is fabricated in the same layer as the pixel electrode 61, covers at least a portion of the data line 53. If the data line 53 has cracks or gaps during the fabrication of the array substrate, the compensation electrode 62 can repair the data line 53, preventing the data line 53 from being open-circuited, thereby improving the fabrication yield of the array substrate and increasing product efficiency.

[0163] It should be noted that the array substrates provided in the embodiments of this application are all fabricated using a 5-mask process. A 5-mask process refers to the use of 5 photomasks during the fabrication of the array substrate; a 6-mask process refers to the use of 6 photomasks during the fabrication of the array substrate. Because the precision and fabrication requirements of photomasks are high, the design and manufacturing of photomasks constitute a significant portion of the display product cost. Saving one photomask can significantly reduce the manufacturing cost of the array substrate. In the 5-mask process, the semiconductor layer 4 and the first conductive layer 5 are fabricated simultaneously using a single photomask, greatly reducing the fabrication process cost.

[0164] In some embodiments of this application, step S04, simultaneously patterning the semiconductor thin film (e.g., including 4A and 4N) and the first conductive thin film 50 to obtain the semiconductor layer 4 and the first conductive layer 5, includes:

[0165] S041, Reference Figure 13 As shown, a photoresist film 101 is formed on the first conductive film 50;

[0166] S042. The photoresist film 101 is patterned using a halftone mask to obtain the following: Figure 14 The first photoresist pattern 102 shown;

[0167] A halftone mask (HTM) is a mask in which some areas are halftone (HT) and some areas are full tone (FT). The halftone and full tone are determined based on the transmittance of the local areas in the mask. For details on halftone masks, please refer to relevant technologies, which will not be elaborated here.

[0168] S043. Using the first photoresist pattern 102 as a mask, patterning is performed on the semiconductor thin film (e.g., including 4A and 4N) and the first conductive thin film 50 to obtain the following: Figure 15 The first semiconductor pattern (including 104 and 105) and the first conductive pattern 103 are shown;

[0169] S044. The first photoresist pattern 102 is etched to obtain the following: Figure 16 The second photoresist pattern 106 is shown;

[0170] S045. Using the second photoresist pattern 106 as a mask, patterning processing is performed on the first semiconductor pattern (including 104 and 105) and the first conductive pattern 103, simultaneously obtaining... Figure 17 The semiconductor layer 4 and the first conductive layer 5 are shown.

[0171] S046, Remove the second photoresist pattern 106.

[0172] The first conductive layer 5 includes a first electrode 51 of the transistor and a second electrode 52 of the transistor.

[0173] In an exemplary embodiment, Figure 17 The semiconductor layer 4 (second active portion 42) shown includes a semiconductor sublayer 42A and a conductor sublayer 42N that is in direct contact with the first electrode 51 and the second electrode 52 of the transistor.

[0174] After removing the second photoresist pattern 106, the following can be formed sequentially: Figure 18 The second conductive layer 6, the interlayer dielectric layer 7, and as shown are shown. Figure 5 The fourth conductor layer 8 is shown.

[0175] It should be noted that this section only introduces the fabrication methods of the structures and films related to the invention. The fabrication methods of other structures of the array substrate can be found in the relevant technologies and will not be elaborated here.

[0176] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate, wherein, include: Substrate; The first conductive layer, located on one side of the substrate, includes multiple data lines arranged in an array; The second conductive layer is in direct contact with a portion of the first conductive layer, including pixel electrodes; The array substrate further includes a third conductive layer located between the first conductive layer and the substrate; the third conductive layer includes multiple gate lines arranged in an array, the gate lines intersecting with the data lines and being insulated from them; The array substrate further includes a transistor, the first conductive layer further includes a first electrode and a second electrode of the transistor, the pixel electrode is in direct contact with a portion of the first electrode of the transistor, and the data line is connected to the second electrode of the transistor; The first electrode of the transistor includes a first part parallel to the extension direction of the gate line, a second part parallel to the extension direction of the gate line, and a connecting part connecting the first part and the second part; the extension direction of the connecting part intersects the extension direction of the gate line and the extension direction of the data line; in a direction perpendicular to the substrate, on the side of the second part and the pixel electrode close to the gate line, the pixel electrode covers the second part.

2. The array substrate according to claim 1, wherein, Includes a compensation electrode, wherein the orthographic projection of the compensation electrode on the substrate is located within the orthographic projection of the data line on the substrate; The extension direction of the compensation electrode is the same as the extension direction of the data line, and the length of the compensation electrode is less than or equal to the length of the data line in the extension direction of the data line.

3. The array substrate according to claim 1, wherein, Includes a compensation electrode, wherein the orthographic projection of the compensation electrode on the substrate is located within the orthographic projection of the data line on the substrate; In the direction perpendicular to the extension of the data line, the size of the orthographic projection pattern of the data line on the substrate is greater than or equal to the size of the orthographic projection pattern of the compensation electrode on the substrate.

4. The array substrate according to claim 1, wherein, The portion of the data line located between two adjacent gate lines includes a first segment, a bend, and a second segment connected in sequence.

5. The array substrate according to claim 4, wherein, The data line further includes a third segment and a fourth segment. The third segment is connected to the end of the first segment away from the bend. The fourth segment is connected to the end of the second segment away from the bend. The orthographic projections of the third segment and the fourth segment on the substrate overlap with the orthographic projections of the gate line on the substrate.

6. The array substrate according to claim 5, wherein, The width of the third line segment along the direction perpendicular to the extension of the third line segment is greater than the width of the first line segment along the direction perpendicular to the extension of the first line segment; the width of the fourth line segment along the direction perpendicular to the extension of the fourth line segment is greater than the width of the second line segment along the direction perpendicular to the extension of the second line segment.

7. The array substrate according to claim 6, wherein, The width of the portion of the compensation electrode covering the third line segment along the direction perpendicular to the extension of the third line segment is greater than the width of the portion of the compensation electrode covering the main structure of the first line segment along the direction perpendicular to the extension of the first line segment. The width of the portion of the compensation electrode covering the fourth line segment along the direction perpendicular to the extension of the fourth line segment is greater than the width of the portion of the main structure of the compensation electrode covering the second line segment along the direction perpendicular to the extension of the second line segment.

8. The array substrate according to claim 4, wherein, The pixel electrode is located at a position defined by two adjacent data lines and two adjacent gate lines.

9. The array substrate according to claim 1, wherein The minimum distance between the second part and the gate line is greater than or equal to the minimum distance between the first part and the gate line.

10. The array substrate according to claim 9, wherein, The minimum distance between the second part and the gate line is greater than the minimum distance between the first part and the gate line, and the pixel electrode covers the second part and part of the connection part.

11. The array substrate according to claim 1, wherein, The array substrate further includes a semiconductor layer located between the first conductive layer and the third conductive layer, and a portion of the semiconductor layer is in direct contact with the first conductive layer. The semiconductor layer includes a first active portion, and the orthographic projection of the data line on the substrate is located within the orthographic projection of the first active portion on the substrate.

12. The array substrate according to claim 11, wherein, The semiconductor layer further includes a second active portion, the first active portion and the second active portion are connected, and the orthographic projection of the first electrode of the transistor on the substrate and the orthographic projection of the second electrode of the transistor on the substrate overlap with the orthographic projection of the second active portion on the substrate, respectively. The pixel electrode also covers the side of the second active portion away from the second electrode of the transistor, and the pixel electrode is in direct contact with the side.

13. The array substrate according to claim 4, wherein, The array substrate further includes a fourth conductive layer, which is located on the side of the second conductive layer away from the substrate and is insulated from the second conductive layer. The orthographic projection of the fourth conductive layer on the substrate overlaps with the orthographic projections of the pixel electrode, the data line, and the gate line on the substrate, respectively. The fourth conductive layer has multiple slits, and the orthographic projection of the region where the slits are located on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate.

14. The array substrate according to claim 13, wherein, The third conductive layer further includes a storage electrode line arranged parallel to the gate line, and the storage electrode line is electrically connected to the fourth conductive layer through a via. The orthographic projection of the storage electrode line on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the storage electrode line on the substrate also overlaps with the orthographic projection of the fourth conductive layer on the substrate.

15. A display panel, wherein, Includes the array substrate as described in any one of claims 1-14.

16. A method for fabricating an array substrate, wherein, The method is applied to the fabrication of the array substrate according to claim 11 or 12, the method comprising: Provide substrate; Forming semiconductor thin films; Forming a first conductive thin film; Simultaneously, the semiconductor thin film and the first conductive thin film are patterned to obtain a semiconductor layer and a first conductive layer; wherein, the first conductive layer includes multiple data lines arranged in an array; A second conductive layer is formed; the second conductive layer is in direct contact with a portion of the first conductive layer and includes a pixel electrode; It also includes a third conductive layer located between the first conductive layer and the substrate; the third conductive layer includes multiple gate lines arranged in an array, the gate lines intersecting with the data lines and being insulated from them; It also includes a transistor, the first conductive layer further includes a first electrode and a second electrode of the transistor, the pixel electrode is in direct contact with a portion of the first electrode of the transistor, and the data line is connected to the second electrode of the transistor; The first electrode of the transistor includes a first part parallel to the extension direction of the gate line, a second part parallel to the extension direction of the gate line, and a connecting part connecting the first part and the second part; the extension direction of the connecting part intersects the extension direction of the gate line and the extension direction of the data line; in a direction perpendicular to the substrate, on the side of the second part and the pixel electrode close to the gate line, the pixel electrode covers the second part.

17. The method for fabricating an array substrate according to claim 16, wherein, The simultaneous patterning of the semiconductor thin film and the first conductive thin film to obtain the semiconductor layer and the first conductive layer includes: A photoresist film is formed on the first conductive film; The photoresist film is patterned using a halftone mask to obtain a first photoresist pattern. Using the first photoresist pattern as a mask, the semiconductor thin film and the first conductive thin film are patterned to obtain the first semiconductor pattern and the first conductive pattern. The first photoresist pattern is etched to obtain the second photoresist pattern; Using the second photoresist pattern as a mask, the first semiconductor pattern and the first conductive pattern are patterned to obtain the semiconductor layer and the first conductive layer. Remove the second photoresist pattern.

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