Adjustable timer component for semiconductor devices

Abstract

Systems, devices, and methods related to adjustable timer components are described. A memory device includes a memory controller coupled to the memory device, the memory controller comprising an adjustable timer component. The adjustable timer component is configured to receive a timer generation request and, in response to receiving the request, store an active timer entry corresponding to a particular first address in a cache, generate a timer corresponding to the active timer entry and the particular first address, and monitor the timer to determine when the timer expires. In response to the expiration of the timer, the timer entry is dequeued and the timer entry stored in the cache is invalidated. The memory device can also include command logic configured to, prior to issuing a second command, query the cache of the adjustable timer component to determine whether the cache includes an active timer entry corresponding to a particular second address.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more particularly to apparatus, systems and methods for adjustable timer components in semiconductor devices. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Thyristor Random Access Memory (TRAM), among others. Non-volatile memory provides persistent data by retaining stored data when not powered and includes NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistive variable memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM) such as spin torque transfer random access memory (STT RAM), among others.

[0003] A memory controller can be used to select commands for execution by a memory device. The memory controller can determine which commands are ready to be executed based on a specific selection strategy. In various examples, timers can be used to determine whether a particular command is selectable for execution, because some memory devices may not function properly if sufficient time has not elapsed between access requests to the same row of the memory device. For example, a timer can be used to monitor the delay between the closing time of a particular row and the next opening time of that row (e.g., precharge to activation time delay). Attached Figure Description

[0004] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This is a block diagram of a controller that can be used in association with a timer creation according to several embodiments of the present disclosure.

[0006] Figure 3 This describes a functional block diagram illustrating an adjustable timer component for a semiconductor device according to several embodiments of the present disclosure.

[0007] Figure 4 This section describes functional block diagrams in the form of a memory device and an adjustable timer component according to several embodiments of the present disclosure.

[0008] Figure 5 Timing diagrams of an adjustable timer component in a semiconductor device according to several embodiments of the present disclosure are provided.

[0009] Figure 6 Another timing diagram is provided for an adjustable timer component in a semiconductor device according to several embodiments of the present disclosure.

[0010] Figure 7 A flowchart illustrating example methods for operating an adjustable timer component according to several embodiments of the present disclosure. Detailed Implementation

[0011] This document describes systems, apparatus, and methods relating to an adjustable timer component for a semiconductor device. The controller includes an adjustable timer component for creating active timer entries upon receiving a timer generation request. The adjustable timer component receives the timer generation request when a command completes (e.g., when the execution of the command completes). As used herein, the term "active timer entry" refers to data set in a computing system (e.g., on a memory bank, memory die, or line of the computing system) between the completion of a command and the execution of a subsequent command in the computing system. The adjustable timer component can use the same address detection logic circuitry to determine whether an active timer entry exists on a line of memory, thereby limiting the number of commands that can be executed on a line of memory within a time period. The size of the command queue for the memory device determines the maximum number of active timer entries that can be placed on a line of memory at a time. For example, increasing the size of the memory device increases the maximum number of active timer entries that can be placed on a line at a time.

[0012] Systems, apparatus, and methods relating to adjustable timer components for semiconductor devices are described. In some embodiments, appropriate delays may be inserted to satisfy stringent timing requirements imposed by a memory device; for example, a minimum delay may be inserted between precharging and activating the same row to allow for proper operation of the memory device. After a command to a row is completed, a single active timer entry may be used to ensure a delay between the time when the command to the row (e.g., a precharge event) is completed and the time when a subsequent command (e.g., an activation event) to the same row can be issued. The length of the delay may be based on the type of memory device executing the command. An active timer entry may be initialized corresponding to the precharge event of the row. The row may then be kept in an "unavailable" state for an amount of time corresponding to the active timer entry. Once the active timer entry expires, the row may be activated. As used herein, the term "expired" may mean that an active timer entry expires after an amount of time has elapsed since its creation.

[0013] In some embodiments, a predefined number of active timer entries may be associated with rows of memory in a memory device. The predefined number of active timer entries may be determined based on the memory device coupled to a controller in which adjustable timer components are implemented. Therefore, the number of active timer entries that can be created may vary depending on the type of memory device coupled to the controller.

[0014] Because memory systems are tasked with performing more complex operations, various types of memory devices can be implemented to store different types of data. In some methods, last-page detection can be used to set a timer for a row after a command has been completed. However, existing methods lack the flexibility to work with different types of memory.

[0015] In contrast, the embodiments described herein relate to an adjustable timer component of a controller configured to create active timer entries for multiple types of memory devices, such as memory devices operating according to different sets of timing characteristics. Memory devices may include a last-page access detection circuitry to limit consecutive accesses to the same row. The length of the delay between consecutive accesses to the same row may vary based on the type of memory device being accessed. Benefits of the adjustable timer component include providing flexibility in how the circuitry is structured. For example, the adjustable timer component can be implemented in multiple types of controllers and used with multiple types of memory devices. A set of timing characteristics may include at least a row precharge time (tRP). As used herein, the term "row precharge time" generally refers to the time between executing a precharge command (e.g., to close a row) and executing a subsequent activation command on the same row. By implementing an adjustable timer component in the controller to allow the controller to create and monitor active timer entries for multiple types of memory devices with different sets of timing characteristics, less space in the memory system can be dedicated to managing memory devices, as a single controller can be used instead of multiple controllers to create and monitor active timer entries for multiple memory devices. By dedicating less space within the memory system to creating and monitoring active timer entries for the memory devices, more space within the memory system becomes available for implementing components that perform different functions. Furthermore, because some embodiments of this disclosure involve a single memory controller for performing the operations described herein (as opposed to the multi-controller architecture of some methods), problems that may arise from insufficient heat dissipation and are prevalent in multi-controller approaches can be mitigated.

[0016] In some embodiments, the memory system may be a Compute Fast Link (CXL) compliant memory system (e.g., the memory system may include a PCIe / CXL interface). CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to accelerate the performance of next-generation data centers. CXL technology maintains memory consistency between the CPU memory space and the memory on the attached device, which allows resource sharing to achieve higher performance, reduced software stack complexity, and lower total system cost.

[0017] CXL is designed as an industry-open standard interface for high-speed communications, as accelerators are increasingly being used to complement CPUs to support emerging applications such as artificial intelligence and machine learning. CXL technology is built on the Peripheral Component Interconnect Fast (PCIe) infrastructure, thereby leveraging the PCIe physical and electrical interfaces to provide advanced protocols in areas such as input / output (I / O) protocols, memory protocols (e.g., initially allowing the host and accelerator to share memory), and coherence interfaces.

[0018] In the following detailed description of this disclosure, reference is made to the accompanying drawings, which form part of and illustrate by way of example how one or more embodiments of this disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice embodiments of this disclosure, and it should be understood that other embodiments may be utilized and process, electrical, and structural changes may be made without departing from the scope of this disclosure.

[0019] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” may include both singular and plural references unless the context clearly specifies otherwise. Additionally, “a number,” “at least one,” and “one or more” (e.g., a number of memory banks) may refer to one or more memory banks, while “more” is intended to mean more than one such thing.

[0020] Furthermore, the terms “may” and “can” are used throughout this application in a permissive sense (i.e., possible, able) rather than in a mandatory sense (i.e., required). The term “comprising” and its derivatives mean “including but not limited to”. Depending on the context, the terms “coupled” and “coupling” mean a physical direct or indirect connection, or for accessing and moving (transmitting) commands and / or data. Depending on the context, the terms “data” and “data value” are used interchangeably and may have the same meaning herein.

[0021] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0022] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs), as well as CXL memory expanders.

[0023] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0024] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, the terms “coupled to” or “coupled with” can refer to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and include, for example, electrical, optical, magnetic, and other connections.

[0025] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 may write data to and / or read data from the memory subsystem 110.

[0026] Host system 120 may be coupled to memory subsystem 110 via an interface (e.g., a physical host interface). Examples of interfaces may include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface, such as CXL. The interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize a Fast NVM (NVMe) interface to access memory components (e.g., memory device 130). The interface provides a means for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 For example, memory subsystem 110 is described. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0027] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional crosspoint (“3D crosspoint”) memory device, which is a crosspoint array of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without previously erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Although non-volatile memory components (such as 3D cross-point arrays of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND)) are described, memory device 130 may be based on a variety of other types of non-volatile memory or storage devices, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0032] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0033] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and translate them into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations associated with memory device 130, such as wear leveling operations, discard item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses (PBAs)). The memory subsystem controller 115 may further include a host interface (not depicted) circuitry for communicating with the host system 120 via a physical host interface (not depicted). The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory devices 130 and / or 140.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 from an external source (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. Examples of managed memory devices are managed NAND (MNAND) devices, such as UFS or eMMC memory.

[0036] Memory subsystem 110 includes an adjustable timer component 113. In some embodiments, the adjustable timer component 113 is located on memory subsystem controller 115. In some embodiments, the adjustable timer component 113 is not part of memory subsystem controller 115. The adjustable timer component 113 can be used to create and monitor active timer entries stored in a cache. In some embodiments, memory subsystem 110 includes the adjustable timer component 113 capable of creating active timer entries in response to receiving a timer generation request from a memory device. In some embodiments, memory subsystem controller 115 includes at least a portion of the adjustable timer component 113. For example, memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0037] Adjustable timer component 113 can create an active timer entry after receiving a timer generation request. The timer generation request may contain an indication that a command has been completed on a memory device (e.g., a row in the memory bank of the memory device). The active timer entry can be set to expire after a certain amount of time. During the time period between the creation of the active timer entry and its expiration, commands cannot be executed on the row to which the active timer entry is applied. Once the active timer entry expires, commands can be executed on the row to which the active timer entry is applied.

[0038] Figure 2 This is a block diagram of a portion of a controller that can be used in association with timer creation according to several embodiments of the present disclosure. The memory controller 215 may include a write path 204, a read path 210, scheduling logic 216, a DDR PHY interface (DFI) interface 222, physical (PHY) layers 224-0, 224-1, ..., 224-N (individually referred to or collectively referred to as PHY layer 224), a credit management component 226, and a register pool component 228. In some embodiments, the memory controller 215 may be coupled to a central controller 202, wherein the memory controller 215 acts as a "back-end" controller coupled to the memory device via PHY layer 224.

[0039] The memory controller 215 can receive write requests from the central controller 202 via write path 204 and read requests from the central controller 202 via read path 210. Write path 204 may include a command buffer 206 and a data buffer 208. Commands associated with a write request can be sent via command buffer 206, and corresponding data can be sent via data buffer 208. Read path 210 may also include a command buffer 212 and a data buffer 214. Commands associated with a read request may be stored in command buffer 212 before execution, and data corresponding to the read request may be provided to the central controller 202 via data buffer 214. In some embodiments, when a write request is received from the central controller 202, an acknowledgment may be sent to the central controller 202, and data may be written to the memory according to the timing of the memory device. In some embodiments, a read request acknowledgment may be sent after the read request is completed. The read request acknowledgment may be accompanied by data.

[0040] In some embodiments, the central controller 202 may initiate the intent to perform memory access via the credit management component 226. The credit management component 226 may be used to prevent overflows at internal buffers (e.g., 206, 208, 212, 214). When a command is executed, control may be passed to the PHY layer 224 via the DFI interface 222. The command may then be sent to the PHY layer 224 in parallel.

[0041] In some embodiments, physical (PHY) layer 224 may couple memory controller 215 to multiple memory rows. As used herein, the term “PHY layer” generally refers to the physical layer in the Open Systems Interconnection (OSI) model of a computing system. PHY layer 224 may be the first (e.g., lowest) layer of the OSI model and may be used to transmit data over a physical data transmission medium. In some embodiments, the physical data transmission medium may be multiple channels (not depicted). As used herein, the term “memory row” generally refers to a group of memory chips (e.g., DRAM memory chips and / or FeRAM memory chips) that can be accessed simultaneously. For example, PHY layer 224 may correspond to a corresponding channel, which may include multiple chips. Chips capable of sending / receiving data in parallel across multiple channels may be referred to as a row. Chips comprising a memory row may also share a chip selection. As used herein, the term “chip selection” may refer to a control line used to select one or more memory chips from multiple memory chips connected to the same memory bus.

[0042] Scheduling logic 216 may include content-addressable memory (CAM) 218 ​​and selection logic 220. The scheduling logic may implement a command selection strategy to determine the order in which commands are selected for execution. In some embodiments, the command may be a column command or a row command. As used herein, a "column" command refers to a command pointing to an address corresponding to an open (e.g., activated) row (e.g., a page) of an array of memory devices, and a "row" command refers to a command pointing to an address corresponding to a closed (e.g., deactivated) row of the array. In some embodiments, an adjustable timer component ( Figure 3 The adjustable timer component 313 shown can be integrated into the scheduling logic 216 to create and monitor active timer entries corresponding to commands sent to various types of memory devices.

[0043] Figure 3 This illustration shows a functional block diagram in the form of an adjustable timer component for a semiconductor device, according to several embodiments of the present disclosure. The adjustable timer component 313 may be integrated into a memory controller (e.g., Figure 2 The adjustable timer component 313 may include a time logic section 332, a cache 348, and a cache interface 354. The time logic section 332 may include an input data queue 334, a time manager 336, a timestamp queue 338, a time counter 341, a timer value 342, a compare flip-flop 344, and an update logic circuit system 346.

[0044] Input data queue 334 can store input data received from an external circuit system. Input data can be received from the external circuit system via port 358. In some embodiments, the external circuit system may be a memory device (e.g., Figure 4 The memory device 440 in the memory controller (e.g., memory device 440) or a part of the memory controller (e.g., memory device 440 in the memory controller) Figure 4 (Part 460). In various embodiments, the input data may include the memory address of the storage of the completed command and the line address of the line in which the completed command is located. Additionally, the input data may include an indication that a command has been completed. Input data may be transferred from the input data queue 334 to the time manager 336. In some embodiments, the input data queue 334 may hold input data associated with multiple completed commands before sending the input data associated with the completed command to the time manager 336. Furthermore, in some embodiments, the input data queue may be a first-in, first-out (FIFO) queue.

[0045] Time manager 336 can be configured to create active timer entries when input data is inserted into input data queue 334. As previously stated, input data queue 334, which receives input data, can activate time manager 336. As used herein, the term "activate time manager" can refer to instructing time manager 336 to create active timer entries for input data. In some embodiments, time manager 336 can create active timer entries for a completed command after receiving a request for an active timer entry associated with the completed command.

[0046] An active timer entry indicates the amount of time expected to elapse between command completion and the commencement of subsequent commands for that row. Subsequent commands may be executed after the command is executed. In some embodiments, an active timer entry may be created for each completed command. Therefore, after a particular command completes, a subsequent command may not be executed for that row until the active timer entry corresponding to that particular command expires. In some embodiments, commands may be completed for rows different from the row containing the active timer entry.

[0047] An active timer entry may correspond to a row precharge. For example, when an active timer entry is created for a row, precharging of that row can be initiated. Each active timer entry corresponds to a row of the memory device, and a command corresponding to the active timer entry is executed in that row. In some embodiments, after a precharge command, the row may remain unused for an amount of time equal to the timer value of the corresponding active timer entry. In some embodiments, the row is precharged (e.g., by executing a precharge command) to close the row. An active timer entry expires after an amount of time corresponding to the value of the active timer entry has elapsed. An active timer entry is considered to have expired when an amount of time associated with the timer value of the active timer entry has elapsed since the active timer entry was created. Once an active timer entry has expired, the row on which the active timer entry was applied can be opened. Opening the row (e.g., via executing an activation command) allows another command to be performed on that row. Active timer entries can be used to ensure that an amount of time has elapsed between the execution of multiple commands in the same row of the memory bank of the memory device.

[0048] The time manager 336 may also send information to the cache 348. In some embodiments, the information may be information about rows in the memory bank of the memory device. For example, the time manager 336 may send information indicating whether an active timer entry exists on a row to the cache 348. As will be further described herein, the information sent from the time manager 336 to the cache 348 may determine whether an query to the cache 348 will result in a hit or a miss.

[0049] Time manager 336 can create timestamps for input data. As used herein, the term "timestamp" can refer to the time at which an active timer entry is created. In some embodiments, time manager 336 can apply timestamps to corresponding input data. Time manager 336 can queue (e.g., place) the input data and its corresponding timestamp in timestamp queue 338. Time manager 336 can receive the time corresponding to the timestamp and the input data from time counter 341 (a free-running counter used to indicate the elapsed time).

[0050] The timestamp queue 338 can store data including multiple fields. In some embodiments, as previously stated, the timestamp queue 338 can store input data and timestamps corresponding to the input data received from the time manager 336. In some embodiments, the timestamp queue 338 can be a first-in, first-out (FIFO) queue. In a FIFO queue, the oldest entry in the queue can be processed before newer entries in the queue.

[0051] Comparison trigger 344 can be used to compare the sum of the timestamp value in timestamp queue 338 and the timer value stored in timer value register 342 with the value of the time counter stored in time counter 341. The result of that comparison can be sent to the cache via update logic circuitry 346. As used herein, the term "time counter" can refer to a component used to indicate the elapsed time. In some embodiments, time counter 341 can be a free-running counter. As used herein, the term "free-running counter" can refer to a time counter that runs continuously regardless of operations being performed by other memory components in the memory controller. For example, the value of time counter 341 can be the value of the timestamp at the time the timestamp was created. The timer value stored in timer value register 342 can be the amount of time expected to elapse between the completion of a command and the start of execution of a subsequent command on the same line.

[0052] In some embodiments, the result of a comparison performed by comparison trigger 344 may indicate whether an active timer entry for a row is still active or whether an active timer entry has expired. For example, if the comparison performed by comparison trigger 344 indicates that the sum of the timestamp and the timer value stored in timer value register 342 is at least equal to the value of time counter 341 at the moment the comparison is being performed, then this may indicate an amount of time corresponding to the timer value stored in timer value register 342 has elapsed since the timestamp was created. Therefore, the comparison indicates a programmed amount of time has elapsed since the row has completed its precharge, allowing the next command to be executed on the same row. However, if the comparison indicates that the sum of the timestamp and the timer value stored in timer value register 342 is not equal to (e.g., less than) the value of time counter 341, then this may indicate that the amount of time expected to elapse between the completion of a command and the start of subsequent command execution on the row has not yet elapsed. Therefore, the row will remain closed, and a command will not be executed on the row until an amount of time corresponding to the timer value stored in timer value register 342 has elapsed.

[0053] The update logic system 346 can be configured to invalidate (e.g., remove) active timer entries stored in the cache 348. As previously stated, the update logic system 346 can send a comparison result performed by the comparison flip-flop 344 to the cache 348. By sending the comparison result to the cache 348, the update logic 346 can invalidate (e.g., remove) active timer entries stored in the cache 348. For example, if the update logic system 346 sends a comparison result indicating that an estimated amount of time has elapsed since the creation of the active timer entry to the cache 348, then the active timer entry can be removed from the cache 348.

[0054] Cache 348 may store data associated with the location of an executed command in the memory device. In some embodiments, the data stored in data cache 348 may include valid bits 350-1, 350-2, 350-3, ..., 350-N (collectively referred to as valid bits 350) and the line address of the executed command line in the memory device. Valid bits 350 may be used to determine whether a data entry in cache 348 is valid (e.g., the data stored in cache 348 is the same as the data stored in memory device 340) or invalid (e.g., the data stored in cache 348 has been changed so that it is no longer the same as the data in memory device 340). In some embodiments, input data may include valid bits 350, the line address of the executed command line in the memory device, and the command. In some embodiments, cache 348 may store data 352-1, 352-2, 352-3, ..., 352-N (collectively referred to as data 352) associated with a completed command. As previously stated, cache 348 can store active timer entries received from time manager 336, including resource tags such as the address, memory bank, and row corresponding to the location of the applied active timer entry in the memory device. The cache can also receive updated states of active timer entries from update logic circuitry 346. Cache interface 354 can be used to connect cache 348 to external circuitry (e.g., ...). Figure 4 The interface for transmitting data between the controller section 460 in the system and the cache 348. In some embodiments, data can be sent from the cache 348 to an external circuit system and from the external circuit system to the cache 348 via port 356.

[0055] In some embodiments, cache 348 may be capable of operating without accessing a memory device (e.g., memory device). Figure 4In the case of memory device 440, a data cache is provided to indicate active timer entries for requested data active on the memory device. In other embodiments, cache 348 may be SRAM that can be used to store a greater number of active timer entries than a data cache. The data cache may be a memory component smaller than SRAM and can access data from the data cache in a shorter time than accessing data from SRAM. Furthermore, SRAM may hold programs and data currently accessed by the memory system, and the data cache may hold data frequently accessed by the memory system. The characteristics of cache 348 may vary depending on whether cache 348 is a data cache or SRAM. For example, if cache 348 is SRAM, then cache 348 may have a larger size (e.g., higher memory capacity) compared to the case where cache 348 is a data cache. However, due to the increased memory capacity compared to a data cache, embodiments where cache 348 is SRAM may have higher latency than embodiments where cache 348 is a data cache. This higher latency may be caused by the increased time required to search for data in a larger SRAM compared to searching data in a smaller data cache. In some embodiments, the size of cache 348 can be adjusted to adjust the number of commands executed in the memory device within a time period. For example, the size of cache 348 (e.g., memory capacity) can be increased to increase the number of commands executed in the memory device within a time period, and the size of cache 348 can be decreased to decrease the number of commands executed in the memory device within a time period. In some embodiments, the size of cache 348 may correspond to the size of a corresponding memory device. This allows the adjustable timer section 313 to adapt to different memory types and sizes. For example, the same adjustable timer section 313 can be implemented in a memory controller coupled to a memory device having a tRP and in a memory controller coupled to a memory device having a different tRP. In some embodiments, when adjusting the number of commands executed within a time period, the number of active timer entries created within a time period is adjusted. For example, when the number of commands executed in the memory device within a time period increases, the number of active timer entries created within a time period increases. Furthermore, for example, when the number of commands executed in a memory storage device within a time period decreases, the number of active timer entries created within that time period also decreases.

[0056] Figure 4 This illustration describes functional block diagrams in the form of memory devices and adjustable timer components for semiconductor devices, according to several embodiments of the present disclosure. Figure 4 Includes a memory controller (e.g., coupled to the adjustable timer component 413) Figure 2 The memory controller 215 described herein includes a portion 460 and a memory device 440 coupled to the controller portion 460. The controller portion 460 may include a command queue 464, command logic 466, and command execution queue 470.

[0057] Adjustable timer component 413 and Figure 3 The adjustable timer component 313 described herein is identical. Command queue 464 may hold commands 462 received by memory controller section 460. Command logic 466 may select a command 462 for execution. In some embodiments, the command 462 may be sent by a host device, and in other embodiments, the command 462 may be sent from another part of the memory system. In some embodiments, command logic 466 may select which command 462 to execute from a plurality of commands 462 stored in command queue 464. Command logic 466 may determine which command 462 to execute based on a scheduling policy. As used herein, the term "scheduling policy" may refer to the method used to allocate computing resources to processors (e.g., ...). Figure 1 The algorithm for concurrent tasks of processor 117 is shown in the figure.

[0058] In some embodiments, the scheduling strategy may be a First-Come, First-Served (FCFS) or First-Ready-First-Come, First-Served (FR-FCFS) strategy. An FCFS strategy may include scheduling commands sent to the memory controller for execution by the main memory device (e.g., the main memory of a DRAM device) based on the order in which commands are received (e.g., decoded) by the controller. Thus, the earliest command is executed first. However, various memory systems include timing constraints that can affect whether a command can be issued (e.g., from the memory controller to the memory device). For example, various supporting circuitry systems associated with a memory array (e.g., row decoding circuitry, column decoding circuitry, sense amplifier circuitry, precharge circuitry, refresh circuitry, etc.) may include timing constraints that determine when / whether a particular command is ready for execution by the memory device. An FR-FCFS strategy may take such constraints into account and increase the execution delay whenever a newer command becomes ready to be issued to the memory device (e.g., based on timing constraints), but the command is not sent to the memory device until an earlier command has been executed.

[0059] Compared to the FCFS strategy, the FR-FCFS strategy can reduce average latency. For example, in the FR-FCFS strategy, the memory controller can traverse the command queue and select the commands it encounters that are ready to be issued. Therefore, earlier commands that are not yet ready can be skipped to support newer pending commands that are ready.

[0060] As an example, the FR-FCFS strategy may include prioritizing column commands over row commands, such that the strategy includes searching a command queue for the earliest column command ready to be issued, and if no column command is found ready to be issued, then selecting the earliest row command ready to be issued for use in issuing to the memory device.

[0061] Command logic 466 may include enable pins 468-0, 468-1, 468-2, and 468-3 (individually referred to as or collectively as enable pin 468) that can be used to implement scheduling policies. Enable pin 468 can be used in association with scheduling policies and allows command logic to monitor various characteristics of memory device 440. These characteristics may include at least whether a row is busy, whether a row is waiting for a precharge command, and whether a row is waiting for an activation command.

[0062] In some embodiments, after command 462 is executed on memory device 440, an active timer entry may be created and associated with the line on which command 462 was executed, such that a subsequent command may not be executed on that line until the active timer entry expires. Once the active timer entry corresponding to command 462 expires, command logic 466 may issue the next (e.g., subsequent) command 462. In some embodiments, before issuing a subsequent command 462 for execution to a specific second address of memory device 440, command logic 466 may be configured to query cache 448 of adjustable timer component 413 to determine whether cache 448 contains an active timer entry corresponding to that specific second address. Data and queries may be transferred between command logic 466 and cache 448 via cache interface 454. Command logic 466 may be further configured to issue a specific subsequent command 462 to memory device 440 in response to determining that cache 448 does not contain an active timer entry corresponding to a specific second address. In some embodiments, the specific second address may be the same address as the specific first address, such that command logic 466 is further configured to delay issuing a specific subsequent command 462 to memory device 440 in response to determining that cache 448 contains an active timer entry. In some embodiments, the command 462 corresponding to the specific first address is a precharge command, and the timer expiration is based on a minimum amount of time to precharge the row before activating the row in memory device 440.

[0063] In some embodiments, the cache 448 may be sized based on the type of memory device 440 in the memory subsystem. For example, if the memory device 440 is an LPDDR5 memory device with 16 banks per device, then the cache 448 may have N cache elements, for example, 16 cache elements corresponding to 16 memory banks, one cache element per bank. In some embodiments, each cache element may be identified by a bank address and a row address.

[0064] Figure 5 Timing diagrams of an adjustable timer component in a semiconductor device according to several embodiments of the present disclosure are provided. Figure 5 It includes various signals associated with the operation of the adjustable timer component. Figure 5 The example shown includes clock signal 574, timer value 542, time counter 541, input data valid bits 550, input data 534, time manager 536, timestamp valid bits 576, timestamp 538, compare trigger 544, and update logic 546. Each created timer expires after timer value 542 * clock cycles (e.g., fifteen clock cycles).

[0065] The time counter 541 can be configured to maintain free-running counting based on a clock cycle of clock signal 574. Furthermore, a signal different from the clock signal can indicate the operation of an adjustable timer component (e.g., Figure 4 The adjustable timer component 413 in the middle receives the input data at a time (e.g., start time 578). Figure 5 In the example illustrated, the value of start time 578 is five (e.g., the sixth clock cycle from when time counter 541 starts tracking clock 574). Figure 5 In the example described, when the value of time counter 541 is five, time manager 536 can place a timestamp on input data 580. For example... Figure 5 As shown, the time manager 536 can be in idle state 582-1, 582-2, or processing state 584. Figure 5In the example described, before receiving input data 580, time manager 536 may be in a first idle state 582-1. The first idle state 582-1 may be a state in which time manager 536 has not placed a timestamp on input data 580 or has not placed updated input data 586 in timestamp queue 538. After receiving input data 580, time manager 536 may be in a first processing state 584-1. In the first processing state 584-1, time manager 536 may place a timestamp on input data 580. Once a timestamp is placed on input data 580, input data 580 becomes updated input data 586. Updated input data 586 may be placed in timestamp queue 538.

[0066] exist Figure 5 In the example timing diagram shown, when the value of timer 541 is twenty, comparator trigger 544 compares the sum of timer value 542 and timestamp with the value of timer 541. If the sum of timer value 542 and timestamp is equal to or greater than the value of timer 541, then update logic 546 updates the cache (e.g., ...). Figure 4 The corresponding active timer entry in the cache 448 is invalidated and dequeued. For example, such as... Figure 5 As shown, timer value 542 can be programmed for fifteen clock cycles. The value of time counter 541 at time 578 can be the time when the adjustable timer component receives input data 580. In this example, the value of time counter 541 when the adjustable timer component receives input data 580 is five. If comparison trigger 544 performs a comparison at time 578, then the sum of timer value 542 and timestamp will not be equal to the value of time counter 541. Therefore, updated input data 586 will be queued in timestamp queue 538, or if updated input data 586 is already queued in timestamp queue 538, then it remains queued. At time 588, the amount of time corresponding to timer value 542 has elapsed since the timestamp was placed on input data 580. At time 588, the value of time counter 541 is twenty. The comparison performed by comparison trigger 544 will indicate that the sum of timestamp and timer value 542 will be equal to the value of time counter 541 at time 588. This indicates the amount of time corresponding to timer value 542 that has elapsed since the adjustable timer component received input data 580 at time 578. Therefore, update logic 546 will invalidate the corresponding active timer entry in the cache and dequeue input data 580 from input data queue 534.

[0067] When update logic 546 is not updating the state of active timer entries in the cache, update logic 546 can be in idle state 582-3. When update logic is updating the state of active timer entries in the cache, update logic can be in processing state 584-2. Once update logic 546 updates the state of active timer entries in the cache, update logic can return to idle state 582-4.

[0068] Figure 6 Another timing diagram is provided for an adjustable timer component in a semiconductor device according to several embodiments of the present disclosure. Figure 6 Include Figure 5 The signals in the timing diagram described herein. However, with Figure 5 Compared to the single timer entry described in the document, Figure 6 This illustrates a timing diagram with two active timer entries.

[0069] The first time counter value is 678-1, and the adjustable timer component (e.g., Figure 4 The adjustable timer component 413 shown can receive first input data 680-1 and, at a second time counter value 678-2, can receive second input data 680-3. For example, as Figure 6 As shown, the first time counter value 678-1 can be five and the second time counter value 678-2 can be eight. The first input data 680-1 and the second input data 680-2 can respectively contain data corresponding to the execution of the command and subsequent commands.

[0070] In some embodiments, the input data queue 634 may simultaneously store first input data 680-1 and second input data 680-2. The time manager 636 may place a timestamp on the first input data 680-1 in the input data queue 634 and a timestamp on the second input data 680-2 in the input data queue 634. The time manager 636 may place a first active timer entry corresponding to the first input data 680-1 and a second active timer entry corresponding to the second input data 680-2 in a cache (e.g., ...). Figure 4 The time manager 636 can place the first input data 680-1 and the second input data 680-2 in the timestamp queue 638. In some embodiments, the timestamp queue 638 can store the first input data 680-1 and the second data simultaneously.

[0071] As previously stated, the timestamp queue 638 can be a FIFO queue. Therefore, the comparison trigger 644 can perform a comparison on the first input data 680-1 before performing a comparison on the second input data 680-2. Figure 6In the example shown, the comparison trigger 644 compares the sum of timer value 642 and the timestamp placed on the first input data 680-1 with a time counter value 688-1 of 20. In this example, the timestamp of the first input data 680-1 has a value of 5 and timer value 642 is 15. Therefore, the sum of timer value 642 and the timestamp of the first input data 680-1 is 20, which is the time counter value 688-1 at the time of comparison. Therefore, an estimated amount of time has elapsed since the timestamp corresponding to the first input data 680-1 was created (e.g., the time corresponding to timer value 642), and the active timer entry corresponding to the first input data 680-1 is invalidated and removed from the cache. Furthermore, the first input data 680-1 is removed from the timestamp queue 638.

[0072] In addition, such as Figure 6 As shown, the comparison trigger 644 compares the sum of the timer value 642 and the timestamp placed on the second input data 680-2 with the time counter value 688-2 of twenty-three. In this example, the timestamp of the second input data 680-2 has a value of eight and the timer value 642 is fifteen. Therefore, the sum of the timestamp of the second input data 680-2 and the timer value 642 is twenty, which is the time counter value 688-2 at the time of comparison. Therefore, an estimated amount of time has elapsed since the timestamp corresponding to the second input data 680-2 was created, invalidating the active timer entry corresponding to the second input data 680-2 and removing it from the cache. Furthermore, the second input data 680-2 is removed from the timestamp queue 638.

[0073] In some embodiments, the adjustable timer component may include a same-address detection logic circuitry for detecting the state of rows in a cache. The same-address detection logic circuitry can monitor the state of multiple memory banks and multiple rows in the cache. The same-address detection logic circuitry can detect whether an active timer entry currently exists on the row. If an active timer entry exists on the row that has not yet expired, another command will not be executed on that row until that active timer entry expires. In some embodiments, the adjustable timer component includes a timer value register indicating the amount of time that will elapse between executing a command on the row and executing a subsequent command on that row.

[0074] Figure 7 A flowchart illustrating example methods for operating an adjustable timer component according to several embodiments of the present disclosure. Figure 7 This describes the communication between various components (e.g., command logic 766, cache 748, memory device 740, time manager 736, timestamp queue 738, and update logic 746). These components may be similar to, for example... Figure 3 and4 The components described in [the document / document].

[0075] Figure 7 Command 762-1 describes a command targeting a specific row (“ROWY”) within a specific memory bank (“BANKX”) of memory device 740. For example, the host may send command 762-1 to the memory controller (e.g., Figure 4 The command queue (e.g., in the memory controller section 460) of the memory controller (in the memory controller section 460) Figure 4 Command queue 464 in the command queue. When command 762-1 is in the command queue, command logic 766 may perform an interrogation 781-1 on cache 748. In some embodiments, command 762-1 may be a precharge command. In this example, interrogation 781-1 results in a miss 783-1. Miss 783-1 may indicate that the memory bank and row where command 762-1 is to be executed does not currently have an active timer entry associated with that memory bank and row. Therefore, command 762-1 may be sent to memory device 740 for execution 785-1. After execution of command 762-1, command completion indication 787-1 may be sent to command logic 766, and command completion indication 787-2 may be sent to time manager 736 (for example, e.g., Figure 4 The adjustable timer component 413 shown in the figure has a time manager. In response to receiving instruction 787-2, time manager 736 can create an active timer entry corresponding to command 762-1. Time manager 736 can provide the active timer entry corresponding to command 762-1 (e.g., as indicated by 789) to cache 748. Time manager 736 can also queue the active timer entry in timestamp queue 738 791. The entries in timestamp queue 738 will contain timestamps corresponding to when the entry corresponding to command 762-1 entered queue 738.

[0076] like Figure 7 As shown, command logic 766 receives subsequent commands 762-2 for the same row (“ROWY”) and memory bank (“BANKY”). In some embodiments, command 762-2 may be an activation command. Command logic 766 performs an interrogation 781-2 on cache 748 (e.g., to determine if an active timer entry corresponding to the address exists). In this example, interrogation 781-2 causes a cache “hit” 792-1 because the cache already contains an active timer entry corresponding to the address (e.g., the active timer entry corresponding to command 762-1 has not yet expired). In response to the cache hit 792-1, the execution of command 762-2 is deferred (e.g., by being returned to, for example...). Figure 4 The command queue 464 shown in the image). Figure 7 As shown, due to a cache hit of 792-1, a subsequent query 781-3 of cache 748 is executed after a delay of command 762-2 (793-1). Since the active timer entry corresponding to command 762-1 has not yet expired, query 781-3 also causes a cache hit of 792-2 and a further delay of command 762-2 (793-2).

[0077] like Figure 7 As explained above, due to a cache hit of 792-2, a subsequent query 781-4 of cache 748 is executed after a delay of command 762-2 (793-2). In this case, query 781-4 results in a cache miss of 783-2 because the active timer entry corresponding to command 762-1 has now expired. As described above, the comparator flip-flop circuit system (e.g., Figure 3 The comparison trigger 344 shown in the figure Figure 4 The 444 shown can be used to determine the expiration of an active timer entry. For example, a compare-triggered circuitry system can compare the sum of a timestamp and a timer value with the value of a time counter. If the comparison performed by the compare trigger indicates that the sum of the timestamp and the timer value equals the value of the time counter at the moment the comparison is being performed, then this indicates that the amount of time corresponding to the timer value has elapsed since the timestamp was created. Therefore, the active timer value has expired. After the active timer entry corresponding to command 762-1 expires, update 795 is provided from update logic 746 to remove the active timer entry from cache 748.

[0078] Since the active timer entry corresponding to command 762-1 has expired (e.g., as confirmed by a cache miss 783-2), command logic 766 can send command 762-2 to memory device 740 for execution 785-2. In this way, execution of a subsequent command 762-2 at the same address as command 762-1 is not allowed until a predetermined time has elapsed (e.g., as indicated by a timer value). As described herein, various embodiments can be configurable such that timers can be dynamically created and multiple active timers can be created, and the amount of time delay between consecutive accesses to the same address (e.g., a page) can be configurable.

[0079] The figures in this document follow a numbering convention, where the first few digits correspond to the figure number and the remaining digits identify the elements or components within the figure. Similar elements or components between different figures can be identified by using similar digits. For example, 115 could refer to... Figure 1 Component "15" in the text, and similar components can be found in the text. Figure 2Reference numeral is 215. Groups or plurality of similar elements or components are generally referred to herein by a single element number. For example, a plurality of reference elements 350-1 to 350-N may be collectively referred to as 350. As will be understood, elements shown herein in various embodiments may be added, interchanged, and / or removed to provide several additional embodiments of the present disclosure. In addition, the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of the present disclosure and should not be construed as limiting.

[0080] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the foregoing description. The scope of one or more embodiments of this disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of this disclosure should be determined by reference to the full scope of the appended claims together with their authorized equivalents.

[0081] In the foregoing detailed description, some features have been grouped into a single embodiment for the purpose of simplifying this disclosure. This disclosure should not be construed as reflecting an intention that the disclosed embodiments of this disclosure must use more features than expressly recited in each claim. Rather, as reflected in the appended claims, the inventive body lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is itself a separate embodiment.

Claims

1. A device (110) comprising: Memory devices (130, 140); and A memory controller (115, 215) coupled to the memory device (130, 140), the memory controller (115, 215) comprising: Adjustable timer components (113, 313, 413), configured as follows: Receive a timer generation request associated with a first command (462, 762), the first command (462, 762) corresponding to a specific first address of the memory device (130, 140); In response to receiving the timer generation request: The active timer entry corresponding to the specific first address is stored in the cache (348, 748) of the adjustable timer components (113, 313, 413); and A timer corresponding to the active timer entry and the specific first address is generated by queuing the active timer entry, timestamp (538) and corresponding address information in the timer logic (332) of the adjustable timer components (113, 313, 413); In response to the expiration of the timer: Dequeue the active timer entry; and Invalidate the active timer entries stored in the caches (348, 748); and Command logic (466, 766) is configured to query the cache (348, 748) of the adjustable timer components (113, 313, 413) to determine whether the cache (348, 748) contains the active timer entry corresponding to the specific second address before issuing a second command (462, 762) to a specific second address of the memory device (130, 140) for execution, and to issue a specific second command to the memory device in response to a query that occurs when the sum of the timestamp of the active timer entry and the timer value of the active timer entry is greater than or equal to the amount of time that has elapsed since the time counter of the adjustable timer component began tracking the clock signal, wherein the active timer entry is generated before the query occurs.

2. The device of claim 1, wherein the specific second address is the same as the specific first address, such that the command logic is further configured to delay issuing the specific second command to the memory device in response to determining that the cache contains the active timer entry corresponding to the specific first address.

3. The device of claim 1, wherein the first command corresponding to the particular first address is a precharge command, and wherein the timer expiration is based on a minimum precharge-to-activation delay associated with the memory device.

4. The device of claim 1, wherein the adjustable timer component includes an input data queue (334, 534, 634) configured to store input data (580, 586, 680) received from the command logic.

5. The device according to claim 1, wherein: The adjustable timer component includes a time manager (336, 536, 636, 736) configured to place the timestamp on the input data (580, 586, 680); and The adjustable timer component includes a timestamp queue (338, 538, 638, 738) for storing the input data (580, 586, 680) and the timestamps.

6. The device of claim 1, wherein the adjustable timer component includes the time counter (341, 541) for indicating the time of execution of the first command and the second command.

7. The device of claim 1, wherein the adjustable timer component includes a timer value register (342) for indicating the amount of time to elapse between the execution of the first command and the execution of the second command.

8. The device of claim 1, wherein the adjustable timer component includes a comparison trigger (344, 544) for: comparing the timer value (342, 542, 642, 678) of the active timer entry corresponding to the specific first address with the value of the time counter (341, 541); and Compare the timer value of the active timer entry corresponding to the specific second address with the value of the time counter.

9. The device of claim 1, wherein the adjustable timer component includes an update logic circuitry (346) configured to invalidate the active timer entry corresponding to the particular first address and the active timer entry corresponding to the particular second address.

10. The device of claim 1, wherein the size of the cache is adjusted based on the type of the memory device coupled to the memory controller.

11. A method comprising: The adjustable timer components (113, 313, 413) receive a request associated with a first command (462, 762), the first command (462, 762) corresponding to a specific first address of the memory device (130, 140); In response to receiving the request, the active timer entry corresponding to the specific first address is stored in the cache (348, 748) of the adjustable timer components (113, 313, 413); In response to receiving the request, a timer corresponding to the active timer entry and the specific first address is generated by queuing the active timer entry, the timestamp (538) of the active timer entry, and the corresponding address information in the timer logic (332) of the adjustable timer components (113, 313, 413); In response to the expiration of the timer, the active timer entry is dequeued; In response to the expiration of the timer, the active timer entry stored in the cache (348, 748) is invalidated; Before issuing a second command (462, 762) to a specific second address of the memory device (130, 140) for execution, the command logic (466, 766) queries the cache (348, 748) of the adjustable timer components (113, 313, 413) to determine whether the cache (348, 748) contains the active timer entry corresponding to the specific second address; and In response to a query that occurs when the sum of the timestamp of the active timer entry and the timer value of the active timer entry is greater than or equal to the amount of time that has elapsed since the time counter of the adjustable timer component began tracking the clock signal, the second command is issued to the memory device, wherein the active timer entry was generated prior to the query.

12. The method of claim 11, further comprising: In response to receiving a first timer generation request, the active timer entry corresponding to the specific first address is stored in the cache; In response to receiving a second timer generation request, the active timer entry corresponding to the specific second address is stored in the cache; and The execution of the second command is postponed when the active timer entry corresponding to the specific first address is in the cache.

13. The method according to any one of claims 11 to 12, wherein: The active timer entry corresponding to the specific first address expires when an amount of time corresponding to the timer value (342, 542, 642, 678) of the active timer entry corresponding to the specific first address has elapsed since its creation; and When the active timer entry corresponding to the specific first address expires, the active timer entry corresponding to the specific first address is removed from the cache.

14. The method according to any one of claims 11 to 12, wherein the active timer entry corresponding to the particular first address includes a valid bit (350) and a row address in the memory device of the row in which the command is executed.

15. The method of claim 11, wherein the active timer entry corresponding to the particular first address includes a valid bit, a row address of the line in the memory device in which the command is executed, and the command.

16. The method according to any one of claims 11 to 12, further comprising: If the first query (781) returns a cache hit (792), then the first command is sent to the cache before the first command is executed; and If the second query (781) returns a cache miss (783), then the first command is sent from the cache to the memory device.

17. The method according to any one of claims 11 to 12, further comprising: Adjust the size of the cache to adjust the number of commands executed within a time period; and When adjusting the number of commands executed within the time period, the number of active timer entries corresponding to multiple addresses created within the time period is also adjusted.

18. An apparatus (110) comprising: Timer logic (332), which includes: Input data queues (334, 534, 634) are used to store input data (580, 586, 680) received from memory controllers (115, 215); A time manager (336, 536, 636, 736) is configured to create an active timer entry when the input data (580, 586, 680) is inserted into the input data queue (334, 534, 634), assign a timestamp to the input data (580, 586, 680), and store the active timer entry in a cache (348, 748); A timestamp queue (338, 538, 638, 738) is used to store the input data (580, 586, 680) and the timestamps; The timer values ​​(342, 542, 642, 678) are used to set the amount of time elapsed between executing the first command (462, 762) and executing the second command (462, 762); A time counter (341, 541) is used to indicate the amount of time that has elapsed between the execution of the first command (462, 762) at the first specific address and the execution of the second command (462, 762); At a second specific address, wherein the timer logic is configured to query the cache to determine whether the cache contains an active timer entry corresponding to the specific second address before issuing the second command, and to issue the second command to the memory device in response to the query occurring when the sum of the timestamp of the active timer entry and the timer value of the active timer entry is greater than or equal to the amount of time that has elapsed since the time counter began tracking the clock signal, wherein the active timer entry is generated before the query occurs; Comparison triggers (344, 544) are used to compare the timer values ​​(342, 542, 642, 678) with the values ​​of the time counters (341, 541); Update the logic circuit system (346), which is configured to invalidate the active timer entry corresponding to the specific first address or the active timer entry corresponding to the specific second address; and The same address detection logic circuit system is used to detect the status of rows in the cache (348, 748).

19. The device of claim 18, wherein the same address detection logic circuitry system monitors the state of a plurality of memory banks in the cache and the state of a plurality of rows in the cache.

20. The device according to any one of claims 18 to 19, wherein the timestamp is the time when the timer was created.

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