Decoding architecture for memory devices

Abstract

This application relates to decoding architectures for memory devices. Word line plates of a memory array can each include a sheet of conductive material including a first portion extending in a first direction within a plane and a plurality of fingers extending in a second direction within the plane. Two word line plates in the same plane can be activated via a shared electrode. Memory cells or a subset thereof coupled with the two word line plates sharing the electrode can represent a logical page for accessing memory cells. Memory cells can be accessed via a first voltage applied to a word line plate coupled with the memory cells and a second voltage applied to a pillar electrode coupled with the memory cells. Parallel or simultaneous access operations can be performed for two or more memory cells within a same page of memory cells.

Description

[0001] Cross-reference

[0002] This patent application is a national phase application of International Patent Application No. PCT / US2022 / 071592, filed April 7, 2022, entitled “Decoding Architecture for Memory Devices”, filed by Fantini et al., claiming priority to U.S. Patent Application No. 17 / 231,657, filed April 15, 2021, entitled “Decoding Architecture for Memory Devices”, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to decoding architectures for memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read (or sense) at least one stored state in the memory device. To store information, a component can write (or program) the state in the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-select memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Summary of the Invention

[0006] Describe a device. The device may include: a first word line board including a plurality of first word lines, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a plurality of first memory cells; a second word line board including a plurality of second word lines, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a plurality of second memory cells; and electrodes coupled to the first word line board and the second word line board, the electrodes being operable to simultaneously activate the first word lines of the plurality of first word lines and the second word lines of the plurality of second word lines to access the first memory cells of the plurality of first memory cells and the second memory cells of the plurality of second memory cells.

[0007] A method is described. The method may include: applying a first voltage to electrodes coupled to a first word line board and a second word line board, the first word line board including a plurality of first word lines each coupled to one or more corresponding memory cells of a plurality of first memory cells, and the second word line board including a plurality of second word lines each coupled to one or more corresponding memory cells of a plurality of second memory cells; accessing a first memory cell of the plurality of first memory cells at least in part based on the application of the first voltage to the first word line board via the electrodes; and accessing a second memory cell of the plurality of second memory cells at least in part based on the application of the first voltage to the second word line board via the electrodes.

[0008] Describe an apparatus. The apparatus may include: a first word line tile including a first word line board comprising a plurality of first word lines, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a plurality of first memory cells; a second word line tile addressable independently of the first word line tile and including a second word line board comprising a plurality of second word lines, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a plurality of second memory cells; and a pillar tile associated with the first word line tile and the second word line tile, the pillar tile including a pillar group, the pillar group including: a plurality of first pillars, each of the plurality of first pillars being coupled to a corresponding memory cell of the plurality of first memory cells; and a plurality of second pillars, each of the plurality of second pillars being coupled to a corresponding memory cell of the plurality of second memory cells.

[0009] A method is described. The method may include: applying a first voltage to a first word line board including a plurality of first word lines of a first word line chip using a first decoding circuit system, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a plurality of first memory cells; applying a second voltage to a second word line board including a plurality of second word lines of a second word line chip addressable independently of the first word line chip using a second decoding circuit system, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a plurality of second memory cells; and applying a third voltage to a first pillar of a pillar chip using a third decoding circuit system. The first pillar is coupled to a first memory cell among the plurality of first memory cells, wherein the first memory cell is operable to be accessed at least in part based on applying the first voltage to the first word board and applying the third voltage to the first pillar; and a second pillar of the pillar block is coupled to a second memory cell among the plurality of second memory cells, wherein the second memory cell is operable to be accessed at least in part based on applying the second voltage to the second word board and applying the fourth voltage to the second pillar using the third decoding circuitry.

[0010] A device is described. The device may include: a first word line board including a plurality of first word lines; a second word line board including a plurality of second word lines; electrodes coupled to the first word line board and the second word line board; and a controller operable to cause the device to: apply a first voltage to the electrodes; access a first memory cell coupled to a first word line of the plurality of first word lines based at least in part on the application of the first voltage to the first word line board via the electrodes; and access a second memory cell coupled to a second word line of the plurality of second word lines based at least in part on the application of the first voltage to the second word line board via the electrodes. Attached Figure Description

[0011] Figure 1 This describes an example of a system that supports a decoding architecture for memory devices, based on examples disclosed herein.

[0012] Figure 2 This describes instances of memory dies that support decoding architectures for memory devices, based on examples disclosed herein.

[0013] Figure 3 This describes aspects of an instance of a memory array that supports a decoding architecture for a memory device, based on examples disclosed herein.

[0014] Figure 4A and 4BThis describes aspects of an instance of a memory array that supports a decoding architecture for a memory device, based on examples disclosed herein.

[0015] Figure 5A , 5B And 5C describes aspects of an example of a memory array that supports a decoding architecture for a memory device, based on examples disclosed herein.

[0016] Figure 6 This describes an example of an array architecture that supports decoding architectures for memory devices, based on examples disclosed herein.

[0017] Figure 7 This describes an example of an array architecture that supports decoding architectures for memory devices, based on examples disclosed herein.

[0018] Figure 8 This describes an example of an array architecture that supports decoding architectures for memory devices, based on examples disclosed herein.

[0019] Figure 9 A block diagram of a memory device is shown, based on examples disclosed herein, that supports a decoding architecture for memory devices.

[0020] Figure 10 and 11 The flowchart illustrates one or more methods for supporting decoding architectures for memory devices, based on examples disclosed herein. Detailed Implementation

[0021] The word line boards of a memory array may each include multiple word lines in a "comb" structure (e.g., a structure resembling a tool having fingers and space between each pair of adjacent fingers). The word line board may, for example, include a sheet of conductive material comprising a first portion extending in a first direction within a plane and multiple fingers extending in a second direction within a plane. Each finger of the word line board may represent a word line as described herein. The word line board may be coupled to electrodes, and a word line decoder may be operable to apply a voltage to the word line board via the electrodes for accessing an associated memory cell. To reduce the footprint of the supporting circuitry of the memory device, two word line boards in the same plane may share electrodes for activating the word line board. The two word line boards sharing electrodes may be (or alternatively include) pages for accessing memory cells (e.g., logical pages for accessing memory cells). For example, a first page (e.g., an even-numbered page) may include two first word line plates extending from a first electrode (e.g., to the left and right), and a second page (e.g., an odd-numbered page) may include two second word line plates extending from a second electrode (e.g., to the left and right). In some cases, word line plates may be vertically stacked above or below one or more other word line plates, and groups of electrodes coupled to different word line plates at different levels or planes of the stack may be referred to as steps.

[0022] A memory cell can be accessed via a first voltage applied to a word line board coupled to the memory cell and a second voltage applied to a pillar coupled to the memory cell (e.g., a vertical electrode structure electrically isolated from the word line board). A pillar patch can be associated with multiple word line patches (e.g., representing one or two word line boards), wherein a pillar patch can represent a portion of a pillar within a memory array, which can be accessed using a set of complementary decoders, such as an X-direction pillar decoder for decoding lines extending in the Y direction and a Y-direction pillar decoder for decoding pillar lines extending in the X direction, wherein the X and Y directions can correspond to row lines and column lines respectively (or vice versa), which can be referred to as pillar row lines and pillar column lines, and can be coupled to a pillar selector and operable to selectively activate the pillar selector. A pillar patch can define (e.g., independently of word line patches) the total area (e.g., maximum area) of the pillars and associated memory cells that can be decoded using a first pillar decoder (e.g., in the X direction) and a second pillar decoder (e.g., in the Y direction). Associating a pillar block with multiple word line blocks (e.g., making the pillar block larger than the word line blocks and containing memory cells within the multiple word line blocks) can, for example, reduce the footprint of the pillar decoder by supporting a single pillar decoder for all pillars of the pillar block (e.g., compared to a single pillar decoder for each word line block).

[0023] The memory arrays described herein can support parallel or concurrent (e.g., simultaneous) access to two or more memory cells within the same page of a memory cell. For example, a first pillar coupled to a first memory cell associated with (e.g., coupled to) the left word line board (e.g., the first word line board) of the page can be activated, and the first word line board of the page can be activated. In parallel, a second pillar coupled to a second memory cell associated with (e.g., coupled to) the right word line board (e.g., the second word line board) of the page can be activated, and the second word line board of the page can be activated. Additionally or alternatively, multiple memory cells coupled to different word lines of the same word line board can be accessed simultaneously using the array architecture and other aspects taught herein. Thus, memory cells associated with the left word line board, the right word line board, or both can be accessed in parallel, which can improve access speed, data processing capability, or both. Additionally or alternatively, the decoding structures and configurations described herein can support reduced area requirements for decoding circuitry systems associated with accessing memory cells as described herein. This improves the ability to physically mount the decoder within the area occupied by the memory cell array (e.g., within one or more circuitry layers located between the array and the substrate or otherwise beneath the array, within the array's occupied area). Such benefits are merely exemplary, and additional benefits will be appreciated by those skilled in the art.

[0024] First, refer to Figures 1 to 3 Features of this disclosure are described in the context of the memory system, die, and array described herein. (See references...) Figures 4A to 8 The features of this disclosure are described in the context of the memory arrays and array architectures described herein. (See references...) Figures 10 to 11 The device diagrams and flowcharts relating to the decoding architecture of the memory device further illustrate and describe these and other features of this disclosure, and are referred to in connection with the device diagrams and flowcharts.

[0025] Figure 1 This document describes an example of a system 100 that supports a decoding architecture for memory devices, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0026] System 100 may include portions of an electronic device, such as a computing device, mobile computing device, wireless device, graphics processing device, vehicle, or other system. For example, system 100 may describe aspects of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or the like. Memory device 110 may be a component of a system operable to store data for use by one or more other components of system 100.

[0027] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or some other fixed or portable electronic device, and other examples. In some examples, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0028] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation scheme of the modulated signal, various pin configurations for transmitting the signal, various form factors of the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0029] Memory device 110 is operable to store data for components of host device 105. In some instances, memory device 110 may be used as a slave device of host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0030] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0031] Processor 125 is operable to provide control or other functionality to at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other instances. In some instances, external memory controller 120 may be implemented by or be part of processor 125.

[0032] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0033] Memory device 110 may include a device memory controller 155 supporting a desired or specified capacity for data storage and one or more memory dies 160 (e.g., memory chips). Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more dies, one or more segments), wherein each memory cell is operable to store at least one data bit. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory, a multi-die package, a multi-chip memory, or a multi-chip package.

[0034] The memory die 160 may be an instance of a two-dimensional (2D) memory cell array or an instance of a three-dimensional (3D) memory cell array. The 2D memory die 160 may contain a single memory array 170. The 3D memory die 160 may contain two or more memory arrays 170 that may be stacked on top of each other or positioned adjacent to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in the 3D memory die 160 may be referred to as layers, stacks, layers, or dies. The 3D memory die 160 may contain any number of stacked memory arrays 170 (e.g., two highs, three highs, four highs, five highs, six highs, seven highs, eight highs).

[0035] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions enabling the memory device 110 to perform various operations, and is operable to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 is operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0036] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, the local memory controller 165 is operable to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with another local memory controller 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0037] External memory controller 120 is operable to enable the communication of one or more of the following between a component of system 100 or host device 105 (e.g., processor 125) and memory device 110: information, data, or commands. External memory controller 120 may translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, the external memory controller 120, or other components of system 100 or host device 105, or its functionality as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, system 100, or other components of host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120, or its functionality as described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0038] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 are operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path operable to carry a signal. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins are operable to act as part of a channel.

[0039] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be conveyed via channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0040] The memory arrays described herein can support parallel or simultaneous access to two or more memory cells within the same page of a memory cell. For example, a first pillar coupled to a first memory cell associated with (e.g., coupled to) the left word line board (e.g., a first word line board) of the page can be activated, and the first word line board of the page can be activated. In parallel, a second pillar coupled to a second memory cell associated with (e.g., coupled to) the right word line board (e.g., a second word line board) of the page can be activated, and the second word line board of the page can be activated. Thus, memory cells associated with the left and right word line boards respectively can be accessed in parallel, which can improve access speed, data processing capability, or both. Additionally or alternatively, the decoding structures and configurations described herein can support reduced area requirements for decoding circuitry associated with accessing memory cells as described herein, which can improve the ability to physically mount the decoder within the area occupied by the memory cell array (e.g., within one or more circuitry layers located between the array and the substrate or otherwise below the array, within the area occupied by the array).

[0041] Figure 2 This document describes an example of a memory die 200 that supports a decoding architecture for memory devices, based on the examples disclosed herein. The memory die 200 may be used as a reference. Figure 1 Examples of memory die 160 described. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each programmable to store different logic states (e.g., a set of two or more programmable possible states). For example, memory cell 205 may be operable to store one information bit at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., multilevel memory cell 205) may be operable to store more than one information bit at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, such as referenced in [reference]. Figure 1 The memory array 170 is described.

[0042] Figure 2 Various characteristics related to the electrical operation of the memory array can be described, but the physical location and configuration of the components may deviate from the description. Figure 2 The description in the text. For example, by Figure 2 The described features may indicate that the memory cell 205 is located at the intersection of corresponding access lines (e.g., row line 210 and column line 215), may indicate the electrical function of the memory cell and other array components, or both, but in some cases the memory array may have a relative function to the array. Figure 2 The physical architecture or structure described is different from the entity architecture or structure (e.g., as referenced below). Figures 3 to 8describe).

[0043] Memory cell 205 may use configurable materials (which may be referred to as memory elements, memory storage elements, material elements, material memory elements, material portions, or polarized write material portions, etc.) to store logical states. The configurable materials of memory cell 205 may refer to chalcogenide-based memory components, as referenced in [reference needed]. Figure 3 To describe in more detail. For example, chalcogenide storage elements can be used in phase-change memory (PCM) cells, limit memory cells, or selectable memory cells.

[0044] Memory die 200 may include access lines (e.g., row lines 210 and column lines 215). Access lines may be formed of one or more conductive materials. In some instances, row lines 210 may be referred to as word lines. In some instances, column lines 215 may be referred to as digital lines or bit lines. In some cases, additional types of access lines may be present, as described elsewhere herein. Without loss of understanding or operability, references to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, are interchangeable. Memory cell 205 may be located, for example, at the intersection of row lines 210 (e.g., fingers of a word line board) and column lines 215 (e.g., pillars or other vertical electrode structures).

[0045] In some cases, one or more column lines 215 (e.g., column line CL_i) may extend perpendicularly to the substrate, and one or more row lines 210 (e.g., row line RL_i) may be on a different layer than those described (e.g., each row line 210 may be a word line finger of a word line board stacked vertically). In such cases, memory cells 205 may be formed at the intersection of column line CL_i and row line RL_i (e.g., between the pillar and the word line finger of the stacked word line board). One or more other memory cells 205 may be coupled to one or more other stacked word line boards (…). Figure 2 One or more other line 210 (not shown in the drawing) Figure 2 (Not shown in the image) and column line CL_i, as well as one or more other row lines 210 (not shown in the image) Figure 2 (Not shown in the text) between one or more other column lines 215 (e.g., pillars, not depicted).

[0046] Read and write operations can be performed on memory cell 205 by activating or selecting access lines (e.g., one or more of row lines 210 or column lines 215). A single memory cell 205 can be accessed at its intersection by applying a bias voltage to row lines 210 and column lines 215 (e.g., applying a voltage to row lines 210 or column lines 215). The intersection of row lines 210 and column lines 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205. Access lines can be conductive lines coupled to memory cell 205 and can be used to perform access operations on memory cell 205.

[0047] The memory cell 205 can be controlled by either row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 245 and activate row line 210 based on the received row addresses. Column decoder 225 receives column addresses from local memory controller 245 and can activate column line 215 based on the received column addresses.

[0048] Sensing component 230 is operable to detect the state of memory cell 205 (e.g., material state, resistance, threshold state) and determine the logic state of memory cell 205 based on the stored state. Sensing component 230 may include one or more sensing amplifiers to amplify or otherwise convert the signal generated by accessing memory cell 205. Sensing component 230 may compare the signal detected from memory cell 205 with reference 235 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 230 (e.g., to input / output 240) and may indicate the detected logic state to another component of the memory device including memory die 200.

[0049] The local memory controller 245 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 230). The local memory controller 245 may be used as a reference. Figure 1 Examples of local memory controller 165 described herein. In some instances, one or more of row decoder 220, column decoder 225, and sensing components 230 may co-locate with local memory controller 245. Local memory controller 245 is operable to receive one or more commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transmit data from memory die 200 to host device 105 based on the performance of one or more operations. Local memory controller 245 may generate row signals and column address signals to activate target row line 210 and target column line 215. Local memory controller 245 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for various operations discussed when operating memory die 200.

[0050] The local memory controller 245 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, as well as other operations. In some instances, access operations may be performed by the local memory controller 245 in response to various access commands (e.g., from the host device 105) or otherwise coordinated. The local memory controller 245 is operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing memory cells 205.

[0051] Local memory controller 245 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of memory die 200. During a write operation, memory cells 205 of memory die 200 can be programmed to store a desired logical state. Local memory controller 245 can identify the target memory cell 205 to which a write operation will be performed. Local memory controller 245 can identify target row lines 210 and target column lines 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). Local memory controller 245 can activate the target row lines 210 and target column lines 215 (e.g., apply a voltage to row lines 210 or column lines 215) to access the target memory cell 205. Local memory controller 245 can apply a specific signal (e.g., a write pulse) to column line 215 during a write operation to store a specific state in the memory element of memory cell 205. The pulse used as part of the write operation may include one or more voltage levels over a duration.

[0052] Local memory controller 245 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 205 of memory die 200. During a read operation, a logical state stored in the memory cells 205 of memory die 200 can be determined. Local memory controller 245 can identify a target memory cell 205 to which a read operation will be performed. Local memory controller 245 can identify target row lines 210 and target column lines 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). Local memory controller 245 can activate the target row lines 210 and target column lines 215 (e.g., apply a voltage to the row lines 210 or column lines 215) to access the target memory cell 205. Sensing component 230 can detect signals received from memory cell 205 based on pulses applied to row lines 210, pulses applied to column lines, and / or the resistance or threshold characteristics of memory cell 205. Sensing component 230 can amplify the signals. The local memory controller 245 can activate the sensing component 230 (e.g., a latching sensing component) and thereby compare the signal received from the memory cell 205 with the reference 235. Based on the comparison, the sensing component 230 can determine the logic state stored in the memory cell 205. The pulse used for the read operation may include one or more voltage levels over a duration.

[0053] As described herein, word line boards may each include multiple word lines (e.g., column lines 215 or row lines 210) in a “comb” structure (e.g., a structure that may resemble a tool having fingers and space between each pair of adjacent fingers). The word line boards may be coupled to a word line decoder (e.g., row decoder 220) via electrodes operable to apply voltage to the word line boards for accessing associated memory cells. To reduce the footprint of the memory device's supporting circuitry, two word line boards in the same plane may share electrodes for activating the word line boards. The two word line boards sharing electrodes may be (or alternatively include) pages for accessing memory cells 205 (e.g., logical pages for accessing memory cells).

[0054] Memory cell 205 can be accessed via a first voltage applied to a word line board coupled to memory cell 205 and a second voltage applied to a pillar coupled to memory cell 205 (e.g., a vertical electrode structure electrically isolated from the word line board). In some cases, as referenced... Figure 2The described column line 215 or row line 210 may correspond to a pillar as described herein. A pillar block may be associated with multiple word line blocks (e.g., representing one or two word line boards), wherein a pillar block may represent a portion of a pillar within a memory array, which may be accessed using a set of complementary decoders, such as a set of X-direction pillar decoders and a set of Y-direction pillar decoders, wherein the X and Y directions may respectively correspond to access lines coupled to pillar selectors, and may be described in more detail elsewhere herein.

[0055] This configuration can support parallel or simultaneous access operations of two or more memory cells 205 within the same page of memory cell 205. For example, a first pillar coupled to a first memory cell 205 associated with (e.g., coupled to) the left word line board (e.g., the first word line board) of the page can be activated, and the first word line board of the page can be activated. In parallel, a second pillar coupled to a second memory cell 205 associated with (e.g., coupled to) the right word line board (e.g., the second word line board) of the page can be activated, and the second word line board of the page can be activated. Therefore, memory cells 205 associated with the left and right word line boards respectively can be accessed in parallel, which can improve access speed, data processing capability, or both.

[0056] Figure 3 This describes an example of a memory array 300 that supports a decoding architecture for a memory device, as disclosed herein. The memory array 300 may be used as a reference. Figure 1 and 2 An example of a described memory array. Memory array 300 may include multiple layers of memory cells 310 stacked vertically relative to a substrate to create a memory cell stack 335, which may be as shown in the reference. Figure 1 and 2 Examples of memory cells and memory cell stacks are described. Therefore, in some instances, memory array 300 may be referred to as a 3D memory array. Memory array 300 may include word line boards 315 and pillars 325, which may be as described in the reference. Figure 2 Examples of the described word lines and bit lines (e.g., row line 210 and column line 215).

[0057] Word line board 315 may include multiple word lines in a “comb” structure (e.g., a structure resembling a tool having fingers and space between each pair of adjacent fingers). Word line board 315 may, for example, include a sheet of conductive material comprising a first portion extending in a first direction within a plane and multiple fingers extending in a second direction within a plane. Each finger of word line board 315 may represent a word line as described herein. The number of fingers (e.g., word lines) and the length of the fingers may define the size of word line board 315, wherein the size of word line board 315 may be based on the capacitance of word line board 315 relative to one or more storage class memories (SCMs). Various exemplary details of the comb structure, fingers, and other aspects of word line board 315 may be further described elsewhere herein.

[0058] Each pillar 325 can be selectively coupled to a corresponding pillar row 320 via a pillar selector 345 (e.g., a transistor or switching component). For example, a pillar row 350 for a pillar 325 can be coupled to a pillar selector 345 for a pillar 325, and the pillar selector 345 can be selectively activated or deactivated based on the voltage of the pillar row 350 (e.g., the voltage difference between the voltage of the pillar row 350 and the voltage of the pillar row 320). When activated (e.g., on, off, conduction), the pillar selector 345 for a pillar 325 can couple the pillar 325 to the pillar row 320 for a pillar 325, and thus the voltage of the pillar 325 can become equal to or approximately equal to the voltage of the pillar row 320. In some cases, the pillar selector 345 may be a transistor (e.g., a thin-film transistor (TFT) or other type of transistor), and the gate of the transistor may be coupled to the pillar column line 350, the source of the transistor may be coupled to the pillar row line 320, and the drain of the transistor may be coupled to the pillar 325. Therefore, in some cases, the pillar column line 350 may alternatively be referred to as the pillar gate line, and the pillar row line 320 may alternatively be referred to as the pillar source line. The pillar decoder as described herein is operable to selectively activate (e.g., apply a selection voltage to) or deactivate (e.g., apply a deselect voltage to) the pillar column line 350 in the set of pillar column lines 350 associated with the pillar decoder, or selectively activate (e.g., apply a selection voltage to) or deactivate (e.g., apply a deselect voltage to) the pillar row line 320 in the set of pillar row lines 320 associated with the pillar decoder.

[0059] Pillar column lines 350 and pillar row lines 320 may span and are thus coupled to pillar selectors 345 corresponding to rows or columns of pillars 325 within a single word line plate, a single word line block, multiple word line plates, or multiple word line blocks, as described herein. Those skilled in the art will appreciate that what direction (e.g., X or Y direction) is considered as a row and column can be arbitrary. In some cases, pillars 325 may correspond (e.g., for one or more functionalities) to, as referenced... Figure 2 Column line 215 is described. Similarly, the pillar decoder, pillar column line 350, pillar row line 320, and pillar selector 345 may correspond (e.g., for one or more functionalities) to, as referenced Figure 2 The described line decoder 225.

[0060] In some cases, a pillar 325 coupled to the same pillar row line 350 can be viewed as a comb-like structure having vertical comb fingers (e.g., pillar 325) selectable via the respective pillar row line 320 (e.g., individually relative to other pillars 325 coupled to the same pillar row line 350), and each memory cell 310 can be located at the intersection of the horizontal fingers and vertical fingers (e.g., pillar 325, which can be viewed as a digital line or a portion of a digital line) of the word line plate 315 (e.g., a word line), but the teachings herein are not limited to such conceptualizations.

[0061] The memory array 300 may also include an insulating layer 305, a trench insulating layer 306, a via 330, and a substrate 340. Although Figure 3 The examples illustrate that the pillar row line 320 and pillar column line 350 are above the pillar 325, but in some embodiments, the pillar row line 320 and pillar column line 350 may alternatively be below the pillar 325 (e.g., between the pillar 325 and the substrate 340).

[0062] The insulating layer 305 may be electrically insulating and may provide insulation between alternating word lines 315. As described herein, various logic states may be stored via the resistance of the programmable memory cell 310. In some cases, the programmable resistor comprises allowing current to flow through the memory cell 310, heating the memory cell 310, melting the material of the memory cell 310 (e.g., all or part of it), applying a voltage of a specific polarity to the memory cell, or any combination thereof. The insulating layer 305 may consist of multiple sublayers, thereby creating one or more interfaces between the memory cells 310.

[0063] Memory array 300 may comprise an array of memory cell stacks 335, and each memory cell stack 335 may comprise a plurality of memory cells 310. Memory array 300 may be fabricated by stacking conductive layers (e.g., word line boards 315), wherein each conductive layer may be separated from adjacent conductive layers by one or more electrically insulating layers 305. The electrically insulating layers may comprise oxide or nitride materials, such as silicon oxide, silicon nitride, or other electrically insulating materials. In some cases, the electrically insulating layer 305 may comprise one or more sublayers. The layers of memory array 300 may be formed on a substrate 340, such as a silicon wafer, or any other semiconductor or oxide substrate. Through-passages 330 (e.g., openings) may be formed by removing material from the layer stack using etching or mechanical techniques, or both.

[0064] In some cases, a memory cell 310 (e.g., a memory element) can be formed by removing material from a conductive layer to create a recess adjacent to the passage 330, and forming a variable-resistivity material in the recess. For example, material can be removed from a conductive layer by etching, and a variable-resistivity material can be deposited in the resulting recess to form a memory cell 310 (e.g., a memory element, which may be a storage element). Each passage 330 can be filled with an electrically conductive material and a dielectric material to create a pillar 325, which can be coupled (e.g., selectively, for example, using a pillar selector 345) to a pillar row line 320. In other words, memory cells 310 in the memory cell stack 335 can share a common electrode (e.g., pillar 325). Thus, each memory cell 310 can be coupled to a word line board 315 and a pillar 325. In some cases, each pillar 325 (e.g., within each passage 330) can be coupled to a first word line finger via a corresponding first memory cell and to a second word line finger via a corresponding second memory cell, as referenced. Figure 4A and 4B Further detailed description. The trench insulation layer 306 may be electrically insulating and may provide insulation between alternating (e.g., interdigitated) word line fingers of each word plate 315 (e.g., word line fingers on each side of the passage 330 in the direction of the strut column line 350, wherein word line fingers on opposite sides of the trench insulation layer 306 may extend parallel but in opposite directions away from the ridges of their respective word plates, for example, wherein a first word line finger on the side immediately adjacent to the trench insulation layer 306 extends to the right and a second word line finger on the opposite side immediately adjacent to the trench insulation layer 306 extends to the left).

[0065] In some instances, the material of the memory cell 310 (e.g., the memory element) may comprise a chalcogenide material or other alloy, comprising selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some instances, a chalcogenide material primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some instances, the SAG alloy may also comprise silicon (Si), and this chalcogenide material may be referred to as a SiSAG alloy. In some instances, the SAG alloy may comprise silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, or combinations thereof, respectively. In some instances, the chalcogenide glass may comprise additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F). Other chalcogenide alloys not explicitly listed herein may also be used.

[0066] In some instances, such as for a limited memory cell or a selectable memory cell 310, some or all of the set of logical states supported by the memory cell 310 may be associated with the same state, such as the amorphous state of a chalcogenide material, which is the opposite of the crystalline state of the chalcogenide material (e.g., the material is operable to store different or multiple logical states while remaining in the amorphous state). In some such instances, the memory cell 310 may be an instance of a selectable memory cell 310. In such instances, the material used in the memory cell 310 may be based on an alloy (e.g., the alloys listed above) and may be operable to undergo state changes during normal operation of the memory cell (e.g., due to ion migration or separation within the memory cell 310). For example, the selectable memory cell 310 may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logical state (e.g., a reset state) and the low threshold voltage state may correspond to a second logical state (e.g., a set state). In some instances, memory cell 310 may alternately switch between amorphous and crystalline states during operation, wherein the amorphous and crystalline states correspond to different resistances or threshold voltages and thus to different logic states, and in some cases, this operation may be referred to as a phase-change operation.

[0067] In some cases, during the programming (writing) operation of the self-selection memory cell 310, the polarity of one or more pulses used for the write operation can affect (determine, set, program) specific behavior or characteristics of the material of the memory cell 310, such as the threshold voltage of the material. The difference in threshold voltage of the material of the memory cell 310 depending on the logic state stored by the material of the memory cell 310 (e.g., the difference between the threshold voltage when the material stores a logic state '0' and the threshold voltage when it stores a logic state '1') can correspond to the read window of the memory cell 310.

[0068] Various techniques can be used to form materials or components on substrate 340. These may include, for example, chemical vapor deposition (CVD), metal-organic vapor deposition (MOCVD), physical vapor deposition (PVD), sputtering deposition, atomic layer deposition (ALD), or molecular beam epitaxy (MBE), as well as other thin film growth techniques. Various techniques may be used to remove materials, including, for example, chemical etching (also known as “wet etching”), plasma etching (also known as “dry etching”), or chemical mechanical planarization.

[0069] As described herein, regions of the discrete memory cell 310 (e.g., insulating layer 305, trench insulating layer 306, or both) may contain one or more interfaces. In some instances, the interfaces of insulating layer 305 separate memory cells 310 stacked in a vertical direction. In other words, memory cells 310 may be stacked on top of each other and separated from each other by interfaces. In some instances, the interfaces of trench insulating layer 306 separate word line fingers from each other in a horizontal direction.

[0070] The memory cell 310 described herein may contain (but is not limited to) a phase change material. Other types of memory cells 310 may contain, for example, resistive memory or resistive RAM. In some cases, resistive RAM may use a metal oxide material, and the resistance of the metal oxide material may be changed by controlling the ionic state of atoms in the material or by controlling the number or location of atomic vacancies (e.g., missing atoms) in the material.

[0071] Figure 4A and 4B Examples of memory arrays 400-a and 400-b supporting decoding architectures for memory devices, as disclosed herein, are provided. For example, Figure 4A and 4B Various views illustrating example 3D memory arrays 400-a and 400-b are provided, which may be examples of 3D memory arrays according to the examples disclosed herein. A plurality of openings 460 may be formed through alternating planes of a conductive material 445 (e.g., a word line plane or word line board), a dielectric material 418, and (e.g.,) a second dielectric material in a trench 450. As shown, the diameters of the plurality of openings 460 may be approximately the same width as the trench 450. In some embodiments, the diameters of the plurality of openings 460 may be greater than the width of the trench 450.

[0072] Each of the multiple openings 460 can be approximately concentric with a different corresponding conductive contact. For example... Figure 4A and 4BAs shown, a pillar 480 (e.g., a circular pillar 480) can be formed in a geometric pattern within each corresponding opening 460, for example, formed above and coupled to a corresponding conductive contact (e.g., which may be a pillar selector 345 or coupled thereto). In some instances, the opening 460 (e.g., and the corresponding pillar 480) can be square or another shape. In some cases, multiple openings 460 can have an alternating (e.g., hexagonal) arrangement of conductive contacts associated with the pillar 480. For example, a corresponding conductive contact may be surrounded by six other conductive contacts.

[0073] An interlaced pattern can refer to any pattern in which the position of an object in the first row (e.g., a contact, opening 460, or pillar 480) is offset in a given direction from the position of an object in a second row adjacent to the first row (e.g., a contact, opening 460, or pillar 480). For example, an interlaced pattern can have objects (e.g., contacts, openings 460, or pillars 480) that are adjacent to each other in the x-direction (e.g., a row or horizontal direction) but not in the y-direction (e.g., a column or vertical direction). For example, as... Figure 4A and 4B The text describes how conductive contacts can be adjacent to each other and aligned in a straight line in the x-direction. However, conductive contacts may not be adjacent to each other in the y-direction and may, for example, alternate (e.g., skip) rows in the y-direction. Although Figure 4A and 4B Examples of this disclosure show generally uniform spacing between conductive contacts throughout the substrate, but are not limited to this. For instance, the spacing between conductive contacts may vary throughout the substrate.

[0074] Figure 4B The 3D memory array may comprise a plurality of memory element materials 465, each comprising a chalcogenide material or other memory element positioned between at least one word line board, at least one pillar 480, and at least one dielectric material 418. In some instances (e.g., depending on decoding optimization), each pillar 480 may be coupled to a corresponding selector (e.g., a switching element, such as a transistor) positioned at the top, bottom, or both of the 3D memory array 400 (e.g., below or above the plurality of word line boards).

[0075] Figure 5A , 5B The 5C description refers to instances of memory arrays 500-a, 500-b, and 500-c that support decoding architectures for memory devices, as disclosed herein. For example, Figure 5A , 5B Various views of examples 3D memory arrays 500-a, 500-b, and 500-c may be provided, illustrating examples of 3D memory arrays as disclosed herein. Memory arrays 500-a, 500-b, and 500-c may include and reference... Figure 4A and 4B The described memory array 400 has similar features. Specific separation trenches 450', filled with insulating or dielectric materials, can be formed between two sub-arrays (e.g., a first sub-array 500-a1 and a second sub-array 500-a2) such that the first sub-array 500-a1 and the second sub-array 500-a2 are electrically isolated from each other. In some instances, the memory array 500-a may comprise a plurality of vertically stacked word lines separated from each other by respective dielectric layers (see reference). Figure 5C (Side view of the memory array shown in the image).

[0076] Word lines can be formed from conductive material 445 of memory arrays 500-a, 500-b, and 500-c, each word line board containing multiple word lines. In the first subarray 500-a1, a first set of word lines associated with the first word line board can be isolated from a second set of word lines associated with the second word line board using a dielectric material extending in a serpentine shape (e.g., the shape of trench 450). In the second subarray 500-a2, a third set of word lines associated with the third word line board can be isolated from a fourth set of word lines associated with the fourth word line board using a dielectric material extending in a serpentine shape (e.g., the shape of trench 450). The first and second word line sets can be isolated from the third and fourth word line sets via separating trench 450'. Figures 5A to 5C The diagram illustrates a separation trench 450' for illustrative purposes. The number of separation trenches 450' and subarrays 500-a1 and 500-a2 may be limited. Figures 5A to 5C The quantity is as described in the text. For example, multiple separation trenches 450' may be formed in the 3D memory array as needed (e.g., to isolate various subarrays of the 3D memory array).

[0077] By using separation trenches 450' (which may also be referred to as separation layers) filled with insulating or dielectric materials, the power consumption of 3D memory arrays can be reduced while conforming to SCM specifications. For example, compared to a 3D memory array in which multiple subarrays are coupled to each other, a 3D memory array with several separation layers can experience a corresponding decrease in the capacitance value of the memory array (e.g., of individual subarrays) and can further reduce power consumption without increasing the decoding burden.

[0078] like Figure 5AAs shown, in some instances, after forming trenches 450 in a serpentine shape in a 3D memory array 500-a, a portion of trench 450 can be selected as a separation trench 450', which can be used to divide the 3D memory array 500-a into a first subarray 500-a1 and a second subarray 500-a2. For example, the separation trench 450' can undergo another etching operation such that two subarrays on either side of a particular separation trench 450' can be separated, which can cut one or more word line board structures to create a separate word line board or word line board assembly on either side of the separation trench 450'. In some instances, during subsequent processing steps, the separation trench 450' can be filled with an insulating or dielectric material, for example, without any other material formed therein (e.g., memory element material or conductive material). In some instances, a portion from the serpentine trench 450 can be used as a separation trench 450' between different word line sets (e.g., every X word lines, where X is a certain number).

[0079] In another example, multiple subarrays may be formed in the same substrate, and a separation layer 450' may be deposited on one or both sides of each subarray along the horizontal direction of the serpentine trench 450, such that the multiple subarrays are electrically isolated from each other. In another example, after the 3D memory array is formed and based on one or more dimensions of the 3D memory array, a number of separation trenches 450' may be formed along a plane parallel to both the digital lines and word lines to cut the 3D memory array into multiple subarrays, wherein an etching operation may be performed on the memory array to form the separation trenches 450'.

[0080] The position of the separation trench 450' (or separation layer 450') can be adjusted according to the size of the 3D memory array, such as by... Figure 5B and 5C Explanation. For example, Figure 5B The cross-sectional area of ​​the memory array shown herein can be 120 μm × 120 μm. It should be understood that these and any other specific numerical values ​​provided herein are examples provided for clarity only and are not intended to limit the scope of the claims. In some instances, 3D memory arrays can be formed based on the spacing between instances of adjacent pillars.

[0081] In some instances, the insertion of the separation layer 450' can assist in a sufficiently low corresponding capacitance value, such that the word line can be biased by a driver that consumes the desired low energy (e.g., in some cases, the order of energy used to drive the word line can be calculated as (1 / 2CV)). 2 Furthermore, using struts to partition the 3D memory array allows for optimization of the under-array decoding circuitry (CuA), such as minimizing the number of strut decoders, sense amplifiers, or the like, while conforming to SCM specifications based on higher-level memory array segmentation (e.g., due to word line cuts at the insertion separation layer 450').

[0082] In some instances, depending on the decoding implementation, each pillar 480 may be coupled to a corresponding selector (e.g., a switching component or transistor) located at the top, bottom, or both of the 3D memory array (e.g., below or above multiple word line boards). Spatial terms including (but not limited to) "top," "bottom," "under," "above," "below," "below," "above," etc. (if used herein) are used for the convenience of describing the spatial relationship between one element(s) and another element(s). Such spatial terms cover different orientations of the device other than the specific orientation depicted in the figures and described herein. For example, if the structure depicted in the figures is inverted or flipped, then a portion previously described as below or beneath other elements will then be above or above those other elements.

[0083] Figure 6 This describes an example of an array architecture 600 supporting a decoding architecture for a memory device, as disclosed herein. Array architecture 600 may represent an array comprising multiple pillars 650, which may represent a reference... Figure 3 Examples of the pillars described in section 5. For example, each pillar 650 may extend through an alternating layer of dielectric or insulating material and a stack of word line board materials. Each pillar 650 may also be coupled to one or more memory cells (e.g., two memory cells) at each word line board layer. Figure 6 The illustrated view may represent a top or bottom view of the array, allowing the support column 650 to extend into and out of the page. The support column 650 may extend through the array structure 600 in rows and columns, for example, including... Figure 6 Unspecified locations (e.g., column and row pillars may largely fill each line segment 605). Although pillars 650 are shown arranged linearly, pillars 650 may additionally or alternatively be arranged in another geometric pattern (e.g., staggered), as referenced. Figures 4A to 5C describe.

[0084] The array architecture 600 may include multiple word line tiles 605, each representing (e.g.) a set of word lines separated from the word lines of other word line tiles 605 by steps 620 and 625 and slots 655. Each word line tile 605 may include two independently addressable word line boards that can face each other (e.g., as an interlocking comb structure, which may alternatively be referred to as a comb with interdigitated fingers, but such details may be omitted). Figure 6 The text is omitted for clarity and is relative to... Figure 6 Other details described herein are described in more detail elsewhere, and it can be separated by dielectric or insulating materials in a serpentine or other shape, as referenced. Figures 4A to 5CDescription. Additionally or alternatively, word line block 605 may represent the number or arrangement of memory cells accessible through a comb-like structure of the word line plate. The word line plate within word line block 605 may be positioned at alternating layers of material stacking, as referenced. Figure 3 The description allows the word line board of the array architecture 600 to be positioned above or below one or more other word line boards of the same word line block 605.

[0085] The size of word line block 605 (e.g., length and width, based on the number and length of the fingers of the associated word line board) may be based on the capacitance of word line block 605 or the word line board therein relative to one or more SCM specifications (e.g., may be sized to conform to SCM specifications).

[0086] Word line decoding circuitry (e.g., word line decoder 640 or 645) can be used to access or activate different word line boards (and therefore different word lines) at different stack levels and different locations within the array architecture 600. Word line decoder 640 or 645 can activate word lines of one or more word line boards, for example, via steps 620 or 625 (e.g., electrodes or a series of electrodes with different heights). Similarly, pillar decoding circuitry (e.g., pillar decoders 630 and 635) can be used to access or activate different pillars 650, which can activate or access bit lines and gate lines (e.g., pillar gate lines) associated with a particular pillar 650.

[0087] To reduce the footprint of the CuA and other peripheral or supporting circuitry of the array architecture 600, two word line boards of different word line slabs 605 may share a step 620 or 625. The two word line boards sharing electrodes within the step 620 or 625 may be (or alternatively comprise) pages 610 or 615 (e.g., logical pages for accessing memory cells) at the same level of the array architecture 600. For example, a first page 610 (e.g., an even-numbered page) may comprise two first word line boards extending away from the first step 620 (e.g., to the left and right), and a second page 615 (e.g., an odd-numbered page) may comprise two second word line boards extending away from the second step 625 (e.g., to the left and right). Thus, for example, the word lines or fingers of the right-extending word line board of the first page 610 may interlock with (but be separated from) the word lines or fingers of the left-extending word line board of the second page 615 via serpentine trenches.

[0088] In some instances, refer to Figure 6The first word line decoder 640 or the second word line decoder 645 for word line block 605 is operable to activate a selected word line plate in the vertically stacked set of word line plates within word line block 605. For example, the first word line decoder 640 is operable to activate a first selected word line plate within the first word line block 605 on the left side of the first step 620 (e.g., the left side of the step area that can signal the output of the first word line decoder 640) and (e.g., simultaneously) activate a second selected word line plate within the second word line block 605 on the right side of the first step 620 (e.g., the right side of the step area that can signal the output of the first word line decoder 640) at the same step as the first word line plate. For example, the first selected word line board in the first word line block 605 on the left side of the first step 620 and the second selected word line board in the second word line block 605 on the right side of the first step 620 can both be coupled to the same electrode in the first step 620, and thus the first word line decoder 640 can select two word line boards in two adjacent word line blocks and thus the corresponding page 610 by applying a selection voltage to the shared electrode in the first step 620 for the two word line boards. The second word line decoder 645 can similarly operate to (e.g.) activate the first selected word line board in the first word line block 605 on the left side of the second step 625 (e.g., the left side of the step area that can signal the output of the second word line decoder 645) by applying a selection voltage to an electrode in the second step 625 coupled to the two selected word line boards and thereby selecting the corresponding page 615 of the memory cell, and (e.g., simultaneously) activate the second selected word line board in the second word line block 605 on the right side of the second step 625 (e.g., the right side of the step area that can signal the output of the second word line decoder 645).

[0089] In some instances, for example, based on the ability to simultaneously access half of the memory cells associated with two different word line blocks 605 (e.g., via the respective first or second word line boards of the two word line blocks 605), page 610 or 615 may contain the same or substantially the same number of memory cells as contained within word line blocks 605. For example, compared to an architecture where word line boards within adjacent word line blocks 605 do not share electrodes (e.g., where a step is dedicated only to a single word line block 605, rather than a pair or other set of word line blocks 605), sharing the electrodes of step 620 or 625 between two word line boards can reduce the total number of step electrodes associated with array architecture 600 and the total number of word line decoders 640 and 645 (e.g., can halve the number).

[0090] Each first word line board can be selectively activated using a corresponding first word line decoder 640 (e.g., a first decoding circuit system), and each second word line board can be selectively activated using a corresponding second word line decoder 645. In some instances, to activate a first word line board (or a pair of first word line boards), the first word line decoder 640 may activate or apply a voltage to a corresponding electrode within the first step 620. Similarly, to activate a second word line board (or a pair of second word line boards), the second word line decoder 645 may selectively activate or apply a voltage to a corresponding electrode within the second step 625.

[0091] Similarly, to reduce the footprint of the CuA and other peripheral or supporting circuitry used in the array architecture, the strut patch 660 may be associated with a plurality of word line patches 605 (e.g., any number of word line patches 605, such as 15 or 16 word line patches 605). In some cases, for example, based on one or more connectivity and spacing constraints (e.g., to reduce a connectivity between the clustered array and the CuA), the strut patch 660 may contain or be associated with a non-integer number of word line patches 605 (e.g., based on the independence between word line patches 605 and strut patch 660). The strut patch 660 may represent a portion of the strut 650 of the array architecture 600, which can be accessed using a complementary set of decoders, such as a set of X-direction strut decoders (e.g., a first strut decoder 630 for decoding strut column lines) for decoding strut lines extending in the Y direction and a set of Y-direction strut decoders (e.g., a second strut decoder 635 for decoding strut row lines) for decoding strut lines extending in the X direction.

[0092] The strut block 660 can be defined (e.g., independent of the boundaries of the word line block 605) to use the struts 650 and associated memory cells decoded by the first strut decoder 630 (e.g., in the X direction) and the corresponding second strut decoder 635 (e.g., in the Y direction). The size of the strut block 660 (e.g., length and width, based on the lengths of the strut decoders 630 and 635 and the associated number of struts 650) can be based on the capacitance of the strut block 660 relative to one or more SCM specifications (e.g., it can be sized to conform to SCM specifications).

[0093] Pillars 650 within pillar block 660 can be selectively accessed using a first pillar decoder 630 and a second pillar decoder 635 (e.g., a pillar decoding circuitry). For example, the first pillar decoder 630 can be used to access or activate a pillar column line, and the second pillar decoder 635 can be used to selectively access or activate a pillar row line. A pillar column line can activate one or more switching components coupled to the pillar column line, which can couple to the activated pillar row line and thereby select or activate pillars 650 associated with the activated pillar column line and the activated pillar row line (e.g., because a switching component (e.g., pillar selector 345) can be activated based on the difference between the voltage of the corresponding pillar column line and the voltage of the corresponding pillar row line, in cases where the switching component system or includes transistors, the corresponding pillar row line can be coupled to the source or drain of the switching component). Voltage can be applied to pillar 650 via the pillar row line.

[0094] In some cases, such as if a multi-thin-film transistor decoder is positioned below each pillar 650 (e.g., for coupling pillar 650 and pillar rows to activate pillar 650, as pillar selector 345), then the first pillar decoder 630 and the second pillar decoder 635 may represent areas for accessing other decoders that can operate at a more global level (e.g., device level). In the case where a single thin-film transistor is positioned below each pillar 650, the first pillar decoder 630 and the second pillar decoder 635 may represent the decoding level of the pillars of the pillar patch 660.

[0095] Associating the strut block 660 with a plurality of word line blocks 605 (e.g., such that the strut block 660 is larger than the word line blocks 605 and contains memory cells within the plurality of word line blocks 605) can, for example, reduce the footprint of the strut decoder 630 by supporting a single strut decoder 630 for all struts 650 of the strut block 660 (e.g., relative to a single strut decoder 630 for each word line block 605).

[0096] Memory cells can be accessed (e.g., for read or write operations) by activating the corresponding pillar 650 and word line board. For example, a first voltage can be applied to the pillar column line and a second voltage can be applied to the pillar row line to activate or access the corresponding pillar 650 (e.g., at the intersection of the pillar column line and the pillar row line). Similarly, a third voltage can be applied to the word line board (e.g., to activate the word line board) to access the memory cell coupled to the activated pillar 650. For example, a memory cell can be coupled to the word line board and the pillar 650 and can be accessed based on the corresponding voltage applied to the word line board and the pillar 650.

[0097] In some cases, array architecture 600 can support parallel or simultaneous access to two or more memory cells within the same page 610 or 615 (e.g., two or more memory cells coupled to pillars 650 in the same column of pillars 650), which can improve access speed and / or data processing capability. In some cases, two or more memory cells associated with the same column of pillars 650 can be accessed simultaneously, provided that memory cells on opposite sides of the same word line finger are not accessed simultaneously. For example, within pillar patch 660, a pillar column line can be activated, and every other pillar row line (or some other subset of pillar rows where no two active pillar rows are adjacent) can be activated simultaneously, thereby activating every other pillar 650 within a column of pillars 650 (or some other subset of pillars 650 within a column where no two active pillars are adjacent). In some of these cases, one word line board from each word line block 605 can be activated at a time (e.g., for a given active pillar 650, the memory cell can be accessed based on the simultaneous activation of a word line board coupled to a memory cell in a plurality of vertically stacked word line boards coupled to the pillar 650). And in some cases, any number of word line boards within any number of even-numbered pages 610 or odd-numbered pages 615 can be activated simultaneously, thus supporting simultaneous access across any number of word line blocks 605 to two or more memory cells associated with the same column of the pillar 650.

[0098] Additionally or alternatively, in some cases, array architecture 600 may support partially parallel access operations for two or more memory cells within the same page 610 or 615 (e.g., two or more memory cells coupled to pillars 650 in the same row of pillars 650), which can improve access speed and / or data processing capabilities. For example, within pillar patch 660, a first pillar column line may be activated, and every other pillar row line (or a subset of pillar rows where no two pillar row lines are adjacent) may be activated simultaneously, thereby simultaneously activating every other pillar 650 in the first column of pillars 650 (or a subset of pillars 650 in the first column where no two activated pillars are adjacent). One or more word line boards may also be activated simultaneously to access memory cells coupled to activated pillars 650 in the first column. Subsequently, the activation of the first pillar column line may be deactivated, and a second pillar column line may be activated, possibly with one or more word line boards remaining active simultaneously. Therefore, by sequentially activating different pillar column lines, different memory cells coupled to pillars 650 in different columns of pillar 650 can be accessed while one or more word line boards remain active. In some cases, the same one or more pillar row lines may also remain active while one or more word line boards remain active, allowing partial parallel access to different memory cells coupled to different pillars 650 in different columns of the same one or more rows of pillar 650 (e.g., the same set of one or more word line boards remains active simultaneously, the same set of one or more pillar row lines remains active simultaneously, or both). Furthermore, in some cases, different pillar row lines may be activated when different pillar column lines are activated, allowing partial parallel access to different memory cells coupled to different pillars 650 in different rows and columns of pillar 650. In some cases, this partial parallel access may occur on two or more memory cells distributed across the left and right word line boards of a page 610 or page 615.

[0099] Figure 7 This describes an example of an array architecture 700 supporting a decoding architecture for a memory device, as disclosed herein. Array architecture 700 may represent various instances of array architecture 600. For example, array architecture 700 may include word line slabs 705, word line boards 710 and 715, ladders 720 and 725, word line decoders 740 and 745, and struts 750, which may represent instances elsewhere herein (including references). Figure 6 ) describes the instance of the corresponding component.

[0100] As described herein, a step 720 or 725 may comprise a plurality of electrodes 755, each of which may be coupled to a different step of a word line board 710 or 715. Thus, by activating one electrode 755 of a step 720 or 725, the word line board 710 or 715 may be activated at the step corresponding to the activated electrode 755. An exemplary first step 720 is shown. Figure 7 The diagram is viewed from a side angle, while Figure 7 Other diagrams are viewed from a top-down perspective. Furthermore, although an exemplary first step 720 is illustrated, it should be understood that a second step 725 may have the same structure, but its electrodes 755 may instead be coupled to the second word plate 715.

[0101] Referring to two adjacent word line tiles 705, a first step 720 between the two word line tiles 705 may include a first electrode 755-a, a second electrode 755-b, and a third electrode 755-c, wherein each electrode 755 may represent one or more electrodes coupled together. For example, the first electrode 755-a may include a horizontal portion coupled to a first layer of the word line board 710, and a vertical portion coupled to said horizontal portion (e.g., operable to activate said horizontal portion). Electrodes 755-b and 755-c may similarly include corresponding horizontal and vertical portions and be operable to activate corresponding layers of the word line board 710. The first electrode 755-a may be coupled to a first pair of word line boards 710 at a first layer of the array architecture 700 (e.g., on the left and right sides of the associated first step 720). Similarly, the second electrode 755-b may be coupled to the second pair of word line boards 710 at a second step of the array architecture 700 (e.g., above the first step), and the third electrode 755-c may be coupled to the third pair of word line boards 710 at a third step of the array architecture 700 (e.g., above the second step). It should be understood that the array architecture 700 may include any number of steps of word line boards 710 and 715 and corresponding steps of associated staircases 720 and 725 within the word line patch 705 without departing from the scope of this disclosure.

[0102] The vertical electrode 755 of the first step 720 can be coupled to and selectively activated or deactivated by the first word line decoder 740, and the vertical electrode 755 of the second step 725 can be coupled to and selectively activated or deactivated by the second word line decoder 745. In the illustrated example of the first step 720, the first word line decoder 740 can, for example, activate selected steps of the word line board 710 coupled to the corresponding electrode 755 of the first step 720. For example, the first word line decoder 740 can activate a portion of the first step 720 corresponding to electrode 755-a (e.g., by applying voltage to the vertical portion of electrode 755-a), which can activate the top word line board 710 (e.g., by applying voltage to the top word line board 710). Similar techniques can be used, for example, to activate other steps of the word line board 710 via other corresponding electrodes 755 or portions of the first step 720.

[0103] For reference Figure 6 Described, two word lines 710 or 715 at the same level may share a corresponding step 720 or 725 (e.g., a portion thereof, such as electrode 755), which can reduce the footprint of the CuA and other peripheral or support circuitry systems used in the array architecture 700. For example, two first word lines 710-a and 710-b may be coupled to and share the first step 720, and two second word lines 715-b and 715-c may be coupled to and share the second step 725. In such an example, the first word lines 710-a and 710-b may be located at the same level and may be coupled to the same portion of the first step 720 (e.g., the same electrode 755). Similarly, the second word lines 715-a and 715-b may be located at the same level and may be coupled to the same portion of the second step 725 (e.g., the same electrode 755). Other first character plates 710 (e.g., positioned above or below first character plates 710-a and 710-b) may be coupled to different corresponding portions of the first step 720 (e.g., electrodes 755). Similarly, other first character plates 715 (e.g., positioned above or below first character plates 715-b and 715-c) may be coupled to different corresponding portions of the second step 725 (e.g., electrodes 755).

[0104] Each first word line decoder 740 can be used to activate each first word line board 710, and each second word line decoder 745 can be used to activate each second word line board. For example, the first word line decoder 740 is operable to activate word line boards 710-a and 710-b via a shared portion of the first step 720 (e.g., electrode 755) (e.g., simultaneously). Similarly, the second word line decoder 745 is operable to activate word line boards 715-b and 715-c via a shared portion of the second step 725 (e.g., electrode 755) (e.g., simultaneously). In some instances, the first word line decoder 740 can activate or apply a voltage to a corresponding portion of the first step 720 (e.g., electrode 755) to activate word line board 710, and the second word line decoder 745 can activate or apply a voltage to a corresponding portion of the second step 725 (e.g., electrode 755) to activate word line board 715.

[0105] In some cases, word line decoders 740 and 745 may include semiconductor circuitry (e.g., silicon circuitry) that provides this voltage bias to the corresponding word line boards 710 or 715 (e.g., applying voltage to both word line boards via corresponding steps 720 or 725). In some cases, increasing the number of word line boards 710 and 715 biased by word line decoders 740 and 745 may increase the capacitance associated with such a structure and may reduce the amount of total area (e.g., transistor area) occupied by word line decoders 740 and 745.

[0106] For example, compared to an architecture that does not share stairs, sharing stairs 720 or 725 between two word line boards 710 or 715 can reduce the total number of stairs associated with the array architecture 700 and the total number of word line decoders 740 and 745 (e.g., halve the number). Two word line boards 710 or 715 sharing the same electrode 755 of the respective stairs 720 or 725 can represent pages for accessing memory cells. For example, a first page (e.g., an even-numbered page) may include first word line boards 710-a and 710-b coupled to and extending from the first stairs 720, and a second page (e.g., an odd-numbered page) may include second word line boards 715-b and 715-c coupled to and extending from the second stairs 725.

[0107] In some cases, array architecture 700 can support parallel or simultaneous access operations, partially parallel access operations, or any combination thereof to two or more memory cells within the same page. For example, in some cases, if the set of memory cells is not contained in memory cells on opposite sides of the same word line finger, a set of memory cells coupled to pillars (e.g., pillars coupled to the same pillar column line) within the same column of the same word line board (or a set of word line boards with shared steps 720 or 725) can be accessed. As another example, a set of memory cells coupled to pillars (e.g., pillars coupled to the same pillar row line) within the same row of the same word line board (or a set of word line boards with shared steps 720 or 725) can be accessed while keeping the word line board (or the set of word line boards with shared steps 720 or 725) active based on sequentially activating different pillar column lines (e.g., continuously deactivating and reactivating the word line board). Such technologies can improve access speed and / or data processing capabilities, as well as other benefits that can be understood by those skilled in the art.

[0108] Figure 8 This describes an example of an array architecture 800 that supports a decoding architecture for a memory device, as disclosed herein. Array architecture 800 may represent various instances of array architecture 600 or array architecture 700. For example, array architecture 800 may include pillars 805, a first word line board 810, a second word line board 815, a memory cell 820, pillar row lines 825, and pillar column lines 830, which may be represented elsewhere herein (including references). Figure 6 Examples of the corresponding components described. Array architecture 800 may represent a top view of a memory array and may illustrate the strut row lines 825 and strut column lines 830 above or below the array, as well as word line boards 810 and 815 at a level of the array. The struts 805 may be oriented to extend into or out of the page.

[0109] For reference Figure 6 The description indicates that a pillar patch can represent a portion of pillar 805 of an array architecture 800 that can be accessed using a set of decoders (e.g., pillar row decoders and pillar column decoders). Pillar 805 within the pillar patch can be accessed using pillar column decoders (e.g., a first pillar decoding circuitry) and pillar row decoders (e.g., a second pillar decoding circuitry). For example, pillar column decoders can access or activate pillar column lines 830 associated with the pillar patch, and pillar row decoders can access or activate pillar row lines 825 associated with the pillar patch. Pillar column line 830 can activate one or more switching components coupled to pillar column line 830, which can couple activated pillar row line 825 to a selected or activated pillar 805. Voltage can be applied to pillar row line 825 and applied to the pillar via pillar row line 825 (e.g., because of activating the switching components).

[0110] As described herein, the row line 825 and column line 830 may extend across multiple letter plates 810 or 815 in the corresponding horizontal or vertical direction. Alternatively, in some cases, the row line 825 or column line 830 may each extend across one letter plate 810, 815 (or alternatively, one letter piece) in the corresponding horizontal or vertical direction.

[0111] Memory cell 820 can be accessed (e.g., for read or write operations) by activating the corresponding pillar 805 and word line board 810 or 815. For example, a first voltage can be applied to pillar column line 830 and a second voltage can be applied to pillar row line 825 to activate or access a corresponding pillar 805 (e.g., at the intersection of pillar row line 825 and pillar column line 830). Similarly, a third voltage can be applied to word line board 810 or 815 (e.g., to activate word line board 810 or 815) to access memory cell 820 coupled to the activated pillar 805. For example, memory cell 820 can be coupled to word line board 810 or 815 and pillar 805 and can be accessed based on the corresponding voltage applied to word line board 810 or 815 and pillar 805.

[0112] As described herein, array architecture 800 can support parallel or simultaneous access operations of two or more memory cells 820 within the same page and associated with different word boards 810 or 815. Array architecture 800 can additionally or alternatively support parallel or partially parallel access operations of two or more memory cells 820 associated with the same word board 810 or 815 and associated with different pillars 805.

[0113] For example, array architecture 800 may support parallel access to memory cells 835-a, 835-b, and 835-c, as well as other instances. In this instance, a first word line board 810 and corresponding pillars 805 coupled to memory cells 835-a, 835-b, and 835-c may be activated, resulting in access to memory cells 835-a, 835-b, and 835-c. To activate the corresponding pillars 805 of memory cells 835-a, 835-b, and 835-c, pillar column lines 830-a and pillar row lines 825-a, 825-b, and 825-c may be activated. In some cases, array architecture 800 may restrict (e.g., exclude) activation of pillars 805 on adjacent pillar row lines 825. For example, a pillar 805 coupled to memory cell 835-a can be activated (e.g., via pillar row line 825-a), but pillar row lines 825 adjacent to or immediately adjacent to pillar row line 825-a (e.g., one or more pillar row lines 825-a and pillar row line 825-b) can be kept at an inactive or deactivated voltage to prevent activation of the pillar 805 coupled to the adjacent pillar row line 825. Limiting such activation prevents simultaneous access attempts to memory cells 820 on the same word line finger, which could result in insufficient current or voltage to complete the access operation. Thus, parallel programming can occur on every other pillar row line 825 (e.g., on even-numbered pillar row lines 825 or on odd-numbered pillar row lines 825), which can limit parallel programming at the page level. For example, a page containing two word line boards 810 or 815 can be further subdivided into pages of memory cells 820 (e.g., and pillar 805) associated with even-numbered pillar lines 825 (e.g., even-numbered pillar lines) and pages of memory cells 820 (e.g., and pillar 805) associated with odd-numbered pillar lines 825 (e.g., odd-numbered pillar lines).

[0114] Therefore, array architecture 800 can support at least four types of logical pages, including a first type of memory cells contained within one or more even-numbered pages (e.g., page 610) and coupled to pillars in even-numbered pillar columns; a second type of memory cells contained within one or more even-numbered pages and coupled to pillars in odd-numbered pillar columns; a third type of memory cells contained within one or more odd-numbered pages (e.g., page 615) and coupled to pillars in even-numbered pillar columns; and a fourth type of memory cells contained within one or more odd-numbered pages and coupled to pillars in odd-numbered pillar columns. Such pages can represent the largest unit of memory cell 820 that can be used for parallel programming using array architecture 800. In some cases, the size of these units for pages used for parallel reading or writing can be approximately equal to 128,000 bits (e.g., based on the size of word line board 810 or 815 and the number of associated pillar rows).

[0115] The array architecture 800 may support other operations that do not involve parallel or partially parallel access every other pillar row line 825 (e.g., even or odd pillar row lines 825). For example, the array architecture 800 may perform any parallel access that avoids simultaneously activating adjacent pillar row lines 825 facing the same finger of an active word line board 810 or 815. Such operations may involve activating pillars 805 associated with the same pillar column line 830 (e.g.) to avoid selecting additional memory cells 820. In some cases, different corresponding pillar column lines 830 may be sequentially activated while a single word line board 810 or 815 is activated (e.g., while word line board 810 or 815 remains biased and loaded) to perform sequential access operations (e.g., partially parallel access operations) on multiple memory cells 820 coupled to word line board 810 or 815. In some cases, the same set of one or more pillar row lines 825 can remain active, while word line board 810 or 815 remains active and sequentially activates different pillar column lines 830, such that the set of memory cells accessed in a partially parallel manner can all be within the set of one or more non-adjacent rows. In other cases, when word line board 810 or 815 remains active and sequentially activates different pillar column lines 830, different sets of one or more pillar row lines 825 can be activated simultaneously with the activation of different pillar column lines 830, such that one or more columns of memory cells accessed in a partially parallel manner can vary as different pillar column lines 830 are activated (e.g., when the first pillar column line 830 is activated, a first set of one or more non-adjacent pillar row lines 825-a, 825-b, 825-c can be activated, and when the second pillar column line 830 is activated, a second set of one or more different non-adjacent pillar row lines 825 can be activated, such that memory cells coupled to adjacent pillar row lines 825 can be accessed in a partially parallel manner).

[0116] Figure 9 A block diagram 900 illustrates a memory device 920 that supports a decoding architecture for a memory device, based on examples disclosed herein. The memory device 920 may be as described in the references... Figures 1 to 8 Examples of aspects of the described memory device. Memory device 920 or its various components may be examples of components for performing various aspects of a decoding architecture for a memory device as described herein. For example, memory device 920 may include word line voltage application component 925, memory cell access component 930, word line block access component 935, pillar block access component 940, pillar voltage application component 945, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0117] Word line voltage application component 925 may be configured or otherwise support means for applying a first voltage to electrodes coupled to a first word line board and a second word line board, the first word line board including a plurality of first word lines each coupled to one or more corresponding memory cells of a first memory cell set, and the second word line board including a plurality of second word lines each coupled to one or more corresponding memory cells of a second memory cell set. Memory cell access component 930 may be configured or otherwise support means for accessing first memory cells of the first memory cell set based on the application of a first voltage to the first word line board via electrodes. In some embodiments, memory cell access component 930 may be configured or otherwise support means for accessing second memory cells of the second memory cell set based on the application of a first voltage to the second word line board via electrodes.

[0118] In some instances, word line voltage application component 925 may be configured or otherwise support means for applying a second voltage to a second electrode coupled to a third word line board positioned below the first word line board, the third word line board including a plurality of third word lines each coupled to one or more corresponding memory cells of a set of third memory cells, wherein the third word line board is electrically isolated from the first word line board. In some instances, memory cell access component 930 may be configured or otherwise support means for accessing third memory cells of the set of third memory cells based on the application of a second voltage to the third word line board via the second electrode.

[0119] In some instances, the word line voltage application component 925 may be configured or otherwise support a component for applying a third voltage to a third electrode coupled to a fourth word line board that is positioned in the same plane as the first word line board and includes one or more corresponding memory cells, each coupled to a set of fourth memory cells, wherein the fourth word line board is electrically isolated from the first word line board. In some instances, the memory cell access component 930 may be configured or otherwise support a component for accessing fourth memory cells of the fourth memory cell set based on the application of a third voltage to the fourth word line board via electrodes. In some instances, logical pages for accessing the first and second memory cell sets include memory cells coupled to the first and second word line boards.

[0120] In some instances, the pillar voltage application component 945 may be configured or otherwise support a component for applying a fifth voltage to a member extending through a material stack including a first word line board and a second word line board, the first pillar being coupled to a first memory cell of the first memory cell set, wherein access to the first memory cell of the first memory cell set is based on the application of the fifth voltage to the first pillar. In some instances, the pillar voltage application component 945 may be configured or otherwise support a component for applying a sixth voltage to a member of a second pillar extending through a material stack, the second pillar being coupled to a second memory cell of the second memory cell set, wherein access to the second memory cell of the second memory cell set is based on the application of the sixth voltage to the second pillar.

[0121] In some instances, the first and second pillars are contained in different rows of pillars inserted through at least one other row of pillars, said rows of pillars being associated with the first and second word lines. In some instances, the capacitance of the first word line is based on the number of first word lines of the first word line and the length of each of the plurality of first word lines, and wherein the capacitance of the second word line is based on the number of second word lines of the second word line and the length of each of the plurality of second word lines.

[0122] Word line block access component 935 may be configured or otherwise support a component for applying a first voltage to a first word line board comprising a plurality of first word lines of a first word line block using a first decoding circuitry system, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a first memory cell set. In some instances, word line block access component 935 may be configured or otherwise support a component for applying a second voltage to a second word line board comprising a plurality of second word lines of a second word line block addressable independently of the first word line block, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a second memory cell set. Pillar block access component 940 may be configured or otherwise support a component for applying a third voltage to a first pillar of a pillar block using a third decoding circuitry system, the first pillar being coupled to a first memory cell of the first memory cell set, wherein the first memory cell is operable to access based on applying a first voltage to a first word line board and applying the third voltage to the first pillar. In some instances, the pillar block access component 940 may be configured or otherwise support a component for applying a fourth voltage to a second pillar of the pillar block using a third decoding circuitry system, the second pillar being coupled to a second memory cell of the second memory cell set, wherein the second memory cell is operable to access based on applying a second voltage to a second word board and the fourth voltage to the second pillar.

[0123] In some instances, the word line block access component 935 may be configured or otherwise support means for applying a first voltage to the first word line board via electrodes coupled to a first word line board and a third word line board comprising one or more respective memory cells, each coupled to a set of third memory cells. The electrodes are operable to simultaneously activate a first word line among the plurality of first word lines and a third word line among the plurality of third word lines. In some instances, a logical page for accessing the first set of memory cells and the third set of memory cells comprises memory cells coupled to the first word line board and the third word line board.

[0124] In some instances, the word line block access component 935 may be configured or otherwise support a component of a fourth word line board located below the first word line board and comprising a plurality of fourth word lines addressable independently of the first word line block, for applying a fifth voltage using a first decoding circuitry system to a fourth word line board located below the first word line board. Each of the plurality of fourth word lines is coupled to one or more corresponding memory cells of the set of fourth memory cells. In some instances, the first word line board and the second word line board are electrically isolated via a dielectric material positioned in a serpentine shape between the plurality of first word lines and the plurality of second word lines.

[0125] In some instances, the pillar block access assembly 940 may be configured or otherwise support a component for applying a sixth voltage to a first pillar row line to activate a first switching component coupled to the first pillar. In some instances, the pillar block access assembly 940 may be configured or otherwise support a component for applying a sixth voltage to a second pillar row line to activate a second switching component coupled to the second pillar. In some instances, the pillar block access assembly 940 may be configured or otherwise support a component for applying a third voltage to a first pillar row line coupled to the first switching component, wherein applying the third voltage to the first pillar is based on applying the third voltage to the first pillar row line. In some instances, the pillar block access assembly 940 may be configured or otherwise support a component for applying a fourth voltage to a second pillar row line coupled to the second switching component, wherein applying the fourth voltage to the second pillar is based on applying the fourth voltage to the second pillar row line.

[0126] In some instances, the first and second pillar lines comprise a pair of pillar lines interposed by at least one other pillar line. In some instances, the capacitance of the pillar sheet is based on the number of pillars in the pillar sheet and the length of each pillar in the pillar sheet.

[0127] Figure 10 The flowchart illustrates a method 1000 for supporting a decoding architecture for a memory device, based on examples disclosed herein. The operation of method 1000 can be implemented by a memory device or its components as described herein. For example, it can be implemented by... (refer to...) Figures 1 to 9 The described memory device performs the operation of method 1000. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described functions.

[0128] In 1005, the method may include applying a first voltage to electrodes coupled to a first word line board and a second word line board, the first word line board including a plurality of first word lines each coupled to one or more corresponding memory cells of a first set of memory cells, and the second word line board including a plurality of second word lines each coupled to one or more corresponding memory cells of a second set of memory cells. The operation of 1005 may be performed according to examples disclosed herein. In some examples, it may be performed by, as referenced... Figure 9 The described aspect of the word line voltage application component 925 performing the operation of 1005.

[0129] In 1010, the method may include accessing a first memory cell of the first set of memory cells based on applying a first voltage to a first word line board via electrodes. Operation of 1010 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 9 The described aspect of the memory cell access component 930 performing the operation of 1010.

[0130] In 1015, the method may include accessing second memory cells of the second memory cell set based on (e.g., simultaneously) applying a first voltage to a second word line board via electrodes. Operation 1015 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 9 The described aspect of the memory cell access component 930 performing the operation 1015.

[0131] In some instances, the device as described herein may perform one or more methods, such as method 1000. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a first voltage to electrodes coupled to a first word line board and a second word line board, the first word line board including a plurality of first word lines each coupled to one or more corresponding memory cells of a first set of memory cells, and the second word line board including a plurality of second word lines each coupled to one or more corresponding memory cells of a second set of memory cells; accessing a first memory cell of the first set of memory cells based on the first voltage applied to the first word line board via the electrodes; and accessing a second memory cell of the second set of memory cells based on the first voltage applied to the second word line board via the electrodes.

[0132] Some examples of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: applying a second voltage to a second electrode coupled to a third word board positioned below a first word board, the third word board including a plurality of third word lines each coupled to one or more corresponding memory cells of a set of third memory cells, wherein the third word board may be electrically isolated from the first word board; and accessing third memory cells of the set of third memory cells based on applying the second voltage to the third word board via the second electrode.

[0133] Some examples of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: applying a third voltage to a third electrode coupled to a fourth word line plate that is positioned in the same plane as the first word line plate and includes one or more corresponding memory cells, each coupled to a set of fourth memory cells, wherein the fourth word line plate may be electrically isolated from the first word line plate; and accessing the set of fourth memory cells based on applying the third voltage to the fourth word line plate via the electrode to a fourth memory cell.

[0134] In some instances of the method 1000 and apparatus described herein, a logical page for accessing the first set of memory cells and the second set of memory cells may include memory cells coupled to the first word board and the second word board.

[0135] Some examples of the method 1000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: applying a fifth voltage to a first pillar extending through a material stack including a first word line board and a second word line board, the first pillar being coupled to a first memory cell of the first memory cell set, wherein access to the first memory cell of the first memory cell set may be based on the application of the fifth voltage to the first pillar; and applying a sixth voltage to a second pillar extending through the material stack, the second pillar being coupled to a second memory cell of the second memory cell set, wherein access to the second memory cell of the second memory cell set may be based on the application of the sixth voltage to the second pillar.

[0136] In some instances of the method 1000 and apparatus described herein, the first pillar and the second pillar may be contained in different rows of pillars inserted through at least one other row of the pillars, the rows of which are associated with the first word plate and the second word plate.

[0137] In some examples of the method 1000 and apparatus described herein, the capacitance of the first word line board may be based on the number of first word lines of the first word line board and the length of each of the plurality of first word lines, and the capacitance of the second word line board may be based on the number of second word lines of the second word line board and the length of each of the plurality of second word lines.

[0138] Figure 11 The flowchart illustrates a method 1100 for supporting a decoding architecture for a memory device, based on examples disclosed herein. The operation of method 1100 can be implemented by a memory device or its components as described herein. For example, it can be implemented by... (refer to...) Figures 1 to 9The described memory device performs the operation of method 1100. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described functions.

[0139] In 1105, the method may include applying a first voltage to a first word line board comprising a plurality of first word lines of a first word line block, using a first decoding circuit system, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a set of first memory cells. The operation of 1105 may be performed according to examples disclosed herein. In some examples, it may be performed by reference to... Figure 9 The described aspect of the word line block access component 935 performing the operation of 1105.

[0140] In 1110, the method may include applying a second voltage to a second word line board comprising a plurality of second word lines of a second word line block addressable independently of the first word line block, using a second decoding circuit system. Each of the plurality of second word lines is coupled to one or more corresponding memory cells of a set of second memory cells. The operation of 1110 may be performed according to examples disclosed herein. In some examples, it may be performed by reference to... Figure 9 The described aspect of the word line block access component 935 performing the operation of 1110.

[0141] In 1115, the method may include applying a third voltage to a first pillar of a pillar block using a third decoding circuit system, the first pillar being coupled to a first memory cell of the first memory cell set, wherein the first memory cell is operable to access based on the application of a first voltage to a first word board and the application of the third voltage to the first pillar. The operation of 1115 may be performed according to examples disclosed herein. In some examples, it may be performed by, as referenced... Figure 9 The described aspect of the pillar block access component 940 performing the operation 1115.

[0142] In 1120, the method may include applying a fourth voltage to a second pillar of a pillar block using a third decoding circuit system, the second pillar being coupled to a second memory cell of the second memory cell set, wherein the second memory cell is operable to access based on the application of a second voltage to a second word board and the application of the fourth voltage to the second pillar. The operation of 1120 may be performed according to examples disclosed herein. In some examples, it may be performed by, as referenced... Figure 9 The described aspect of the pillar block access component 940 performing the operation of 1120.

[0143] In some instances, the device as described herein may perform one or more methods, such as method 1100. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a first voltage to a first word line board comprising a plurality of first word lines of a first word line block, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a set of first memory cells using a first decoding circuitry system; applying a second voltage to a second word line board comprising a plurality of second word lines of a second word line block addressable independently of the first word line block, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a set of second memory cells using a second decoding circuitry system. The third voltage is applied to a first pillar of the pillar block using a third decoding circuit system, the first pillar being coupled to a first memory cell of the first memory cell set, wherein the first memory cell is operable to access based on the application of the first voltage to the first word board and the application of the third voltage to the first pillar; and a fourth voltage is applied to a second pillar of the pillar block using the third decoding circuit system, the second pillar being coupled to a second memory cell of the second memory cell set, wherein the second memory cell is operable to access based on the application of the second voltage to the second word board and the application of the fourth voltage to the second pillar.

[0144] Some examples of the method 1100 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for applying a first voltage to the first word line board via electrodes coupled to the third word line board and the third word line board comprising one or more respective memory cells coupled to a set of third memory cells, the electrodes being operable to simultaneously activate the first word line of the plurality of first word lines and the third word line of the plurality of third word lines.

[0145] In some instances of the method 1100 and apparatus described herein, a logical page for accessing the first set of memory cells and the third set of memory cells may include memory cells coupled to the first word board and the third word board.

[0146] Some examples of the method 1100 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for applying a fifth voltage to a fourth word line board located below the first word line board and comprising a plurality of fourth word lines addressable independently of the first word line block, each of the plurality of fourth word lines being coupled to one or more corresponding memory cells of the set of fourth memory cells.

[0147] In some examples of the method 1100 and apparatus described herein, the first word line board and the second word line board can be electrically isolated via a dielectric material positioned in a serpentine shape between a plurality of first word lines and a plurality of second word lines.

[0148] Some examples of the method 1100 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: applying a sixth voltage to a first pillar row line to activate a first switching component coupled to the first pillar; applying the sixth voltage to a second pillar row line to activate a second switching component coupled to the second pillar; applying a third voltage to a first pillar row line coupled to the first switching component, wherein applying the third voltage to the first pillar may be based on applying the third voltage to the first pillar row line; and applying a fourth voltage to a second pillar row line coupled to the second switching component, wherein applying the fourth voltage to the second pillar may be based on applying the fourth voltage to the second pillar row line.

[0149] In some instances of the method 1100 and apparatus described herein, the first and second pillar lines comprise a pair of pillar lines inserted through at least one other pillar line.

[0150] In some examples of the method 1100 and apparatus described herein, the capacitance of the support plate may be based on the number of supports in the support plate and the length of each support in the support plate.

[0151] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods may be combined.

[0152] Describe a device. The device may include: a first word line board including a plurality of first word lines, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a set of first memory cells; a second word line board including a plurality of second word lines, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a set of second memory cells; and electrodes coupled to the first word line board and the second word line board, the electrodes being operable to simultaneously activate the first word lines of the plurality of first word lines and the second word lines of the plurality of second word lines to access the first memory cells of the first memory cell set and the second memory cells of the second memory cell set.

[0153] Some examples of the device may further include: a third character line board positioned below the first character line board and including a plurality of third character lines; a second electrode coupled to the third character line board and operable to activate a third character line among the plurality of third character lines; and a dielectric material inserted between the first character line board and the third character line board, the dielectric material electrically isolating the first character line board from the third character line board.

[0154] Some examples of the device may further include: a fourth word line board comprising a plurality of fourth word lines and positioned in the same plane as the first word line board, each of the plurality of fourth word lines being coupled to one or more corresponding memory cells of the set of fourth memory cells; a dielectric material positioned between the plurality of first word lines and the plurality of fourth word lines, wherein a first portion of the dielectric material extends in the same plane along a first direction, and wherein a second portion of the dielectric material extends in the same plane along a second direction; and a third electrode coupled to the fourth word line board and operable independently of the electrode to activate a fourth word line among the plurality of fourth word lines to access a fourth memory cell of the set of fourth memory cells.

[0155] In some instances of the device, the logical pages for accessing the first set of memory cells and the second set of memory cells may include memory cells coupled to the first word board and the second word board.

[0156] Some examples of the device may further include: a plurality of first pillars extending through a material stack including a first word line plate and a second word line plate, each of the plurality of first pillars being coupled to a corresponding memory cell of the first memory cell set; and a plurality of second pillars extending through the material stack, each of the plurality of second pillars being coupled to a corresponding memory cell of the second memory cell set, wherein each memory cell of the first memory cell set and the second memory cell set comprises chalcogenide material positioned between at least one word line plate and at least one pillar (e.g., in a recess positioned between at least one word line plate and at least one pillar).

[0157] Some instances of the device may further include: a plurality of first rows of pillars, each comprising two or more first pillars and two or more second pillars; and a plurality of second rows of pillars, each comprising two or more first pillars and two or more second pillars, each second row of pillars being interposed between corresponding sets of two first rows of pillars, wherein the plurality of first rows of pillars comprises a first logical page and the plurality of second rows of pillars comprises a second logical page, the first logical page being used to access a first subset of the first memory cell set and a first subset of the second memory cell set, and the second logical page being used to access a second subset of the first memory cell set and a second subset of the second memory cell set.

[0158] In some instances of the device, a first memory cell is operable to access based on activating a first pillar of a plurality of first pillars and a first word line of a plurality of first word lines, and a second memory cell of the second memory cell set is operable to access based on activating a second pillar of a plurality of second pillars and a second word line of a plurality of second word lines.

[0159] In some instances of the device, the capacitance of the first character board may be based on the number of first character lines on the first character board and the length of each of the plurality of first character lines, and the capacitance of the second character board may be based on the number of second character lines on the second character board and the length of each of the plurality of second character lines.

[0160] In some instances of the device, a first word line board may include a first conductive material sheet comprising a first portion extending in a first direction in a plane and a plurality of first fingers extending in a second direction in the plane, each of the first fingers corresponding to a corresponding word line among the plurality of first word lines, and a second word line board may include a second conductive material sheet comprising a second portion extending in the first direction in the plane and a plurality of second fingers extending in the second direction in the plane, each of the second fingers corresponding to a corresponding word line among the plurality of second word lines.

[0161] Describing another device. The device may include: a first word line tile including a first word line board comprising a plurality of first word lines, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a set of first memory cells; a second word line tile addressable independently of the first word line tile and including a second word line board comprising a plurality of second word lines, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a set of second memory cells; and a pillar tile associated with the first word line tile and the second word line tile, the pillar tile comprising a pillar group comprising: a plurality of first pillars, each of the plurality of first pillars being coupled to a corresponding memory cell of the first set of memory cells; and a plurality of second pillars, each of the plurality of second pillars being coupled to a corresponding memory cell of the second set of memory cells.

[0162] Some examples of the device may further include: a third word line board comprising a plurality of third word lines, each of the plurality of third word lines being coupled to one or more corresponding memory cells of a set of third memory cells; and an electrode coupled to the first word line board and the third word line board, the electrode being operable to simultaneously activate a first word line of the plurality of first word lines and a third word line of the plurality of third word lines.

[0163] In some instances of the device, the logical pages for accessing the first set of memory cells and the third set of memory cells may include memory cells coupled to the first word board and the third word board.

[0164] Some instances of the device may further include: a plurality of first rows of pillars, each comprising two or more first pillars and two or more second pillars; and a plurality of second rows of pillars, each comprising two or more first pillars and two or more second pillars, each second row of the pillars being interposed between corresponding sets of two first rows of the pillars, wherein the plurality of first rows of the pillars comprises a first logical page and the plurality of second rows of the pillars comprises a second logical page, the first logical page being used to access a first subset of the first memory cell set and a first subset of the third memory cell set, and the second logical page being used to access a second subset of the first memory cell set and a second subset of the third memory cell set.

[0165] Some examples of the device may further include: a third word line panel that is addressable independently of the first word line panel and includes a fourth word line board that can be positioned below the first word line board and includes a plurality of fourth word lines; a dielectric material that is inserted between the first word line board and the fourth word line board, the dielectric material electrically isolating the first word line board and the fourth word line board; and a first decoding circuit system that is coupled to the first word line board via a first electrode and to the fourth word line board via a second electrode, the first decoding circuit system being operable to activate a first word line among the plurality of first word lines or a fourth word line among the plurality of fourth word lines.

[0166] Some examples of the device may further include a dielectric material positioned between a plurality of first word lines and a plurality of second word lines, the dielectric material electrically isolating the first word line board from the second word line board, wherein a first portion of the dielectric material extends in a first direction in the same plane as the first word line board and the second word line board, and wherein a second portion of the dielectric material extends in a second direction in the same plane.

[0167] Some examples of the device may further include: a first decoding circuit system associated with a first word line block and operable to activate one or more of a plurality of first word lines; a second decoding circuit system associated with a second word line block and operable to activate one or more of a plurality of second word lines; and a third decoding circuit system associated with a pillar block and operable to activate one or more pillars of a pillar group.

[0168] In some instances of the device, the third decoding circuitry may include: a plurality of pillar column lines, each associated with a corresponding column of a pillar group; a plurality of pillar row lines, each associated with a corresponding row of the pillar group; a plurality of switching components, each coupled to a corresponding pillar of the pillar group, a corresponding pillar column line of the plurality of pillar column lines, and a corresponding pillar row line of the plurality of pillar row lines; a first decoder operable to activate the pillar column lines to activate one or more of the switching components; and a second decoder operable to activate the pillar row lines coupled to the switching components of the one or more switching components, wherein activating the pillar column lines and the pillar row lines activates pillars of the pillar group that can be associated with the pillar column lines, the pillar row lines, and the switching components.

[0169] In some instances of the device, the capacitance of the support plate can be based on the number of supports in the support group and the length of each support in the support group.

[0170] In some instances of the device, each memory cell of the first memory cell set and the second memory cell set may contain chalcogenide material positioned between at least one word line plate and at least one pillar (e.g., in a recess positioned between at least one word line plate and at least one pillar).

[0171] Describe another device. The device may include: a first word line board including a plurality of first word lines; a second word line board including a plurality of second word lines; electrodes coupled to the first word line board and the second word line board; and a controller. The controller is operable to cause the device to apply a first voltage to the electrodes, access a first memory cell coupled to a first word line among the plurality of first word lines based on the application of the first voltage to the first word line board via the electrodes, and access a second memory cell coupled to a second word line among the plurality of second word lines based on the application of the first voltage to the second word line board via the electrodes (e.g., simultaneously).

[0172] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0173] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) if there is any conductive path between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0174] The term "coupling" refers to the condition that changes from an open-circuit relationship between components (where signals cannot currently travel between components via conductive paths) to a closed-circuit relationship between components (where signals can travel between components via conductive paths). When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0175] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0176] As used herein, the term "layer" or "layer step" refers to a layer or sheet-like structure of geometry (e.g., relative to a substrate). Each layer or layer step may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or layer step may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a thin film. Layers or layer steps may contain different elements, components, and / or materials. In some instances, a layer or layer step may consist of two or more sublayers or sub-layer steps.

[0177] As used herein, the term "electrode" may refer to an electrical conductor and, in some instances, may serve as an electrical contact to a memory cell or other component of the memory array. Electrodes may comprise traces, wires, conductive lines, conductive layers, or the like that providing a conductive path between elements or components of the memory array.

[0178] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0179] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0180] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other instances." The detailed description includes specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0181] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral and is independent of the second reference numeral.

[0182] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distribution such that portions of the functions are implemented at different physical locations.

[0183] For example, the various specification boxes and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0184] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0185] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave) is included in the media definition. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these contents are also included within the scope of computer-readable media.

[0186] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand various modifications to this disclosure and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: The first word line block includes a first word line board containing a plurality of first word lines, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a plurality of first memory cells; A second word line block, addressable independently of the first word line block, includes a second word line board comprising a plurality of second word lines, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a plurality of second memory cells; and A support panel, associated with the first and second letter bar panels, the support panel comprising a support group, the support group comprising: A plurality of first pillars, each of the plurality of first pillars being coupled to a corresponding memory cell in the plurality of first memory cells; and A plurality of second pillars, each of the plurality of second pillars being coupled to a corresponding memory cell in the plurality of second memory cells.

2. The memory device according to claim 1, further comprising: The third word line board includes a plurality of third word lines, each of the plurality of third word lines being coupled to one or more corresponding memory cells in a plurality of third memory cells; and An electrode coupled to the first word line board and the third word line board, the electrode being operable to simultaneously activate the first word line of the plurality of first word lines and the third word line of the plurality of third word lines.

3. The memory device of claim 2, wherein the logic page for accessing the plurality of first memory cells and the plurality of third memory cells comprises a memory cell coupled to the first word board and the third word board.

4. The memory device according to claim 2, further comprising: The first row of the pillars, each comprising two or more first pillars and two or more second pillars; and The pillar has a plurality of second rows, each comprising two or more first pillars and two or more second pillars, each second row of the pillar being interposed between corresponding sets of two first rows of the pillar, wherein the plurality of first rows of the pillar includes a first logical page and the plurality of second rows of the pillar includes a second logical page, the first logical page being used to access a first subset of the plurality of first memory cells and a first subset of the plurality of third memory cells, and the second logical page being used to access a second subset of the plurality of first memory cells and a second subset of the plurality of third memory cells.

5. The memory device according to claim 1, further comprising: The third character line block can be addressed independently of the first character line block and includes a fourth character line plate located below the first character line plate and containing multiple fourth character lines; A dielectric material is inserted between the first word line board and the fourth word line board, wherein the dielectric material electrically isolates the first word line board from the fourth word line board; and A first decoding circuit system is coupled to the first word line board via a first electrode and to the fourth word line board via a second electrode. The first decoding circuit system is operable to activate either a first word line among the plurality of first word lines or a fourth word line among the plurality of fourth word lines.

6. The memory device of claim 1, further comprising: A dielectric material is positioned between the plurality of first word lines and the plurality of second word lines, the dielectric material electrically isolating the first word line board and the second word line board, wherein a first portion of the dielectric material extends along a first direction in the same plane as the first word line board and the second word line board, and wherein a second portion of the dielectric material extends along a second direction in the same plane.

7. The memory device according to claim 1, further comprising: A first decoding circuit system is associated with the first word line block and operable to activate one or more of the plurality of first word lines; A second decoding circuit system is associated with the second word line block and operable to activate one or more of the plurality of second word lines; and A third decoding circuit system is associated with the pillar piece and operable to activate one or more pillars of the pillar group.

8. The memory device of claim 7, wherein the third decoding circuit system comprises: Multiple pillar columns, each associated with a corresponding column of the pillar group; Multiple pillar rows, each associated with a corresponding row of the pillar group; Multiple switching components, each coupled to a corresponding pillar of the pillar group, a corresponding pillar column of the multiple pillar columns, and a corresponding pillar row of the multiple pillar rows; A first decoder is operable to activate a pillar line to activate one or more of the multiple switching components; and A second decoder is operable to activate a strut row line coupled to a switching component of the one or more switching components, wherein activating the strut column line and the strut row line activates the struts of the strut group associated with the strut column line, the strut row line and the switching component.

9. The memory device of claim 1, wherein the capacitance of the pillar block is at least partially based on the number of pillars in the pillar group and the length of each pillar in the pillar group.

10. The memory device of claim 1, wherein each of the plurality of first memory cells and the plurality of second memory cells comprises a chalcogenide material positioned between at least one word line board and at least one pillar.

11. A method for memory operation, comprising: A first voltage is applied to a first word line board comprising a plurality of first word lines, including a first word line block, using a first decoding circuit system; each of the plurality of first word lines is coupled to one or more corresponding memory cells of a plurality of first memory cells. A second voltage is applied to a second word line board comprising a plurality of second word lines addressable independently of the first word line block using a second decoding circuit system, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a plurality of second memory cells; A third voltage is applied to a first pillar of a pillar block using a third decoding circuit system. The first pillar is coupled to a first memory cell among the plurality of first memory cells, wherein the first memory cell is operable to access at least in part based on the application of the first voltage to the first word board and the application of the third voltage to the first pillar. and The third decoding circuitry system applies a fourth voltage to the second pillar of the pillar block, the second pillar being coupled to a second memory cell among the plurality of second memory cells, wherein the second memory cell is operable to access at least in part based on applying the second voltage to the second word board and applying the fourth voltage to the second pillar.

12. The method of claim 11, further comprising: The first voltage is applied to the first word line board via electrodes coupled to the first word line board and the third word line board, which includes a plurality of third word lines each coupled to one or more corresponding memory cells of a plurality of third memory cells. The electrodes are operable to simultaneously activate the first word lines of the plurality of first word lines and the third word lines of the plurality of third word lines.

13. The method of claim 12, wherein the logical pages for accessing the plurality of first memory cells and the plurality of third memory cells comprise memory cells coupled to the first word board and the third word board.

14. The method of claim 11, further comprising: The first decoding circuit system applies a fifth voltage to a fourth word line board located below the first word line board and including a third word line block addressable independently of the first word line block, each of the plurality of fourth word lines being coupled to one or more corresponding memory cells of a plurality of fourth memory cells.

15. The method of claim 11, wherein the first word line board and the second word line board are electrically isolated via a dielectric material positioned in a serpentine shape between the plurality of first word lines and the plurality of second word lines.

16. The method of claim 11, further comprising: A sixth voltage is applied to the first pillar line to activate the first switching component coupled to the first pillar; The sixth voltage is applied to the second pillar line to activate the second switching component coupled to the second pillar; The third voltage is applied to a first pillar line coupled to the first switching component, wherein applying the third voltage to the first pillar is at least partially based on applying the third voltage to the first pillar line; and The fourth voltage is applied to the second pillar line coupled to the second switching component, wherein applying the fourth voltage to the second pillar is at least partially based on applying the fourth voltage to the second pillar line.

17. The method of claim 16, wherein the first support line and the second support line comprise a pair of support lines inserted through at least one other support line.

18. The method of claim 11, wherein the capacitance of the support plate is at least partially based on the number of supports of the support plate and the length of each support of the support plate.

Images