Fault-tolerant forward error correction ordered set message decoder

Abstract

Methods are described for recognizing and applying operations to predetermined message patterns in the course of receiving a data stream structured as USB message frames. In a first embodiment, pattern matching is performed between received message bits and one or more predetermined sequences to recognize unscrambled ordered set messages. In a second embodiment, a descrambling operation is first applied, and then comparable pattern matching is performed between descrambled received message bits and one or more other predetermined sequences to recognize scrambled ordered set messages.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Application No. 17 / 207,565, filed on March 19, 2021, entitled “Fault-Tolerant Forward Error Correction Ordered Set Message Decoder,” the entire contents of which are incorporated herein by reference for all purposes. Background Technology

[0003] Generally, a data transmission system is defined by its architectural model, the protocols that embody each layer of that model, and the physical implementation of these protocol layers. Therefore, it is often said that "this system uses layers one through seven of the OSI network model, contains custom applications using TCP / IP transport, and the MAC / PHY layer is optimized for transmission over printed circuit traces." However, in real-world systems, the underlying transmission details, such as the lines and the physical signals they carry, can significantly impact the overall performance and functionality of the system. Therefore, a wealth of technologies have been developed to facilitate the transmission operations of the Physical Layer (PHY), which forms the foundation of the network.

[0004] For example, optimized line drivers and line receivers can be used to initiate line transmission and detect the transmitted content, and when the line path is long, repeater amplifiers can be introduced to mitigate the effects of wire attenuation by restoring the original signal amplitude.

[0005] However, if the physical medium (wire or fiber) exhibits any diffusion characteristics, not only will the amplitude of the signal transitions be attenuated, but the rise and fall times of such transitions will also be affected. This phenomenon is generally referred to as pulse edge "diffusion" or "softening," and the receiver may interpret it as timing fluctuations. Therefore, during signal regeneration, relay devices such as "retimers" not only amplify the signal but also re-timing it in an attempt to restore not only its original signal amplitude but also its pulse edge timing characteristics.

[0006] In addition, the network's PHY / MAC layer may impose additional constraints, which are typically related to the identification of the beginning and end of message blocks or "packets," and may optionally include an interactive process for determining the access party sharing the communication medium. A "repeater" is generally considered as an amplifier and pulse regenerator / retimer that further understands and participates in such medium access behavior.

[0007] Even though the operation of relay devices such as timers and repeaters may only require the transmission of individual bits and does not involve higher-level protocol behavior, they may still need to receive and respond to the protocol messages as part of their general compliance with the system's management, configuration, and other operational requirements. Summary of the Invention

[0008] In some USB-enabled devices, providing sufficient memory and / or processing power to fully buffer entire USB message frames can be problematic. Such buffering is generally considered necessary because conventional practices rely on the state of synchronization bits received near the end of the message to better resolve earlier received segments (supercodes) of the message.

[0009] In an alternative approach, specific USB messages are progressively identified during data reception via pattern matching, and the identified message patterns are confirmed by the finally received synchronization bits and / or error correction checksums. The local storage space used for buffering, comparing, and identifying the identified matching patterns is much smaller than the local storage space required for buffering the entire frame. In another approach, the required computational power can be further reduced because a full forward error correction calculation is not required when an error is detected. Attached Figure Description

[0010] Figure 1 shows the standardized format of Universal Serial Bus messages.

[0011] Figure 2 The diagram illustrates the parsing of a received Universal Serial Bus message according to an embodiment of the present invention.

[0012] Figure 3 This is a flowchart illustrating the processing procedure according to one embodiment.

[0013] Figure 4 This is a flowchart illustrating the transmission of data frames via a wired communication channel according to some implementation methods.

[0014] Figure 5 This is a flowchart of a low-power startup handshake protocol according to some implementation methods. Detailed Implementation

[0015] Since its introduction in 1996, the Universal Serial Bus (USB) standard has evolved significantly—from its initial host-to-peripheral connection mechanism to now supporting a wide range of use cases far more sophisticated than its origins—from high-speed peer-to-peer connections to basic power delivery. Advanced versions of the USB standard have also incorporated other protocol standards, a notable example being Apple's Thunderbolt standard.

[0016] Due to the constantly evolving nature of the USB standard, and the need for backward compatibility with earlier versions with each evolution, multiple data encoding and data integrity functions are superimposed on the underlying data stream, and there are a corresponding number of special cases that need to be handled.

[0017] The USB4 standard involves channels carrying 10 or 20 gigabits per second data streams. To facilitate the recovery of the receive clock, the transmit stream is scrambled by an existing cyclic sequence generator (often called a pseudo-random number generator or PRNG) initialized at link startup, and data integrity is maintained by forward error correction (FEC) codes that can correct errors up to two bytes and detect larger errors.

[0018] Because USB receivers often use decision feedback equalization (DFE) to counteract inter-symbol interference, a single bit error can potentially lead to misinterpretations of blocks or strings of bits. This is because the feedback from the DFE calculation of the erroneous data value can pull the sampling threshold away from the correct level. This situation persists until the erroneous data stream is eventually cleared from the DFE history. To mitigate this effect, advanced versions of the USB4 standard introduce a precoding operation that performs bit-by-bit consolidation on the transmitted data stream and complementary splitting on the received data stream. This precoding operation effectively transforms block errors into two single-bit errors located at the beginning and end of the block. Since these errors fall within the error correction capabilities of FEC codes, data integrity is significantly improved.

[0019] Figure 4 This is a flowchart illustrating the transmission of supercode symbols via a wired communication channel according to some embodiments, where the channel may be, for example, one or more lines of a multi-line bus. Figure 4 As shown, a 194-byte frame including payload data and synchronization bits is encoded, for example, using a Reed-Solomon coding scheme to calculate, for example, four parity bytes, which are then added to the original 194-byte frame. The FEC-coded frame is digitally integrated by the pre-encoder as described above and transmitted via a wired communication channel. During transmission, bit errors may occur, resulting in string errors in the transmitted frame. As described above, the decoder converts these string errors into two single-bit errors through digital splitting. Subsequently, an algorithm identifies the unscrambled ordered set (UOS) and the scrambled ordered set (SOS) by comparing the supercode symbol in the received frame with known ordered set values, which will be described in further detail below.

[0020] Figure 1 shows the protocol format of a USB4 frame. The payload of this frame consists of 192 bytes, followed by a two-byte "synchronization" control field and a four-byte FEC parity codeword. The payload is divided into twelve 16-byte "supercode characters," each of which is one of the following:

[0021] 1. Unscrambled Ordered Set (UOS): This type of ordered set includes specific control messages that are not scrambled during transmission and have specific low-level protocol control behaviors;

[0022] 2. Scrambled Ordered Set (SOS): This type of ordered set is also a low-level protocol control message, but it is sent after being scrambled by ordinary data;

[0023] 3. Scrambled data: Unconstrained user data sent after being scrambled by ordinary data.

[0024] The aforementioned two-byte synchronization field includes 4 reserved bits and 12 flag bits, each flag bit corresponding to a supercode symbol in the current frame. A flag bit set to "1" indicates that the supercode symbol at the corresponding index number or position in the data frame includes a scrambled or unscrambled ordered set.

[0025] In previous versions of the USB standard, each supercoder consisted of 8 bytes or 64 bits. To achieve compatibility between these previous versions and the larger 128-byte supercoders of the latest version, the USB4 standard always sends two copies of the same 64-bit UOS control message simultaneously, creating a 128-bit gap or pause in the normal process of the scrambler. In current USB practice, the UOS control messages SKIP and TSNOS are periodically interleaved with the scrambled data messages. The UOS control message CL_WAKE2 can also be received upon exiting CL0s.

[0026] For the resulting frame, the traditional (i.e., existing technology) software-guided parsing method is as follows:

[0027] Receive 192+2+4 bytes into the message buffer.

[0028] Calculate the ECC parity of the entire message. As is well known in the art, this operation may involve recalculating the overall parity of the first 194 bytes of the message when they were sent and comparing the result with the received four-byte FEC parity codeword. An alternative known practice is to calculate the parity of the entire 198-byte message, including the received FEC parity codeword, using the same method; if the result is zero, no error was found. For convenience, the latter calculation method is used, but this is not intended to be limiting.

[0029] If an error is found, FEC error correction is performed to identify the erroneous bytes in the message and the bits in such bytes that need to be corrected (if there are uncorrectable errors, this message parsing process is exited and any resynchronization / error correction procedures designed for error correction failure are initiated).

[0030] For each superkeyword in the message, determine whether it is scrambled or unscrambled. Superkeywords, including those in ordered sets, are marked with synchronization tags.

[0031] 1. If the (ordered set or data) is scrambled, the supercoder content is descrambled using the scrambler's pseudo-random generator. As is known in the art, after each use, the scrambler's content must be shifted forward; for example, after each bit descrambled, the pseudo-random scrambling sequence generator is shifted forward by a count value. After the scrambled ordered set (such as the ordered set corresponding to a command message) is descrambled, it can be examined and subjected to existing message parsing or pattern matching processing.

[0032] 2. If no scrambling is applied, the received (or FEC-corrected) data is directly parsed or pattern matched. The scrambling data is not shifted forward.

[0033] For ordinary host computer systems or client devices with moderate storage space or processing power, the above process is straightforward. However, for low-level embedded devices such as repeaters or retimers, several aspects of this process are more challenging. First, the process requires sufficient space to store the entire frame, while the buffer or storage capacity of embedded hardware devices may be limited to only a few dozen bytes. Second, when the FEC parity result indicates an error, the entire FEC error correction process must be executed to determine whether the error occurred within the current frame, and such calculations require significant storage and processing power. In the worst case, synchronization bits may malfunction, leading to the inability to recognize the supercode symbol of the unscrambled ordered set, thus making it impossible to maintain scrambler synchronization required for subsequent message parsing.

[0034] In contrast, the embodiments described in this invention can perform "on-demand" parsing of supercode symbols in received data frames (i.e., parsing simultaneously with reception) and process the supercode symbols in their received-time form without buffering the entire frame. In some embodiments, this parsing process includes pattern matching of the received-time data with known SOS and UOS messages to identify candidate SOS and UOS. This allows for dynamic decisions regarding whether the descrambler should be moved forward or paused for the detected supercode symbol type. Furthermore, it can guide other components of the chip to perform various other tasks, such as entering a low-power mode upon identification of certain SOS.

[0035] In practical applications, since the types of UOS messages to be identified are limited (in some schemes, only two or three), a finite state machine can be used to perform pattern matching operations. The following example illustrates a comparison or match operation performed every eight bits (i.e., one byte) received, with each operation comparing the eight received bits one by one with a corresponding portion of one or more known values ​​representing a known UOS message pattern, which may be stored, for example, in memory or some other storage circuitry. This is not intended to be limiting. In one such implementation, an explicit XOR comparison is performed between the received data byte and the byte of each possible message. In another implementation, such comparisons involve "don't care" elements that force a match regardless of the value, allowing the same comparison operation to detect two or more messages that differ by only a few bit positions. Similarly, such "don't care" elements can be flexibly and cleverly applied to known message patterns that do not extend beyond the 128 bits (64 bits in earlier versions) of the entire supercode, skipping redundant or irrelevant portions of the message.

[0036] Figure 2 The diagram shows a retimer chip 200, where received data frames 205 are processed and buffered (210) by receiver 202, and then retransmitted by transmitter 204 as retimed data frames 215. In the repeater / retimer implementation, buffer 210 can be a first-in-first-out (FIFO) register, typically buffering only eight bits, but with the capacity to buffer hundreds of bits. As the content of input messages gradually accumulates in the buffer, pattern matching 220 and 250 are performed on known UOS and SOS messages respectively for subsequent operations. Although Figure 2 The data flow direction in the operation of the receiving (Rx) element 202 and the transmitting (Tx) element 204 shown is unidirectional. However, it should be noted that, as combined with the following... Figure 5 In further detail, many embodiments relate to a bidirectional data flow and include equivalent receiving and transmitting means for operation in the opposite data flow direction.

[0037] like Figure 2As shown, an apparatus 200 includes a buffer 210 for buffering received data frames processed by a receiver 202, the received data frames including a set of supercode symbols, a set of synchronization bits, and received forward error correction (FEC) parity codewords. The apparatus also includes, for example, a transmit driver located within a transmitter 204 for outputting retiming data 215. The apparatus further includes a mode comparison circuit 220 for identifying candidate unscrambled ordered sets (UOS) in the set of supercode symbols by comparing portions of each supercode symbol with corresponding portions of one or more known UOS values, which may be stored, for example, in a storage circuit 230. The apparatus also includes an FEC check circuit 270 for calculating local FEC parity codewords based on the received data frames. Such calculations may be performed incrementally in a "calculate as soon as data is received" manner. The apparatus also includes a controller 280 for providing a control signal ctrl to a descrambler 240 to pause forward movement in the descrambling operation during the processing of identified candidate UOSs. Furthermore, if a candidate UOS is found to be a false candidate UOS after verification using the corresponding synchronization bits by comparing the local FEC parity codeword with the received FEC parity codeword, the control signal ctrl can further advance the descrambler 240. In some embodiments, the control signal ctrl advances the descrambling operation by a predetermined amount (e.g., several bytes). Alternatively, the controller can maintain the typical performance value of the descrambler at the start of processing each supercodeword or data frame and can restore the state of the descrambler using the stored typical performance value. Accordingly, the descrambler 240 can be used to descramble received scrambled supercodewords in subsequent data frames to identify scrambled ordered sets by, for example, comparing them with known scrambled ordered set messages 260 that can be stored in a storage device similar to 230, via a second mode comparison circuit.

[0038] In one implementation, the input data is buffered and compared incrementally in increments of 8 bits (e.g., 1 byte), and each received byte is compared with a corresponding byte portion of one or more known UOSs stored in storage circuitry 230 via pattern comparison circuitry 220. If the raw (e.g., undescrambled) content of the received data stream matches one of the detectable message patterns of a given known UOS, the count value of an associated "match counter" for that message pattern, for example, operated by controller 280, is incremented.

[0039] If at least six bytes in a given 64-bit received sequence match, the matching sequence is identified as a candidate unscrambled ordered set (candidate UOS). In a further implementation, a continuous matching operation is performed on the entire 128-bit supercode (instead of just the traditional 64-bit message length), where a candidate UOS is identified when at least 14 out of the corresponding 16 bytes match. Since the USB standard's FEC error correction capability is up to two byte errors per frame, the aforementioned "6 out of 8" or "14 out of 16" byte matching processing can detect input messages in the target format even when there are two mutually separated byte errors (e.g., each of two different received message bytes has one or more bit errors). For a finite set of detectable UOS messages, the probability of such partial matching resulting in a misidentification of one message is extremely low, and in the worst case, the consequence of such a misidentification is only that the embedded device can only receive subsequent scrambled messages after the descrambler has been resynchronized. Statistically, the probability estimate of misidentification is:

[0040]

[0041] This value is approximately 4.6 × 10⁻⁶. -32 .

[0042] In some implementations, the process of identifying candidate UOSs by comparing buffered supercode symbols with known UOS messages bit-by-bit or byte-by-byte can overlap or occur substantially in parallel with a similar comparison process for identifying known SOS messages. The latter operation includes: progressively scrambling the received message data (240) (and thus shifting the scrambler state forward by a certain number of bit time intervals); then, using a pattern comparison circuit 250, similar to the pattern comparison circuit 220 described above, performing a pattern comparison operation with the known SOS message pattern 260 as the comparison object. Before identifying a candidate UOS, the descrambler used for the concurrent SOS message comparison operation may have been incorrectly shifted forward by a certain number of bit time intervals. This will cause the receiver's descrambler state to become out of sync with the transmitter's descrambler state, thereby hindering the reception of subsequent scrambled data.

[0043] In some implementations, when the pattern matching function identifies a candidate UOS, the descrambling operation of the descrambling unit 240 can be paused by a predetermined number of bit time intervals (e.g., 128 bit time intervals for the latest frame format; 64 bit time intervals for earlier versions) to resynchronize the descrambling unit. In an alternative implementation, typical scrambling performance values ​​can be recorded at the start of supercode processing, and its state can then be restored to a descrambling state that has been unnecessarily timed or shifted forward after a false candidate UOS was detected.

[0044] The FEC parity check 270 at the receiving end can also be dynamically calculated during message reception. If no error is found and the previously identified message pattern matching result has been confirmed by the synchronized bit marker, the operation of pattern matching identification can be performed. In some embodiments, the operation may include: pausing the forward shift of the scrambler state during the processing of the supercodeword; and executing the USB command associated with the identified UOS message. It should be noted that in some embodiments, the FEC parity check 270 may compare the locally generated FEC parity codeword with the received FEC parity codeword and notify the controller 280 whether an error has occurred.

[0045] It should be reiterated that since the FEC parity check 270 calculates the data bits received, its calculation and verification are independent of the synchronization state of the scrambler or whether the descrambler 240 is moved forward or paused.

[0046] If the number of synchronization flag bits set does not match the number of UOS supercode symbols determined by pattern matching, it indicates that a candidate UOS may have been misidentified, thus unnecessarily pausing the forward shift of the descrambler state, or that one or more synchronization flag bits have been received incorrectly.

[0047] In one implementation, if the FEC parity check at the receiving end identifies an error, priority is given to the pattern matching result over the value of the non-synchronization flag bit in both determining the state of the descrambler 240 and executing the USB command determined by the correct identification of the UOS and SOS messages. Statistically, the probability of a reception error occurring in the synchronization flag bit is much greater than the probability of a pattern matching error occurring in the implementation described in this invention. Although the probability calculation incorporates the synergistic benefits of precoding to limit block data errors and the two-byte error correction implemented by FEC, the message parsing processing described in this invention can still function even without one or both of these functions.

[0048] In a further implementation, if the FEC parity check at the receiving end confirms that no error occurred in the received frame, but the number of candidate UOS determined by pattern matching does not match the number of synchronization flag bits set for that frame, it can be determined that one or more candidate UOS have been misidentified. In this case, priority is given to the set synchronization flag, rather than the pattern matching result, to indicate that the scrambler state may have been unnecessarily paused during the instantaneous UOS pattern matching process. Furthermore, the position of the synchronization bits can be used to check the position of candidate UOS in the received data frame to determine whether a candidate UOS is a true UOS or a false candidate UOS. In this case, when the synchronization bits indicate a misidentification of a candidate UOS, the scrambler state can subsequently be shifted forward by the corresponding number of bit time intervals (depending on the version of the USB standard used, 64 or 128 bit time intervals per supercode).

[0049] Because the descrambler 240 maintains synchronization at the beginning of each received frame of the codeword, the SOS mode comparison circuit 250 can accurately identify various SOSs and notify the controller 280 to perform specific operations within the retimer chip 200 itself. As described above, Figure 2 The retimer chip 200 includes transceiver circuitry with a transmitter 204 and a receiver 202. The transmitter 204 may include components such as a transmit driver, and the receiver 202 may include components such as a phase-locked loop (PLL) and a clock data recovery (CDR) circuit. In some embodiments, the SOS message identified by the SOS mode comparison circuit 250 may include various low-power commands, such as CL_req (low-power request), CL_ack (acknowledgment and initiation of a low-power request in the first data flow direction), and CL_off (low-power initiation in the second data flow direction). Upon identification of such an SOS message, the controller 280 may provide control signals to the receiving element 202 and the transmitting element 204 to save power by shutting down various circuit elements. In a non-limiting embodiment, the transmit driver in the transmitting circuit 204 may be turned off, and the CDR circuit in the receiving circuit 202 may be turned off. Furthermore, the controller may include an analog filter for identifying low-frequency power-on signals entering a high-speed data operation mode (i.e., normal operation mode).

[0050] Figure 5 The figure illustrates the operation of a low-power handshake protocol according to some implementations. As shown in the figure, Figure 5 Includes bidirectional data flow between devices 1 and 2, with a retimer (e.g.) between them. Figure 2The protocol uses a re-timer to process input data from each device and output re-timed / re-buffered data to the other device. In this protocol, device 1 first periodically sends a low-power request message (CL_req) to device 2, and device 2 responds by periodically sending an acknowledgment message (CL_ack). Device 2 can start a timer upon receiving a CL_req message and can shut down its transmitter after sending a certain number of CL_ack messages to device 1. Device 1 receives the CL_ack messages and can shut down its own receiver and begin sending CL_off messages for a predetermined duration to notify device 2 that it will shut down its transmitter, thus allowing device 2 to shut down its receiver. In this specific case, both data stream directions enter low-power mode. However, it should be noted that in most cases, one of the high-speed data stream directions can remain open.

[0051] Because the retimer between the two devices is synchronized within its own local descrambler 240, the retimer can accurately identify SOS messages transmitted between devices 1 and 2. Therefore, the controller 280 within the retimer 200 can configure its own receiving and transmitting elements to enter a low-power operating mode in either direction to save power within the chip.

[0052] Although the above example uses the low-power startup handshake protocol, it is important to understand that the controller 280 can be used to perform various other operations by recognizing the SOS message with the descrambler 240 and the SOS mode comparison circuit 250.

[0053] In one implementation, the high-level processing for performing this type of parsing is as follows:

[0054]

[0055]

[0056] Figure 3The following is a flowchart of method 300 according to some embodiments. As shown, method 300 includes: receiving (302) a data frame including a set of supercode symbols, a set of synchronization bits, and a received forward error correction (FEC) parity codeword. Method 300 further includes: identifying (304) a candidate unscrambled ordered set (UOS) in the set of supercode symbols by comparing portions of each supercode symbol with corresponding portions of one or more known UOS values; and pausing (306) the forward shift of the descrambling operation during the processing of the identified candidate UOS when a candidate UOS is identified. Based on the received frame, a local FEC parity codeword is calculated (308). After comparing the local FEC parity codeword with the received FEC parity codeword, the candidate UOS is verified with the corresponding synchronization bits to determine (310) a false candidate UOS by verifying the candidate UOS with the corresponding synchronization bits after comparing the local FEC parity codeword with the received FEC parity codeword. When a candidate UOS is verified as a false candidate UOS, the descrambling operation is moved forward accordingly (312) to resynchronize the descrambler. In subsequent data frames (such as frames without any UOS), the scrambling supercode is descrambled (314) to identify the scrambled ordered set.

[0057] In some implementations, candidate UOS identification includes, for example, comparing each byte of each supercoder in the set of supercoders with the corresponding bytes of one or more known UOS values ​​230, byte by byte, using pattern comparison circuit 220. In some such implementations, candidate UOS identification includes determining that a predetermined number of bytes in a given supercoder completely match the corresponding bytes of a known UOS value. In some implementations, each supercoder comprises 8 bytes, and pattern comparison circuit 220 determines that at least 6 bytes in the given supercoder match the corresponding bytes of a known UOS value 230 to identify a candidate UOS. Alternatively, each supercoder comprises 16 bytes, and pattern comparison circuit 220 may determine that at least 14 bytes in the given supercoder match the corresponding bytes of a known UOS value 230 to identify a candidate UOS.

[0058] In some implementations, at least one scrambled supercode character in a subsequent data frame corresponds to a low-power mode start command.

[0059] In some implementations, method 300 includes: identifying a second candidate UOS among a set of supercodes in the second received data frame by comparing portions of each supercode in the second received data frame with corresponding portions of one or more known UOS values; and pausing the forward descrambling operation during the processing of the second candidate UOS when the second candidate UOS is identified.

[0060] In some implementations, the method includes: calculating a second local FEC parity codeword based on a second received data frame; and comparing the second local FEC parity codeword with a second received FEC parity codeword.

[0061] In some implementations, the second candidate UOS can be determined as the true UOS, thus eliminating the need for a forward descrambling operation. Two examples of determining the second UOS as the true UOS are given below. In the first implementation, when no error is determined based on the comparison result between the second local FEC parity codeword and the second received FEC parity codeword, the corresponding synchronization bit received in the second received data frame is used to verify the second candidate UOS. In the second implementation, the second candidate UOS is determined as the true UOS by determining the presence of a bit error based on the comparison result between the second local FEC parity codeword and the second received FEC parity codeword.

[0062] In some implementations, similar to the above, method 300 may further include: determining a second candidate UOS as another false candidate UOS by comparing the second local FEC parity codeword with the second received FEC parity codeword to determine that no error exists; and verifying the second candidate UOS with the corresponding synchronization bit in the second received data frame. Similarly, in such implementations, when the second candidate UOS is determined to be a false candidate UOS, the descrambling operation can be moved forward to maintain the synchronization of the descrambler.

[0063] In some implementations, one method parses the input data as it is received to identify the message. Because USB4's message FEC function can correct for errors of up to two independent bytes in each frame, at most two comparisons (each of which is of size (match segment)) may fail to match in the total number of matches for each message segment.

[0064] sizeof(message segment) / sizeof(match segment)

[0065] However, it can still identify specific received messages with a relatively high probability.

[0066] Various embodiments of the present invention may employ different criteria regarding acceptable pattern matching accuracy (e.g., how many symbols in the supercode must match a certain pattern), whether the determined match result must be confirmed by association with a properly configured synchronization flag, and ignoring conditions for FEC parity errors. Similarly, different embodiments may choose to perform pattern matching on a single instance of a 64-bit UOS control message (thus treating the actual 128-bit UOS supercode as two consecutive control messages), or they may perform pattern matching on the entire 128-bit sequence consisting of two repetitions of the same 64-bit message (thus significantly reducing the risk of false positives). Within the scope of the embodiments described in this invention, the aforementioned criteria can be selected based on the expected error-correctable and non-error-correctable rates when identifying specific messages for a specific system and instance, statistical estimates of matching success and failure rates, implementation difficulty, cost and power consumption, and the relative benefits / risks of positive and negative matching failure rates.

Claims

1. A communication method, characterized in that, include: Receive a data frame, the data frame including a set of super code symbols, a set of synchronization bits and the received forward error correction parity codeword; Candidate unscrambled ordered sets in the set of supercode symbols are identified by comparing each part of each supercode symbol with the corresponding part of at least one known unscrambled ordered set value. In response to the identification of the candidate unscrambled ordered set, the forward movement of the descrambling operation is paused during the processing of the identified candidate unscrambled ordered set; Calculate the local forward error correction parity codeword based on the received data frame; In response to the comparison between the local forward error correction parity codeword and the received forward error correction parity codeword, the candidate unscrambled ordered set is verified by using the corresponding synchronization bits, thereby identifying the false candidate unscrambled ordered set; In response to the identification of the false candidate unscrambled ordered set, the scrambling operation is moved forward; as well as The scrambled supercode symbols received in subsequent data frames are descrambled in order to identify the scrambled ordered set.

2. The method as described in claim 1, characterized in that, Identifying the candidate unscrambled ordered set includes: comparing each byte of each supercode symbol in the set of supercode symbols with the corresponding byte of the at least one known unscrambled ordered set value byte by byte.

3. The method as described in claim 2, characterized in that, Identifying the candidate unscrambled ordered set includes: determining that a predetermined number of bytes of a given supercode symbol completely match the corresponding bytes of the known unscrambled ordered set value.

4. The method as described in claim 3, characterized in that, Each supercode symbol comprises 8 bytes, wherein identifying the candidate unscrambled ordered set comprises: at least 6 bytes of the given supercode symbol matching the corresponding bytes of the known unscrambled ordered set value.

5. The method as described in claim 3, characterized in that, Each supercode symbol comprises 16 bytes, wherein identifying the candidate unscrambled ordered set comprises: at least 14 bytes of the given supercode symbol matching the corresponding bytes of the known unscrambled ordered set value.

6. The method as described in claim 1, characterized in that, At least one scrambled supercode in the subsequent data frame corresponds to a low-power mode start command, wherein the method further includes: setting at least one local circuit element in the low-power mode.

7. The method as described in claim 1, characterized in that, Also includes: A second candidate unscrambled ordered set is identified from a set of supercode symbols in a second received data frame by comparing each portion of each supercode symbol in the second received data frame with the corresponding portion of the at least one known unscrambled ordered set value. In response to the identification of the second candidate unscrambled ordered set, the forward movement of the descrambling operation of the second candidate unscrambled ordered set is paused; Calculate the second local forward error correction parity codeword based on the second received data frame; as well as The second local forward error correction parity codeword is compared with the second received forward error correction parity codeword.

8. The method as described in claim 7, characterized in that, Also includes: In response to determining that no error exists based on the comparison between the second local forward error correction parity codeword and the second received forward error correction parity codeword, the second candidate unscrambled ordered set is verified by using the corresponding synchronization bits received within the second received data frame to determine that the second candidate unscrambled ordered set is a true unscrambled ordered set.

9. The method as described in claim 8, characterized in that, It also includes determining the presence of bit errors by comparing the second local forward error correction parity codeword with the second received forward error correction parity codeword, so as to determine that the second candidate unscrambled ordered set is a true unscrambled ordered set.

10. The method as described in claim 8, characterized in that, Also includes: Based on the comparison between the second local forward error correction parity codeword and the second received forward error correction parity codeword, it is determined that there is no error, and the corresponding synchronization bits received in the second received data frame are used to verify the second candidate unscrambled ordered set, so as to determine that the second candidate unscrambled ordered set is a false unscrambled ordered set. as well as In response to determining that the second candidate unscrambled ordered set is a false candidate unscrambled ordered set, the scrambling operation is moved forward.

11. A communication device, characterized in that, include: A mode comparison circuit is used to receive a data frame, the data frame including a set of supercode symbols, a set of synchronization bits, and a received forward error correction parity codeword, wherein the mode comparison circuit is used to identify a candidate unscrambled ordered set in the set of supercode symbols by comparing each part of each supercode symbol with a corresponding part of at least one known unscrambled ordered set value. A forward error correction verification circuit is used to calculate a local forward error correction parity codeword based on the received data frame, and to compare the local forward error correction parity codeword with the received forward error correction parity codeword. Controller, wherein the controller is used for: In response to the identification of candidate unscrambled ordered sets, during the processing of the identified candidate unscrambled ordered sets, the forward movement of the descrambling operation of the descrambling unit is paused; and In response to the comparison between the local forward error correction parity codeword and the received forward error correction parity codeword, the candidate unscrambled ordered set is verified by corresponding synchronization bits to identify false candidate unscrambled ordered sets, and in response to the identification of the false candidate unscrambled ordered sets, the descrambling operation of the descrambler is moved forward, and The descrambler is used to descramble the scrambled supercodes received in subsequent data frames in order to identify the scrambled ordered set.

12. The apparatus as claimed in claim 11, characterized in that, The pattern comparison circuit is used to compare each byte of each supercode in the set of supercodes with the corresponding byte of the at least one known unscrambled ordered set value byte by byte to identify the candidate unscrambled ordered set.

13. The apparatus as claimed in claim 12, characterized in that, The pattern comparison circuit is used to determine whether a predetermined number of bytes of a given supercode symbol completely match the corresponding bytes of a known unscrambled ordered set value, in order to identify the candidate unscrambled ordered set.

14. The apparatus as claimed in claim 13, characterized in that, Each supercode symbol comprises 8 bytes, wherein the pattern comparison circuit is used to determine that at least 6 bytes of a given supercode symbol match the corresponding bytes of the known unscrambled ordered set value to identify the candidate unscrambled ordered set.

15. The apparatus as claimed in claim 13, characterized in that, Each supercode symbol comprises 16 bytes, wherein the pattern comparison circuit is used to determine that at least 14 bytes of a given supercode symbol match the corresponding bytes of the known unscrambled ordered set value to identify the candidate unscrambled ordered set.

16. The apparatus as claimed in claim 13, characterized in that, It also includes a forward error correction circuit for correcting errors in the bytes of the unscrambled ordered set.

17. The apparatus as claimed in claim 11, characterized in that, At least one scrambled supercode in the subsequent data frame corresponds to a low-power mode start command, wherein the controller is further configured to set at least one local circuit element in the low-power mode.

18. The apparatus as claimed in claim 11, characterized in that, The mode comparison circuit is used for: A second candidate unscrambled ordered set is identified from a set of supercode symbols in a second received data frame by comparing each portion of each supercode symbol in the second received data frame with the corresponding portion of the at least one known unscrambled ordered set value. as well as In response to the identification of the second candidate unscrambled ordered set, the forward movement of the descrambling operation for the second candidate unscrambled ordered set is paused; The forward error correction verification circuit is used to calculate a second local forward error correction parity codeword based on the second received data frame, and the controller is used to compare the second local forward error correction parity codeword with the second received forward error correction parity codeword.

19. The apparatus as claimed in claim 18, characterized in that, The controller is configured to determine that there is no error when it is determined that there is no error by comparing the second local forward error correction parity codeword with the second received forward error correction parity codeword according to the forward error correction verification circuit, and thereby verifying the second candidate unscrambled ordered set with the corresponding synchronization bits received in the second received data frame, thereby determining that the second candidate unscrambled ordered set is a true unscrambled ordered set.

20. The apparatus as claimed in claim 18, characterized in that, The controller is configured to determine that a bit error exists by comparing the second local forward error correction parity codeword with the second received forward error correction parity codeword, thereby determining that the second candidate unscrambled ordered set is a true unscrambled ordered set.

21. The apparatus as claimed in claim 18, characterized in that, The controller is configured to: determine that there is no error by comparing the second local forward error correction parity codeword with the second received forward error correction parity codeword, and verify the second candidate unscrambled ordered set with the corresponding synchronization bit in the second received data frame, thereby determining that the second candidate unscrambled ordered set is a false candidate unscrambled ordered set; And in response to determining that the second candidate unscrambled ordered set is a false candidate unscrambled ordered set, the scrambling operation is moved forward.

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