A circuit for SPAD device quench shaping and method thereof

Abstract

The application discloses a circuit and a method thereof for quench shaping of a SPAD device. The circuit comprises an active quench circuit, a delay inverter, an NOR gate and a shaping circuit, wherein the active quench circuit receives an avalanche signal generated by the SPAD device when detecting photons and outputs a high level; the delay inverter is used to generate a low level signal with a certain delay from the output of the active quench circuit; the NOR gate performs NOR logic processing on the outputs of the active quench circuit and the delay inverter and generates a pulse output; and the shaping circuit is used for shaping the pulse output. The active quench circuit of the application forcibly adjusts the voltage difference between two ends of the SPAD to below the avalanche voltage after the SPAD detects photons by connecting a signal, so that the device is separated from the avalanche breakdown state and active quenching is realized. The circuit structure of the application can realize effective and rapid quenching of the SPAD device and shaping output of a photon detection pulse signal, and is compatible with a standard integrated circuit process.

Description

Technical Field

[0001] This invention relates to a circuit and method for quenching and shaping SPAD devices, belonging to the field of SPAD single-photon imaging based on semiconductor technology. Background Technology

[0002] A single-photon avalanche diode (SPAD) is capable of detecting a single photon and converting the optical signal into an electrical signal. Its working principle is as follows: when a photon enters the photosensitive region of the SPAD, there is a certain probability that the photon will be absorbed by the depletion region, generating an electron-hole pair. Under the influence of the strong electric field in the depletion region, this electron-hole pair can rapidly generate a large number of charge carriers through a multiplication effect, triggering an avalanche breakdown. Therefore, SPADs have advantages such as high sensitivity, high gain, and fast speed, making them popular among researchers and widely used in fields such as quantum communication, radioactivity detection, and high-sensitivity sensors.

[0003] However, SPAD avalanche breakdown is a self-continuous behavior; without external interference to suppress it, its avalanche behavior cannot stop autonomously. If subjected to the high current conditions of avalanche breakdown for an extended period, the SPAD will overheat or even burn out and will be unable to enter a new detection cycle to resume normal operation. Therefore, SPADs often need to be used in conjunction with a quenching circuit to suppress avalanche in a timely manner. The working process of the quenching circuit is as follows: First, when the SPAD avalanche signal is generated, the quenching circuit senses the avalanche current and promptly quenches the large avalanche current, reducing the reverse bias voltage of the device below the avalanche voltage and outputting a pulse signal. Then, the device is reset, returning to its initial state, and the next cycle begins.

[0004] Quenching circuits currently mainly include passive quenching circuits, active quenching circuits, and gated quenching circuits. The principle of passive quenching is to connect a large resistor in series with the SPAD. When a large avalanche current arrives, the resistor diverts a significant portion of the voltage, making the voltage across the SPAD less than the avalanche breakdown voltage, thus achieving quenching. Although this circuit structure is simple, it requires a long recovery time, and the large resistor occupies a large area. The principle of active quenching is to introduce a feedback loop. When an avalanche occurs, once a feedback signal is received, the reverse bias voltage across the SPAD is immediately reduced to less than the avalanche breakdown voltage, thereby quenching the avalanche current. Its response speed is much faster than passive quenching. In traditional active quenching circuits, the cathode of the SPAD is connected to a fixed bias voltage. By changing its anode voltage, the magnitude of the reverse bias voltage is controlled, thereby controlling the quenching of the device. However, there is still considerable room for improvement in its speed. Summary of the Invention

[0005] To address the shortcomings of the existing technology, the present invention aims to provide a circuit and method for quenching and shaping SPAD devices. This circuit structure can achieve effective and rapid quenching of SPAD devices and shaping output of photon detection pulse signals, and is compatible with standard integrated circuit processes.

[0006] The technical solution adopted in this invention is as follows:

[0007] A circuit for quenching and shaping a SPAD device includes an active quenching circuit, a delay inverter, a NOR gate, and a shaping circuit. The active quenching circuit receives an avalanche signal generated by photons detected by the SPAD device and outputs a high-level signal; the delay inverter generates a low-level signal with a certain delay from the output of the active quenching circuit; the NOR gate performs NOR logic processing on the outputs of the active quenching circuit and the delay inverter to generate a pulse output; and the shaping circuit shapes the pulse output.

[0008] Furthermore, the active quenching circuit is composed of P-type transistors PM0 and PM1 and N-type transistors NM0, NM1, and NM2. The SPAD device is connected to the drain terminal of transistor NM0 and the gate terminal of NM1 as the input terminal. The drain terminal signal of transistor NM1 is output through an inverter composed of transistors PM1 and NM2.

[0009] Furthermore, the delay inverter is composed of P-type transistors PM2 and PM3 and N-type transistor NM3. The high-level signal generated by the active quenching circuit is input to the gate terminal connected to transistors PM3 and NM3, which will generate a low-level signal with a certain time delay from the original signal at the drain terminal connected to transistors PM3 and NM3.

[0010] Furthermore, the NOR gate is composed of P-type transistors PM4 and PM5 and N-type transistors NM4 and NM5. The gate terminals connected to transistors PM4 and NM5 are the first input terminals, the gate terminals connected to transistors PM5 and NM4 are the second input terminals, and the drain terminals connected to transistors PM5, NM4, and NM5 are the output terminals.

[0011] Furthermore, the shaping circuit is composed of P-type transistors PM6 and PM7 and N-type transistors NM6 and NM7. The gate terminals of transistors PM6 and NM6 are connected as input terminals, and the drain terminals of transistors PM7 and NM7 are connected as output terminals. Transistors PM6 and NM6 constitute the first-stage inverter, and transistors PM7 and NM7 constitute the second-stage inverter.

[0012] The present invention also provides a quenching and shaping method using the above-mentioned circuit, the method comprising the following steps:

[0013] When a photon arrives at the SPAD device, avalanche breakdown occurs. The gate of transistor NM1 is connected to a high level and thus turns on, while its drain outputs a low level. This low level signal is then converted to a high level by the inverter in the active quenching circuit. This high-level signal is then converted to a low-level signal with a certain time delay by the delay inverter. The high-level and low-level signals are then passed through the NOR gate to generate a high-level pulse output. Finally, the pulse is shaped by the shaping circuit and output as a pulse signal indicating that the SPAD device has detected a photon.

[0014] This invention provides a circuit structure and method for quenching and shaping SPAD devices. Compared to existing SPAD quenching circuit structures, it adds a pulse shaping component, resulting in more standardized pulse output and facilitating direct input when adding other modules. Furthermore, the active quenching method improves circuit efficiency; since SPAD device quenching is achieved by directly adjusting the gate voltage, the response speed reaches the nanosecond level. Simultaneously, the circuit's compatibility with standard integrated circuit processes enables its application in large-scale SPAD arrays. Attached Figure Description

[0015] Figure 1 This is an overall schematic diagram of the circuit structure of the present invention, including an active quenching circuit, a delay inverter, a NOR gate, and a shaping circuit, which consists of a SPAD, eight PMOS transistors, and eight NMOS transistors.

[0016] Figure 2 This is a functional simulation diagram of the delayed inverter of the present invention. The input signal IN passes through a circuit structure composed of PM2, PM3, and NM3 to obtain the output signal OUT. The delay time t can be changed... Figure 1 The gate voltage VM of transistor PM2 is used for regulation.

[0017] Figure 3 This is the simulation result diagram corresponding to Embodiment 1 of the present invention, where the VM voltage value is set to 0.65V, the delay of the delay inverter is 10ns, and the final output is a 10ns pulse, each pulse representing that the SPAD has detected a photon.

[0018] Figure 4 This is the simulation result diagram corresponding to Embodiment 2 of the present invention, where the VM voltage value is set to 1V, the delay of the delay inverter is 4ns, and the final output is a 4ns pulse, each pulse representing that the SPAD has detected a photon. Detailed Implementation

[0019] This invention provides a circuit structure and method for quenching and shaping SPAD devices, the circuit schematic is shown below. Figure 1As shown, the circuit mainly includes an active quenching circuit, a delay inverter, a NOR gate, and a shaping circuit. The active quenching circuit consists of P-type transistors PM0 and PM1 and N-type transistors NM0, NM1, and NM2. A SPAD device is connected to the drain of transistor NM0 and the gate of NM1 as input terminals. The signal at the drain of transistor NM1 is output through an inverter formed by PM1 and NM2. The delay inverter consists of P-type transistors PM2 and PM3 and N-type transistor NM3. A high-level signal generated by the active quenching circuit is input to the gate of transistors PM3 and NM3, generating a low-level signal with a certain time delay at the drain of transistors PM3 and NM3. The NOR gate circuit is composed of P-type transistors PM4 and PM5 and N-type transistors NM4 and NM5. The gate terminal connected to transistors PM4 and NM5 is the first input terminal, the gate terminal connected to transistors PM5 and NM4 is the second input terminal, and the drain terminal connected to transistors PM5, NM4 and NM5 is the output terminal. The shaping circuit is composed of two-stage inverters consisting of P-type transistors PM6 and NM6 and P-type transistors PM7 and NM7. The gate terminal connected to transistors PM6 and NM6 is the input terminal, and the drain terminal connected to transistors PM7 and NM7 is the output terminal.

[0020] When a photon arrives at the SPAD, the device undergoes avalanche breakdown. The gate of transistor NM1 is connected to the high-level HV, thus turning it on. The drain outputs a low-level signal, which is then converted to a high-level signal by an inverter composed of transistors PM1 and NM2. This high-level signal is then output as a low-level signal with a certain time delay from the original signal by a delay inverter. These two high and low-level signals (i.e., the original high-level signal and the time-delayed low-level signal) are then passed through a NOR gate to generate a high-level pulse output. Finally, the pulse is shaped by a shaping circuit and ultimately output as a pulse signal indicating that the SPAD has detected a photon.

[0021] Furthermore, different levels of time delay can be achieved by adjusting the gate voltage VM of transistor PM2; by using the gate voltage signal GATE of the external transistor NM0 in the active quenching circuit, the voltage difference across the SPAD device can be autonomously adjusted to be below the avalanche voltage. That is, once a high-level signal is detected at the output terminal, the GATE signal can be pulled high to turn on transistor NM0, and the drain voltage is reduced to 0V, thereby resetting the device from the avalanche breakdown state and achieving active quenching.

[0022] Functional simulation of the circuit structure of this invention was performed. To prevent damage to the SPAD from prolonged avalanche state during actual use, the GATE signal was set to a 50MHz clock signal, limiting the duration of the SPAD avalanche state to within 10ns. During simulation, the HV terminal was connected to a 1.2V high level, and the GATE terminal was given a periodic signal of 10ns high level and 10ns low level (i.e., a 20ns period) to verify the active quenching function: when the GATE is high level, the transistor NM0 is turned on, and the drain voltage is reduced to 0V, thereby resetting the device from the avalanche breakdown state and realizing active quenching; when the GATE is low level, when the SPAD detects a photon and avalanche breakdown occurs, the gate terminal of the transistor NM1 is pulled to HV and turned on, and the circuit works normally. Assuming that the applied voltage VM at the gate of transistor PM2 can achieve a time delay of t, the electrical signal generated by the photon detected by SPAD will eventually output a pulse signal after being processed by the active quenching circuit, inverter, delay inverter, NOR gate and shaping circuit.

[0023] Example 1

[0024] In this embodiment, a 50MHz clock signal is applied to the GATE terminal, a 1.2V high level is connected to the HV terminal, and the VM terminal voltage is 0.65V for simulation. A schematic diagram of the simulation conditions and results is shown below. Figure 3 As shown.

[0025] Figure 3 The top arrow indicates the time point when the photon arrives at the SPAD. The first line shows the voltage waveform at the GATE port, with each high and low level lasting 10ns. The second line shows the gate voltage change waveform of transistor NM1. It can be seen that when GATE is high, the gate of transistor NM1 is forcibly pulled low by the activated NM0. During this time, the SPAD is in a quenched state and cannot detect photons, so photons arriving during this period will not generate a pulse output. When GATE becomes low, the SPAD works normally. When a photon arrives, the SPAD undergoes avalanche breakdown, and the gate of transistor NM1 is pulled to HV high, allowing the subsequent circuit to start working normally. The third line shows the output waveform of the quenching circuit. Since the drain voltage and gate voltage of transistor NM1 are out of phase, after passing through the inverter composed of transistors PM1 and NM2, they are in phase with the gate voltage, so the waveform is consistent with the second line. The fourth line shows the output waveform of the delay inverter. In this embodiment, the delay time corresponding to the 0.65V VM voltage value is 10ns, i.e., t1 in the figure. The last line is the output OUT signal waveform, which is the result of performing a OR operation on the output of the quenching circuit and the output of the delay inverter, and then shaping it.

[0026] As can be seen, when the SPAD and circuit are working normally (i.e., GATE is low), each arriving photon will generate a corresponding output pulse. However, it is worth noting that the delay time of the delay inverter in this embodiment is relatively long (exceeding the high-level width of the quenching circuit output), so the width of the output pulse (i.e., t2 in the figure) is consistent with the output of the quenching circuit, and is not fixed.

[0027] Example 2

[0028] In this embodiment, a 50MHz clock signal is applied to the GATE terminal, a 1.2V high level is connected to the HV terminal, and the VM terminal voltage is 1V for simulation. A schematic diagram of the simulation conditions and results is shown below. Figure 4 As shown.

[0029] Figure 4 The top arrow indicates the time point when the photon arrives at the SPAD. The first line shows the voltage waveform at the GATE port, with each high and low level lasting 10ns. The second line shows the gate voltage change waveform of transistor NM1. It can be seen that when GATE is high, the gate of transistor NM1 is forcibly pulled low by the enabled NM0. During this time, the SPAD is in a quenched state and cannot detect photons, so photons arriving during this period will not generate a pulse output. When GATE becomes low, the SPAD works normally. When a photon arrives, the SPAD undergoes avalanche breakdown, and the gate of transistor NM1 is pulled to HV high, allowing the subsequent circuit to start working normally. The third line shows the output waveform of the quenching circuit. Since the drain voltage and gate voltage of transistor NM1 are out of phase, after passing through the inverter composed of transistors PM1 and NM2, they are in phase with the gate voltage, so the waveform is consistent with the second line. The fourth line shows the output waveform of the delay inverter. In this embodiment, the delay time corresponding to a 1V VM voltage value is 4ns, i.e., t1 in the figure. The last line is the output OUT signal waveform, which is the result of performing a OR operation on the output of the quenching circuit and the output of the delay inverter, and then shaping it.

[0030] As can be seen, when the SPAD and circuit are working normally (i.e., GATE is low), each arriving photon will generate a corresponding output pulse. However, it is worth noting that in this embodiment, the delay time of the delay inverter is relatively short, so the width of the output pulse (i.e., t2 in the figure) is consistent with the delay time t1 of the delay inverter (i.e., t...). 1＝ t2) is fixed.

Claims

1. A circuit for quenching and shaping SPAD devices, comprising an active quenching circuit, a delayed inverter, a NOR gate, and a shaping circuit, characterized in that, The active quenching circuit receives the avalanche signal generated by photons detected by the SPAD device and outputs a high level; the delay inverter is used to generate a low level signal with a certain delay from the output of the active quenching circuit; the NOR gate performs NOR logic processing on the outputs of the active quenching circuit and the delay inverter and generates a pulse output; the shaping circuit is used to shape the pulse output. The active quenching circuit is composed of P-type transistors PM0 and PM1 and N-type transistors NM0, NM1 and NM2. The SPAD device is connected to the drain terminal of transistor NM0 and the gate terminal of transistor NM1 as the input terminal. The drain terminal signal of transistor NM1 is output through an inverter composed of transistors PM1 and NM2. The drain terminal of transistor PM0 is connected to the drain terminal of transistor NM1. The delay inverter is composed of P-type transistors PM2 and PM3 and N-type transistor NM3. A high-level signal generated by the active quenching circuit is input to the gate terminal of transistors PM3 and NM3, which will generate a low-level signal with a certain time delay from the original signal at the drain terminal of transistors PM3 and NM3. The drain terminal of transistor PM2 is connected to the source terminal of transistor PM3. The NOR gate is composed of P-type transistors PM4 and PM5 and N-type transistors NM4 and NM5. The gate terminal connected to transistors PM4 and NM5 is the first input terminal, the gate terminal connected to transistors PM5 and NM4 is the second input terminal, and the drain terminal connected to transistors PM5, NM4 and NM5 is the output terminal. The shaping circuit consists of P-type transistors PM6 and PM7 and N-type transistors NM6 and NM7. The gate terminals of transistors PM6 and NM6 are connected as input terminals, and the drain terminals of transistors PM7 and NM7 are connected as output terminals. Transistors PM6 and NM6 form the first-stage inverter, and transistors PM7 and NM7 form the second-stage inverter.

2. The quenching and shaping method using the circuit for quenching and shaping of SPAD devices as described in claim 1, characterized in that, The steps of this method are as follows: When a photon arrives at the SPAD device, avalanche breakdown occurs. The gate of transistor NM1 is connected to a high level and thus turns on, while its drain outputs a low level. This low level signal is then converted to a high level by the inverter in the active quenching circuit. This high-level signal is then converted to a low-level signal with a certain time delay by the delay inverter. The high-level and low-level signals are then passed through the NOR gate to generate a high-level pulse output. Finally, the pulse is shaped by the shaping circuit and output as a pulse signal indicating that the SPAD device has detected a photon.

3. The quenching and shaping method for a circuit used in quenching and shaping of SPAD devices according to claim 2, characterized in that, The delay inverter is composed of P-type transistors PM2 and PM3 and N-type transistor NM3. Different levels of delay are achieved by adjusting the gate voltage VM of transistor PM2.

4. The quenching and shaping method for a circuit used in quenching and shaping of SPAD devices according to claim 2, characterized in that, The active quenching circuit consists of P-type transistors PM0 and PM1 and N-type transistors NM0, NM1, and NM2. The SPAD device is connected to the drain of transistor NM0 and the gate of NM1 as input terminals. The drain signal of transistor NM1 is output through an inverter composed of transistors PM1 and NM2. The voltage difference across the SPAD device is autonomously adjusted to below the avalanche voltage by the gate voltage signal GATE of transistor NM0. That is, once a high-level signal is detected at the output terminal, the gate voltage signal GATE is pulled high, which turns on transistor NM0 and reduces the drain voltage to 0V, thereby resetting the device from the avalanche breakdown state and realizing active quenching.

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