A test system and test method for passive crystal oscillator

Abstract

The application provides a passive crystal oscillator testing system and testing method, the system comprises a programmable logic chip, a crystal oscillator unit and a comparator; the input end of the programmable logic chip is connected with the first input end of the comparator; the output end of the crystal oscillator unit is connected with the second input end of the comparator; the output end of the comparator is connected with the signal input end of the programmable logic chip; the programmable logic chip selects a reference voltage, collects a to-be-tested signal generated by the passive crystal oscillator unit, and inputs the reference voltage and the to-be-tested signal into the comparator; the comparator is used for comparing the reference voltage and the to-be-tested signal to obtain two trigger signals; the programmable logic chip records the trigger time corresponding to the two trigger signals; and the frequency of the crystal oscillator is determined according to the two trigger times. Based on the testing system, a passive crystal oscillator testing method is provided. The frequency is calculated through the time difference between the two trigger levels, the frequency is displayed on the digital tube in real time, and the testing period is greatly shortened by matching the adjustable capacitor.

Description

Technical Field

[0001] This invention belongs to the field of passive crystal oscillator testing technology, and specifically relates to a passive crystal oscillator testing system and testing method. Background Technology

[0002] The explosive popularity of ChatGPT has once again driven the development of AI technology. This rapid development relies heavily on the support of hardware devices such as servers, and it's foreseeable that servers will see even greater demand in the future market. Passive crystal oscillators are an essential component of server hardware circuits, providing the motherboard system with basic clock signals to ensure normal circuit operation. Due to the uninterrupted operation of servers, their stability is of paramount importance; therefore, evaluating the performance parameters of passive crystal oscillators is crucial.

[0003] A passive crystal oscillator, also known as a quartz crystal resonator, is essentially a quartz crystal resonator. Crystal oscillators are a general term for both quartz crystal units and crystal oscillators. They are primarily used in various electronic circuits to generate frequencies. A passive crystal oscillator is a non-polarized component with two pins that requires a clock circuit to generate an oscillation signal; it cannot oscillate on its own. Passive crystal oscillators are available in through-hole and surface-mount types. Passive crystal oscillators have three important parameters: frequency offset, negative impedance, and excitation power. In server hardware testing, these three points are evaluated. Frequency offset indicates the accuracy of the frequency in the circuit; if the frequency offset is too large, it will cause clock instability and data reception errors. Negative impedance represents the oscillation capability of the passive crystal oscillator; the larger this parameter, the better the performance. Excitation power is the power in the passive crystal oscillator circuit; an excessively large value can shorten the lifespan of the passive crystal oscillator. Server motherboards contain numerous passive crystal oscillators, each requiring testing of three parameters. Traditional passive probes contact the circuit during testing, introducing capacitive interference and resulting in inaccurate test results. Traditional testing methods cannot adjust the load capacitance during frequency testing, often requiring the replacement of capacitors after frequency measurement, significantly increasing time costs. Current technology necessitates continuously replacing capacitors in the circuit to adjust the frequency, and desoldering resistors and connecting copper wires to the passive crystal oscillator to test negative impedance and excitation power. This is difficult to operate, time-consuming, and prone to damaging the circuit board if handled improperly. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a testing system and method for passive crystal oscillators. In this invention, the substrate management controller acquires the loop current via a PMBus, which offers advantages over existing testing methods, providing more accurate current measurements and reducing testing costs.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A test system for a passive crystal oscillator includes a programmable logic chip, a passive crystal oscillator unit, and a comparator;

[0007] The power input terminal of the programmable logic chip is connected to the first input terminal of the comparator; the signal output terminal of the passive crystal oscillator unit is connected to the second input terminal of the comparator; the output terminal of the comparator is connected to the signal input terminal of the programmable logic chip.

[0008] The programmable logic chip is used to select a reference voltage, convert the reference voltage into an analog-to-digital signal, and input it to the first input terminal of the comparator; and to acquire the test signal generated by the passive crystal oscillator unit, and input the test signal to the second input terminal of the comparator; the comparator is used to compare the reference voltage and the test signal and obtain a first trigger signal and a second trigger signal; the programmable logic chip records the first time of the first trigger signal and the second time of the second trigger signal; and determines the passive crystal oscillator frequency based on the first time and the second time.

[0009] Furthermore, the passive crystal oscillator unit consists of a crystal oscillator module, multiple resistors, multiple capacitors, and multiple CMOS inverters;

[0010] The output of the first CMOS inverter is connected to the input of the second CMOS inverter;

[0011] A first resistor Rf is connected between the first input and the output of the first CMOS inverter. A crystal oscillator module, a second resistor Rs, and a third resistor Rd are connected in series between the second input and the output of the first CMOS inverter. The third input of the first CMOS inverter is grounded through a first capacitor Cg. The output of the first CMOS inverter is grounded through a third resistor Rd and a second capacitor Cd. The output of the second CMOS inverter is connected to an uplink device.

[0012] Furthermore, the testing system also includes a digital-to-analog converter;

[0013] The digital voltage signal output from the power input terminal of the programmable logic chip is converted into an analog signal by a digital-to-analog converter and input to the first input terminal of the comparator.

[0014] Furthermore, the testing system also includes a first display module; the first display module adopts a digital tube display;

[0015] The output of the programmable logic chip is connected to a digital tube display; the digital tube display is used to display the current frequency offset.

[0016] Furthermore, the formula for determining the passive crystal oscillator frequency based on the first time and the second time is as follows:

[0017] f = 1 / (T2-T1);

[0018] Where f is the passive crystal oscillator frequency; T2 is the second time; and T1 is the first time.

[0019] Furthermore, the first resistor Rf, the second resistor Rs, and the third resistor Rd are all adjustable resistors; the first capacitor Cg and the second capacitor Cd are both adjustable capacitors.

[0020] Furthermore, the test system also includes a substrate management controller;

[0021] The substrate management controller is connected to the current output terminal of the passive crystal oscillator unit; it is used to monitor the current in the passive crystal oscillator unit circuit and calculate the excitation power of the passive crystal oscillator unit based on the current in the circuit.

[0022] The excitation power is calculated as follows: P = I 2 *Rd; where I is the current in the passive crystal oscillator unit circuit.

[0023] Furthermore, the baseboard management controller is connected to the second display module via two GPIO signals; the second display module uses LED lights.

[0024] The substrate management controller is used to set the maximum current I. max and minimum current I min When the current I in the passive crystal oscillator unit circuit is between the maximum current threshold I... max and minimum current threshold I min During this period, the baseboard management controller pulls one GPIO signal high and the other GPIO signal low; at this time, the LED indicator shows the normal status.

[0025] When the current I in the circuit is greater than the maximum current threshold I max The baseboard management controller pulls both GPIO signals high, at which point the LED display status is abnormal; when the second display module displays an abnormal status, the third resistor Rd is increased to restore the LED display status to normal.

[0026] Furthermore, based on the calculation of the excitation power of the passive crystal oscillator unit, the second resistor Rs is increased. When the second display module is observed to change from the normal state to the intermediate state, the value of the second resistor Rs at this time is recorded as a negative impedance.

[0027] This invention also proposes a testing method for a passive crystal oscillator, which is based on the aforementioned testing system for a passive crystal oscillator, and includes the following steps:

[0028] The reference voltage is selected by a programmable logic chip, and after digital-to-analog conversion, the reference voltage is input to the first input terminal of the comparator; and the test signal generated by the passive crystal oscillator unit is acquired and input to the second input terminal of the comparator.

[0029] The reference voltage and the signal under test are compared by a comparator to obtain the result with the first trigger signal and the second trigger signal.

[0030] The first time of the first trigger signal and the second time of the second trigger signal are recorded by a programmable logic chip; the passive crystal oscillator frequency is determined based on the first time and the second time.

[0031] The effects described in the invention are merely those of the embodiments, and not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects:

[0032] This invention proposes a testing system and method for passive crystal oscillators. The system includes: a programmable logic chip, a passive crystal oscillator unit, and a comparator; the power input terminal of the programmable logic chip is connected to the first input terminal of the comparator; the signal output terminal of the passive crystal oscillator unit is connected to the second input terminal of the comparator; the output terminal of the comparator is connected to the signal input terminal of the programmable logic chip; the programmable logic chip is used to select a reference voltage, convert the reference voltage to analog-to-digital conversion, and input it to the first input terminal of the comparator; it also collects the test signal generated by the passive crystal oscillator unit and inputs the test signal to the second input terminal of the comparator; the comparator is used to compare the reference voltage and the test signal to obtain a first trigger signal and a second trigger signal; the programmable logic chip records the first time of the first trigger signal and the second time of the second trigger signal; and the passive crystal oscillator frequency is determined based on the first time and the second time. Based on the testing system for passive crystal oscillators, a testing method for passive crystal oscillators can also be proposed. This invention uses a programmable logic chip to collect trigger levels, calculates the frequency using the time difference between two trigger levels, and displays the frequency in real time on a digital tube. Combined with an adjustable capacitor, this significantly shortens the testing cycle. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the connection of a test system for a passive crystal oscillator according to Embodiment 1 of the present invention;

[0034] Figure 2 The waveform diagram of the passive crystal oscillator frequency proposed in Embodiment 1 of the present invention;

[0035] Figure 3 This is a flowchart of a test method for a passive crystal oscillator proposed in Embodiment 2 of the present invention. Detailed Implementation

[0036] To clearly illustrate the technical features of this solution, the invention will be described in detail below through specific embodiments and in conjunction with the accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure of the invention, components and arrangements of specific examples are described below. Furthermore, reference numerals and / or letters may be repeated in different examples. This repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. It should be noted that the components illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components, processing techniques, and processes are omitted in this invention to avoid unnecessarily limiting the invention.

[0037] Example 1

[0038] Embodiment 1 of this invention proposes a test system for a passive crystal oscillator. The substrate management controller collects the loop current through the PMBus, which has advantages over the existing test methods. Not only is the measured current more accurate, but the test cost is also reduced.

[0039] FPGA: Field Programmable Gate Array;

[0040] BMC: Baseboard Management Controller.

[0041] The FPGA uses a comparator to acquire the waveform of the passive crystal oscillator and obtain the time between two trigger levels. The frequency of the passive crystal oscillator is calculated by the time difference between the two levels. At the same time, the FPGA inputs the acquired frequency value into the digital tube display to visualize the frequency value. Adjustable capacitors are used in the circuit instead of ordinary capacitors, which can quickly adjust the frequency value.

[0042] The current value of the passive crystal oscillator circuit is monitored in real time by the BMC, and the current value is displayed by adjusting the LED light color through GPIO. The resistance values ​​of the two adjustable resistors can be changed to control the current value in real time, and the excitation power and negative impedance are calculated.

[0043] The EEPROM memory is used to store the current value tested in the circuit. When the resistance in the circuit is modified and the current changes, the EEPROM continues to store the new test value and calculates the excitation power based on the actual measurement.

[0044] Figure 1 This is a schematic diagram of the connection of a test system for a passive crystal oscillator according to Embodiment 1 of the present invention; the system includes a programmable logic chip, a passive crystal oscillator unit, and a comparator;

[0045] The power input terminal of the programmable logic chip is connected to the first input terminal of the comparator; the signal output terminal of the passive crystal oscillator unit is connected to the second input terminal of the comparator; the output terminal of the comparator is connected to the signal input terminal of the programmable logic chip.

[0046] The programmable logic chip is used to select a reference voltage, convert the reference voltage into an analog-to-digital signal, and input it to the first input terminal of the comparator; and to acquire the test signal generated by the passive crystal oscillator unit, and input the test signal to the second input terminal of the comparator; the comparator is used to compare the reference voltage and the test signal and obtain a first trigger signal and a second trigger signal; the programmable logic chip records the first time of the first trigger signal and the second time of the second trigger signal; and determines the passive crystal oscillator frequency based on the first time and the second time.

[0047] The passive crystal oscillator unit consists of a crystal oscillator module, multiple resistors, multiple capacitors, and multiple CMOS inverters. The output of the first CMOS inverter is connected to the input of the second CMOS inverter. A first resistor Rf is connected between the first input and the output of the first CMOS inverter. The crystal oscillator module, a second resistor Rs, and a third resistor Rd are connected in series between the second input and the output of the first CMOS inverter. The third input of the first CMOS inverter is grounded through a first capacitor Cg. The output of the first CMOS inverter is grounded through a third resistor Rd and a second capacitor Cd. The output of the second CMOS inverter is connected to the uplink device.

[0048] In this application, the output terminal of the second CMOS inverter of the passive crystal oscillator unit is connected to the main chip module, i.e., the uplink device.

[0049] The testing system also includes a digital-to-analog converter; the digital voltage signal output from the power input terminal of the programmable logic chip is converted into an analog signal by the digital-to-analog converter and input to the first input terminal of the comparator.

[0050] The testing system also includes a first display module; the first display module uses a digital tube display; the output of the programmable logic chip is connected to the digital tube display; the digital tube display is used to display the current frequency offset.

[0051] After the device is powered on, the FPGA selects 0.5V as the reference voltage, denoted as the first voltage V. m The digital signal is converted into an analog signal by a DAC and input to a comparator. Simultaneously, a passive crystal oscillator sine wave signal is acquired and input to the comparator. The reference voltage is compared with the signal under test to obtain two trigger signals. The FPGA records the times of the two trigger signals, T1 and T2, and calculates the frequency f = 1 / (T2-T1). Figure 2 This is the passive crystal oscillator frequency waveform diagram proposed in Embodiment 1 of the present invention. The FPGA displays the current frequency value in real time through a digital tube display. The display consists of six digital tubes, and a dynamic display method is used. Within 1 ms, the first digital tube is lit up; within 2 ms, the second digital tube is lit up; and so on, until the sixth digital tube is lit up within 6 ms. Utilizing the persistence of vision, since each LED module is lit for a relatively short time, it appears to the human eye that the six digital tubes are displaying different numbers simultaneously. If the display frequency exceeds the frequency deviation requirement, the adjustable capacitors Cd and Cg in the circuit are manually adjusted until the frequency deviation requirement is met.

[0052] The first resistor Rf, the second resistor Rs, and the third resistor Rd are all adjustable resistors; the first capacitor Cg and the second capacitor Cd are both adjustable capacitors.

[0053] The testing system also includes a substrate management controller;

[0054] The substrate management controller is connected to the current output terminal of the passive crystal oscillator unit; it is used to monitor the current in the passive crystal oscillator unit circuit and calculate the excitation power of the passive crystal oscillator unit based on the current in the circuit.

[0055] The excitation power is calculated as follows: P = I 2 *Rd; where I is the current in the passive crystal oscillator unit circuit.

[0056] The baseboard management controller is connected to the second display module via two GPIO signals; the second display module uses LEDs.

[0057] The substrate management controller is used to set the maximum current I. max and minimum current I min When the current I in the passive crystal oscillator unit circuit is between the maximum current threshold I... max and minimum current threshold I min During this period, the baseboard management controller pulls one GPIO signal high and the other GPIO signal low; at this time, the LED indicator shows the normal status.

[0058] When the current I in the circuit is greater than the maximum current threshold I maxThe baseboard management controller pulls both GPIO signals high, at which point the LED display status is abnormal; when the second display module displays an abnormal status, the third resistor Rd is increased to restore the LED display status to normal.

[0059] Adjust Rs to 0 to ensure the excitation power test is not affected. The BMC module collects the passive crystal oscillator circuit current through PMBus, sets the current threshold value, and sets the maximum current to Imax and the minimum current to Imin. When the detected current is greater than Imax, the BMC pulls P1 and P0 high (i.e., I1), and the LED turns red. Manually adjust Rd to make the LED green, store the value of I at this time in EEPROM, and record the value of Rd at this time. The excitation power is P = I. 2 *Rd.

[0060] Based on the calculated excitation power of the passive crystal oscillator unit, the second resistor Rs is increased. When the second display module changes from the normal state to the intermediate state, the value of the second resistor Rs at this time is recorded as a negative impedance. Rs is increased further, and the color of the LED is observed. When it changes from green to yellow, the value of Rs at this time is recorded; this value is the negative impedance.

[0061] The passive crystal oscillator testing system proposed in Embodiment 1 of this invention uses an FPGA to acquire trigger levels and calculates the frequency by the time difference between two trigger levels. This application has advantages over the method of directly using a probe for testing. On the one hand, traditional passive probes will contact the circuit during testing, introducing capacitive interference to the circuit and causing inaccurate test results. On the other hand, traditional testing schemes cannot adjust the load capacitor when testing the frequency. Often, after measuring the frequency, a capacitor needs to be found and soldered to match the actual test results, which undoubtedly increases the time cost. By using an FPGA to display the frequency on a digital tube in real time, and with the addition of an adjustable capacitor, the testing cycle is greatly shortened.

[0062] The passive crystal oscillator testing system proposed in Embodiment 1 of this invention has significant advantages over previous testing systems. Traditional testing methods require connecting the passive crystal oscillator to the motherboard via wires and stringing a current probe between them. This method is very cumbersome. Some low-frequency passive crystal oscillators (k-level) have very high impedance and very small current in the circuit, requiring more sophisticated testing instruments, which are very expensive. The BMC collects the circuit current through the PMBus, which not only provides more accurate current measurements but also reduces testing costs.

[0063] Example 2

[0064] Based on the passive crystal oscillator testing system proposed in Embodiment 1 of the present invention, Embodiment 2 of the present invention also proposes a passive crystal oscillator testing method.

[0065] The FPGA uses a comparator to acquire the waveform of the passive crystal oscillator and obtain the time between two trigger levels. The frequency of the passive crystal oscillator is calculated by the time difference between the two levels. At the same time, the FPGA inputs the acquired frequency value into the digital tube display to visualize the frequency value. Adjustable capacitors are used in the circuit instead of ordinary capacitors, which can quickly adjust the frequency value.

[0066] The current value of the passive crystal oscillator circuit is monitored in real time by the BMC, and the current value is displayed by adjusting the LED light color through GPIO. The resistance values ​​of the two adjustable resistors can be changed to control the current value in real time, and the excitation power and negative impedance are calculated.

[0067] The EEPROM memory is used to store the current value tested in the circuit. When the resistance in the circuit is modified and the current changes, the EEPROM continues to store the new test value and calculates the excitation power based on the actual measurement.

[0068] Figure 3 This is a flowchart of a test method for a passive crystal oscillator proposed in Embodiment 2 of the present invention.

[0069] In step S300, the device is powered on.

[0070] In step S301, the FPGA selects 0.5V as the reference voltage, denoted as the first voltage V. m The digital signal is converted into an analog signal by a DAC and input to a comparator. Simultaneously, a passive crystal oscillator sine wave signal is acquired and input to the comparator. The comparator compares the reference voltage with the signal under test to obtain two trigger signals: the first trigger signal and the second trigger signal.

[0071] In step S302, the programmable logic chip records the first time of the first trigger signal and the second time of the second trigger signal; the passive crystal oscillator frequency is determined based on the first time and the second time.

[0072] f = 1 / (T2-T1);

[0073] Where f is the passive crystal oscillator frequency; T2 is the second time; and T1 is the first time.

[0074] The FPGA displays the current frequency value in real time through a digital tube display. The display consists of six digital tubes and uses a dynamic display method. Within the first 1ms, the first digital tube is lit up; within the second 2ms, the second digital tube is lit up; and so on, until the sixth digital tube is lit up within the sixth 6ms. Taking advantage of the persistence effect of the human eye, since each LED module is lit for a relatively short time, it appears to the human eye that the six digital tubes are displaying different numbers at the same time.

[0075] In step S303, it is determined whether the passive crystal oscillator frequency meets the requirements. If it does not meet the requirements, step S304 is executed. If it meets the requirements, step S305 is executed.

[0076] In step S304, the adjustable capacitors Cd and Cg in the circuit are manually adjusted until the frequency deviation requirement is met, and then the process returns to step S301.

[0077] In step S305, the current frequency is recorded as the passive crystal oscillator frequency.

[0078] In step S306, determine whether Rs is 0. If it is not 0, proceed to step S307; if it is 0, proceed to step S308.

[0079] In step S307, Rs is adjusted to 0. To ensure that the excitation power test is not affected, the BMC module collects the passive crystal oscillator circuit current through PMBus, sets the current threshold value, sets the maximum current to Imax and the minimum current to Imin. When the detected current is greater than Imax, the BMC pulls P1 and P0 high, i.e., I1, and the LED turns red. Rd is manually adjusted to make the LED turn green.

[0080] In step S308, observe the color status of the LED light.

[0081] In step S309, it is determined whether the LED light is displaying a normal green color. If it is green, step S310 is executed; otherwise, step S311 is executed.

[0082] In step S310, Rd is reduced.

[0083] In step S311, the current in the passive crystal oscillator unit circuit is monitored, and the excitation power of the passive crystal oscillator unit is calculated based on the current in the circuit.

[0084] The excitation power is calculated as follows: P = I 2 *Rd; where I is the current in the passive crystal oscillator unit circuit.

[0085] In step S312, based on the calculated excitation power of the passive crystal oscillator unit, the second resistor Rs is increased. When the second display module changes from the normal state to the intermediate state, the value of the second resistor Rs at this time is recorded as a negative impedance. Rs is increased, and the color of the LED is observed.

[0086] In step S313, Rs is an adjustable resistor. When testing the excitation power, this value needs to be adjusted to 0 to avoid affecting the actual test results. Similarly, the BMC detects the current in the circuit through the PMBus, increases Rs, and makes the current in the circuit lower than Imin. At this time, the BMC pulls both P1 and P0 low, making the LED yellow. The value of Rs at this time is recorded, which is the negative impedance.

[0087] In step S314, the test is completed and the process ends.

[0088] The passive crystal oscillator testing method proposed in this invention is implemented based on a passive crystal oscillator testing system, which specifically includes: a programmable logic chip, a passive crystal oscillator unit, and a comparator;

[0089] The power input terminal of the programmable logic chip is connected to the first input terminal of the comparator; the signal output terminal of the passive crystal oscillator unit is connected to the second input terminal of the comparator; the output terminal of the comparator is connected to the signal input terminal of the programmable logic chip.

[0090] The programmable logic chip is used to select a reference voltage, convert the reference voltage into an analog-to-digital signal, and input it to the first input terminal of the comparator; and to acquire the test signal generated by the passive crystal oscillator unit, and input the test signal to the second input terminal of the comparator; the comparator is used to compare the reference voltage and the test signal and obtain a first trigger signal and a second trigger signal; the programmable logic chip records the first time of the first trigger signal and the second time of the second trigger signal; and determines the passive crystal oscillator frequency based on the first time and the second time.

[0091] The passive crystal oscillator unit consists of a crystal oscillator module, multiple resistors, multiple capacitors, and multiple CMOS inverters. The output of the first CMOS inverter is connected to the input of the second CMOS inverter. A first resistor Rf is connected between the first input and the output of the first CMOS inverter. The crystal oscillator module, a second resistor Rs, and a third resistor Rd are connected in series between the second input and the output of the first CMOS inverter. The third input of the first CMOS inverter is grounded through a first capacitor Cg. The output of the first CMOS inverter is grounded through a third resistor Rd and a second capacitor Cd. The output of the second CMOS inverter is connected to the uplink device.

[0092] The testing system also includes a digital-to-analog converter; the digital voltage signal output from the power input terminal of the programmable logic chip is converted into an analog signal by the digital-to-analog converter and input to the first input terminal of the comparator.

[0093] The testing system also includes a first display module; the first display module uses a digital tube display; the output of the programmable logic chip is connected to the digital tube display; the digital tube display is used to display the current frequency offset.

[0094] The test system also includes a substrate management controller; the substrate management controller is connected to the current output terminal of the passive crystal oscillator unit; it is used to monitor the current in the circuit of the passive crystal oscillator unit and calculate the excitation power of the passive crystal oscillator unit based on the current in the circuit.

[0095] The baseboard management controller is connected to the second display module via two GPIO signals; the second display module uses LED lights.

[0096] In this application, the output terminal of the second CMOS inverter of the passive crystal oscillator unit is connected to the main chip module, i.e., the uplink device.

[0097] The baseboard management controller is connected to the second display module via two GPIO signals; the second display module uses LEDs.

[0098] The board management controller is used to set the maximum current I. max and minimum current I min When the current I in the passive crystal oscillator unit circuit is between the maximum current threshold I... max and minimum current threshold I min During this period, the baseboard management controller pulls one GPIO signal high and the other GPIO signal low; at this time, the LED indicator shows the normal status.

[0099] When the current I in the circuit is greater than the maximum current threshold I max The baseboard management controller pulls both GPIO signals high, at which point the LED display status is abnormal; when the second display module displays an abnormal status, the third resistor Rd is increased to restore the LED display status to normal.

[0100] The present invention provides a test method for a passive crystal oscillator in Embodiment 2. The FPGA acquires the trigger level, calculates the frequency by the time difference between two trigger levels, and displays the frequency on a digital tube in real time through the FPGA. With the help of an adjustable capacitor, the test cycle is greatly shortened.

[0101] The passive crystal oscillator testing method proposed in Embodiment 2 of this invention uses a PMBus to collect the circuit current of the BMC, which not only makes the measured current more accurate, but also reduces the testing cost.

[0102] For a description of the relevant parts of the passive crystal oscillator testing method provided in this application embodiment, please refer to the detailed description of the corresponding parts of the passive crystal oscillator testing system provided in embodiment 1 of this application, which will not be repeated here.

[0103] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0104] While specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art can make other modifications or variations based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A testing system for a passive crystal oscillator, characterized in that, Includes programmable logic chips, passive crystal oscillators, and comparators; The power input terminal of the programmable logic chip is connected to the first input terminal of the comparator; the signal output terminal of the passive crystal oscillator unit is connected to the second input terminal of the comparator; the output terminal of the comparator is connected to the signal input terminal of the programmable logic chip. The programmable logic chip is used to select a reference voltage and input the reference voltage into the first input terminal of the comparator after digital-to-analog conversion. The system acquires the test signal generated by the passive crystal oscillator unit and inputs the test signal to the second input terminal of the comparator; the comparator is used to compare the reference voltage and the test signal to obtain a first trigger signal and a second trigger signal; the programmable logic chip records the first time of the first trigger signal and the second time of the second trigger signal; and determines the passive crystal oscillator frequency based on the first time and the second time. The testing system also includes a substrate management controller; The substrate management controller is connected to the current output terminal of the passive crystal oscillator unit to monitor the current in the passive crystal oscillator unit circuit and calculate the excitation power of the passive crystal oscillator unit based on the current in the circuit. The method for calculating the excitation power is as follows: ;in, This refers to the current in the passive crystal oscillator unit circuit. The baseboard management controller is connected to the second display module via two GPIO signals; the second display module uses LED lights. The substrate management controller is used to set the maximum current value. and minimum current ; When the current in the passive crystal oscillator unit circuit Between the maximum current threshold and minimum current threshold During this period, the baseboard management controller pulls one GPIO signal high and the other GPIO signal low; at this time, the LED indicator shows the normal status. When the current in the circuit Greater than the maximum current threshold The baseboard management controller pulls both GPIO signals high, at which point the LED display status is abnormal; when the second display module displays an abnormal status, the third resistor Rd is increased to restore the LED display status to normal. Based on the calculation of the excitation power of the passive crystal oscillator unit, the second resistor Rs is increased. When the second display module is observed to change from the normal state to the intermediate state, the value of the second resistor Rs at this time is recorded as a negative impedance.

2. The test system for a passive crystal oscillator according to claim 1, characterized in that, The passive crystal oscillator unit consists of a crystal oscillator module, multiple resistors, multiple capacitors, and multiple CMOS inverters; The output of the first CMOS inverter is connected to the input of the second CMOS inverter; A first resistor Rf is connected between the first input and the output of the first CMOS inverter. A crystal oscillator module, a second resistor Rs, and a third resistor Rd are connected in series between the second input and the output of the first CMOS inverter. The third input of the first CMOS inverter is grounded through a first capacitor Cg. The output of the first CMOS inverter is grounded through a third resistor Rd and a second capacitor Cd. The output of the second CMOS inverter is connected to an uplink device. The current value in the passive crystal oscillator unit circuit is monitored in real time by the BMC, and the current value is displayed by adjusting the LED light color through GPIO. The current value can be controlled in real time by changing the resistance values ​​of the second resistor Rs and the third resistor Rd, and the excitation power and negative impedance can be calculated.

3. The test system for a passive crystal oscillator according to claim 1, characterized in that, The testing system also includes a digital-to-analog converter; The digital voltage signal output from the power input terminal of the programmable logic chip is converted into an analog signal by a digital-to-analog converter and input to the first input terminal of the comparator.

4. The test system for a passive crystal oscillator according to claim 1, characterized in that, The testing system further includes a first display module; the first display module uses a digital tube display. The output of the programmable logic chip is connected to a digital tube display; the digital tube display is used to display the current frequency offset.

5. The test system for a passive crystal oscillator according to claim 1, characterized in that, The formula for determining the passive crystal oscillator frequency based on the first time and the second time is as follows: ； in, This is the frequency of the passive crystal oscillator; For the second time; For the first time.

6. The test system for a passive crystal oscillator according to claim 2, characterized in that, The first resistor Rf, the second resistor Rs, and the third resistor Rd are all adjustable resistors; the first capacitor Cg and the second capacitor Cd are both adjustable capacitors.

7. A method for testing a passive crystal oscillator, implemented based on a testing system for a passive crystal oscillator as described in any one of claims 1 to 6, characterized in that, Includes the following steps: The reference voltage is selected by a programmable logic chip, and after digital-to-analog conversion, the reference voltage is input to the first input terminal of the comparator; and the test signal generated by the passive crystal oscillator unit is acquired and input to the second input terminal of the comparator. The reference voltage and the signal under test are compared by a comparator to obtain the result with the first trigger signal and the second trigger signal. The first time of the first trigger signal and the second time of the second trigger signal are recorded by a programmable logic chip; the passive crystal oscillator frequency is determined based on the first time and the second time.

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