A memory access method, device, apparatus, and storage medium

Abstract

The application discloses a memory access method and device, equipment and a storage medium, and relates to the technical field of addressing. The method comprises the following steps: obtaining a physical address of a target entity memory and a logical address of a central processing unit; judging whether the physical address and the logical address intersect; if yes, determining the address of the intersection as a first address, and obtaining the address of the non-intersection as a second address; writing data in the target entity memory located in the first address to the logical address, or reading data in the logical address to the first address; writing the second address to a preset address register, and writing data in the target entity memory located in the second address to a preset data register corresponding to the address register, or reading data in the preset data register to the second address of the target entity memory. The application can enable the memory exceeding the size of the addressing space to be read and written, and reduce the complexity of the mapping relationship management.

Description

Technical Field

[0001] This application relates to the field of addressing technology, and in particular to a memory access method, apparatus, device and storage medium. Background Technology

[0002] Currently, when a CPU (Central Processing Unit) needs to retrieve data from external memory for computation, it typically uses address lines to determine which address to retrieve the required data from. For example, when a CPU has 32 address lines (32 bits), its maximum addressing range is 2^32, or 4GB. Within this range, the CPU can retrieve any data for computation. However, as firmware and application complexity increase, the demand for physical memory also grows. This can lead to situations where even a 32-bit CPU cannot fully address the memory, such as when the physical memory size is 8GB.

[0003] To address the aforementioned issues, the current mainstream approach is to access all physical memory either by directly increasing the CPU's address lines or through direct-address dynamic mapping. However, directly increasing CPU address lines increases chip cost, while direct-address dynamic mapping has the following drawbacks: ① It requires more mapping registers, resulting in higher chip costs. ② The management complexity of the mapping is high. For example, one logical space may be mapped to multiple physical spaces, or multiple logical spaces may be mapped to one physical space. This many-to-one or one-to-many relationship is not the intended functionality of firmware design, thus significantly increasing management complexity. Without proper management, troubleshooting becomes much more difficult when the program malfunctions. ③ Dynamic mapping can easily lead to situations where physical memory has available space but cannot be mapped to contiguous logical space. For example, if there are three logical spaces of 1GB each, totaling 3GB, and numbered L0, L1, and L2 (logical space 0-2), while the physical memory space is 8GB, divided into 1GB segments and numbered P0-P7 (physical space 0-7), the application initially uses mapping registers to achieve L0→P0, L1→P1, and L2→P2. Then, the application releases the mapping relationships of L0 and L2. At this point, when the application needs 2GB of physical space, since there is no contiguous 2GB of space in the logical space, the application will have no memory available, resulting in low access efficiency of the physical memory. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a memory access method, apparatus, device, and storage medium that enables memory exceeding the address space size to be read and written, while reducing the complexity of mapping management and chip cost. The specific solution is as follows:

[0005] In a first aspect, this application discloses a memory access method, including:

[0006] Obtain the physical address of the target entity's memory and the logical address of the central processing unit;

[0007] Determine whether there is an intersection between the physical address and the logical address;

[0008] If the physical address and the logical address intersect, then determine the address where the physical address and the logical address intersect to obtain the first address, and obtain the address in the physical address that does not intersect with the logical address to obtain the second address;

[0009] Write data located at the first address in the target physical memory to the logical address, or read data from the logical address to the first address located in the target physical memory;

[0010] Write the second address to a preset address register, and write the data located at the second address in the target physical memory to a preset data register corresponding to the address register, or read the data in the preset data register to the second address located in the target physical memory.

[0011] Optionally, the memory access method further includes:

[0012] The address access spaces of the target physical memory and the central processing unit are obtained respectively to obtain the physical space and the logical space;

[0013] Determine whether the size of the entity space exceeds the size of the logical space;

[0014] If the size of the entity space exceeds the size of the logical space, the entity space is divided according to the size of the logical space to obtain a first space with the same size as the logical space and a second space other than the first space;

[0015] The first space is mapped to the logical space to obtain the target mapping relationship, and the target mapping relationship is recorded in a preset mapping register.

[0016] Optionally, determining whether the physical address and the logical address have an intersection includes:

[0017] Based on the target mapping relationship recorded in the preset mapping register, it is determined whether there is an address in the physical address that corresponds to the logical address.

[0018] Optionally, dividing the entity space according to the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space includes:

[0019] The entity space is divided according to the order from low address to high address and based on the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space.

[0020] Optionally, the memory access method further includes:

[0021] The access frequencies of each region in the target entity's memory are statistically analyzed to obtain the memory access frequencies corresponding to each region.

[0022] Determine whether the memory access frequency corresponding to each region exceeds a preset frequency threshold;

[0023] If the memory access frequency exceeds the preset frequency threshold, the corresponding region is determined to be a frequently accessed region.

[0024] If the memory access frequency does not exceed the preset frequency threshold, the corresponding region is determined to be a non-frequent access region.

[0025] Optionally, dividing the entity space according to the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space includes:

[0026] The entity space is divided according to the size of the logical space and the preset frequency threshold to obtain a first space with the same size as the logical space and a second space other than the first space; wherein the first space is located in the frequent access area and the second space is located in the infrequent access area.

[0027] Optionally, mapping the first space to the logical space to obtain the target mapping relationship includes:

[0028] The first space is mapped to the logical space to obtain a target mapping relationship including the logical starting address, the physical starting address, and the mapping length.

[0029] Secondly, this application discloses a memory access device, comprising:

[0030] The address acquisition module is used to acquire the physical address of the target entity's memory and the logical address of the central processing unit.

[0031] The judgment module is used to determine whether there is an intersection between the physical address and the logical address;

[0032] The address determination module is used to determine the address where the physical address and the logical address intersect if there is an intersection between the physical address and the logical address, thereby obtaining the first address, and to obtain the address in the physical address that does not intersect with the logical address, thereby obtaining the second address.

[0033] The first data access module is used to write data located at the first address in the target physical memory to the logical address, or to read data in the logical address to the first address located in the target physical memory.

[0034] The second data access module is used to write the second address to a preset address register, and to write the data located at the second address in the target physical memory to a preset data register corresponding to the address register, or to read the data in the preset data register to the second address located in the target physical memory.

[0035] Thirdly, this application discloses an electronic device, including a processor and a memory; wherein, when the processor executes a computer program stored in the memory, it implements the aforementioned memory access method.

[0036] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned memory access method.

[0037] As can be seen, this application first obtains the physical address of the target physical memory and the logical address of the central processing unit, then determines whether the physical address and the logical address have an intersection. If the physical address and the logical address have an intersection, the address where the physical address and the logical address intersect are determined to obtain the first address, and the address in the physical address that does not intersect with the logical address is obtained to obtain the second address. Then, the data in the target physical memory located at the first address is written to the logical address, or the data in the logical address is read to the first address located in the target physical memory. The second address is then written to a preset address register, and the data in the target physical memory located at the second address is written to a preset data register corresponding to the address register, or the data in the preset data register is read to the second address located in the target physical memory. This application uses a preset address register and a preset data register to perform access operations on the target physical memory that exceeds the address space size, thereby enabling the memory that exceeds the address space size to be read and written, and reducing the complexity of mapping relationship management and chip cost. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] Figure 1 This is a flowchart of a memory access method disclosed in this application;

[0040] Figure 2 This is a schematic diagram illustrating a specific mapping relationship between logical space and entity space disclosed in this application;

[0041] Figure 3 This is a flowchart of a specific memory access method disclosed in this application;

[0042] Figure 4 This is a schematic diagram of a memory access device disclosed in this application;

[0043] Figure 5 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] This application discloses a memory access method, see [link to relevant documentation] Figure 1 As shown, the method includes:

[0046] Step S11: Obtain the physical address of the target physical memory and the logical address of the central processing unit.

[0047] In this embodiment, when a read request for the target physical memory is obtained, the physical address of the target physical memory and the logical address of the central processing unit (CPU) to be read are first obtained.

[0048] It should be noted that before obtaining the physical address of the target physical memory and the logical address of the central processing unit, the method further includes: obtaining the address access spaces of the target physical memory and the central processing unit respectively to obtain a physical space and a logical space; determining whether the size of the physical space exceeds the size of the logical space; if the size of the physical space exceeds the size of the logical space, dividing the physical space according to the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space; mapping the first space to the logical space to obtain a target mapping relationship, and recording the target mapping relationship in a preset mapping register. In this embodiment, to ensure that a target physical memory exceeding the address space size can still be read and written, this application pre-acquires the address access spaces of the target physical memory and the central processing unit to be accessed, obtaining corresponding physical spaces and logical spaces. Then, it determines whether the size of the physical space is greater than the size of the logical space. If the physical space is greater than the logical space, the physical space is divided according to the size of the logical space, resulting in a first space of the same size as the logical space and a second space other than the first space. The first space is then addressed and mapped to the logical space to obtain the corresponding target mapping relationship, which is saved to a preset mapping register. For example, see... Figure 2As shown, when the physical memory's address access space (i.e., physical space) is 8GB and the address range is 0x0_0000_0000~0x1_FFFF_FFFF, while the CPU's address access space (i.e., logical space) is 2GB and the address range is 0x8000_0000~0xFFFF_FFFF, the physical space is divided into two 2GB segments, resulting in a 2GB physical space and a 6GB physical space. Then, the 2GB physical space is mapped to the 2GB logical space. The logical spaces located at 0x8000_0000~0xFFFF_FFFF, numbered L0 and L1, are mapped to the physical spaces located at 0x0_0000_0000~0x0_7FFF_FFFF, numbered P0 and P1. The corresponding mapping relationships L0→P0 and L1→P1 are obtained by using space, and the mapping relationships L0→P0 and L1→P1 are saved to the preset mapping temporary register.

[0049] Step S12: Determine whether there is an intersection between the physical address and the logical address.

[0050] In this embodiment, after obtaining the physical address of the target physical memory and the logical address of the central processing unit, it is further determined whether there is an intersection between the physical address and the logical address. Specifically, it is determined whether the physical address falls within the address range corresponding to the logical address.

[0051] Specifically, determining whether the physical address and the logical address have an intersection can include: determining whether there is an address in the physical address that corresponds to the logical address based on the target mapping relationship recorded in the preset mapping register. For example, based on the target mapping relationships L0→P0 and L1→P1 recorded in the preset mapping register, it is known that the current physical addresses 0x0_0000_0000~0x1_FFFF_FFFF contain addresses 0x0_0000_0000~0x0_7FFF_FFFF, i.e., P0 and P1, that correspond to the logical addresses 0x8000_0000~0xFFFF_FFFF.

[0052] Step S13: If the physical address and the logical address have an intersection, then determine the address where the physical address and the logical address intersect to obtain the first address, and obtain the address in the physical address that does not intersect with the logical address to obtain the second address.

[0053] In this embodiment, if the physical address and the logical address intersect, the address where the physical address and the logical address intersect are further determined to obtain the corresponding first address, and then the address in the physical address that does not intersect with the logical address is obtained to obtain the corresponding second address. For example, Figure 2 The addresses where physical addresses and logical addresses intersect are 0x0_0000_0000 to 0x0_7FFF_FFFF, and the addresses where they do not intersect are 0x0_8000_0000 to 0x1_FFFF_FFFF.

[0054] Step S14: Write the data located at the first address in the target physical memory to the logical address, or read the data in the logical address to the first address located in the target physical memory.

[0055] In this embodiment, after obtaining the first address that intersects with the physical address and the second address that does not intersect with the logical address, if the current operation is a memory store operation, the data located in the first address (i.e., 0x0_0000_0000~x0_7FFF_FFFF) in the target physical memory can be written to the logical address (i.e., 0x8000_0000~0xFFFF_FFFF), that is, the final data of P0 and P1 are written to L0 and L1 respectively; if the current operation is a memory fetch operation, the data in the logical address can be read into the first address located in the target physical memory, that is, the data in L0 and L1 are read into P0 and P1 respectively.

[0056] Step S15: Write the second address to a preset address register, and write the data located at the second address in the target physical memory to a preset data register corresponding to the address register, or read the data in the preset data register to the second address located in the target physical memory.

[0057] In this embodiment, after writing the data located at the first address in the target physical memory to the logical address, or reading the data at the logical address to the first address in the target physical memory, the second address in the physical address that does not intersect with the logical address can be further written to a preset address register. Then, the data located at the second address in the target physical memory is written to a preset data register corresponding to the address register, or the data in the preset data register corresponding to the address register is read to the second address in the target physical memory. That is, the data in the physical space (0x0_8000_0000~0x1_FFFF_FFFF) in the target physical memory that exceeds the logical space is stored in the preset data register. In other words, the addresses P2 to P7 are written to the preset address register, and the data in P2 to P7 is written to the preset data register, or the data in the data register is read to P2 to P7 in the target physical memory. The size of the address register and the preset data register can be set according to the size of the target physical memory, and no specific limitation is made here.

[0058] As can be seen, in this embodiment, the physical address of the target physical memory and the logical address of the central processing unit are first obtained. Then, it is determined whether the physical address and the logical address have an intersection. If the physical address and the logical address have an intersection, the address where the physical address and the logical address intersect are determined to obtain the first address. Then, the address in the physical address that does not intersect with the logical address is obtained to obtain the second address. Next, the data in the target physical memory located at the first address is written to the logical address, or the data in the logical address is read to the first address in the target physical memory. Then, the second address is written to a preset address register. The data in the target physical memory located at the second address is written to a preset data register corresponding to the address register, or the data in the preset data register is read to the second address in the target physical memory. This application embodiment uses a preset address register and a preset data register to perform access operations on the target physical memory that exceeds the address space size, thereby enabling the memory that exceeds the address space size to be read and written, and reducing the complexity of mapping relationship management and chip cost.

[0059] This application discloses a specific memory access method, see [link to relevant documentation]. Figure 3 As shown, the method includes:

[0060] Step S21: Obtain the address access space of the target physical memory and the central processing unit respectively to obtain the physical space and the logical space.

[0061] Step S22: Determine whether the size of the entity space exceeds the size of the logical space.

[0062] Step S23: If the size of the entity space exceeds the size of the logical space, the entity space is divided according to the size of the logical space to obtain a first space with the same size as the logical space and a second space other than the first space.

[0063] In one specific implementation, dividing the physical space according to the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space may specifically include: dividing the physical space according to the order from low address to high address and based on the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space. In this embodiment, the physical space of the target physical memory may be divided according to the order from low address to high address and based on the size of the logical space. For example, the physical space of the target physical memory may be divided according to the logical space size of 2GB to obtain a first space with low address (0x0_0000_0000~0x0_7FFF_FFFF) and a second space with high address (0x0_8000_0000~0x1_FFFF_FFFF).

[0064] In this embodiment, considering that some memory regions are used more frequently in practical applications while others are used less frequently, the access frequency of each region in the target physical memory can be statistically analyzed to obtain the memory access frequency corresponding to each region. It is then determined whether the memory access frequency corresponding to each region exceeds a preset frequency threshold. If the memory access frequency exceeds the preset frequency threshold, the corresponding region is identified as a frequently accessed region; if the memory access frequency does not exceed the preset frequency threshold, the corresponding region is identified as a less frequently accessed region. That is, the access frequency of each region in the target physical memory is first statistically analyzed to obtain the memory access frequency corresponding to each region. Then, it is determined whether the memory access frequency corresponding to each region exceeds a preset frequency threshold. If it does, the corresponding region is identified as a frequently accessed region; if it does not, the corresponding region is identified as a less frequently accessed region.

[0065] Accordingly, dividing the physical space according to the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space can specifically include: dividing the physical space according to the size of the logical space and the preset frequency threshold to obtain a first space of the same size as the logical space and a second space other than the first space; wherein, the first space is located in the frequently accessed region, and the second space is located in the infrequently accessed region. That is, the frequently accessed region in the physical space is used as the direct addressing region and its addressing is mapped to the logical space, while the infrequently accessed region in the physical space is used as the indirect addressing region. For example, the frequently accessed regions P2 and P3 in the physical space are addressed and mapped to the logical spaces L0 and L1. In this way, the fast and simple access of direct addressing is combined, while also satisfying the access to the target physical memory beyond the direct addressing space.

[0066] Step S24: Map the first space to the logical space to obtain a target mapping relationship including the logical starting address, the physical starting address and the mapping length, and record the target mapping relationship in a preset mapping register.

[0067] In this embodiment, the first spatial address can be mapped to the aforementioned logical space, thereby obtaining a target mapping relationship including the logical starting address, the physical starting address, and the mapping length. For example, ... Figure 2 The physical space address (0x0_0000_0000~0x0_7FFF_FFFF) is mapped to the logical space (0x8000_0000~0XFFFF_FFFF), resulting in the logical start address (0x8000_0000), physical start address (0x0_0000_0000), and target mapping relationship with a mapping length of 2GB.

[0068] Step S25: Obtain the physical address of the target physical memory and the logical address of the central processing unit.

[0069] Step S26: Determine whether there is an address in the physical address that corresponds to the logical address based on the target mapping relationship recorded in the preset mapping register.

[0070] Step S27: If there is an address in the physical address that corresponds to the logical address, then determine the address where the physical address and the logical address intersect to obtain the first address, and obtain the address in the physical address that does not intersect with the logical address to obtain the second address.

[0071] Step S28: Write the data located at the first address in the target physical memory to the logical address, or read the data in the logical address to the first address located in the target physical memory.

[0072] Step S29: Write the second address to a preset address register, and write the data located at the second address in the target physical memory to a preset data register corresponding to the address register, or read the data in the preset data register to the second address located in the target physical memory.

[0073] For more detailed processing procedures regarding steps S21, S22, and S25 to S29, please refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0074] As can be seen, this application combines direct addressing and indirect addressing, thus possessing the advantages of both methods. Since only one mapping register is needed to record the relationship between the logical space and physical space within the directly addressed region, and one address register and one data register are used to access the target physical memory exceeding the direct address space size, target physical memory of any length and address exceeding the address space size can be read and written. This minimizes the number of mapping registers, reduces the complexity of managing mapping relationships, and allows access to target physical memory exceeding the address space size. Furthermore, since only one mapping register, one address register, and one data register are needed, chip costs are minimized. Simultaneously, it solves the problem of insufficient CPU address lines preventing the addressing of memory spaces exceeding capacity.

[0075] Accordingly, embodiments of this application also disclose a memory access device, see [link to relevant documentation]. Figure 4 As shown, the device includes:

[0076] Address acquisition module 11 is used to acquire the physical address of the target physical memory and the logical address of the central processing unit;

[0077] The judgment module 12 is used to determine whether there is an intersection between the physical address and the logical address;

[0078] Address determination module 13 is used to determine the address where the physical address and the logical address intersect if there is an intersection between the physical address and the logical address, to obtain the first address, and to obtain the address in the physical address that does not intersect with the logical address, to obtain the second address.

[0079] The first data access module 14 is used to write data located in the first address in the target physical memory to the logical address, or to read data in the logical address to the first address located in the target physical memory.

[0080] The second data access module 15 is used to write the second address to a preset address register, and to write the data located at the second address in the target physical memory to a preset data register corresponding to the address register, or to read the data in the preset data register to the second address located in the target physical memory.

[0081] The specific workflow of each of the above modules can be found in the relevant content disclosed in the foregoing embodiments, and will not be repeated here.

[0082] As can be seen, in this embodiment, the physical address of the target physical memory and the logical address of the central processing unit are first obtained. Then, it is determined whether the physical address and the logical address have an intersection. If the physical address and the logical address have an intersection, the address where the physical address and the logical address intersect are determined to obtain the first address. Then, the address in the physical address that does not intersect with the logical address is obtained to obtain the second address. Next, the data in the target physical memory located at the first address is written to the logical address, or the data in the logical address is read to the first address in the target physical memory. Then, the second address is written to a preset address register. The data in the target physical memory located at the second address is written to a preset data register corresponding to the address register, or the data in the preset data register is read to the second address in the target physical memory. This application embodiment uses a preset address register and a preset data register to perform access operations on the target physical memory that exceeds the address space size, thereby enabling the memory that exceeds the address space size to be read and written, and reducing the complexity of mapping relationship management and chip cost.

[0083] In some specific embodiments, the memory access device may further include:

[0084] A space acquisition unit is used to acquire the address access spaces of the target physical memory and the central processing unit respectively, to obtain physical space and logical space;

[0085] The first judgment unit is used to determine whether the size of the entity space exceeds the size of the logical space;

[0086] The first space partitioning unit is used to partition the entity space according to the size of the logical space if the size of the entity space exceeds the size of the logical space, so as to obtain a first space with the same size as the logical space and a second space other than the first space.

[0087] The first mapping unit is used to map the first space to the logical space to obtain the target mapping relationship;

[0088] The mapping relationship recording unit is used to record the target mapping relationship into a preset mapping temporary register.

[0089] In some specific embodiments, the determination module 12 may specifically include:

[0090] The second judgment unit is used to determine whether there is an address in the physical address that corresponds to the logical address based on the target mapping relationship recorded in the preset mapping register.

[0091] In some specific embodiments, the first spatial partitioning unit may specifically include:

[0092] The second space partitioning unit is used to partition the entity space according to the order from low address to high address and based on the size of the logical space, to obtain a first space with the same size as the logical space and a second space other than the first space.

[0093] In some specific embodiments, the memory access device may further include:

[0094] The statistics unit is used to count the access frequency of each region in the target entity memory to obtain the memory access frequency corresponding to each region.

[0095] The third judgment unit is used to determine whether the memory access frequency corresponding to each region exceeds a preset frequency threshold.

[0096] The first determination unit is used to determine the corresponding region as a frequent access region if the memory access frequency exceeds the preset frequency threshold.

[0097] The second determination unit is used to determine the corresponding region as a non-frequent access region if the memory access frequency does not exceed the preset frequency threshold.

[0098] In some specific embodiments, the first spatial partitioning unit may specifically include:

[0099] The third space partitioning unit is used to partition the entity space according to the size of the logical space and the preset frequency threshold to obtain a first space with the same size as the logical space and a second space other than the first space; wherein the first space is located in the frequent access area and the second space is located in the infrequent access area.

[0100] In some specific embodiments, the first mapping unit may specifically include:

[0101] The second mapping unit is used to map the first space to the logical space to obtain a target mapping relationship including the logical starting address, the physical starting address, and the mapping length.

[0102] Furthermore, embodiments of this application also disclose an electronic device, Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0103] Figure 5 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the memory access method disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0104] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0105] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0106] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the memory access method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0107] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned disclosed memory access method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0108] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0109] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0110] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0111] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0112] The foregoing has provided a detailed description of a memory access method, apparatus, device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A memory access method, characterized in that, include: Obtain the physical address of the target entity's memory and the logical address of the central processing unit; Determine whether there is an intersection between the physical address and the logical address; If the physical address and the logical address intersect, then determine the address where the physical address and the logical address intersect to obtain the first address, and obtain the address in the physical address that does not intersect with the logical address to obtain the second address; Write data located at the first address in the target physical memory to the logical address, or read data from the logical address to the first address located in the target physical memory; Write the second address to a preset address register, and write the data located at the second address in the target physical memory to a preset data register corresponding to the address register, or read the data in the preset data register to the second address located in the target physical memory. The method further includes: acquiring the address access spaces of the target physical memory and the central processing unit respectively to obtain a physical space and a logical space; determining whether the size of the physical space exceeds the size of the logical space; if the size of the physical space exceeds the size of the logical space, dividing the physical space according to the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space; mapping the first space to the logical space to obtain a target mapping relationship, and recording the target mapping relationship in a preset mapping register; Determining whether there is an intersection between the physical address and the logical address includes: determining whether there is an address in the physical address that corresponds to the logical address based on the target mapping relationship recorded in the preset mapping register; The step of writing data located at the first address in the target physical memory to the logical address, or reading data from the logical address to the first address in the target physical memory, includes: if the current operation is a memory store operation, writing data located at the first address in the target physical memory to the first space corresponding to the logical address; or, if the current operation is a memory fetch operation, reading data from the first space corresponding to the logical address to the first address in the target physical memory.

2. The memory access method according to claim 1, characterized in that, The step of dividing the entity space according to the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space includes: The entity space is divided according to the order from low address to high address and based on the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space.

3. The memory access method according to claim 1, characterized in that, Also includes: The access frequencies of each region in the target entity's memory are statistically analyzed to obtain the memory access frequencies corresponding to each region. Determine whether the memory access frequency corresponding to each region exceeds a preset frequency threshold; If the memory access frequency exceeds the preset frequency threshold, the corresponding region is determined to be a frequently accessed region. If the memory access frequency does not exceed the preset frequency threshold, the corresponding region is determined to be a non-frequent access region.

4. The memory access method according to claim 3, characterized in that, The step of dividing the entity space according to the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space includes: The entity space is divided according to the size of the logical space and the preset frequency threshold to obtain a first space with the same size as the logical space and a second space other than the first space; wherein the first space is located in the frequent access area and the second space is located in the infrequent access area.

5. The memory access method according to any one of claims 1 to 4, characterized in that, The step of mapping the first space to the logical space to obtain the target mapping relationship includes: The first space is mapped to the logical space to obtain a target mapping relationship including the logical starting address, the physical starting address, and the mapping length.

6. A memory access device, characterized in that, include: The address acquisition module is used to acquire the physical address of the target entity's memory and the logical address of the central processing unit. The judgment module is used to determine whether there is an intersection between the physical address and the logical address; The address determination module is used to determine the address where the physical address and the logical address intersect if there is an intersection between the physical address and the logical address, thereby obtaining the first address, and to obtain the address in the physical address that does not intersect with the logical address, thereby obtaining the second address. The first data access module is used to write data located at the first address in the target physical memory to the logical address, or to read data in the logical address to the first address located in the target physical memory. The second data access module is used to write the second address to a preset address register, and to write the data located at the second address in the target physical memory to a preset data register corresponding to the address register, or to read the data in the preset data register into the second address located in the target physical memory. The apparatus is further configured to: acquire the address access spaces of the target physical memory and the central processing unit respectively to obtain a physical space and a logical space; determine whether the size of the physical space exceeds the size of the logical space; if the size of the physical space exceeds the size of the logical space, divide the physical space according to the size of the logical space to obtain a first space of the same size as the logical space and a second space other than the first space; map the first space to the logical space to obtain a target mapping relationship, and record the target mapping relationship in a preset mapping register; The judgment module is specifically used to determine whether there is an address in the physical address that corresponds to the logical address based on the target mapping relationship recorded in the preset mapping register; The step of writing data located at the first address in the target physical memory to the logical address, or reading data from the logical address to the first address in the target physical memory, includes: if the current operation is a memory store operation, writing data located at the first address in the target physical memory to the first space corresponding to the logical address; or, if the current operation is a memory fetch operation, reading data from the first space corresponding to the logical address to the first address in the target physical memory.

7. An electronic device, characterized in that, It includes a processor and a memory; wherein, when the processor executes a computer program stored in the memory, it implements the memory access method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, Used for storing computer programs; wherein, when the computer programs are executed by a processor, they implement the memory access method as described in any one of claims 1 to 5.

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