PXIE architecture-based LED point measurement machine backboard

Abstract

The application provides an LED point measurement machine backboard based on a PXIE architecture, which comprises a switching circuit, an uplink slot, at least one PCIE Switch chip, a plurality of downlink slots, a first clock circuit and a second clock circuit. The uplink slot comprises a first port, a plurality of second ports and a third port; the at least one PCIE Switch chip; the PCIE Switch chip is connected with all / partial second ports and all / partial downlink slots simultaneously; the plurality of downlink slots are independent of each other, and each downlink slot comprises a fourth port and a fifth port. The application can realize various routing modes of PCIE signals, and does not need to re-link when switching between slot positions.

Description

Technical Field

[0001] This invention relates to the field of testing equipment, and more specifically, to a backplane for an LED spot tester based on a PXIE architecture. Background Technology

[0002] PXIE bus technology has developed rapidly and is widely used in the field of automated testing. Currently, test boards provide abundant resources for the rapid construction of automated test systems. PXIE is an extension of PCIe in the instrumentation field. It adds instrument control signals or synchronous triggering functions to the PCIe bus and modifies the mechanical structure to be ruggedized, making the PCIe bus more suitable for industrial testing while maintaining its strong expandability and high bandwidth.

[0003] However, although the total bandwidth of the current LED spot tester backplane can meet the needs of conventional high-speed testing, each routing method requires a corresponding backplane architecture design, making LED spot tester backplanes diverse, thereby increasing the equipment cost and maintenance cost of LED spot tester backplanes; in addition, when switching between slots, the PCIe signals need to be relinked, that is, the two PCIe components directly re-establish the connection, making the LED spot tester backplane design more complicated. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a backplane for an LED spot testing machine based on a PXIE architecture, which can realize various routing methods for the PCIE signals of the LED spot testing machine, and does not require relinking when switching between slots.

[0005] This invention provides a backplane for an LED spot testing machine based on the PXIE architecture, including a switching circuit connected to an uplink slot;

[0006] The upstream slot includes a first port, multiple second ports, and a third port; the first port is connected to the switching circuit; the second ports are connected to a PCIe Switch chip or the downstream slot; and the third port is connected to a first clock circuit.

[0007] At least one PCIe Switch chip, which is simultaneously connected to all / part of the second port and all / part of the downstream slot;

[0008] Multiple downstream slots, which are independent of each other; each downstream slot includes a fourth port and a fifth port; each fourth port is connected to a PCIe Switch chip or a second port; each fifth port is simultaneously connected to the first clock circuit and the second clock circuit;

[0009] The first clock circuit is simultaneously connected to the third port, each of the PCIe Switch chips, and the fifth port of each of the downstream slots;

[0010] The second clock circuit includes a plurality of sixth ports, one of which is connected to a corresponding fifth port of the downstream slot.

[0011] Furthermore, the second port has n ports;

[0012] Each of the n second ports is connected to at least one PCIe Switch chip;

[0013] or,

[0014] m second ports are each connected to at least one PCIe Switch chip, and nm second ports are each connected to the fourth ports of nm downstream slots.

[0015] Where n is greater than m, and both n and m are positive integers.

[0016] Furthermore, the second port has four ports, and the PCIe Switch chip has one or two.

[0017] Furthermore, the internal structure of each downstream slot is identical.

[0018] Furthermore, there is one PCIe switch chip and eight downstream slots;

[0019] The PCIe Switch chip is simultaneously connected to four of the second ports and eight of the downstream slots.

[0020] Furthermore, there is one PCIe switch chip and eight downstream slots;

[0021] One of the second ports is connected to the PCIe Switch chip, and the other three second ports are respectively connected to the three downstream slots.

[0022] The remaining five downstream slots are simultaneously connected to the PCIe Switch chip.

[0023] Furthermore, there are two PCIe Switch chips, namely a first PCIe Switch chip and a second PCIe Switch chip, and there are eight downstream slots;

[0024] Two of the second ports are simultaneously connected to the first PCIe Switch chip; the remaining two of the second ports are simultaneously connected to the second PCIe Switch chip.

[0025] The first PCIe Switch chip is connected to all four downstream slots simultaneously, and the second PCIe Switch chip is connected to the remaining four downstream slots simultaneously.

[0026] Furthermore, there are two PCIe Switch chips, namely a first PCIe Switch chip and a second PCIe Switch chip, and there are eight downstream slots;

[0027] The two second ports are respectively connected to the first PCIe Switch chip and the second PCIe Switch chip; the remaining two second ports are respectively connected to the two downstream slots.

[0028] The remaining six downstream slots are respectively connected to the first PCIe Switch chip and the second PCIe Switch chip.

[0029] Furthermore, the second clock circuit includes: a first sub-circuit, a second sub-circuit, and a third sub-circuit; wherein the second sub-circuit and the third sub-circuit are respectively connected to the first sub-circuit.

[0030] Furthermore, each of the sixth ports includes a first sub-port of the first sub-circuit, a second sub-port of the second sub-circuit, and a third sub-port of the third sub-circuit.

[0031] In general, the technical solution conceived in this invention can achieve the following beneficial effects compared with the prior art:

[0032] This invention provides a PXIE-based LED testing machine backplane. By designing the connection method between the PCIe switch chip and the slot, and simultaneously using a first clock circuit to control the chip and the downstream slot, and a second clock circuit to connect to the LED testing machine, the backplane generates a stable oscillating sine wave, achieving unified digital system timing and allowing each component to operate sequentially. This not only meets high-speed testing requirements while expanding the PCIe signals of the LED testing machine backplane, enabling multiple PCIe signal expansions without affecting the communication process and speed of the LED testing machine, but also allows the PXIE-based LED testing machine backplane to support multi-master switching modes. That is, when switching between slots, the PCIe signals do not need to re-establish the link; the control card directly provides the corresponding mode to achieve various routing methods for the LED testing machine. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the backplane of an LED spot testing machine based on the PXIE architecture provided by the present invention;

[0035] Figure 2 This is a schematic diagram of the second clock circuit of the backplane of an LED spot tester based on the PXIE architecture provided by the present invention;

[0036] Switch circuit-1; Upstream slot-2; PCIe Switch chip-3; Downstream slot-4; First clock circuit-5; Second clock circuit-6;

[0037] First port -21; Second port -22; Third port -23;

[0038] Port 41; Port 5 42; Port 61;

[0039] First sub-circuit - 601; Second sub-circuit - 602; Third sub-circuit - 603;

[0040] First subport - 611; Second subport - 612; Third subport - 613. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Furthermore, the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other.

[0042] It should be noted that in the description of the embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an LED spot testing machine backplate comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an LED spot testing machine backplate. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the LED spot testing machine backplate including said element.

[0043] like Figure 1As shown, this invention provides a backplane for an LED spot testing machine based on a PXIE architecture, comprising:

[0044] Switching circuit 1 is connected to upstream slot 2. As an embodiment of the present invention, switching circuit 1 includes a 2-pin switch socket and a 16-pin switch socket, and is connected to the first port 21 of upstream slot 2.

[0045] Upstream slot 2 includes a first port 21, multiple second ports 22 and a third port 23; the first port 21 is connected to the switch circuit 1; the second ports 22 are connected to the PCIe Switch chip 3 or the downstream slot 4; and the third port 23 is connected to the first clock circuit 5.

[0046] At least one PCIe Switch chip 3, which has the ability to expand and aggregate, is connected to all / part of the second port 22 and all / part of the downstream slot 4 simultaneously.

[0047] Multiple downstream slots 4 are provided, and the downstream slots 4 are independent of each other; each downstream slot 4 includes a fourth port 41 and a fifth port 42; each fourth port 41 is connected to a PCIe switch chip 3 or a second port 22; each fifth port 42 is simultaneously connected to a first clock circuit 5 and a second clock circuit 6. Furthermore, according to the current design requirements of the LED spot testing machine backplane, the downstream slots 4 are preferably 8 slots, 13 slots, or 17 slots.

[0048] The first clock circuit 5 is also connected to the third port 23, each PCIe Switch chip 3, and the fifth port 42 of each downstream slot.

[0049] The second clock circuit 6 includes multiple sixth ports 61, one of which is connected to a corresponding fifth port 42 of a downstream slot 4.

[0050] As one embodiment of the present invention, such as Figure 2 As shown, the second clock circuit 6 includes a first sub-circuit 601, a second sub-circuit 602, and a third sub-circuit 603; wherein the second sub-circuit 602 and the third sub-circuit 603 are respectively connected to the first sub-circuit 601; it should be noted that each sixth port 61 includes a first sub-port 611 of the first sub-circuit, a second sub-port 612 of the second sub-circuit, and a third sub-port 613 of the third sub-circuit.

[0051] It should be noted that when there are n second ports 22, the n second ports 22 can be connected to at least one PCIE switch chip 3 respectively; or, the m second ports 22 can be connected to at least one PCIE switch chip 3 respectively, and the remaining nm second ports 22 are connected to the fourth ports 41 of the nm downstream slots 4 respectively; where n is greater than m, and both n and m are positive integers.

[0052] The second port 22 can be connected to either the PCIe Switch chip 3 or the downstream slot 4, thereby expanding the PCIe signal of the LED spot tester backplane, enabling the expansion of the PCIe signal of the LED spot tester backplane without affecting the communication process and communication rate of the LED spot tester.

[0053] Furthermore, the internal structure of each downstream slot 4 is identical in this application. This application achieves various testing functions of the LED spot testing machine backplane based on the connection method between the PCIe Switch chip 3 and the slot, rather than by replacing various downstream slots 4.

[0054] In one embodiment of the present invention, there are four second ports 23, and one or two PCIE switch chips 3.

[0055] When there are four second ports 23, one PCIe Switch chip 3, and eight downstream slots 4.

[0056] As a specific embodiment of the present invention, the PCIE Switch chip 3 is simultaneously connected to four second ports 23 and eight downstream slots 4. The signals transmitted between the PCIE Switch chip 3 and the four second ports 23 are 1PET / Rp / n[0-3], 2PET / Rp / n[0-3], 3PET / Rp / n[0-3], and 4PET / Rp / n[0-3], respectively; the signals transmitted between the PCIE Switch chip 3 and the eight downstream slots 4 are PCIE SLOT1 1PET / Rp / n[0-3], PCIE SLOT2 1PET / Rp / n[0-3], PCIE SLOT3 1PET / Rp / n[0-3], PCIE SLOT4 1PET / Rp / n[0-3], PCIE SLOT5 2PET / Rp / n[0-3], PCIE SLOT6 2PET / Rp / n[0-3], PCIE SLOT7 2PET / Rp / n[0-3], and PCIE SLOT8 2PET / Rp / n[0-3]. Based on this connection method, different signals are output to achieve the switching between 2-Link and 4-Link.

[0057] In a specific embodiment of the present invention, a second port 23 is connected to the PCIE Switch chip 3, wherein the signal transmitted between the second port 23 and the PCIE Switch chip is 4PET / Rp / n[0-3]; the other three second ports 23 are respectively connected to three downstream slots, wherein the signals transmitted between the second port 23 and the corresponding downstream slots 4 are 1PET / Rp / n[0-3], 2PET / Rp / n[0-3], and 3PET / Rp / n[0-3]; the other five downstream slots 4 are simultaneously connected to the PCIE Switch chip 3, wherein the signals transmitted between the downstream slots 4 and the PCIE Switch chip 3 are PCIE SLOT4 1PET / Rp / n[0-3], PCIE SLOT5 2PET / Rp / n[0-3], PCIE SLOT6 2PET / Rp / n[0-3], PCIE SLOT7 2PET / Rp / n[0-3], and PCIE SLOT8 2PET / Rp / n[0-3]. Based on this connection method, different signals are output to achieve the 4Link mode.

[0058] When there are four ports 23, two PCIe switch chips 3, and eight downstream slots 4. Specifically, there are two PCIe switch chips 3, serving as the first PCIe switch chip and the second PCIe switch chip.

[0059] In a specific embodiment of the present invention, two second ports 23 are simultaneously connected to the first PCIe Switch chip; the remaining two second ports 23 are simultaneously connected to the second PCIe Switch chip. That is, each PCIe Switch chip 3 is connected to two second ports 23 respectively, wherein the signals transmitted between the two second ports 23 and the first PCIe Switch chip are 1PET / Rp / n[0-3] and 2PET / Rp / n[0-3] respectively; the signals transmitted between the remaining two second ports 23 and the second PCIe Switch chip are 3PET / Rp / n[0-3] and 4PET / Rp / n[0-3] respectively. Simultaneously, the first PCIe switch chip is connected to four downstream slots 4, while the second PCIe switch chip is connected to the remaining four downstream slots 4. The signals transmitted between the first PCIe switch chip and the four downstream slots 4 are PCIe SLOT1 1PET / Rp / n[0-3], PCIe SLOT2 1PET / Rp / n[0-3], PCIe SLOT3 1PET / Rp / n[0-3], and PCIe SLOT4 1PET / Rp / n[0-3], respectively. The signals transmitted between the second PCIe switch chip and the four downstream slots 4 are PCIe SLOT5 2PET / Rp / n[0-3], PCIe SLOT6 2PET / Rp / n[0-3], PCIe SLOT7 2PET / Rp / n[0-3], and PCIe SLOT8 2PET / Rp / n[0-3]. Based on this connection method, different signals are output to achieve the switching between 2-Link and 4-Link.

[0060] In a specific embodiment of the present invention, the two second ports 23 are respectively connected to the first PCIe Switch chip and the second PCIe Switch chip; that is, each PCIe Switch chip 3 is connected to only one second port 23, wherein the signal transmitted between one second port 23 and the first PCIe Switch chip is 4PET / Rp / n[0-3]; and the signal transmitted between the other second port 23 and the second PCIe Switch chip is 3PET / Rp / n[0-3]. The remaining two second ports 23 are respectively connected to two downstream slots 4, wherein the signals transmitted between the second port 23 and the corresponding downstream slots are 1PET / Rp / n[0-3] and 2PET / Rp / n[0-3], respectively. Meanwhile, the remaining six downstream slots 4 are connected to the first and second PCIe switch chips respectively. Specifically, the first PCIe switch chip and the two downstream slots transmit the following signals: PCIe SLOT3 1PET / Rp / n[0-3], PCIe SLOT4 1PET / Rp / n[0-3], and the second PCIe switch chip and the four downstream slots transmit the following signals: PCIe SLOT5 2PET / Rp / n[0-3], PCIe SLOT6 2PET / Rp / n[0-3], PCIe SLOT7 2PET / Rp / n[0-3], and PCIe SLOT8 2PET / Rp / n[0-3]. Based on this connection method, different signals are output to achieve the 4-Link mode.

[0061] It should be noted that, as an embodiment of the present invention, each PCIE Switch chip 3 is also connected to a JTAG interface and a transceiver.

[0062] In summary, this invention proposes a PXIE-based LED testing machine backplane. By designing the connection method between the PCIe switch chip and the slot, and simultaneously using a first clock circuit to control the chip and the downstream slot, and a second clock circuit to connect to the LED testing machine, the backplane generates a stable oscillating sine wave, achieving unified digital system timing and allowing each part to work sequentially. This not only meets the requirements of high-speed testing while expanding the PCIe signals of the LED testing machine backplane, enabling multiple PCIe signals without affecting the communication process and rate of the LED testing machine; but also allows the PXIE-based LED testing machine backplane to support multi-master switching mode. That is, when switching between slots, the PCIe signals do not need to re-establish the link; the control card directly provides the corresponding mode to realize various routing methods of the LED testing machine.

[0063] It should be noted that, for the sake of simplicity, the foregoing embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0064] It should be understood that the embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0065] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

[0066] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A backplane for an LED spot testing machine based on a PXIE architecture, characterized in that, include: Switching circuit, connected to the uplink slot; Uplink slot, including a first port, multiple second ports, and a third port; The first port is connected to the switching circuit; The second port is connected to the PCIe Switch chip or the downstream slot; the third port is connected to the first clock circuit. At least one PCIe Switch chip, which is simultaneously connected to all / part of the second port and all / part of the downstream slot; Multiple downstream slots, which are independent of each other; each downstream slot includes a fourth port and a fifth port; each fourth port is connected to one of the PCIe Switch chips or one of the second ports; each fifth port is simultaneously connected to the first clock circuit and the second clock circuit; The first clock circuit is simultaneously connected to the third port, each of the PCIe Switch chips, and the fifth port of each of the downstream slots; The second clock circuit includes a plurality of sixth ports, one of which is connected to a corresponding fifth port of the downstream slot.

2. The LED spot testing machine backplane based on PXIE architecture as described in claim 1, characterized in that, The second port has n ports; Each of the n second ports is connected to at least one PCIe Switch chip; or, m second ports are each connected to at least one PCIe Switch chip, and nm second ports are each connected to the fourth ports of nm downstream slots. Where n is greater than m, and both n and m are positive integers.

3. The LED spot testing machine backplane based on PXIE architecture as described in claim 2, characterized in that, The second port has four ports, and the PCIe Switch chip has one or two.

4. The LED spot testing machine backplane based on PXIE architecture as described in claim 1, characterized in that, The internal structure of each downslot is identical.

5. The LED spot testing machine backplane based on PXIE architecture as described in claim 3, characterized in that, There is one PCIESwitch chip and eight downstream slots; The PCIe Switch chip is simultaneously connected to four of the second ports and eight of the downstream slots.

6. The LED spot testing machine backplane based on PXIE architecture as described in claim 3, characterized in that, There is one PCIESwitch chip and eight downstream slots; One of the second ports is connected to the PCIe Switch chip, and the other three second ports are respectively connected to the three downstream slots. The remaining five downstream slots are simultaneously connected to the PCIe Switch chip.

7. The LED spot testing machine backplane based on PXIE architecture as described in claim 3, characterized in that, There are two PCIE switch chips, namely the first PCIE switch chip and the second PCIE switch chip, and there are eight downstream slots; Two of the second ports are simultaneously connected to the first PCIe Switch chip; the remaining two of the second ports are simultaneously connected to the second PCIe Switch chip. The first PCIe Switch chip is connected to all four downstream slots simultaneously, and the second PCIe Switch chip is connected to the remaining four downstream slots simultaneously.

8. The LED spot testing machine backplane based on PXIE architecture as described in claim 3, characterized in that, There are two PCIE switch chips, namely the first PCIE switch chip and the second PCIE switch chip, and there are eight downstream slots; The two second ports are respectively connected to the first PCIe Switch chip and the second PCIe Switch chip; the remaining two second ports are respectively connected to the two downstream slots. The remaining six downstream slots are respectively connected to the first PCIe Switch chip and the second PCIe Switch chip.

9. The LED spot testing machine backplane based on PXIE architecture as described in claim 1, characterized in that, The second clock circuit includes a first sub-circuit, a second sub-circuit, and a third sub-circuit; wherein the second sub-circuit and the third sub-circuit are respectively connected to the first sub-circuit.

10. The LED spot testing machine backplane based on PXIE architecture as described in claim 9, characterized in that, Each of the sixth ports includes a first sub-port of the first sub-circuit, a second sub-port of the second sub-circuit, and a third sub-port of the third sub-circuit.

Images