Methods, systems, and computer-readable storage media of fabricating semiconductor devices

Abstract

A method of manufacturing a semiconductor device generates a first performance database for a standard cell library, including: grouping gates for each standard cell including a plurality of gates, including: searching for matching gates among the gates; grouping corresponding matching gates into corresponding multiple-member groups; and (for non-matching gates among the gates) grouping the non-matching gates into corresponding single-member groups; generating corresponding first performance data quantities for each standard cell, including: for each group, calculating the first performance data quantity individually; mapping the performance data quantity to a target gate in the group; and for each multiple-member group, mapping the performance data quantity to a non-target gate; and basing the first performance database at least in part on the first performance data quantities. Such mapping is an example of using redundancy in performance data to reduce computational burden.

Description

Technical Field

[0001] This disclosure relates to a method, system, and non-transitory computer-readable storage medium for manufacturing semiconductor devices. Background Technology

[0002] The integrated circuit (IC) industry produces various analog and digital semiconductor devices to solve problems in different fields. Advances in semiconductor process technology nodes have led to progressively smaller component sizes and closer spacing, resulting in progressively higher transistor density. ICs are becoming increasingly smaller.

[0003] During the design of semiconductor devices, layout diagrams are used to represent the devices. The layout designer selects standard cells from a library of standard cells and includes them in the layout diagram. Once included in the layout diagram, the previous standard cell is referred to as an instance of the standard cell. An instanced cell differs from a standard cell, for example, by further including information such as: the geometric location of the instanced cell in the layout diagram, the specific signal coupled to the input of the instanced cell, the load coupled to the output of the instanced cell, or similar information. Summary of the Invention

[0004] In some embodiments, a method (a method of manufacturing a semiconductor device, wherein a corresponding layout for the semiconductor device includes instantiated cells, each instantiated cell being an instance of a corresponding standard cell selected from a standard cell library composed of standard cells, the layout, the standard cell library, and a first performance database being stored on a non-transitory computer-readable storage medium) includes generating the first performance database, the generation of the first performance database including: classifying the plurality of gates into groups for each standard cell comprising a plurality of gates, including: searching for matching gates among the plurality of gates; grouping corresponding matching gates into corresponding first groups, each first group having a plurality of member gates; and grouping non-matching gates among the plurality of gates into corresponding second groups, each second group having a corresponding single member gate; generating a corresponding first performance database for each standard cell. The performance data volume, wherein the attributes of the standard cells are based on the first performance data volume, and generating the corresponding first performance data volume includes: performing the following operations for each first group of each standard cell: individually calculating the first performance data volume for a first target gate among the member gates in the first group; mapping the first performance data volume to the first target gate; and mapping the first performance data volume to non-target gates in the first group; performing the following operations for each second group of each standard cell: determining the first performance data volume for a second target gate among the member gates in the second group; and mapping the first performance data volume to the second target gate; and making the first performance database at least partially based on the first performance data volume, wherein the attributes of the standard cells in the standard cell library are based on the first performance database.

[0005] In some embodiments, a system for manufacturing a semiconductor device includes: at least one processor; at least one non-transitory computer-readable storage medium storing computer-executable code; a corresponding layout diagram including instantiated cells, each instantiated cell being an instance of a corresponding standard cell selected from a standard cell library composed of standard cells, the layout diagram, the standard cell library, and a first performance database being stored on the non-transitory computer-readable storage medium, the non-transitory computer-readable storage medium, the computer program executable code, and the at least one processor being configured to cause the system to generate the first performance database, the generation of the first performance database including: classifying features of the gates into groups for each standard cell including a plurality of gates, including: searching for matching features among the features of the plurality of gates; grouping corresponding matching features into corresponding first groups, each first group having a plurality of member features; and grouping non-matching features into corresponding second groups for non-matching features among the features. In each group, each second group has a corresponding single member feature; a corresponding first performance data quantity is generated for each standard cell, the attributes of the standard cell being based on the first performance data quantity, the generation of the corresponding first performance data quantity includes: for each first group of each standard cell, performing the following operations: individually calculating the first performance data quantity for a first target feature among the member features in the first group; mapping the first performance data quantity to the first target feature; and mapping the first performance data quantity to a non-target feature among the member features in the first group; for each second group of each standard cell, performing the following operations: determining the first performance data quantity for a second target feature among the member features in the second group; and mapping the first performance data quantity to the second target feature; and making the first performance database at least partially based on the first performance data quantity, the attributes of the standard cells in the standard cell library being based on the first performance database.

[0006] In some embodiments, a non-transitory computer-readable storage medium stores computer-executable instructions representing a method (a method for generating a first performance database, including a standard cell library whose attributes are based on the first performance database, the standard cell library and the first performance database being stored on the non-transitory computer-readable storage medium), the computer-executable instructions being executable by at least one processor to perform the method, the method comprising: classifying the plurality of gates into groups for each standard cell comprising a plurality of gates, each gate having N inputs, where N is a positive integer and N is equal to or greater than 2, the classification of the plurality of gates into groups comprising: searching for matching gates among the plurality of gates; grouping the corresponding matching gates into corresponding first groups, each first group having a plurality of member gates; and grouping the non-matching gates among the plurality of gates into corresponding second groups, each second group having a corresponding single member gate; generating a corresponding first performance data amount for each standard cell, the attributes of the standard cell being based on the first performance data amount, the generation of the corresponding first performance data amount comprising: pinning... For each first group of each standard cell, the following operations are performed: calculating the first performance data quantity individually for a first target gate among the member gates in the first group; mapping the first performance data quantity to the first target gate; and mapping the first performance data quantity to non-target gates in the first group; for each second group of each standard cell, the following operations are performed: determining the first performance data quantity for a second target gate among the member gates in the second group; and mapping the first performance data quantity to the second target gate; and making the first performance database at least partially based on the first performance data quantity; the generation of the corresponding first performance data quantity further includes: for each target gate in each first group and for each target gate in each second group, determining the corresponding 2^N performance data pages for each of the 2^N value combinations of the N inputs based on: the corresponding Nth value combination of the N inputs of the first target gate or the second target gate; and the predefined value combination of the N inputs of each of the non-target gates; and each first performance data quantity is a set including the corresponding 2^N performance data pages. Attached Figure Description

[0007] Various aspects of this disclosure will be understood by reading the following detailed description in conjunction with the accompanying drawings. It should be understood that the devices and / or structures shown in the drawings are not necessarily drawn to scale. Therefore, for clarity of discussion, the dimensions of various features may be arbitrarily increased and / or decreased.

[0008] Figure 1AThis is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0009] Figure 1B This is a block diagram generated based on a performance database of some embodiments.

[0010] Figures 2A to 2C This is a block diagram of the corresponding standard cell according to some embodiments.

[0011] Figures 3A to 3C This is a block diagram of a standard cell according to some embodiments.

[0012] Figure 3D This is a block diagram of a standard cell according to some embodiments.

[0013] Figure 4A It is a data structure for performance data of standard cells according to some embodiments.

[0014] Figures 4B to 4C It is a representation of the corresponding value combination on the input terminal pins according to some embodiments.

[0015] Figure 4D It is a data structure for performance data of standard cells according to some embodiments.

[0016] Figures 4E to 4F It is a representation of the corresponding value combination on the input terminal pins according to some embodiments.

[0017] Figures 5A to 5F It is a corresponding data structure for performance data based on some embodiments.

[0018] Figure 5G to Figure 5N It is a corresponding data structure for performance data based on some embodiments.

[0019] Figures 6A to 6D This is a block diagram of a corresponding multi-bit flip-flop according to some embodiments.

[0020] Figures 6E to 6H This is a block diagram of a corresponding unit cell flip-flop according to some embodiments.

[0021] Figures 7A to 7C This is a flowchart of a corresponding method for manufacturing a semiconductor device according to some embodiments.

[0022] Figure 8 This is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing process associated with the integrated circuit (IC) manufacturing system, according to some embodiments. Detailed Implementation

[0023] The following discloses numerous different embodiments or examples of various features for implementing the target object. Examples of components, materials, values, steps, operations, arrangements, or similar items are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or similar items are expected. For example, the following description includes embodiments where a first feature is formed on or on a second feature, wherein the first and second features are formed in direct contact, and also includes embodiments where additional features are formed between the first and second features, thereby causing the first and second features to be in indirect contact. Furthermore, reference numerals and / or letters are repeatedly used in various examples in this disclosure. This repetition is to simplify the illustrations in the figures and reduce repetition in the corresponding discussions in the specification; the scope of any relationship of common components attributable to the various embodiments and / or configurations discussed will be apparent by examining the common components in the different embodiments and the contextual differences between the different components. For example, these contextual differences include differences caused by the functionality of different components, differences in inline relationships between components that are common in other respects, differences in timing relationships between components that are common in other respects, changes in inline relationships and timing relationships between components that are common in other respects due to the operation of different components, and / or similar differences.

[0024] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” or similar terms are used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly. In some embodiments, the term “standard cell structure” refers to a standardized building block included in a library of various standard cell structures (standard-cell library). In some embodiments, various standard cell structures are selected from the library of standard cell structures and used as components in a layout diagram representing a circuit.

[0025] In some embodiments, a method of manufacturing a semiconductor device includes generating a first performance database for a corresponding standard cell library. This method utilizes redundancy in the first performance data to: (1) reduce the computational load represented by the generation of the first performance database and (2) reduce the file size of the file containing the first performance database.

[0026] Generally, standard cells are used in the design of proposed semiconductor devices. Here (i.e., at the beginning of this paragraph), the adjective "proposed" is used to modify the reference to the semiconductor device, in contrast to the use of the label "actual" to modify the reference to the semiconductor device in this paragraph. Typically, when designing a proposed semiconductor device, the functional and operational requirements of the proposed semiconductor device are drafted. Then, a circuit diagram of the proposed semiconductor device that meets the functional and operational requirements is designed. Next, a layout diagram representing the circuit diagram is designed. The layout diagram includes instantiated cells, each instantiated cell being an instance of a corresponding standard cell selected from a standard cell library consisting of standard cells. The standard cell library corresponds to the semiconductor process technology node that will be used to manufacture the proposed semiconductor device. The layout diagram is then subjected to various verification processes, which, among other things, confirm that the actual semiconductor based on the layout diagram will meet all the functional and operational requirements of the proposed semiconductor device. One or more of the various verification processes also depend, among other things, on the properties of the instantiated cells. The properties of the instantiated cells are based on the properties of the corresponding standard cells. The properties of a standard cell are based on one or more corresponding performance databases.

[0027] According to another method, instead of identifying redundancy in the performance data, each performance database is computed separately using analysis tools. Since there are numerous different combinations of values ​​on the input terminal pins (as explained below), each of these combinations is computed separately, this other method is (at least) computationally intensive. Assume that the standard cell library according to this other method comprises a total of M gates, each gate having a total of n input terminal pins, where each of M and n is a positive integer, 2 ≤ M and 2 ≤ n. Therefore, the total number of input terminal pins for a given gate according to this other method is the product of the number of gates and the number of input terminal pins for each gate (i.e., n*M). As an example, further assume that the given performance database according to this other method contains propagation delay data. According to the other method, the propagation delay library for a given standard cell provides a propagation delay value for each gate in the given standard cell, and more specifically, provides a propagation delay value for each combination of (1) the value applied to the input terminal pin of the given gate and (2) the value applied to the input terminal pins of M-1 other gates in the given standard cell. Thus, according to the other method, the total number of propagation delay values ​​for a given gate in the propagation delay library is 2^^(n*M), which is a large number; and the total number of propagation delay values ​​for a given standard cell is M*2^^(n*M), which is an even larger number. Further assuming that there are L standard cells in the standard cell library according to the other method, where L is a large positive integer; therefore, the total number of propagation delay values ​​in the propagation delay library according to the other method is L*(M*2^^(n*M)), which is an even larger number.

[0028] Since the other method does not recognize redundancy in the performance data, it must perform L*(M*2^^(n*M)) separate calculations to generate a propagation delay library corresponding to the standard cell library. This is a significant computational burden in terms of the amount of computational resources consumed, the time required, or the like. Therefore, the large file size of the propagation delay library according to the other method is a substantial computational burden in terms of making electrical conduction more difficult, making it more difficult for users to maintain caches in the volatile memory of electronic design automation (EDA) systems, and thus allowing EDA systems to access data more slowly (e.g., when performing verification processes), or the like. In contrast, the method for manufacturing a semiconductor device according to at least some embodiments does take redundancy in the performance data into account, which has the following benefits: (1) a reduction in the computational load represented by the generation of a given performance database compared to the other method; and (2) a reduction in the file size of the file containing the first performance database compared to the other method, or similar benefits.

[0029] As part of developing embodiments of this application, the inventors recognized that, for a given standard cell, the performance database corresponding to the standard cell library contains a significant amount of redundancy; and this redundancy provides an opportunity to reduce the computational burden represented by the generation of a given performance database. In generating a first performance database for a corresponding standard cell library by identifying performance data for a given standard cell within the standard cells, the redundancy in the performance data is taken into account more heavily with (A) the values ​​applied to the input terminal pins of a given gate and less heavily with (B) the values ​​applied to the input terminal pins of M-1 other gates.

[0030] Assuming each standard cell has M gates, and each of the M gates has n input terminal pins, then for any one of the 2^^(n*M) combinations of (1) the value applied to the input terminal pin of a given gate and (2) the value applied to the input terminal pin of the M-1 other gates in a given standard cell, most of the total combinations (i.e., 2^^(n*(M-1)) combinations can be attributed to (due to) the sub-combinations of the values ​​applied to the input terminal pins of the M-1 other gates in a given standard cell. However, given that performance data depends more on (A) the value of the input terminal pin applied to a given gate and less on (B) the value of the input terminal pin applied to M-1 other gates, at least some embodiments at least partially represent the inventors’ further understanding that all combinations of 2^^(n*(M-1)) combinations, except for a few (e.g., one) combinations that may belong to the values ​​applied to the input terminal pins of M-1 other gates, contribute negligibly to the individual calculation of performance data, i.e., resulting in redundant performance data.

[0031] Thus, at least some embodiments exploit redundancy in the performance data by focusing on (1) the contribution of 2^^n to the values of the input terminal pins applied to a given gate and (2) the contribution to the individual calculation of the performance data of several value combinations among the 2^^(n*(M-1)) value combinations that can be attributed to the input terminal pins of M-1 other gates. The several value combinations among the 2^^(n*(M-1)) value combinations that can be attributed to the input terminal pins of M-1 other gates are represented by the variable J, which is typically a positive integer less than n (i.e., J < n). In some embodiments, J = 1. In some embodiments, exploiting the performance data redundancy results in J*2^^n individual calculations of the performance data for a given gate. The J*2^^n discrete calculations performed by such embodiments are substantially fewer calculations than the 2^^(n*M) discrete calculations of the performance data for a given gate originally performed according to the other method. In such embodiments, exploiting the performance data redundancy results in Δ fewer discrete calculations for a given gate, where Δ = 2^^(n*M) - J*2^^n. This embodiment of the present application of the J*2^^n discrete calculations of the performance data for a given gate, compared to the 2^^(n*(M-1)) discrete calculations of the performance data for a given gate by the other method, advantageously shows that the number of discrete calculations performed is reduced by M orders of magnitude in base two, which is a substantial reduction and thus represents a substantial reduction in the computational burden on the EDA system.

[0032] In some embodiments, each standard cell includes one or more gates. In some embodiments, at least some of the gates in the standard cell are combinational logic (logic gates). In some embodiments, at least some of the gates in the standard cell are asynchronous logic (flip-flop gates).

[0033] In some embodiments, a method of manufacturing a semiconductor device includes: generating a first performance database for each standard cell in a standard cell library, including: classifying gates into multi-member groups and single-member groups; generating corresponding first performance data amounts including mappings within the multi-member groups on a group-by-group basis; and performing bundling. For each standard cell comprising multiple gates, the classification includes: classifying gates into groups, including searching for matching gates (matching gates) among the gates on a gate-by-gate basis; grouping the corresponding matching gates into corresponding first groups, each first group having multiple member gates; and grouping the unmatching gates (unmatching gates) among the gates that do not have other matching gates into corresponding second groups, each second group having a corresponding single member gate. For each standard cell and each first group, generating the first performance database further includes generating a corresponding first performance data quantity, including: individually calculating the first performance data quantity for a target member gate (first target gate) among the member gates in the first group; mapping the performance data quantity to the first target gate; and mapping the first performance data quantity to the remaining member gates (non-target gates) among the member gates in the first group. This mapping is an example of utilizing redundancy in the first performance data. For each standard cell and each second group, generating the first performance database further includes generating a corresponding first performance data quantity, including: determining the first performance data quantity for a target member gate (second target gate) among the member gates in the second group; and mapping the first performance data quantity to the second target gate of the second group, i.e., mapping to the unique member gate of the second group. In some embodiments, the binding includes binding the first performance data quantity to form the first performance database.

[0034] In some embodiments, a method of manufacturing a semiconductor device includes: generating a first performance database for each standard cell in a standard cell library, including: classifying gate features into multi-member groups and single-member groups; generating corresponding first performance data amounts including mappings within the multi-member groups on a group-by-group basis; and binding. For each standard cell comprising a plurality of gates, the classification includes: searching for matching features (matching features) among the features of the gate on a feature-by-feature basis; grouping the corresponding matching features into corresponding first groups, each first group having a plurality of member features; and grouping the unmatching features (unmatching features) among the features that do not have other matching features into corresponding second groups, each second group having a corresponding single member feature. For each standard cell and each first group, generating the first performance database further includes generating corresponding first performance data amounts, including: calculating the first performance data amount individually for a primary feature (first primary feature) among the member features in the first group; mapping the performance data amount to the first primary feature; and mapping the first performance data amount to the remaining member features (non-primary features) among the member features in the first group. This mapping is an example of utilizing redundancy in the first performance data. For each standard cell and each second group, generating the first performance database further includes generating a corresponding first performance data quantity, including: determining the first performance data quantity for a principal feature (second principal feature) among the member features in the second group; and mapping the first performance data quantity to the second principal feature, i.e., mapping to a unique member feature of the second group. In some embodiments, the binding includes binding the first performance data quantity to form the first performance database.

[0035] Figure 1A This is a block diagram of an electronic design automation (EDA) system 100A according to some embodiments.

[0036] The methods disclosed herein include methods for generating performance databases for standard cellular libraries (see below). According to some embodiments, at least some of the methods disclosed herein (e.g., at least some of the flowcharts disclosed herein) are implemented, for example, using an EDA system 100A.

[0037] In some embodiments, EDA system 100A includes an automated place-and-route (APR) system. In some embodiments, EDA system 100A is a general-purpose computing device including hardware processor 102 and non-transitory computer-readable storage medium 104. Storage medium 104 is also encoded (i.e., stored) with computer program code 106 (i.e., a set of executable instructions) among other things. Execution of the computer program code 106 by hardware processor 102 represents (at least partially) an EDA tool for some or all of the methods or similar methods disclosed in one or more embodiments herein (hereinafter referred to as the proposed process and / or method). Storage medium 104 also stores files, among other things, including: a library 107 of standard cells; one or more libraries 109 of performance data corresponding to the standard cells of library 107, such as some or all or similar libraries of performance databases disclosed herein; one or more integrated circuit (IC) designs 111, including functional and / or operational requirements of the IC designs; one or more circuit diagrams 113; one or more layout diagrams 115; and a user interface 117.

[0038] Processor 102 is electrically coupled to computer-readable storage medium 104 via bus 103. Processor 102 is further electrically coupled to input / output (I / O) interface 108 via bus 103. Network interface 110 is further electrically connected to processor 102 via bus 103. Network interface 110 is connected to network 112 so that processor 102 and computer-readable storage medium 104 can be connected to external components via network 112. Processor 102 is configured to execute computer program code 106 encoded in computer-readable storage medium 104 to make system 100A available for implementing part or all of the proposed process and / or method. In one or more embodiments, processor 102 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0039] In one or more embodiments, the computer-readable storage medium 104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 104 includes semiconductor memory or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 104 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0040] In one or more embodiments, storage medium 104 stores computer program code 106, which is configured to enable system 100A (where such execution (at least partially) represents an EDA tool) to perform one or all of the proposed processes and / or methods. In one or more embodiments, storage medium 104 further stores information facilitating the performance of one or all of the proposed processes and / or methods.

[0041] EDA system 100A includes an I / O interface 108 coupled to an external circuit system. In one or more embodiments, the I / O interface 108 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for transmitting information and commands to processor 102.

[0042] EDA system 100A also includes a network interface 110 coupled to processor 102. Network interface 110 enables system 100A to communicate with network 112, which connects to one or more other computer systems. Network interface 110 includes a wireless network interface, such as Bluetooth, Wireless Fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or Wideband Code Division Multiple Access (WCDMA); or a wired network interface, such as Ethernet, Universal Serial Bus (USB), or Institute of Electrical and Electronics Engineers (IEEE) 1364. In one or more embodiments, one or all of the proposed processes and / or methods are implemented in two or more systems 100A.

[0043] System 100A is configured to receive information via I / O interface 108. The information received via I / O interface 108 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 102. The information is transmitted to processor 102 via bus 103. EDA system 100A is configured to receive information related to the user interface (UI) via I / O interface 108. This information is stored as user interface (UI) 117 in computer-readable storage medium 104.

[0044] In some embodiments, one or all of the proposed processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, one or all of the proposed processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, one or all of the proposed processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the proposed processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, one or all of the proposed processes and / or methods are implemented as a software application used by an EDA system 100A. In some embodiments, tools (e.g., available from Cadence Design Systems) are used. (or another suitable layout generation tool) to generate a layout that includes standard cells.

[0045] In some embodiments, the process is achieved in the form of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memory (e.g., ROM, RAM), memory cards, and one or more of the like.

[0046] Figure 1B This is a data flow diagram 120 generated based on a performance database of some embodiments.

[0047] In data flow diagram 120, various information (discussed below) is provided to analysis tool 142, which generates a performance database 144 for a corresponding standard cellular library. Compared to a corresponding analysis tool based on the other method that does not take into account redundancy in the performance data, analysis tool 142 takes into account redundancy in the performance data (discussed below). Analysis tool 142 utilizes redundancy in the performance data, which has the following benefits: (1) reducing the computational load represented by the generation of a given performance database compared to the other method (discussed above) and (2) reducing the file size of the file containing the first performance database compared to the other method, or similar benefits.

[0048] For the purposes of discussion, it is assumed that each standard cell includes a total of M gates ( Figure 2A Each gate has a total of n input terminal pins. Figure 2A), where each of M and n is a positive integer (2≤M and 2≤n) and there are L standard cells in the standard cell library, where L is a large positive integer. To generate a given performance database (e.g., a transmission delay library) corresponding to the standard cell library, for each of the M gates in each standard cell (i.e., for a given gate in a given standard cell), the analysis tool 142 performs a performance data determination once for each of the M*2^^(n*M) combinations of input values, which are applied to (1) the input terminal pins of the given gate in the given standard cell and (2) the input terminal pins of the M-1 other gates in the given standard cell. However, it should be understood that this determination performed by the analysis tool 142 includes not only individual calculations of performance data, but also mapping of previously calculated performance data rather than calculating performance data that is otherwise redundant. Matching gates ( Figures 2B to 2C and Figures 5A to 5N Classifying them into groups or grouping the features of the gate into groups facilitates this mapping.

[0049] In the case of analyzing a given standard cell and further targeting two or more matching gates in the given standard cell ( Figures 2B to 2C and Figures 5A to 5N In an instance of a given group, the computational burden of mapping performance data previously calculated separately for the target members of a given group to the non-target members of the given group is much less than that of the analysis tool 142, which calculates performance data that is otherwise redundant for each of the non-target members of the given group separately. This mapping is an example of utilizing redundancy in the first performance data.

[0050] More specifically, it should be remembered that the inventors have recognized that all but a few of the 2^^(n*(M-1)) combinations, other than those that can belong to the values of the input terminal pins applied to the M-1 other gates, contribute negligibly to the individual calculation of the performance data, i.e., result in redundant performance data. In view of the inventors' recognition, the analysis tool 142 exploits the redundancy in the performance data that can belong to the values of the input terminal pins applied to the M-1 other gates by representing the 2^^(n*(M-1)) combinations of values that can belong to the input terminal pins applied to the M-1 gates using a few combinations of values that can belong to the input terminal pins of the M-1 other gates out of the 2^^(n*(M-1)) combinations of values. The few combinations of values out of the 2^^(n*(M-1)) combinations of values that can belong to the input terminal pins of the M-1 other gates are represented by J, where typically J < n. In some embodiments, J = 1. Thus, the analysis tool 142 performs a separate calculation of the performance data for each of the 2^^(n*M) combinations of input values applied to (1) the input terminal pins of a given gate in a given standard cell and (2) the few combinations of values that can belong to the input terminal pins of the M-1 other gates out of the 2^^(n*(M-1)) combinations of values. Thus, the analysis tool 142 performs J*2^^n individual calculations of the performance data for a given gate. The J*2^^n individual calculations of the performance data for a given gate performed by the analysis tool 142 are substantially fewer than the 2^^(n*M) individual calculations of the performance data originally performed for a given gate according to the other method. In such an embodiment, the exploitation of the performance data redundancy by the analysis tool 142 results in fewer separate calculations for a given gate, where the difference Δ can be expressed as Δ = 2^^(n*M) - J*2^^n. This embodiment of the present application, with J*2^^n individual calculations of the performance data for a given gate, advantageously shows a reduction in the number of individual calculations performed by a factor of 2 to the power of M orders of magnitude compared to the 2^^(n*(M-1)) individual calculations of the performance data for a given gate performed by the other method, which is a substantial reduction and thus represents a substantial reduction in the computational burden on the EDA system.

[0051] In Figure 1BThe various information provided to the analysis tool 142 includes: a grouping template 138; a preset pin value (pin preset pattern) template 140; a tool command language (Tcl) script 126 for setting up the analysis; a process, voltage, and temperature (PVT) parameter list (PVT list) 128; an integrated circuit general simulation program with integrated circuit emphasis (SPICE) model card 130; and a layout parameter extractor (LPE) file 132. Each of the Tcl script 126, the PVT list 128, the SPICE model card 130, and the layout parameter extractor file 132 is an example of information conventionally provided to the analysis tool 142. In contrast, embodiments of this application additionally provide the analysis tool 142 with preset patterns of the grouping template 138 and the pin value template 140, which in part reflects that the data flow takes into account redundancy in the performance data when generating the performance database 144.

[0052] exist Figure 1B In the middle, group template 138 ( Figure 4A , Figure 4D , Figures 5A to 5N (Or a similar figure) is generated by process 134, which operates on the golden library template 122. Process 134 defines the grouped data structure reflected in the grouping template 138. The golden library template 122 is an example of information that is conventionally provided directly to analysis tools according to the other method.

[0053] Preset pattern of side connector pin value template 140 ( Figures 4B to 4C , Figures 4E to 4F (or a similar figure) is produced by process 136, which operates on arc template 124. In some embodiments, regarding Figure 1BThe side pin value template 140, using the adjective "side" to modify the phrase "pin preset pattern template," aims to imply that the values ​​on the input terminal pins of the M-1 gates (M-1 other gates) besides the given gate do not affect the logic value on the output terminal pin of the given gate. Furthermore, in this embodiment, using the adjective "side" to modify the phrase "pin preset pattern template" aims to imply that the contribution of all input terminal pins other than a few (e.g., one) of the input terminal pins of the M-1 gates (M-1 other gates) besides the given gate to the discrete calculation of performance data is negligible for the calculation of performance data for the n input terminal pins of a given cell in a standard cell. Figure 2B ).

[0054] In some embodiments, "arc" is another term for performance data corresponding to a given combination of 2^(n*M) combinations of input values ​​applied to (1) the input terminal pins of a given gate in a given standard cell and (2) the input terminal pins of M-1 other gates in a given standard cell. Arc template 124 is an example of information conventionally provided directly to analysis tools according to the other method.

[0055] Figures 2A to 2C These are block diagrams of the corresponding standard cells 200A to 200C according to some embodiments.

[0056] exist Figures 2A to 2C In this standard cell, each of 200A to 200C includes gates 206(1), 206(2), ..., 206(M), i.e., a total of M gates. Each of gates 206(1) to 206(M) has a total of n input terminal pins. Each of M and n is a positive integer, 2≤M and 2≤n. In some embodiments, one or more, but not all, of gates 206(1) to 206(M) have several pins in addition to the n pins.

[0057] Gate 206(1) has input terminal pins A1, A2, ..., and An, and output terminal pin ZA. Gate 206(2) has input terminal pins B1, B2, ..., and Bn, and output terminal pin ZB. Gate 206(M) has input terminal pins M1, M2, ..., and Mn, and output terminal pin ZM. In some embodiments, each of gates 206(1) to 206(M) includes a second output terminal pin.

[0058] exist Figure 2B In this document, the various embodiments disclosed herein have not yet been implemented. Figures 2B to 2C (or similar embodiments) subject the standard cell 200A to grouping. In contrast, in Figures 2B to 2CIn this document, the corresponding standard cells 200B to 200C have been grouped according to the various embodiments disclosed herein.

[0059] exist Figure 2B In this document, standard cell 200B has been grouped according to various embodiments disclosed herein. More specifically, gates 206(1) to 206(M) are classified on a gate-by-gate basis for matched gates (matching gates) among the gates. In some embodiments, classification on a gate-by-gate basis means classification based on the properties of the gate as a whole. For example, the properties of a logic gate as a whole are the logical functions performed by logic gates (NOT, AND, OR, XOR, NAND, NOR, XNOR, AND-OR-Inverter (AOI), OR-AND-Inverter (OAI), or similar gates). For example, the overall attribute of a flip-flop gate is the type of storage function performed by the flip-flop gate, such as a set-reset (SR) flip-flop, a JK flip-flop, a data / delay (D) flip-flop, a toggle (T) flip-flop, and any such flip-flop or similar flip-flop including preset and clear input terminal pins. Figure 2B In this context, the gate type is the overall attribute upon which classification and matching are based. In some embodiments, the gate type refers to the function performed by the gate. Figure 2B (or a similar diagram).

[0060] In some embodiments, gate type refers to the current drive capability at the output terminal pin of the gate. In some embodiments, gate type refers to the threshold voltage of the transistor in the gate. In some embodiments, gate type refers to the power domain in which the gate operates. In some embodiments, gate type refers to the height of the gate on the Y-axis. Figure 6A Or a similar diagram). In some embodiments, the gate type refers to the number of fins in the gate (or similar figures). Figure 6B Or a similar diagram). In some embodiments, the gate type refers to the width of the gate on the X-axis (or similar diagram). Figure 6C Or similar figures). In some embodiments, gate type refers to the number of nanosheets in each of the P-type metal-oxide-semiconductor (PMOS) and N-type metal-oxide-semiconductor (NMOS) active regions of the gate. Figure 6DOr a similar diagram). In some embodiments, the gate type refers to the circuit topology (circuit connection relationship) of the gate, such as a transmission gate topology (or similar diagram). Figure 6E Or a similar diagram) for stacked gate topology ( Figure 6F Or a similar diagram). In some embodiments, for a transmission gate topology, the gate type refers to a Q-type coupler (or similar). Figure 6G (or a similar figure) for RPQ type couplers ( Figure 6H or a similar sub-circuit topology (or a similar diagram).

[0061] exist Figure 2B In this process, matched gates are grouped into corresponding first groups 202B, each first group 202B having multiple member gates (multi-member groups). For unmatched gates (unmatched gates) that do not have other matched gates, the unmatched gates are grouped into corresponding second groups 204B, each second group 204B having a corresponding single member gate (single-member group). For simplicity, a single instance of the first group 202B is shown as corresponding to a type A gate. Similarly, for simplicity, a single instance of the second group 204B is shown as corresponding to a type B gate.

[0062] exist Figure 2C In this document, standard cell 200C has been grouped according to various embodiments disclosed herein. More specifically, gates 206(1) to 206(M) are classified on a feature-by-feature basis for matching features (matching features) among the features of the gates. In some embodiments, classification on a feature-by-feature basis means classification based on the attributes of individual input terminal pins, i.e., each input terminal pin represents a feature of a given gate. For example, in the case where at least some gates in the standard cell are flip-flop gates, flip-flop gates are classified based on the type of input terminal pins. Figure 2C In this context, the gate attributes upon which classification and matching are based are feature types. In some embodiments, a feature type refers to an input terminal pin, meaning that each input terminal pin of a given gate represents a feature of that given gate.

[0063] exist Figure 2C In this context, matching features are grouped into corresponding first groups 202C(1), 202C(2), 202C(3) or similar first groups, each of the first groups 202C(1) to 202C(2) having multiple member features. For unmatched features (unmatched features) that do not have other matching features, the unmatched features are grouped into corresponding second groups (not shown), each second group having a corresponding single member feature. For the sake of simplicity, three examples of the first groups 202C(1) to 202C(3) are shown corresponding to the first input pin, the second input terminal pin, and the nth input terminal pin.

[0064] Figures 3A to 3C is a block diagram of a standard cell 300 according to some embodiments.

[0065] Figures 3A to 3C is similar to Figure 2B each of which shows the standard cell 300, but different combinations of input values are applied to the gates 306(1), 306(2),..., and 306(M). Each of the gates 306(1) to 306(M) has n input terminal pins. In some embodiments, one or more but not all of the gates 306(1) to 306(M) have several pins in addition to the n pins. Just as Figures 3A to 3C in general, Figure 2B it is assumed that the standard cell 300 is grouped on a per-gate basis according to various embodiments disclosed herein. Figures 3A to 3C

[0066] Figures 3A to 3C In the overall property of the gates based on which classification and matching are performed is the gate type. In some embodiments, the gate type refers to the function performed by the gate.

[0067] Gate 306(1) is a type-A gate. Gate 306(2) is a type-B gate. Another gate is a type-C gate. At least one of these gates is a member of a multi-member group that includes M gates. It is assumed that each of the gates 306(1) to 306(2) is a representative member (target gate) of its corresponding one or more gate groups.

[0068] Figure 3A shows the combination of input values applied to the gates 306(1), 306(2),..., and 306(M) when calculating the corresponding first amount of performance data for gate 306(1) in an individual manner, where gate 306(1) is also the representative gate of the group to which it belongs. In the instance where the group is a multi-member group, the first amount of performance data calculated for gate 306(1) in an individual manner is mapped to gate 306(1) as the representative gate and also to the remaining member gates (not shown) among the member gates in the first group (i.e., non-representative gates). Such mapping is an example of using redundancy in the performance data.

[0069] Figure 3A More specifically, it should be remembered that the analysis tool 142 utilizes the redundancy in the performance data attributable to the values of the input terminal pins applied to the M - 1 other gates by representing, instead of the 2^^(n*(M - 1)) combinations of values attributable to the input terminal pins applied to the M - 1 gates, J representative combinations among the 2^^(n*(M - 1)) combinations, where typically J < n. In Figures 3B to 3C and also in Figure 3A it is assumed that J = 1. Therefore, in Figure 3A In the middle, the preset pattern of the input terminal pin receiving values ​​of non-target gates 306(2), ..., 306(M) is shown. Figures 4B to 4C ).

[0070] Figure 3B This represents the combination of input values ​​applied to gates 306(1), 306(2), ..., 306(M) when calculating the corresponding first performance data amount for gate 306(2) individually, where gate 306(2) is the representative gate of the group to which it is a member. In an instance where the group is a multi-member group, the first performance data amount calculated individually for gate 306(2) is mapped to gate 306(2) as the representative gate and also to the remaining member gates (not shown) (i.e., non-representative gates) in the first group. This mapping is an example of utilizing redundancy in performance data. Furthermore, in Figure 3B In the middle, the preset pattern of the input terminal pin receiving values ​​of non-target gates 306(1), ..., 306(M) is shown. Figures 4B to 4C ).

[0071] Figure 3C This represents the combination of input values ​​applied to gates 306(1), 306(2), ..., 306(M) when calculating the corresponding first performance data amount individually for gate 306(M), where gate 306(M) is the representative gate of the group to which it is a member. In an instance where the group is a multi-member group, the first performance data amount calculated individually for gate 306(2) is mapped to gate 306(2) as the representative gate and also to the remaining member gates (not shown) (i.e., non-representative gates) in the first group. This mapping is an example of utilizing redundancy in performance data. Furthermore, in Figure 3C In the middle, the preset pattern of the input terminal pin receiving values ​​of non-target gates 306(1), 306(2), ... Figures 4B to 4C ).

[0072] Figure 3D This is a block diagram of a standard cell 301 according to some embodiments.

[0073] Figure 3D and Figure 2C and Figure 3A Each of them is similar. Figure 3D The standard cell 301 is shown, including gates 307(1), 307(2), 307(3), ..., and 307(M). As... Figure 2C generally, Figure 3DAssume that the standard cell 301 is grouped on a feature-by-feature basis according to the various embodiments disclosed herein. Each of gates 307(1), 307(2), 307(3), ..., and 307(M) has a frequency input for receiving a frequency signal CP.

[0074] exist Figure 3D In this circuit, standard cell 301 is a multi-bit flip-flop. Each of gates 307(1), 307(2), 307(3), ..., and 307(M) is a unit cell flip-flop, such that gates 307(1), 307(2), 307(3), ..., and 307(M) respectively represent bits 1, 2, 3, ..., M. Gate 307(1) also has a data input terminal pin D1 and a data output terminal pin Q1. Gate 307(2) also has a data input terminal pin D2 and a data output terminal pin Q2. Gate 307(3) also has a data input terminal pin D3 and a data output terminal pin Q3. Gate 307(M) also has a data input terminal pin DM and a data output terminal pin QM.

[0075] exist Figure 3D In this context, the attribute of the gate upon which classification and matching are based is the feature type. Figure 3D In this context, we assume that the feature type refers to the input terminal pins, i.e., input terminal pins D1, D2, D3, ..., DM represent the features of gates 307(1), 307(2), 307(3), ..., and 307(M) that can be classified for matching.

[0076] exist Figure 3D Furthermore, it is assumed that input terminal pins D1, D2, D3, and DM represent different characteristics. In some embodiments, "arc" is another term for performance data. Figure 3D In this context, the calculated arc is the arc from the input terminal pin of the received frequency signal CP to the output terminal pin (e.g., output terminal pin Q1 of gate 307(1)). At least one of the input terminal pins D1, D2, D3, and DM is a member of a multi-member group, which includes data input terminal pins (not shown) of M gates excluding gates 307(2), 307(3), and 307(M). It is assumed that each of the input terminal pins D1, D2, D3, and DM is a representative member (target feature) of the corresponding group of one or more input terminal pins of the corresponding gate.

[0077] Figure 3DThis refers to the combination of input values ​​applied to gates 307(1), 307(2), 307(3), ..., 307(M) when calculating the corresponding first performance data amount for the feature represented by input terminal pin D1 of gate 307(1) individually, where input terminal pin D1 of gate 307(1) is a representative feature, and therefore gate 307(1) is the representative gate of the group to which it is a member. In an example where the group is a multi-member group, the first performance data amount calculated individually for input terminal pin D1 of gate 307(1) is mapped to the input terminal pin D1 of the representative gate 307(1) as a representative feature and also to the remaining member features (not shown) (i.e., non-representative gates) in the member features of the first group. This mapping is an example of utilizing redundancy in performance data. In addition, Figure 3D In the middle, the preset pattern of the received values ​​of the data input terminal pins of the non-target gates 307(2), 307(3), ..., 307(M) is shown. Figures 4E to 4F ).

[0078] Figure 4A It is a data structure 450 of the performance data of a standard cell according to some embodiments.

[0079] Figures 4B to 4C It is a representation of the corresponding value combination on the input terminal pins according to some embodiments.

[0080] Based on at least some of the method embodiments disclosed herein, Figures 4A to 4C This facilitates classification and mapping in a group-by-group manner.

[0081] exist Figure 4A In this context, data structure 450 is an example of a data structure as follows: As part of generating performance database 144, analysis tool 142 populates the data structure with data from corresponding standard cells in the standard cell library. To generate performance database 144, analysis tool 142 iteratively populates data structure 450 for each standard cell in the standard cell library.

[0082] Data structure 450 includes a nested data structure. At the top nesting level, data structure 450 includes a data structure Cell(name_1), where name_1 is a variable that identifies the standard cell to which the performance data of data structure 450 belongs.

[0083] exist Figure 4A In the next nested level, Cell(name_1) includes one or more bundle data structures (gate_type), where gate_type is a variable that identifies the gate type that the members of the group match. Figure 4A For the sake of brevity, data structure 450 shows two instances of bundle(gate_type), namely bundle(Z1) and bundle(Z2). Figure 4A In this context, we assume that the gate is a logic gate and that the gate type is a logic function of the gate; therefore, variables Z1 and Z2 identify two different logic functions. In practice, the number of instances of `bundle(gate_type)` is specific to a given standard cell and depends on the number of groups identified within that given standard cell.

[0084] At the next nested level, each of bundle(Z1) and bundle(Z2) includes: the first statement members(gate_name,...); the second statement subject pin(pin_name); and the data structure prfrmnc_data.

[0085] Generally, the first statement `members(gate_name,...)` identifies one or more members of the group. Figure 4A For the sake of brevity, bundle(Z1) is shown as a multi-member group and bundle(Z2) as a single-member group. In bundle(Z1), the first instance members(ZA,ZB) of the first statement identifies the members of the multi-member group as gates with output terminal pins ZA and ZB. In bundle(Z2), the second instance members(ZM) of the first statement identifies the members of the single-member group as gates with output terminal pins ZM.

[0086] about Figure 4A Generally, the second statement `subject pin(pin_name)` identifies one of the gates in the gate group as the target gate, that is, it identifies the representative gate for which individual performance data is to be calculated. The performance data calculated individually for the target gate is mapped not only to the target gate but also to the remaining gates in the group (i.e., to the non-target gates in the group). This mapping is an example of utilizing redundancy in performance data. In bundle(Z1), the first instance of the second statement `subject pin(ZA)` identifies the target gate as having output terminal pin ZA. In bundle(Z2), the second instance of the second statement `subject pin(ZM)` identifies the target gate as having output terminal pin ZM.

[0087] exist Figure 4AIn the example, the instance prfrmnc_data of the data structure in bundle (Z1) is labeled with data structure 452(1), and the instance prfrmnc_data of the data structure in bundle (Z2) is labeled with data structure 452(2). Each of data structures 452(1) to 452(2) is an array containing J*2^n performance data values, which correspond to J*2^n combinations of values ​​that may belong to the values ​​applied to the n input terminal pins of the target gate and several combinations of values ​​that may belong to the input terminal pins of M-1 other gates from among 2^^(n*(M-1)) value combinations. For the sake of simplicity, Figure 4A Assume J = 1. Data structure 452(1) has a decomposed graph 454(1). Data structure 452(2) has a decomposed graph 454(2).

[0088] In the exploded diagram 454(1), the when statement associated with an entry in data structure 452(1) (i.e., the when statement associated with a performance data value in data structure 452(1)) identifies the combination of input values ​​that generate the corresponding entry. In other words, each performance data value in data structure 452(1) has a when statement that indicates the combination (causal combination) of values ​​of the input terminal pins of the target gate corresponding to the performance data value.

[0089] It should be noted that Figure 4A as well as Figure 4D The notation convention is used, where the logic low value (logic zero) of an input pin is represented by a text string, in which an exclamation mark precedes the input pin name. For example, the text string !A1 indicates that the value of input pin A1 is logic low (logic zero), i.e., A1 = 0. Conversely, according to the notation convention, the logic high value (logic one) of an input pin is represented by a text string, in which no exclamation mark precedes the input pin name. For example, the text string A1 indicates that the value of input pin A1 is logic high (logic zero), i.e., A1 = 1.

[0090] exist Figure 4A In the context, it should be remembered that the target gate of bundle(Z1) is gate A with output terminal pin ZA. The when statement of the first entry in data structure 452(1) indicates that the causal combination is ! A1&! A2&! A3&...&! Mn&preset_side_pin_pattern_for_ZA. The text string preset_side_pin_pattern_for_ZA is in Figure 4BThe diagram shows and represents the unique combination of input terminal pin values ​​belonging to M-1 other gates that will be considered during the calculation of performance data values ​​for the corresponding entries in data structure 452(1). Therefore, the first entry in data structure 452(1) corresponds to the causal combination 0&0&0&...&0&preset_side_pin_pattern_for_ZA. The when statement of the last entry in data structure 452(1) indicates that the causal combination is A1&A2&A3&...&Mn&preset_side_pin_pattern_for_ZA. Therefore, the first entry in data structure 452(1) corresponds to the causal combination 1&1&1&...&1&preset_side_pin_pattern_for_ZA.

[0091] Regarding the decomposition diagram of data structure 452(2) 454(2), it should be remembered that the target gate of bundle(Z2) is the gate M with output terminal pin ZM. The when statement of the first entry in data structure 452(2) indicates the causal combination is: ! M1&! M2&! M3&...&! Mn&preset_side_pin_pattern_for_ZM. The text string preset_side_pin_pattern_for_ZM is in Figure 4C The diagram shows and represents the unique combination of input terminal pin values ​​attributable to M-1 other gates that will be considered during the calculation of performance data values ​​for the corresponding entries in data structure 452(1). Therefore, the first entry in data structure 452(1) corresponds to the causal combination 0&0&0&...&0&preset_side_pin_pattern_for_ZA. The when statement of the last entry in data structure 452(1) indicates that the causal combination is M1&M2&M3&...&Mn&preset_side_pin_pattern_for_ZA. Therefore, the first entry in data structure 452(1) corresponds to the causal combination 1&1&1&...&1&preset_side_pin_pattern_for_ZA.

[0092] about Figure 4AIn some embodiments, the performance data of a given target gate assumes a slew rate and a load value for the target gate; this is referred to herein as a shade of the performance data of the given target gate. In some embodiments, the slew rate of a given input terminal pin of the given gate is the rate at which the signal amplitude changes from 10% to 90% of the maximum amplitude of the signal. In some embodiments, the output load more specifically refers to the capacitance of the load. In some embodiments, the performance data of a given target gate varies with multiple (P×R) combinations of P slew rates and R output loads, such that there are P×R shades of performance data for the given target gate, where P and R are corresponding positive integers and satisfy at least one of 2≤P or 2≤R. The P×R shades of the performance data in Figure 4A The array is shown as an optional P×R subarray 456. For example, with P=5 and R=5, there are 25 hues of performance data for a given target gate.

[0093] about Figure 4B `preset_side_pin_pattern_for_ZA` includes: preset sub-patterns for the values ​​of input terminal pins B1, B2, ..., Bn of a gate with output terminal pin ZB; ...; and preset sub-patterns for the values ​​of input terminal pins M1, M2, ..., Mn of a gate with output terminal pin ZM. (Regarding...) Figure 4C The preset_side_pin_pattern_for_ZM includes: preset subpatterns for the values ​​of input terminal pins A1, A2, ..., An of a gate with output terminal pin ZA; ...; and preset subpatterns for the values ​​of input terminal pins L1, L2, ..., Ln of a gate with output terminal pin ZL.

[0094] In some embodiments, preset_side_pin_patterns (e.g., preset_side_pin_pattern_for_ZA and preset_side_pin_pattern_for_ZM) represent the worst-case scenario. In some embodiments, preset_side_pin_patterns (e.g., preset_side_pin_pattern_for_ZA and preset_side_pin_pattern_for_ZM) are determined empirically based on analysis of large data types in existing repositories of previous standard cell libraries and corresponding previous performance databases.

[0095] In some embodiments, preset_side_pin_patterns (e.g., preset_side_pin_pattern_for_ZA and preset_side_pin_pattern_for_ZM) are determined by simulation, for example, performed by analysis tool 142 or similar tools.

[0096] Figure 4D It is a data structure 458 of the performance data of standard cells according to some embodiments.

[0097] Figures 4E to 4F It is a representation of the corresponding value combination on the input terminal pins according to some embodiments.

[0098] Based on at least some of the method embodiments disclosed herein, Figures 4D to 4F It facilitates classification and mapping in a feature-by-feature manner.

[0099] exist Figure 4D In this example, data structure 458 is as follows: As part of generating performance database 144, analysis tool 142 populates the data structure with data from corresponding standard cells in the standard cell library. To generate performance database 144, analysis tool 142 iteratively populates data structure 458 for each standard cell in the standard cell library.

[0100] Data structure 458 includes nested data structures. At the top nesting level, data structure 458 includes a data structure Cell(name_1), where name_1 is a variable that identifies the standard cell to which the performance data of data structure 458 belongs.

[0101] exist Figure 4D In the next nested level, Cell(name_1) includes one or more grouped data structures bundle(feature_type), where feature_type is a variable that identifies the feature type matched by the members of the group. Figure 4D For the sake of brevity, data structure 458 shows two instances of (feature_type), namely (I1) and (I2). Figure 4D In this context, the feature is assumed to be an input terminal pin; therefore, variables I1 and I2 identify two different input terminal pins (i.e., input terminal pin I1 and input terminal pin I2). In practice, the number of instances of (feature_type) is specific to a given standard cell and depends on the number of groups identified within that given standard cell.

[0102] At the next nested level, each of bundle(I1) and bundle(I2) includes: the first statement members(feature_name,...); the second statement subject pin(pin_name); and the data structure prfrmnc_data.

[0103] Generally, the first statement `members(feature_name,...)` identifies one or more members of the group. Figure 4D For the sake of brevity, each of bundle(I1) and bundle(I2) is shown as a multi-member group. In bundle(I1), the first instance of the first statement, members(A1,...,M1), identifies the members of the multi-member group as the first input terminal pin (i.e., input terminal pins A1,...,M1) among the n input terminal pins of each of the M gates. In bundle(I2), the second instance of the first statement, members(An,...,Mn), identifies the members of the multi-member group as the last input terminal pin (i.e., input terminal pins An,...,Mn) among the n input terminal pins of each of the M gates.

[0104] about Figure 4D Generally, the second statement `subject pin(pin_name)` identifies one feature from a group of features as the target feature, that is, it identifies the representative feature for which discrete performance data will be computed. Performance data computed discretely against the target feature is mapped not only to the target feature but also to the remaining features in the group (i.e., to the non-target features in the group). This mapping is an example of utilizing redundancy in performance data. In `bundle(I1)`, the first instance of the second statement `subject pin(A1)` identifies the target feature as input pin A1. In `bundle(I2)`, the second instance of the second statement `subject pin(An)` identifies the target feature as input pin An.

[0105] exist Figure 4DIn the example, the instance prfrmnc_data of the data structure in bundle(I1) is labeled with data structure 460(1), and the instance prfrmnc_data of the data structure in bundle(I2) is labeled with data structure 460(2). Each of data structures 460(1) to 460(2) is an array containing J*2^n performance data values, which correspond to J*2^n combinations of values ​​that may belong to the values ​​of the n input terminal pins of the gate including the target feature, and 2^^(n*(M-1)) combinations of values ​​that may belong to the input terminal pins of M-1 other features. For the sake of simplicity, Figure 4D Assume J = 1. Data structure 460(1) has a decomposed graph 462(1). Data structure 460(2) has a decomposed graph 462(2).

[0106] In the exploded diagram 462(1), the when statement associated with an entry in data structure 460(1) (i.e., the when statement associated with the performance data value in array prfrmnc_data 460(1)) identifies the combination of input values ​​that generate the corresponding entry. In other words, each performance data value in data structure 460(1) has a when statement that indicates a combination (causal combination) of values ​​of the input terminal pins of the target gate that includes the target feature corresponding to the performance data value.

[0107] exist Figure 4D In the middle, it should be remembered that the main feature of bundle(I1) is the input terminal pin A1. The when statement of the first entry in data structure 460(1) indicates that the causal combination is ! A1&! A2&! A3&...&! Mn&preset_side_pin_pattern_for_A1. The text string preset_side_pin_pattern_for_A1 is in Figure 4E The diagram shows and represents the unique combination of input terminal pin values ​​attributable to M-1 other features that will be considered during the calculation of performance data values ​​for the corresponding entries in data structure 460(1). Therefore, the first entry in data structure 460(1) corresponds to the causal combination 0&0&0&...&0&preset_side_pin_pattern_for_A1. The when statement of the last entry in data structure 460(1) indicates that the causal combination is A1&A2&A3&...&Mn&preset_side_pin_pattern_for_A1. Therefore, the first entry in data structure 460(1) corresponds to the causal combination 11&1&1&...&1&preset_side_pin_pattern_for_A1.

[0108] Regarding the decomposition diagram 462(2) of data structure 460(2), it should be remembered that the target feature of bundle(I2) is the input terminal pin A2. The when statement of the first entry in data structure 460(2) indicates the causal combination is: M1&! M2&! M3&...&! Mn&preset_side_pin_pattern_for_An. The text string preset_side_pin_pattern_for_An is in Figure 4F The diagram shows and represents the unique combination of input terminal pin values ​​attributable to M-1 other features that will be considered during the calculation of performance data values ​​for the corresponding entries in data structure 460(1). Therefore, the first entry in data structure 460(1) corresponds to the causal combination 0&0&0&...&0&preset_side_pin_pattern_for_An. The when statement of the last entry in data structure 460(1) indicates that the causal combination is M1&M2&M3&...&Mn&preset_side_pin_pattern_for_An. Therefore, the first entry in data structure 460(1) corresponds to the causal combination 1&1&1&...&1&preset_side_pin_pattern_for_An.

[0109] about Figure 4D In some embodiments, performance data for a given target feature assumes a rotation rate and a load value for that target feature; this is referred to herein as a hue of the performance data for the given target feature. In some embodiments, the performance data for a given target feature varies with multiple (P×R) combinations of P rotation rates and R output loads, such that there are P×R hues of performance data for the given target feature, where P and R are corresponding positive integers and satisfy at least one of 2≤P or 2≤R. The P×R hues of the performance data in Figure 4D The array is shown as an optional P×R subarray 464. For example, with P=5 and R=5, there are 25 hues of performance data for a given target feature.

[0110] Figures 5A to 5F These are the corresponding data structures 550A to 550F for performance data according to some embodiments.

[0111] Figures 5A to 5F and Figure 4A Similar. In some embodiments, arc is another term for performance data.

[0112] exist Figure 5AIn the data structure 550A, data structure 552A(1) to 552A(2) are used as two instances of data structure timing_arc, and the two instances are Figure 4A Examples of data structures 452(1) to 452(2) are shown. Each of data structures 552A(1) to 552A(2) is a performance data type, which represents the elapsed time for the target gate to produce the corresponding stable output value (i.e., the propagation delay). Each of data structures 552A(1) to 552A(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the corresponding propagation delay.

[0113] exist Figure 5B In the data structure 550B, data structure 552B(1) to 552B(2) are used as two instances of data structure power_arc, the two instances being Figure 4A Examples of data structures 452(1) to 452(2) are shown. Each of data structures 552B(1) to 552B(2) is a performance data type, which represents the amount of power consumed when the target gate produces the corresponding stable output value. Each of data structures 552B(1) to 552B(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the corresponding power consumption.

[0114] exist Figure 5C In the data structure 550C, data structure 552C(1) to 552C(2) are used as two instances of the data structure setup-time_arc, and the two instances are Figure 4A Examples of data structures 452(1) to 452(2) are shown. Each of data structures 552C(1) to 552C(2) is a performance data type, which represents the minimum elapsed time that the output data must be kept stable by the target gate before the next effective frequency edge. Each of data structures 552C(1) to 552C(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the temperature corresponding to the set time.

[0115] exist Figure 5D In the data structure 550D, data structure 552D(1) to 552D(2) are used as two instances of the data structure hold-time_arc. Figure 4AExamples of data structures 452(1) to 452(2) are shown. Each of data structures 552D(1) to 552D(2) is a performance data type, which represents the minimum elapsed time after which the input of the target gate must remain stable after the effective frequency edge. Each of data structures 552D(1) to 552D(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the corresponding hold time.

[0116] exist Figure 5E In the data structure 550E, there are two instances of data structure 552E(1) to 552E(2) used as the data structure recovery-time_arc, and the two instances are Figure 4A Examples of data structures 452(1) to 452(2) are shown. Each of data structures 552E(1) to 552E(2) is a performance data type that represents the minimum permissible elapsed time from the de-assert of the reset signal to the next effective frequency edge required for the target gate. Each of data structures 552E(1) to 552E(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the corresponding recovery time.

[0117] exist Figure 5F In the data structure 550F, there are two instances of data structures 552F(1) to 552F(2) used as the data structure removal-time_arc. Figure 4A Examples of data structures 452(1) to 452(2) are shown. Each of data structures 552F(1) to 552F(2) is a performance data type that represents the minimum permissible elapsed time after the next effective frequency edge before the reset signal is de-set by the target gate. Each of data structures 552F(1) to 552F(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the temperature corresponding to the removal time.

[0118] Figure 5G to Figure 5N It is the corresponding data structure 558G to 558N for performance data according to some embodiments.

[0119] Figure 5G to Figure 5N and Figure 4A Similar. In some embodiments, arc is another term for performance data.

[0120] exist Figure 5GIn the data structure 558G, data structure 552G(1) to 552G(2) are used as two instances of data structure timing_arc, and the two instances are Figure 4D Examples of corresponding data structures 460(1) to 460(2) are shown. Each of data structures 552G(1) to 552G(2) is a performance data type, representing the elapsed time during which the target gate produces the corresponding stable output value (i.e., propagation delay). In some embodiments, the elapsed time, represented by a timing arc, is from the effective edge of the frequency signal until the target gate produces the corresponding stable output value. Each of data structures 552G(1) to 552G(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the corresponding propagation delay. Each of data structures 552G(1) to 552G(2) also includes the statement relative_pin:name_2, where name_2 represents an input terminal pin included in the path of interest (e.g., for...). Figure 3D The variable is the name of the input terminal pin (or similar input terminal pin) of the frequency signal CP in the input.

[0121] exist Figure 5H In the data structure 558H, data structure 552H(1) to 552H(2) are used as two instances of data structure power_arc, and the two instances are Figure 4D Examples of corresponding data structures 460(1) to 460(2) are shown. Each of data structures 552H(1) to 552H(2) is a performance data type, representing the amount of power consumed when the target gate produces the corresponding stable output value. Each of data structures 552H(1) to 552H(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the corresponding power consumption. Each of data structures 552H(1) to 552H(2) also includes the statement relative_pin:name_2, where name_2 represents the input terminal pin included in the path of interest (e.g., for...). Figure 3D The variable is the name of the input terminal pin (or similar input terminal pin) of the frequency signal CP in the input.

[0122] exist Figure 5I In the data structure 558I, data structure 552I(1) to 552I(2) are used as two instances of the data structure setup-time_arc, and the two instances are Figure 4DExamples of corresponding data structures 460(1) to 460(2) are shown. Each of data structures 552I(1) to 552I(2) is a performance data type, which represents the minimum elapsed time before the next effective frequency edge that the output data must be kept stable by the target gate. Each of data structures 552I(1) to 552I(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the temperature corresponding to the set time. Each of data structures 552I(1) to 552I(2) also includes the statement relative_pin:name_2, where name_2 represents the input terminal pin included in the path of interest (e.g., for...). Figure 3D The variable is the name of the input terminal pin (or similar input terminal pin) of the frequency signal CP in the input.

[0123] exist Figure 5J In the data structure 558J, data structure 552J(1) to 552J(2) are used as two instances of the data structure hold-time_arc. Figure 4D Examples of data structures 460(1) to 460(2) are shown. Each of data structures 552J(1) to 552J(2) is a performance data type, representing the minimum elapsed time after which the input of the target gate must remain stable following the effective frequency edge. Each of data structures 552J(1) to 552J(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the corresponding holding time. Each of data structures 552J(1) to 552J(2) also includes the statement relative_pin:name_2, where name_2 represents the input terminal pin included in the path of interest (e.g., for...). Figure 3D The variable is the name of the input terminal pin (or similar input terminal pin) of the frequency signal CP in the input.

[0124] exist Figure 5K In the data structure 558K, there are two instances of data structures 552K(1) to 552K(2) used as the data structure recovery-time_arc. Figure 4DExamples of data structures 460(1) to 460(2) are shown. Each of data structures 552K(1) to 552K(2) is a performance data type, representing the minimum permissible elapsed time from the reset signal being de-set to the next effective frequency edge required for the target gate. Each of data structures 552K(1) to 552K(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the corresponding recovery time. Each of data structures 552K(1) to 552K(2) also includes the statement relative_pin:name_2, where name_2 represents the input terminal pin included in the path of interest (e.g., for...). Figure 3D The variable is the name of the input terminal pin (or similar input terminal pin) of the frequency signal CP in the input.

[0125] exist Figure 5L In the data structure 558L, there are two instances of data structures 552L(1) to 552L(2) used as the data structure removal-time_arc, and the two instances are Figure 4D Examples of corresponding data structures 460(1) to 460(2) are shown. Each of data structures 552L(1) to 552L(2) is a performance data type, representing the minimum permissible elapsed time after the next effective frequency edge, before which the reset signal is de-set by the target gate. Each of data structures 552L(1) to 552L(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the temperature corresponding to the removal time. Each of 552L(1) to 552L(2) also includes the statement relative_pin:name_2, where name_2 represents the input terminal pin included in the path of interest (e.g., for...). Figure 3D The variable is the name of the input terminal pin (or similar input terminal pin) of the frequency signal CP in the input.

[0126] exist Figure 5M In the data structure 558M, data structure 552M(1) to 552M(2) are used as two instances of the data structure clear-time_arc. Figure 4DExamples of data structures 460(1) to 460(2) are shown. Each of data structures 552M(1) to 552M(2) is a performance data type, representing the minimum elapsed time after the clear pin is enabled for the target gate to produce a stable logic low output value. Each of data structures 552M(1) to 552M(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the corresponding clear time. Each of data structures 552M(1) to 552M(2) also includes the statement relative_pin:name_2, where name_2 represents the input terminal pin included in the path of interest (e.g., for...). Figure 3D The variable is the name of the input terminal pin (or similar input terminal pin) of the frequency signal CP in the input.

[0127] exist Figure 5N In the data structure 558N, data structure 552N(1) to 552N(2) are used as two instances of the data structure preset-time_arc. Figure 4D Examples of data structures 460(1) to 460(2) are shown. Each of data structures 552N(1) to 552N(2) is a performance data type, representing the minimum elapsed time after the default pin is enabled for the target gate to produce a stable logic high output value. Each of data structures 552N(1) to 552N(2) includes the statement temperature:temp_value, where temp_value is a variable representing the temperature at which the target gate exhibits the temperature corresponding to the default time. Each of data structures preset-time_arc 552N(1) to 552N(2) also includes the statement relative_pin:name_2, where name_2 represents the input terminal pin included in the path of interest (e.g., for...). Figure 3D The variable is the name of the input terminal pin (or similar input terminal pin) of the frequency signal CP in the input.

[0128] In some embodiments, for a given standard library including a given flip-flop gate, a corresponding instance of the performance database 144 has a corresponding performance data quantity for the given flip-flop. This performance data quantity includes a first group of transmission delay quantities, a second group of timing arc quantities, a third group of power arc quantities, a fourth group of set time quantities, a fifth group of hold time quantities, a sixth group of recovery time quantities, a seventh group of removal time quantities, an eighth group of clear time quantities, and / or a ninth group of preset time quantities, wherein not all groups are grouped in the same way. In some embodiments, the corresponding performance data quantity for a given flip-flop includes a first group of transmission delay quantities, a second group of timing arc quantities, a third group of power arc quantities, a fourth group of set time quantities, a fifth group of hold time quantities, a sixth group of recovery time quantities, a seventh group of removal time quantities, an eighth group of clear time quantities, and / or a ninth group of preset time quantities, wherein each of the first to ninth groups is grouped in a different way.

[0129] Figure 6A This is a block diagram of standard cell 666A according to some embodiments.

[0130] exist Figure 6A In this context, it is assumed that the standard cell 666A is a multi-bit flip-flop, which includes two-unit flip-flop gates 668(1), one-unit flip-flop gate 668(2), three-unit flip-flop gates 668(3), and one-unit flip-flop gate 668(4). Relative to... Figure 6A In this context, the overall attribute of the gates on which the classification and matching of the various embodiments disclosed herein are based is the gate type, and more specifically, the gate type refers to the gate height. On the Y-axis, the height of gate 668(1) is 1 / 2H, where H is a unit of measurement corresponding to the semiconductor process technology node. The height of gate 668(2) is 2H. The height of gate 668(3) is H. The height of gate 668(4) is 1.5H. Other gate heights are expected. On the X-axis, each of gates 668(1) to 668(3) has the same width. In some embodiments, the standard cell 666A is a cell other than the multi-bit flip-flop cell, and gates 668(1) to 668(4) are gates other than the unit cell flip-flop gate.

[0131] Figure 6B This is a block diagram of the standard cell 666B according to some embodiments.

[0132] exist Figure 6B In this context, it is assumed that the standard cell 666B is a multi-bit flip-flop, which includes a 2-unit flip-flop gate 668(5), a 3-unit flip-flop gate 668(6), and a 2-unit flip-flop gate 668(7). Relative to... Figure 6BIn this context, the overall attribute of the gates on which the classification and matching of the various embodiments disclosed herein are based is the gate type, and more specifically, the gate type refers to the number of fins 670 in the corresponding gate. For example, gate 668(5) has 6 fins 670; gate 668(6) has 8 fins 670; and gate 668(7) has 4 fins 670. Instances of other numbers of fins 670 are expected. On the X-axis, each of gates 668(5) to 668(7) has the same width. On the Y-axis, each of gates 668(5) to 668(7) has the same height. In some embodiments, the standard cell 666B is a cell other than a multi-bit flip-flop cell, and gates 668(5) to 668(7) are gates other than a unit cell flip-flop gate.

[0133] Figure 6C This is a block diagram of the standard cell 666C according to some embodiments.

[0134] exist Figure 6C In this context, it is assumed that the standard cell 666C is a multi-bit flip-flop, which includes two unit flip-flop gates 668(8), one unit flip-flop gate 668(9), three unit flip-flop gates 668(10), and one unit flip-flop gate 668(11). Relative to... Figure 6C For the purposes of classification and matching of the various embodiments disclosed herein, the overall attribute of the gates on which the classification and matching are based is the gate type, and more specifically, the gate type refers to the width of the gate. On the X-axis, the width of gate 668(8) is RW, where W is a unit of measurement corresponding to a semiconductor process technology node, such as a contacted polypin (CPP). The width of gate 668(9) is 2W. The width of gate 668(10) is W. The width of gate 668(11) is 1.5W. Other gate widths are expected to exist. On the Y-axis, each of gates 668(8) to 668(11) has the same height. In some embodiments, the standard cell 666C is a cell other than a multi-bit flip-flop cell, and gates 668(8) to 668(11) are gates other than a unit cell flip-flop gate.

[0135] Figure 6D This is a block diagram of the standard cell 666D according to some embodiments.

[0136] exist Figure 6D In this context, it is assumed that the standard cell 666D is a multi-bit flip-flop, which includes a single-unit flip-flop gate 668 (12), a triple-unit flip-flop gate 668 (13), and a single-unit flip-flop gate 668 (14). Relative to... Figure 6DIn this context, the overall attribute of the gate on which the classification and matching of the various embodiments disclosed herein are based is the gate type, and more specifically, the gate type refers to the number of nanosheets 672 in each of the PMOS and NMOS active regions of the corresponding gate. For example, gate 668(12) has 2 nanosheets 672 in each of the PMOS and NMOS active regions; gate 668(13) has 6 nanosheets 672 in each of the PMOS and NMOS active regions; and gate 668(14) has 4 nanosheets 672 in each of the PMOS and NMOS active regions. Other instances of the number of nanosheets 672 are expected to exist in the PMOS and NMOS active regions. On the X-axis, each of gates 668(12) to 668(14) has the same width. On the Y-axis, each of gates 668(12) to 668(14) has the same height. In some embodiments, gates 668(12) to 668(14) are configured with nanowires or similar items instead of nanosheets. In some embodiments, the standard cell 666D is a cell other than the multi-bit flip-flop cell, and gates 668(12) to 668(14) are gates other than the unit cell flip-flop gate.

[0137] Figures 6E to 6F It is a circuit diagram of a corresponding unit cell flip-flop topology included in a standard cell according to some embodiments.

[0138] In some embodiments, gate type refers to the circuit topology of the gate, such as a transmission gate topology. Figure 6E ) for stacked gate topology ( Figure 6F ). Figure 6E This is a circuit diagram of a transmission gate topology that includes a transmission gate (TXG) coupled between the master latch and the slave latch. The TXG receives the clock_bar signal clkb and the clock_bar_bar signal clkbb. Figure 6F This is a circuit diagram of a stack-gate (SXG) topology, including the stack-gate circuit coupled between the master latch and the slave latch. The SXG circuit receives the clock_bar signal clkb and the clock_bar_bar signal clkbb.

[0139] Figures 6G to 6H It is a circuit diagram of a corresponding unit cell flip-flop topology included in a standard cell according to some embodiments.

[0140] In some embodiments, in instances of a transmission gate topology, the gate type refers to a Q-type coupler ( Figure 6G ) for RPQ type coupler ( Figure 6H The sub-circuit topology of ). Figure 6G This is a circuit diagram of a Q-coupler topology including a Q-type circuit located between the master latch and the transmission gate (TXG), whereby the TXG couples the Q-type circuit to the slave latch. Each of the master latch, the Q-type circuit, the TXG, and the slave latch receives a clock_bar signal clkb and a clock_bar_bar signal clkbb. The master latch also receives: a data signal D; a scan input signal SI; a scan enable signal SE; and a SE_bar signal seb. In some embodiments, Figure 6G The unit flip-flop shown is an example called a scan D flip-flop (SDFQ). Figure 6H This is a circuit diagram of an RPQ-type coupler topology including an RPQ-type circuit located between the master latch and the transmission gate (TXG), whereby the TXG couples the RPQ-type circuit to the slave latch. Each of the master latch, the RPQ-type circuit, the TXG, and the slave latch receives a clock_bar signal clkb and a clock_bar_bar signal clkbb. The master latch also receives: a data signal D; a scan input signal SI; a scan enable signal SE; and a SE_bar signal seb. In some embodiments, Figure 6H The example shown is called an SDFQ (Single Element Shifter).

[0141] Figure 7A This is a flowchart 700A of a method for manufacturing a semiconductor device according to some embodiments.

[0142] According to some embodiments, an EDA system 100A (discussed above) may be used, for example. Figure 1A ) and IC manufacturing system 800 (discussed below) Figure 8 The method of flowchart 700A is implemented accordingly. Examples of semiconductor devices that can be manufactured according to the method of flowchart 700A include layout-based semiconductor devices, wherein verification of the layout is performed at least in part based on a performance database (e.g., 144 or similar performance database) generated according to one or more methods disclosed herein.

[0143] exist Figure 7A In flowchart 700A, the method includes operations 702 to 704. At operation 702, a layout diagram is generated. According to some embodiments, an EDA system 100A (discussed above) may be used, for example. Figure 1A To implement operation 702, the process proceeds from operation 702 to operation 703.

[0144] At operation 703, the layout diagram is subjected to various verification processes, which are at least in part based on a performance database (e.g., performance database 144 or a similar performance database) generated according to one or more methods disclosed herein. According to some embodiments, an EDA system 100A (discussed above) may be used, for example. Figure 1A To perform operation 703, proceed from operation 703 to operation 704.

[0145] At operation 704, based on the layout, at least one of the following operations is performed: (A) performing one or more photolithographic exposures; (B) fabricating one or more semiconductor masks; or (C) fabricating one or more components in a layer of a semiconductor device. See below for further details. Figure 8 The discussion of IC manufacturing system 800.

[0146] Figure 7B This is a flowchart 700B of a method for generating a performance database according to some embodiments.

[0147] For example, it can be used Figure 1B The analysis tool 142 or a similar tool shown can be used to implement the method of flowchart 700B. In some embodiments, an EDA system 100A (discussed above) can be used. Figure 1A The analysis tool 142 is used to implement the analysis. Examples of performance databases generated according to the method of flowchart 700B include performance database 144 or similar performance databases.

[0148] The method in flowchart 700B includes operations 710 to 724. In operation 710, for each standard cell in the corresponding standard cell library, the gates in the standard cells are grouped. Operation 710 includes operations 712 to 714. Within operation 710, the process proceeds to operation 712.

[0149] At operation 712, a gate-to-gate matching search is performed on a gate-by-gate basis for a given standard cell. For gate-by-gate matching, the gate type is the overall attribute of the gates on which the classification and matching are based. In some embodiments, the gate type refers to the function performed by the gate ( Figure 2B Or a similar figure). In some embodiments, gate type refers to the current drive capability at the output terminal pin of the gate. In some embodiments, gate type refers to the threshold voltage of the transistor in the gate. In some embodiments, gate type refers to the power domain in which the gate operates. In some embodiments, gate type refers to the height of the gate on the Y-axis ( Figure 6A Or a similar diagram). In some embodiments, the gate type refers to the number of fins in the gate (or similar diagram). Figure 6B Or a similar diagram). In some embodiments, the gate type refers to the width of the gate on the X-axis (or similar diagram). Figure 6COr a similar figure). In some embodiments, the gate type refers to the number of nanosheets in each of the PMOS and NMOS active regions of the gate (or similar figures). Figure 6D Or a similar diagram). In some embodiments, gate type refers to the circuit topology of the gate, such as a transmission gate topology (or a similar diagram). Figure 6E Or a similar diagram) for stacked gate topology ( Figure 6F Or a similar diagram). In some embodiments, in the context of a transmission gate topology, the gate type refers to a Q-type coupler (or similar). Figure 6G (or a similar figure) for RPQ type couplers ( Figure 6H Or a sub-circuit topology similar to the diagram. The process proceeds from operation 712 to operation 714.

[0150] At operation 714, for a given standard cell, matched gates are grouped into corresponding multi-member groups. Unmatched gates within these groups are grouped into corresponding single-member groups. An example of a multi-member group is... Figure 2B Group 202B or similar multi-member groups. An example of a single-member group is... Figure 2B Group 204B or a similar single-member group. The process proceeds from operation 714 to operation 716.

[0151] At operation 716, performance data is generated for each gate in each standard cell. Operation 716 includes operations 718 to 722. Within operation 716, the process proceeds to operation 718.

[0152] At operation 718, the performance data volume is calculated individually for each target gate in the group. Examples of target gates include... Figure 3A Gate 306(1) in the middle Figure 3B Gate 306(2) in the middle Figure 3C Gate 306(M) in the middle, having in Figure 4A The data structure shown is 450. Figure 5A The data structure shown is 550A. Figure 5B The data structure shown is 550B. Figure 5C The data structure shown is 550C. Figure 5D The data structure shown is 550D. Figure 5E The data structure shown is 550E. Figure 5F The gate (not shown) for the output terminal pin ZA listed in the data structure 550F or a similar data structure. The process proceeds from operation 718 to operation 720.

[0153] At operation 720, the performance data volume is mapped to the target gate for each group. Examples of this mapping include: for multi-member groups. Figure 4A The data structure shown is 450. Figure 5A The data structure shown is 550A. Figure 5B The data structure shown is 550B. Figure 5C The data structure shown is 550C. Figure 5D The data structure shown is 550D. Figure 5E The data structure shown is 550E. Figure 5F The member statements in each of the data structures shown in Data Structure 550F or similar data structures (which identify the target gate among other members (i.e., non-target gates) in a multi-member group); and regarding single-member groups. Figure 4A The data structure shown is 450. Figure 5A The data structure shown is 550A. Figure 5B The data structure shown is 550B. Figure 5C The data structure shown is 550C. Figure 5D The data structure shown is 550D. Figure 5E The data structure shown is 550E. Figure 5F The member statements in each of the data structures shown, 550F or similar data structures (which identify the target gate, where the target gate is the only member of a single-member group); or similar items. The process proceeds from operation 720 to operation 722.

[0154] At operation 722, for each group that is a multi-member group, the performance data volume is also mapped to the non-target gates in the multi-member group. This mapping is an example of utilizing redundancy in performance data. The performance data of the non-target gates in the group is redundant with respect to the performance data of the main group. Therefore, this mapping avoids individual calculations of performance data that is otherwise redundant and thus utilizes the redundancy in the performance data of the non-main group. Examples of this mapping include... Figure 4A The data structure shown is 450. Figure 5A The data structure shown is 550A. Figure 5B The data structure shown is 550B. Figure 5C The data structure shown is 550C. Figure 5D The data structure shown is 550D. Figure 5E The data structure shown is 550E. Figure 5F The member statements of the multi-member group in each of the data structures shown in data structure 550F or similar data structures (which identify the non-target gate of the multi-member group as the target gate of the multi-member group) or similar items. The process proceeds from operation 722 to operation 716 to operation 724.

[0155] At operation 724, performance data is collected to form a performance database. Similarly, an example of a performance database is... Figure 1B The performance database shown is 144 or a similar performance database. In some embodiments, the first performance database is at least partially based on performance energy.

[0156] In some embodiments, operation 730 further includes setting the state of each gate to unclassified (unclassified state) before searching for matching gates (matching gates) among the gates. In this embodiment, searching for matching gates (matching gates) among the gates includes: comparing the description of a target gate (target gate) with the description of a corresponding non-target gate among the gates to identify which non-target gate or which non-target gates (identified gates) among the non-target gates match the target gate, wherein the other gates among the gates are non-target gates relative to the target gate; treating the target gate and the identified gates as matching gates; and setting the state of the target gate and the state of the identified gates to be classified. In this embodiment, for the remaining gates with unclassified states, the search for matching gates (matching gates) among the gates is performed iteratively until no unmatching gates remain.

[0157] Figure 7C This is a flowchart 700C of a method for generating a performance database according to some embodiments.

[0158] For example, it can be used Figure 1B The analysis tool 142 or a similar tool shown can be used to implement the method of flowchart 700C. In some embodiments, an EDA system 100A (discussed above) can be used. Figure 1A The analysis tool 142 is used to implement the analysis. Examples of performance databases generated according to the method of flowchart 700C include performance database 144 or similar performance databases.

[0159] The method in flowchart 700C includes operations 730 to 744. In operation 730, for each standard cell in the corresponding standard cell library, the gates in the standard cells are grouped. Operation 730 includes operations 732 to 734. Within operation 730, the process proceeds to operation 732.

[0160] At operation 732, a matching gate is searched for in the gates on a feature-by-feature basis for a given standard cell. For feature-by-feature matching, the attributes on which classification and matching are based are the features of the gate. In some embodiments, the features of the gate are individual input terminal pins (i.e., each input terminal pin represents a feature of a given gate). Figure 2C , Figure 3D (or a similar diagram). The process proceeds from operation 732 to operation 734.

[0161] At operation 734, for a given standard cell, matching features are grouped into corresponding multi-feature groups. Non-matching features are grouped into corresponding single-feature groups. Examples of multi-member groups include... Figure 2C Groups 202C(1) to 202C(3) or similar multi-member groups. Examples of single-member groups are provided by [examples of single-member groups]. Figure 4DData structure 458 or a similar data structure is identified as I2. The process proceeds from operation 734 to operation 730 and then to operation 736.

[0162] At operation 736, performance data is generated for each gate in each standard cell. Operation 736 includes operations 738 to 742. Within operation 736, the process proceeds to operation 738.

[0163] At operation 738, the performance data volume is calculated individually for each target gate in the group. Examples of target gates include... Figure 3D Gate 307(1) in the middle has such Figure 4D The data structure shown is 458. Figure 5G The data structure shown is 558G. Figure 5H The data structure shown is 558H. Figure 5I The data structure shown is 558I. Figure 5J The data structure shown is 558J. Figure 5K The data structure shown is 558K. Figure 5L The data structure shown is 558L. Figure 5M The data structure shown is 558M. Figure 5N The gate (not shown) for input terminal pin A1 listed in the data structure 558N or a similar data structure. The process proceeds from operation 738 to operation 740.

[0164] At operation 740, the performance data volume is mapped to the target gate for each group. Examples of this mapping include: for multi-member groups. Figure 4D The data structure shown is 458. Figure 5G The data structure shown is 558G. Figure 5H The data structure shown is 558H. Figure 5I The data structure shown is 558I. Figure 5J The data structure shown is 558J. Figure 5K The data structure shown is 558K. Figure 5L The data structure shown is 558L. Figure 5M The data structure shown is 558M. Figure 5N The member statements in each of the data structures shown in the 558N or similar data structures (which identify the target gate among other members (i.e., non-target gates) in a multi-member group); and regarding single-member groups. Figure 4D The data structure shown is 458. Figure 5G The data structure shown is 558G. Figure 5H The data structure shown is 558H. Figure 5I The data structure shown is 558I. Figure 5J The data structure shown is 558J. Figure 5K The data structure shown is 558K. Figure 5LThe data structure shown is 558L. Figure 5M The data structure shown is 558M. Figure 5N The member statement in each of the data structures shown, 558N or similar data structures (which identifies the target gate, where the target gate is the only member of a single-member group); or similar items. The process proceeds from operation 740 to operation 742.

[0165] At operation 742, for each group that is a multi-member group, the performance data volume is also mapped to the non-target gates in the multi-member group. This mapping is an example of utilizing redundancy in the performance data. The performance data of the non-target gates in the group is redundant with respect to the performance data of the main group. Therefore, this mapping avoids discrete computation on performance data that is otherwise redundant and thus utilizes the redundancy in the performance data of the non-main group. Examples of this mapping include... Figure 4D The data structure shown is 458. Figure 5G The data structure shown is 558G. Figure 5H The data structure shown is 558H. Figure 5I The data structure shown is 558I. Figure 5J The data structure shown is 558J. Figure 5K The data structure shown is 558K. Figure 5L The data structure shown is 558L. Figure 5M The data structure shown is 558M. Figure 5N Member statements of multi-member groups in each of the data structures shown, such as 558N or similar data structures (which identify the non-target gate of the multi-member group as the target gate of the multi-member group), or similar items. The process proceeds from operation 742 to operation 736 and then to operation 744.

[0166] At operation 744, performance data is collected to form a performance database. Similarly, an example of a performance database is... Figure 1B The performance database shown is 144 or a similar performance database. In some embodiments, the first performance database is at least partially based on the amount of performance data.

[0167] Figure 8 This is a block diagram of an integrated circuit (IC) manufacturing system 800 and an IC manufacturing process associated with the integrated circuit (IC) manufacturing system 800, according to some embodiments.

[0168] exist Figure 7A Following operation 703, at least one of the following is fabricated using IC manufacturing system 800 based on the layout: (A) one or more semiconductor masks or (B) at least one component in a layer of an early semiconductor integrated circuit.

[0169] exist Figure 8In this IC manufacturing system 800, entities such as design division 820, fab division 830, and IC manufacturer / fab (“IC foundry (fab)”) 850 collaborate with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 860. The entities in the IC manufacturing system 800 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and supplies services to and / or receives services from one or more other entities. In some embodiments, a single, larger company owns two or more of the design division 820, fab division 830, and IC foundry 850. In some embodiments, two or more of the design division 820, fab division 830, and IC foundry 850 coexist in a common facility and use common resources.

[0170] Design division 820 generates IC design layout 822. IC design layout 822 includes various geometric patterns designed for IC device 860. The geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers constituting various components of the IC device 860 to be manufactured. Various layers are combined to form various IC features. For example, a portion of IC design layout 822 includes various IC features (e.g., active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads) to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design division 820 performs appropriate design procedures to form IC design layout 822. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 822 is presented in the form of one or more data files containing information of geometric patterns. For example, IC design layout 822 is expressed in GDSII file format or DFII file format.

[0171] Masking division 830 includes mask data preparation 832 and mask fabrication 834. Masking division 830 uses IC design layout 822 to fabricate one or more masks for various layers of IC device 860. Masking division 830 performs mask data preparation 832, translating IC design layout 822 into a representative data file (RDF). Mask data preparation 832 supplies the RDF to mask fabrication 834. Mask fabrication 834 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a reticle or semiconductor wafer). Mask data preparation 832 manipulates the design layout to conform to the specific characteristics of the mask writer and / or the requirements of IC foundry 850. Figure 8 In this diagram, the mask data preparation 832, the mask production 834, and the mask 835 are shown as separate components. In some embodiments, the mask data preparation 832 and the mask production 834 may be collectively referred to as mask data preparation.

[0172] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors (e.g., image errors that may be caused by diffraction, interference, other process effects, and similar reasons). OPC adjusts the IC design layout 822. In some embodiments, mask data preparation 832 also includes resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution auxiliary features, phase-shift masking, other suitable techniques and similar techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is further used, which treats OPC as an inverse imaging problem.

[0173] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks the IC design layout, which has already undergone the process in the OPC, using a set of mask creation rules containing certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes and similar factors. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 834, which may cancel out part of the modifications implemented by the OPC to meet the mask creation rules.

[0174] In some embodiments, mask data preparation 832 includes lithography process checking (LPC), which simulates the processes to be performed by IC foundry 850 to fabricate IC device 860. LPC models this process based on IC design layout 822 to create a simulated fabricated device, such as IC device 860. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors and similar factors, or combinations thereof. In some embodiments, after a simulated fabricated device has been created using LPC, if the shape similarity of the simulated device is insufficient to meet design rules, OPC and / or MRC are repeated to further improve IC design layout 822.

[0175] The above description of mask data preparation 832 has been simplified for clarity. In some embodiments, mask data preparation 832 includes additional features, such as modifying the logic operation (LOP) of the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 822 during mask data preparation 832 can be performed in various different sequences.

[0176] After mask data preparation 832 and during mask fabrication 834, mask 835 or a group of masks is fabricated based on the modified IC design layout 822. In some embodiments, an electron beam (e-beam) or a mechanism consisting of multiple electron beams is used to form a pattern on the mask (photomask or stencil) based on the modified IC design layout. Masks are formed using various techniques. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the mask. In another example, a phase-shifting technique is used to form the mask. In a phase shift mask (PSM), various features in a pattern formed on the mask are configured to have an appropriate phase difference to enhance resolution and image quality. In various examples, the phase shift mask is an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 834 is used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0177] IC foundry 850 is an IC manufacturing company that includes one or more manufacturing facilities for producing various IC products. In some embodiments, IC foundry 850 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end fabrication (front-end-of-line (FEOL) fabrication) of multiple IC products, a second manufacturing facility for back-end fabrication (back-end-of-line (BEOL) fabrication) of interconnects and packaging of IC products, and a third manufacturing facility for providing other services to the foundry.

[0178] IC foundry 850 uses a mask (or multiple masks) fabricated by mask division 830 to fabricate IC device 860 using fabrication tooling 852. Therefore, IC foundry 850 at least indirectly uses IC design layout 822 to fabricate IC device 860. In some embodiments, IC foundry 850 uses a mask (or multiple masks) to fabricate semiconductor wafer 853 to form IC device 860. Semiconductor wafer 853 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer also includes one or more of various doped regions, dielectric features, multilevel interconnects, and similar features (formed at subsequent manufacturing steps).

[0179] In some embodiments, a method (a method of manufacturing a semiconductor device, wherein a corresponding layout for the semiconductor device includes instantiated cells, each instantiated cell being an instance of a corresponding standard cell selected from a standard cell library composed of standard cells, the layout, the standard cell library, and a first performance database being stored on a non-transitory computer-readable storage medium) includes generating the first performance database, the generation of the first performance database including: classifying the plurality of gates into groups for each standard cell comprising a plurality of gates, including: searching for matching gates among the plurality of gates; grouping corresponding matching gates into corresponding first groups, each first group having a plurality of member gates; and grouping non-matching gates among the plurality of gates into corresponding second groups, each second group having a corresponding single member gate; generating a corresponding first performance database for each standard cell. The performance data volume, wherein the attributes of the standard cells are based on the first performance data volume, and generating the corresponding first performance data volume includes: performing the following operations for each first group of each standard cell: individually calculating the first performance data volume for a first target gate among the member gates in the first group; mapping the first performance data volume to the first target gate; and mapping the first performance data volume to non-target gates in the first group; performing the following operations for each second group of each standard cell: determining the first performance data volume for a second target gate among the member gates in the second group; and mapping the first performance data volume to the second target gate; and making the first performance database at least partially based on the first performance data volume, wherein the attributes of the standard cells in the standard cell library are based on the first performance database.

[0180] In some embodiments, classifying the plurality of gates into groups further includes: setting the state of each gate to an unclassified state before searching for a matching gate among the plurality of gates; the search for a matching gate among the plurality of gates includes: comparing the description of a target gate with the description of a corresponding non-target gate for a target gate among the plurality of gates to identify a identified gate that matches the target gate among the non-target gates; treating the target gate and the identified gate as matching gates; setting the state of the target gate and the state of the identified gate to be classified; and iteratively performing the search for a matching gate among the plurality of gates for the remaining gates having the unclassified state.

[0181] In some embodiments, each description includes the logical function of the corresponding gate.

[0182] In some embodiments, each description includes a count of the input terminal pins of the corresponding gate.

[0183] In some embodiments, each description includes a logical description of each input terminal pin of the corresponding gate among the plurality of gates.

[0184] In some embodiments, each of the plurality of gates has N inputs, where N is a positive integer and N is equal to or greater than 2; generating the corresponding first performance data volume further includes performing the following operations for each first target gate of each first group and each second target gate of each second group: determining the corresponding 2^N performance data pages for each of the 2^N value combinations of the N inputs based on: the corresponding Nth value combination of the N inputs of the first target gate or the second target gate; and the predefined value combination of the N inputs of each of the non-target gates; each first performance data volume is a set including the corresponding 2^N performance data pages.

[0185] In some embodiments, the performance data is a timing arc, which represents the elapsed time for the first target gate and the second target gate to generate corresponding stable output values.

[0186] In some embodiments, where the first target gate and the second target gate are flip-flops, the elapsed time, represented by the timing arc, is from the effective edge of the frequency signal until the first target gate and the second target gate produce the corresponding stable output value.

[0187] In some embodiments, the performance data is a power arc, which represents the amount of power consumed when the first target gate and the second target gate produce corresponding stable output values.

[0188] In some embodiments, the performance data is a set time arc, which represents the minimum elapsed time before the output data must be kept stable by the first target gate and the second target gate before the next effective frequency edge.

[0189] In some embodiments, the performance data is a hold-time arc, which represents the minimum elapsed time after the effective frequency edge during which the inputs of the first target gate and the second target gate must remain stable.

[0190] In some embodiments, the first target gate and the second target gate are flip-flops, and the performance data is a recovery time arc, which represents the minimum permissible elapsed time from the de-setting of the reset signal to the next effective frequency edge required for the first target gate and the second target gate.

[0191] In some embodiments, the first target gate and the second target gate are flip-flops, and the performance data is a removal time arc, which represents the minimum allowable elapsed time after the next effective frequency edge. Before the minimum allowable elapsed time, the first target gate and the second target gate will de-set the reset signal.

[0192] In some embodiments, the first target gate and the second target gate are flip-flops, and the performance data is a clear time arc, which represents the minimum elapsed time after the clear pin is enabled for the first target gate and the second target gate to produce a stable logic low output value.

[0193] In some embodiments, the first target gate and the second target gate are flip-flops, and the performance data is a default time arc, which represents the minimum elapsed time after the default pins of the first target gate and the second target gate are enabled to generate a stable logic high output value.

[0194] In some embodiments, determining the first performance data volume includes: calculating the first performance data volume individually.

[0195] In some embodiments, the method further includes: generating the layout diagram; and performing at least one of the following operations based on the layout diagram: (A) performing one or more photolithographic exposures; (B) fabricating one or more semiconductor devices; and (C) fabricating at least one component in a layer of a semiconductor integrated circuit.

[0196] In some embodiments, a system for manufacturing a semiconductor device includes: at least one processor; at least one non-transitory computer-readable storage medium storing computer-executable code; a corresponding layout diagram including instantiated cells, each instantiated cell being an instance of a corresponding standard cell selected from a standard cell library composed of standard cells, the layout diagram, the standard cell library, and a first performance database being stored on the non-transitory computer-readable storage medium, the non-transitory computer-readable storage medium, the computer program executable code, and the at least one processor being configured to cause the system to generate the first performance database, the generation of the first performance database including: classifying features of the gates into groups for each standard cell including a plurality of gates, including: searching for matching features among the features of the plurality of gates; grouping corresponding matching features into corresponding first groups, each first group having a plurality of member features; and grouping non-matching features into corresponding second groups for non-matching features among the features. In each group, each second group has a corresponding single member feature; a corresponding first performance data quantity is generated for each standard cell, the attributes of the standard cell being based on the first performance data quantity, the generation of the corresponding first performance data quantity includes: for each first group of each standard cell, performing the following operations: individually calculating the first performance data quantity for a first target feature among the member features in the first group; mapping the first performance data quantity to the first target feature; and mapping the first performance data quantity to a non-target feature among the member features in the first group; for each second group of each standard cell, performing the following operations: determining the first performance data quantity for a second target feature among the member features in the second group; and mapping the first performance data quantity to the second target feature; and making the first performance database at least partially based on the first performance data quantity, the attributes of the standard cells in the standard cell library being based on the first performance database.

[0197] In some embodiments, the system further includes at least one of the following: a masking facility configured to fabricate one or more semiconductor masks based on the layout; and a fabrication facility configured to fabricate at least one component in a layer of a semiconductor integrated circuit based on the layout.

[0198] In some embodiments, a non-transitory computer-readable storage medium stores computer-executable instructions representing a method (a method for generating a first performance database, including a standard cell library whose attributes are based on the first performance database, the standard cell library and the first performance database being stored on the non-transitory computer-readable storage medium), the computer-executable instructions being executable by at least one processor to perform the method, the method comprising: classifying the plurality of gates into groups for each standard cell comprising a plurality of gates, each gate having N inputs, where N is a positive integer and N is equal to or greater than 2, the classification of the plurality of gates into groups comprising: searching for matching gates among the plurality of gates; grouping the corresponding matching gates into corresponding first groups, each first group having a plurality of member gates; and grouping the non-matching gates among the plurality of gates into corresponding second groups, each second group having a corresponding single member gate; generating a corresponding first performance data amount for each standard cell, the attributes of the standard cell being based on the first performance data amount, the generation of the corresponding first performance data amount comprising: pinning... For each first group of each standard cell, the following operations are performed: calculating the first performance data quantity individually for a first target gate among the member gates in the first group; mapping the first performance data quantity to the first target gate; and mapping the first performance data quantity to non-target gates in the first group; for each second group of each standard cell, the following operations are performed: determining the first performance data quantity for a second target gate among the member gates in the second group; and mapping the first performance data quantity to the second target gate; and making the first performance database at least partially based on the first performance data quantity; the generation of the corresponding first performance data quantity further includes: for each target gate in each first group and for each target gate in each second group, determining the corresponding 2^N performance data pages for each of the 2^N value combinations of the N inputs based on: the corresponding Nth value combination of the N inputs of the first target gate or the second target gate; and the predefined value combination of the N inputs of each of the non-target gates; and each first performance data quantity is a set including the corresponding 2^N performance data pages.

[0199] In some embodiments, determining the first performance data volume includes calculating the first performance data volume individually.

[0200] It will be apparent to those skilled in the art that one or more of the disclosed embodiments achieve one or more of the aforementioned advantages. After reading the foregoing specification, those skilled in the art will be able to derive various modifications and substitutions of equivalent forms and various other embodiments as broadly disclosed herein. Therefore, this disclosure is intended to limit the protection granted herein only to the definitions contained in the appended claims and their equivalents.

Claims

1. A method of manufacturing a semiconductor device, wherein a corresponding layout for the semiconductor device includes instantiated cells, each instantiated cell being an instance of a corresponding standard cell selected from a standard cell library composed of standard cells, the layout, the standard cell library, and a first performance database are stored on a non-transitory computer-readable storage medium, the method comprising generating the first performance database, the generation of the first performance database comprising: For each standard cell that includes multiple gates, the multiple gates are classified into groups, including: Search for a matching gate among the plurality of gates; The corresponding matching gates in the matching gates are grouped into corresponding first groups, and each first group has multiple member gates; and For mismatched gates among the plurality of gates, the mismatched gates are grouped into corresponding second groups, and each second group has a corresponding single member gate; For each standard cell in the standard cell, a corresponding first performance data quantity is generated. The attributes of the standard cell are based on the first performance data quantity. Generating the corresponding first performance data quantity includes: For each of the first groups in the first group of each standard cell, the following operations are performed: The first performance data volume is calculated individually for the first target gate among the member gates in the first group; Map the first performance data volume to the first target gate; and Map the first performance data volume to the non-target gate in the member gate of the first group; For each of the second groups in the second group of each standard cell, the following operation is performed: Determine the first performance data volume for the second target gate in the member gate of the second group; and Map the first performance data volume to the second target gate; and The first performance database is at least partially based on the first performance data volume, and the attributes of the standard cells in the standard cell library are correspondingly based on the first performance database.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Grouping the multiple gates also includes: Before searching for the matching gate among the plurality of gates, the state of each of the plurality of gates is set to an unclassified state; Searching for the matching gate among the plurality of gates includes: For a target gate among the plurality of gates, the description of the target gate is compared with the description of the corresponding non-target gate to identify the identified gate that matches the target gate among the non-target gates; The target gate and the identified gate are considered as a matched gate; and Set the state of the target gate and the state of the identified gate to be classified; and For the remaining gates that have the unclassified state, the matching gate among the plurality of gates is searched iteratively.

3. The method of manufacturing a semiconductor device according to claim 2, wherein each description includes: The logical functions of corresponding gates among the multiple gates.

4. The method of manufacturing a semiconductor device according to claim 3, wherein each description includes: The count of the input terminal pins of the corresponding gate.

5. The method of manufacturing a semiconductor device according to claim 2, wherein each description includes: Logical description of each input terminal pin of the corresponding gate among the plurality of gates.

6. The method of manufacturing a semiconductor device according to claim 1, wherein: Each of the plurality of gates has N inputs, where N is a positive integer and N is equal to or greater than 2; The generation of the corresponding first performance data volume also includes: For each first target gate in each first group and for each second target gate in each second group, the following operations are performed: For each of the 2^N combinations of values ​​from the N inputs, the corresponding 2^N performance data pages are determined based on the following: The Nth value combination corresponding to the 2^N value combinations of the N inputs of the first target gate or the second target gate; and The predefined combination of the N inputs for each of the non-target gates; Each of the first performance data volumes is a set comprising the corresponding 2^N performance data pages.

7. The method of manufacturing a semiconductor device according to claim 1, wherein: The performance data is a timing arc, which represents the elapsed time for the first target gate and the second target gate to generate corresponding stable output values.

8. The method of manufacturing a semiconductor device according to claim 7, wherein: The first target gate and the second target gate are flip-flops, and the elapsed time, represented by the timing arc, is from the effective edge of the frequency signal until the first target gate and the second target gate produce the corresponding stable output value.

9. The method of manufacturing a semiconductor device according to claim 1, wherein: The performance data is a power arc, which represents the amount of power consumed when the first target gate and the second target gate produce corresponding stable output values.

10. The method of manufacturing a semiconductor device according to claim 1, wherein: The performance data is a set time arc, which represents the minimum elapsed time before the output data must be kept stable by the first target gate and the second target gate before the next effective frequency edge.

11. The method of manufacturing a semiconductor device according to claim 1, wherein: The performance data is a hold-time arc, which represents the minimum elapsed time after the effective frequency edge when the inputs of the first target gate and the second target gate must remain stable.

12. The method of manufacturing a semiconductor device according to claim 1, wherein: The first target gate and the second target gate are flip-flops, and the performance data is a recovery time arc, which represents the minimum allowable elapsed time from the release of the reset signal to the next effective frequency edge required for the first target gate and the second target gate.

13. The method of manufacturing a semiconductor device according to claim 1, wherein: The first target gate and the second target gate are flip-flops, and the performance data is a removal time arc, which represents the minimum allowable elapsed time after the next effective frequency edge. Before the minimum allowable elapsed time, the first target gate and the second target gate will de-set the reset signal.

14. The method of manufacturing a semiconductor device according to claim 1, wherein: The first target gate and the second target gate are flip-flops, and the performance data is a clear time arc, which represents the minimum elapsed time after the clear pin is enabled for the first target gate and the second target gate to generate a stable logic low output value.

15. The method of manufacturing a semiconductor device according to claim 1, wherein: The first target gate and the second target gate are flip-flops, and the performance data is a default time arc, which represents the minimum elapsed time after the default pins of the first target gate and the second target gate are enabled to generate a stable logic high output value.

16. The method of manufacturing a semiconductor device according to claim 1, further comprising: Generate the layout diagram; and perform at least one of the following operations based on the layout diagram: Perform one or more photolithography exposures; Fabrication of one or more semiconductor devices; and At least one component is fabricated in the layers of a semiconductor integrated circuit.

17. A system for manufacturing a semiconductor device, comprising: At least one processor; At least one non-transitory computer-readable storage medium stores computer-executable code; The corresponding layout diagram includes instantiated cells, each of which is an instance of a corresponding standard cell selected from a standard cell library composed of standard cells. The layout diagram, the standard cell library, and the first performance database are stored on the at least one non-transitory computer-readable storage medium. The at least one non-transitory computer-readable storage medium, the computer-executable code, and the at least one processor are configured to cause the system to generate the first performance database, the generation of the first performance database comprising: For each standard cell containing multiple gates, the features of the multiple gates are classified into groups, including: Search for matching features among the features of the plurality of gates; The corresponding matching features in the matching features are grouped into corresponding first groups, and each first group has multiple member features; and For the mismatched features in the features, the mismatched features are grouped into corresponding second groups, and each second group has a corresponding single member feature; For each standard cell in the standard cell, a corresponding first performance data quantity is generated. The attributes of the standard cell are based on the first performance data quantity. Generating the corresponding first performance data quantity includes: For each of the first groups in the first group of each standard cell, the following operations are performed: The first performance data volume is calculated individually for the first target feature among the member features in the first group; Mapping the first performance data volume to the first target feature; and Map the first performance data volume to the non-target features in the member features of the first group; For each of the second groups in the second group of each standard cell, the following operation is performed: The first performance data volume is determined based on the second target feature among the member characteristics in the second group; and Map the first performance data volume to the second target feature; and The first performance database is at least partially based on the first performance data volume, and the attributes of the standard cells in the standard cell library are based on the first performance database.

18. The system for manufacturing a semiconductor device according to claim 17, further comprising at least one of the following: The dome structure is configured to fabricate one or more semiconductor domes based on the layout diagram; and The fabrication facility is configured to fabricate at least one component in a layer of a semiconductor integrated circuit based on the layout diagram.

19. A non-transitory computer-readable storage medium storing computer-executable instructions representing a method for generating a first performance database, including standard cells of a standard cell library whose attributes are based on the first performance database, the standard cell library and the first performance database being stored on the non-transitory computer-readable storage medium, the computer-executable instructions being executable by at least one processor to perform the method, the method comprising: For each standard cell containing multiple gates, the multiple gates are classified into groups. Each of the multiple gates has N inputs, where N is a positive integer and N is equal to or greater than 2. Classifying the multiple gates into groups includes: Search for a matching gate among the plurality of gates; The corresponding matching gates in the matching gates are grouped into corresponding first groups, and each first group has multiple member gates; and For mismatched gates among the plurality of gates, the mismatched gates are grouped into corresponding second groups, and each second group has a corresponding single member gate; For each standard cell in the standard cell, a corresponding first performance data quantity is generated. The attributes of the standard cell are based on the first performance data quantity. Generating the corresponding first performance data quantity includes: For each of the first groups in the first group of each standard cell, the following operations are performed: The first performance data volume is calculated individually for the first target gate among the member gates in the first group; Map the first performance data volume to the first target gate; and Map the first performance data volume to the non-target gate in the first group; For each of the second groups in the second group of each standard cell, the following operation is performed: Determine the first performance data volume for the second target gate in the member gate of the second group; and Map the first performance data volume to the second target gate; and The first performance database is at least partially based on the first performance data volume; The generation of the corresponding first performance data volume also includes: For each first target gate in each first group of the first group and each second target gate in each second group of the second group, the following operations are performed: For each of the 2^N combinations of values ​​from the N inputs, the corresponding 2^N performance data pages are determined based on the following: The Nth value combination corresponding to the 2^N value combinations of the N inputs of the first target gate or the second target gate; and The predefined combination of the N inputs for each of the non-target gates; Each of the first performance data volumes is a set comprising the corresponding 2^N performance data pages.

20. The non-transitory computer-readable storage medium of claim 19, wherein determining the first performance data amount includes: The first performance data volume is calculated individually.

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