A data filling method and device, computer equipment and storage medium

Abstract

The application relates to a data filling method and device, computer equipment and a storage medium, comprising: obtaining a message filling instruction; in response to the message filling instruction, storing target data into a message register according to a sequence, and determining the highest bit of the message register; based on the highest bit of the message register and a specific bit of a data length register, determining the filling length corresponding to the last group of message words in the target data; and controlling the left shift of the last group of message words in the message register by using the filling length, so as to complete the filling of the last group of message words. The application saves CPU resources, improves system operation efficiency, and meets the practical needs of low power consumption, high throughput and high data security. Compared with the prior art, the calculation method has low operation power consumption and small logic circuit area, and can effectively improve the operation speed of the chip and reduce the cost of the chip.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a data filling method, apparatus, computer device, and storage medium. Background Technology

[0002] Existing hash algorithm implementations can generally be divided into two categories: software implementations and hardware implementations. Software implementations mainly rely on the central processing unit (CPU), which not only consumes a large amount of CPU resources and reduces system efficiency, but also makes it difficult to meet performance requirements such as low power consumption, high throughput, and high data security. Hardware implementations of hash algorithms have an urgent practical application need.

[0003] Existing hardware implementations of message stuffing involve complex computational logic and long processing times, thus increasing the power consumption and circuit area required for algorithm execution. Furthermore, increased chip power consumption and area lead to a significant reduction in chip performance and an increase in chip cost. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a data filling method, apparatus, computer device, and storage medium to solve the problems that the hardware implementation method of message filling has complex computational logic, long processing time, and ultimately reduces chip performance and increases chip cost.

[0005] In a first aspect, embodiments of the present invention provide a data filling method, the method comprising:

[0006] Obtain a message filling instruction, wherein the message filling instruction carries the target data to be written;

[0007] In response to the message filling instruction, the target data is stored into the message register in chronological order, and the highest bit of the message register is determined.

[0008] Based on the highest bit of the message register and a specific bit of the data length register, determine the padding length corresponding to the last group of message words in the target data;

[0009] The padding length is used to control the left shift of the last group of message words in the message register to complete the padding of the last group of message words.

[0010] In one embodiment of the present invention, determining the padding length corresponding to the last group of message words in the target data based on the most significant bit of the message register and a specific bit of the data length register includes:

[0011] Calculate the difference between the most significant bit of the message register and a specific bit of the data length register;

[0012] The difference is determined as the padding length corresponding to the last group of message words in the target data.

[0013] In one embodiment of the present invention, after determining the difference as the padding length corresponding to the last group of message words in the target data, the method further includes:

[0014] The fill length is stored in a shift register, wherein the storage length of the shift register is the same as the fill length.

[0015] In one embodiment of the present invention, controlling the left shift of the last group of message words in the message register using the padding length includes:

[0016] Detect whether the currently written message word is the last group of message words in the target data;

[0017] If it is confirmed that the currently written message word is the last group of message words of the target data, then fill the end of the last group of message words with a first preset value of 1 bit.

[0018] The shift counter is controlled to read the parameter values ​​of each bit in the shift register in sequence, and the parameter values ​​of each bit in the shift register are used to control the left shift of the last group of message words.

[0019] In one embodiment of the present invention, the control shift counter sequentially reads the parameter values ​​of each bit in the shift register, and uses the parameter values ​​of each bit in the shift register to control the left shift of the last group of message words, including:

[0020] The shift counter is reset, the first parameter value corresponding to the first bit in the shift register is read, and the first left shift number corresponding to the first parameter value is determined.

[0021] The message register is filled with a second preset value according to the first left shift number, and the value recorded by the shift counter is updated to the first value;

[0022] Read the second parameter value corresponding to the second bit, and determine the second left shift number corresponding to the second parameter value, wherein the second bit is the next bit after the first bit;

[0023] The message register is filled with a second preset value according to the second left shift number, and the value recorded by the shift counter is updated to the second value, wherein the second value is greater than the first value;

[0024] Read the third parameter value corresponding to the third bit, and determine the third left shift number corresponding to the third parameter value, wherein the third bit is the bit following the second bit;

[0025] The message register is filled with a second preset value according to the third left shift number, and the value recorded by the shift counter is updated to a third value, wherein the third value is greater than the first value;

[0026] Detect whether the third bit is the last bit in the message register;

[0027] When the third bit is the last bit in the message register, padding data is constructed based on a first preset value of 1 bit, a second preset value of the total padding bits, and other message words, wherein the total padding bits are the sum of the left shift bits corresponding to each bit.

[0028] In one embodiment of the present invention, the method further includes:

[0029] If it is confirmed that the currently written message word is not the last group of message words of the target data, a hash operation is performed based on the currently written message word.

[0030] In one embodiment of the present invention, after constructing padding data based on a first preset value of 1 bit, a second preset value of the total padding bit length, and other message words, the method further includes:

[0031] The parameter values ​​of the set bits in the filling data are replaced with the parameter values ​​of the set bits in the data length register to obtain the replaced filling data;

[0032] Hash calculation is performed based on the replaced padding data.

[0033] Secondly, embodiments of the present invention provide a data filling device, the device comprising:

[0034] The acquisition module is used to acquire a message filling instruction, wherein the message filling instruction carries the target data to be written;

[0035] The response module is used to respond to the message filling instruction, store the target data into the message register in sequence, and determine the most significant bit of the message register;

[0036] The determination module is used to determine the padding length corresponding to the last group of message words in the target data based on the highest bit of the message register and a specific bit of the data length register.

[0037] The control module is used to control the left shift of the last group of message words in the message register using the padding length, so as to complete the padding of the last group of message words.

[0038] Thirdly, embodiments of the present invention provide a computer device, including: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the method described in the first aspect or any corresponding embodiment thereof.

[0039] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer instructions that cause a computer to perform the method described in the first aspect or any of its corresponding embodiments.

[0040] This application calculates the padding length of the last group of message words and then shifts the last group of message words to the left based on the padding length, thus saving CPU resources, improving system operating efficiency, and meeting the practical requirements of low power consumption, high throughput, and high data security. Compared with existing solutions, the calculation method of this application has low power consumption and small logic circuit area, which can effectively improve the chip's operating speed and reduce chip cost. Attached Figure Description

[0041] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0042] Figure 1 This is a flowchart illustrating a data filling method according to some embodiments of the present invention;

[0043] Figure 2 This is a flowchart illustrating a data filling method according to some embodiments of the present invention;

[0044] Figure 3 This is a flowchart illustrating a data filling method according to some embodiments of the present invention;

[0045] Figure 4 This is a structural block diagram of a data filling device according to an embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] According to embodiments of the present invention, a data filling method, apparatus, computer device, and storage medium are provided. It should be noted that the steps shown in the flowcharts in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0049] This embodiment provides a data filling method. Figure 1 This is a flowchart of a data filling method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0050] Step S11: Obtain message filling instruction, wherein the message filling instruction carries the target data to be written.

[0051] In this embodiment, the process first checks whether the hash algorithm has started. For example, at the start of the hash algorithm, a specific status flag is checked to indicate that the algorithm has started. Alternatively, the state machine of the algorithm is examined to determine whether the hash algorithm has started, for example, if the state changes from "not started" to "running". Secondly, if the hash algorithm is determined to be started, a message filling instruction is generated. The message filling instruction carries the target data to be written to the message register, which can be 32 bits.

[0052] Step S12: Respond to the message filling instruction, store the target data into the message register in the order of the data, and determine the highest bit of the message register.

[0053] In this embodiment, in response to a message padding instruction, the target data can be divided into multiple groups of message words, each group being 512 bits. After each group of message words is stored in the message register [511:0], the highest bit in the message register, i.e., bit 511, is determined. Determining the highest bit of the message register facilitates the subsequent determination of the padding length for the last group of message words. Message padding is a data padding technique in computer science used to ensure that the length of a message meets specific requirements or algorithm requirements. In encryption algorithms, it is usually necessary to pad the input data to a predetermined length to meet the algorithm's input length requirements. Message padding is commonly used in cryptographic applications such as block cipher algorithms and hash functions. The purpose of message padding is to ensure that the length of the input data meets the requirements of a specific algorithm, and it is usually necessary to pad the input data to a multiple of the specified block size.

[0054] It should be noted that the message word length of the hash algorithm is 512 bits, which is a requirement of the hash algorithm itself. The hash algorithm module is generally connected to the AHB bus, which typically has a data width of 32 bits. The 32-bit data can be stored in the 512-bit message register in either big-endian or little-endian mode.

[0055] Step S13: Determine the padding length corresponding to the last group of message words in the target data based on the highest bit of the message register and a specific bit of the data length register.

[0056] In this embodiment, the padding length corresponding to the last group of message words in the target data is determined based on the most significant bit of the message register and a specific bit of the data length register, such as... Figure 2 As shown, it includes the following steps A1-A2:

[0057] Step A1: Calculate the difference between the highest bit of the message register and a specific bit of the data length register.

[0058] Step A3: Determine the difference as the padding length corresponding to the last group of message words in the target data.

[0059] In this embodiment of the application, after determining the difference as the padding length corresponding to the last group of message words in the target data, the method further includes: storing the padding length in a shift register, wherein the storage length of the shift register is consistent with the padding length.

[0060] In this embodiment, a specific bit in the data length register can be the lower 9 bits. The difference between 511 and the lower 9 bits of the data length register data_length[63:0] (data_length[8:0]) is calculated to determine the padding length corresponding to the last group of message words. This padding length is then stored in the 9-bit shift register data_shift[8:0]. It should be noted that the purpose of calculating the difference between 511 and the lower 9 bits of the data length register data_length[63:0] (data_length[8:0]) is to obtain a difference value (i.e., the padding length), which represents the number of zeros that need to be filled in the padding portion of the message register. This difference value is used as the basis for shift control in subsequent operations.

[0061] Additionally, if larger data lengths are required, the number of bits in the data length register can be increased. For example, the data_length register can be expanded to 128 bits to support larger data sizes.

[0062] Step S14: The last group of message words is shifted left in the message register using the padding length control to complete the padding of the last group of message words.

[0063] In this embodiment of the application, the padding length is used to control the left shift of the last group of message words in the message register, such as... Figure 3 As shown, it includes the following steps B1-B3:

[0064] Step B1: Detect whether the currently written message word is the last message word of the target data.

[0065] Step B2: If it is confirmed that the currently written message word is the last group of message words of the target data, fill the end of the last group of message words with 1 bit of the first preset value.

[0066] In this embodiment, when the last group of message words arrives, 1 bit "1" is first added to the end of the message word. It should be noted that 5248 divided by 512 results in 10, with a remainder of 128. Therefore, the last 128 bits of data are virtually filled to 512 bits. According to the hash algorithm filling rules, 1 bit "1" needs to be filled. Then, the remaining 512-128-1=319 bits are filled first, and 319 bits "0" are filled. After filling, the 64 bits of 0-63 are replaced with the 64-bit value in the data length data_length[64:0].

[0067] Step B3: Control the shift counter to read the parameter values ​​of each bit in the shift register in sequence, and use the parameter values ​​of each bit in the shift register to control the left shift of the last group of message words.

[0068] In this embodiment of the application, the shift counter is controlled to sequentially read the parameter values ​​of each bit in the shift register, and the parameter values ​​of each bit in the shift register are used to control the left shift of the last group of message words, including steps B301-B308:

[0069] Step B301: Control the shift counter to reset, read the first parameter value corresponding to the first bit in the shift register, and determine the first left shift number corresponding to the first parameter value.

[0070] In this embodiment, since a 1-bit "1" has been padded to the end of the message word, the shift counter is reset, and its value is 0. Then, the first parameter of the first bit (i.e., bit 0) of the shift register is read, and its value is "1". The corresponding first left shift number is 2.

[0071] It should be noted that the shift counters `shift_count[3:0]` control the number of shift operations. When the last group of message words arrives, by incrementing the value of the shift counters `shift_count[3:0]` one by one, specific position values ​​in the shift registers `data_shift[8:0]` can be read sequentially, and the message words can be shifted left accordingly. The number of bits to be shifted left corresponding to each bit in the shift registers `data_shift[8:0]` determines the number of bits to be filled with 0 during the message filling process. The combined use of the shift counters and shift registers facilitates correct filling operations later.

[0072] Step B302: Fill the message register with the second preset value according to the first left shift number, and update the value recorded by the shift counter to the first value.

[0073] In this embodiment, the first left shift bit is 2. Based on this, the last group of message words is shifted left by 2 bits in the message register according to the first left shift bit, that is, 2 bits of "0" are filled in. Then the value recorded by the shift counter is updated from "0" to "1". By updating the value of the shift counter, the next bit to be read can be determined.

[0074] Step B303: Read the second parameter value corresponding to the second bit and determine the second left shift number corresponding to the second parameter value, wherein the second bit is the bit following the first bit.

[0075] In this embodiment of the application, the value recorded by the current shift counter is "1". At this time, the second parameter value corresponding to the second bit is read. The second parameter value is "1" and the left shift number corresponding to the second parameter value is "4".

[0076] Step B304: Fill the message register with the second preset value according to the second left shift number, and update the value recorded by the shift counter to the second value, wherein the second value is greater than the first value.

[0077] In this embodiment, the second left shift bit is 4. At this time, the last group of message words is shifted left by 4 bits in the message register according to the second left shift bit, that is, 4 bits of "0" are filled in. Then the value recorded by the shift counter is updated from "1" to "2".

[0078] Step B305: Read the third parameter value corresponding to the third bit and determine the third left shift number corresponding to the third parameter value, wherein the third bit is the bit following the second bit.

[0079] In this embodiment of the application, the value recorded by the current shift counter is "2". At this time, the value of the third parameter corresponding to the third bit is read. The value of the third parameter is "1" and the number of left shifts corresponding to the value of the third parameter is "8".

[0080] Step B306: Fill the message register with the second preset value according to the third left shift number, and update the value recorded by the shift counter to the third value, wherein the third value is greater than the first value.

[0081] In this embodiment, the second left shift bit is 8. At this time, the last group of message words is shifted left by 8 bits in the message register according to the second left shift bit, that is, 8 bits of "0" are filled in. Then the value recorded by the shift counter is updated from "2" to "3".

[0082] Step B307: Check if the third bit is the last bit in the message register.

[0083] Step B308: When the third bit is the last bit in the message register, construct padding data based on the first preset value of 1 bit, the second preset value of the total padding bit length, and other message words, wherein the total padding bit length is the sum of the left shift bits corresponding to each bit.

[0084] In this embodiment, if the third bit is not the last bit, the next bit of the third bit is obtained, and its corresponding left shift number is determined, until the shift counter accumulates to the threshold. Finally, the padding data is constructed based on the first preset value of 1 bit, the second preset value of the total padding number of bits, and other message words.

[0085] In this embodiment of the application, the method further includes: if it is confirmed that the currently written message word is not the last group of message words of the target data, performing a hash operation based on the currently written message word.

[0086] In this embodiment of the application, after constructing the padding data based on a first preset value of 1 bit, a second preset value of the total padding bit length, and other message words, the method further includes: replacing the parameter value of a set bit in the padding data with the parameter value of a set bit in the data length register to obtain the replaced padding data; and performing hash calculation based on the replaced padding data.

[0087] It should be noted that, firstly, the lower 64 bits of the message register `message[511:0]`, specifically the value of `message[63:0]`, are replaced with the value of the data length register `data_length[63:0]`. This means replacing the last 64 bits stored in the message register with the data length value. The data length register stores the length of the input data. After the replacement, the final value stored in the message register `message[511:0]` is the padded message. The padded process ensures that the message length meets the requirements of the specific algorithm. Next, the replaced value in the message register `message[511:0]` is sent to the subsequent calculation module to perform the hash operation. The subsequent calculation module may perform further processing, such as dividing the message into multiple blocks for iterative calculation or applying a specific hash algorithm.

[0088] During this process, by adding the data length to the message register and padding the message, the integrity of the input data and its compliance with the requirements of the specific algorithm are ensured. This allows subsequent computation modules to perform correct hash operations using the padded message.

[0089] This application calculates the padding length of the last group of message words and then shifts the last group of message words to the left based on the padding length, thus saving CPU resources, improving system operating efficiency, and meeting the practical requirements of low power consumption, high throughput, and high data security. Compared with existing solutions, the calculation method of this application has low power consumption and small logic circuit area, which can effectively improve the chip's operating speed and reduce chip cost.

[0090] In this embodiment, message padding rules can also be customized: that is, message padding rules can be customized according to specific needs. For example, specific markers can be added before and after message padding to prevent the hash algorithm from being attacked. The specific process is as follows: Add a bit 1 to the end of the message word to indicate the end of the message. Pad enough bits 0 after the 1 until a message block is filled (depending on the specific hash algorithm and message block size). If the message has been filled to the last message block, a new message block can be added and filled with all 0s. This process ensures that a clear end marker is added to the message, preventing attackers from adding extra data to the end of the message. After padding the message, the length of the original message (in bits) is added to the padded message. This length should be represented using a fixed number of bits (e.g., 64 bits) and can be stored using big-endian or little-endian byte order. This length marker will ensure that the length of the message is always checked during the hash calculation process, preventing attackers from modifying the message undetected. By adding markers before and after message padding, the security and integrity of the hash algorithm can be improved.

[0091] This application provides a specific embodiment of the message word filling method described above, and the filling process specifically includes:

[0092] (1) The hash algorithm is started, 32 bits of data are input and stored in the message register message[511:0].

[0093] (2) Assuming the data length register data_length[63:0] has a value of 5248, then according to the message filling rules, it can be divided into 11 groups. The last group has 128 bits of data, which needs to be filled with 1 bit "1", 319 bits "0" and 64 bits of data length data_length[63:0].

[0094] (3) Calculate the difference between 511 and the value of the lower 9 bits of the data length register, data_length[8:0]. Store the difference in the shift register data_shift[8:0]. If the value of data_length[8:0] is 128, then the value of data_shift[8:0] is 511-128=383, which is represented in binary as 101111111.

[0095] (4) When the last message word arrives, first fill the end of the message word with 1 bit "1". The shift counter is 0 at this time, so read the value of the 0th bit of the shift register. The value is "1", so shift the message word left by 1 bit, that is, fill it with 1 bit "0".

[0096] (5) If the value of the shift counter is 1 when it is incremented by 1, then the value of the first bit of the shift register is read. If the value is "1", then the message word is shifted left by 2 bits, that is, 2 bits "0" are filled.

[0097] (6) The shift counter increments sequentially from 1 to 2, 3, 4, 5, 6, 7, 8. The values ​​of bits 2, 3, 4, 5, 6, 7, and 8 of the shift register are read sequentially, and their values ​​are "1", "1", "1", "1", "1", "0", and "1" respectively. The message word is then shifted left by 4, 8, 16, 32, 64, 0, and 256 bits respectively, that is, 4, 8, 16, 32, 64, 0, and 256 bits of "0" are filled in sequentially.

[0098] (7) At this time, the message word is filled with 1 bit "1", 383 bits "0", plus 128 bits of input data, for a total of 512 bits.

[0099] (8) After completing step 7, replace the lower 64 bits of the message register message[63:0] with the data length register data_length[63:0], that is, update the value of message[511:64]||data_length[63:0] to message[511:0], thus completing the hash algorithm message filling. Here, "||" represents the concatenation operator.

[0100] This embodiment also provides a data filling device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0101] This embodiment provides a data filling device, such as... Figure 4 As shown, it includes:

[0102] The acquisition module 41 is used to acquire message filling instructions, wherein the message filling instructions carry the target data to be written;

[0103] The response module 42 is used to respond to message filling instructions, store the target data into the message register in the order of the data, and determine the highest bit of the message register.

[0104] The determination module 43 is used to determine the padding length corresponding to the last group of message words in the target data based on the highest bit of the message register and a specific bit of the data length register.

[0105] The control module 44 is used to control the last group of message words to shift left in the message register using the padding length, so as to complete the padding of the last group of message words.

[0106] In this embodiment of the application, the determining module 43 is used to calculate the difference between the highest bit of the message register and a specific bit of the data length register; and to determine the difference as the padding length corresponding to the last group of message words in the target data.

[0107] In this embodiment of the application, the data filling device further includes: a storage module for storing the filling length in a shift register, wherein the storage length of the shift register is consistent with the filling length.

[0108] In this embodiment of the application, the control module 44 is used to detect whether the currently written message word is the last group of message words of the target data; if it is confirmed that the currently written message word is the last group of message words of the target data, a first preset value of 1 bit is filled at the end of the last group of message words; the shift counter is controlled to read the parameter values ​​of each bit of the shift register in sequence, and the parameter values ​​of each bit in the shift register are used to control the left shift of the last group of message words.

[0109] In this embodiment, the control module 44 is used to control the shift counter to reset, read the first parameter value corresponding to the first bit in the shift register, and determine the first left shift number corresponding to the first parameter value; fill the message register with a second preset value according to the first left shift number, and update the value recorded by the shift counter to the first value; read the second parameter value corresponding to the second bit, and determine the second left shift number corresponding to the second parameter value, wherein the second bit is the bit following the first bit; fill the message register with a second preset value according to the second left shift number, and update the value recorded by the shift counter to the second value. The process involves: reading the third parameter value corresponding to the third bit and determining the third left shift number corresponding to the third parameter value, where the third bit is the bit following the second bit; filling the message register with the second preset value according to the third left shift number and updating the value recorded by the shift counter to the third value, where the third value is greater than the first value; detecting whether the third bit is the last bit in the message register; and constructing the filling data based on the first preset value of 1 bit, the second preset value of the total filling bits, and other message words if the third bit is the last bit in the message register.

[0110] In this embodiment of the application, the apparatus further includes: an execution module, configured to perform a hash operation based on the currently written message word if it is confirmed that the currently written message word is not the last group of message words of the target data.

[0111] In this embodiment of the application, the apparatus further includes: a processing module, configured to replace the parameter value of a set bit in the padding data with the parameter value of a set bit in the data length register to obtain the replaced padding data; and to perform hash calculation based on the replaced padding data.

[0112] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 5 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system).

[0113] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0114] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0115] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device as shown by a landing page for an app. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0116] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0117] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0118] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0119] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A data filling method, characterized in that, The method includes: Obtain a message filling instruction, wherein the message filling instruction carries the target data to be written; In response to the message filling instruction, the target data is stored into the message register in chronological order, and the highest bit of the message register is determined; Based on the highest bit of the message register and a specific bit of the data length register, determine the padding length corresponding to the last group of message words in the target data; The padding length is used to control the left shift of the last group of message words in the message register to complete the padding of the last group of message words; The step of determining the padding length corresponding to the last group of message words in the target data based on the most significant bit of the message register and a specific bit of the data length register includes: calculating the difference between the most significant bit of the message register and the specific bit of the data length register; and determining the difference as the padding length corresponding to the last group of message words in the target data. After determining the difference as the padding length corresponding to the last group of message words in the target data, the method further includes: storing the padding length in a shift register, wherein the storage length of the shift register is consistent with the padding length; The step of using the padding length to control the left shift of the last group of message words in the message register includes: detecting whether the currently written message word is the last group of message words of the target data; if it is confirmed that the currently written message word is the last group of message words of the target data, padding the end of the last group of message words with a first preset value of 1 bit; controlling the shift counter to read the parameter values ​​of each bit of the shift register in sequence, and using the parameter values ​​of each bit in the shift register to control the left shift of the last group of message words.

2. The method according to claim 1, characterized in that, The control shift counter sequentially reads the parameter values ​​of each bit in the shift register, and uses the parameter values ​​of each bit in the shift register to control the left shift of the last group of message words, including: The shift counter is reset, the first parameter value corresponding to the first bit in the shift register is read, and the first left shift number corresponding to the first parameter value is determined. The message register is filled with a second preset value according to the first left shift number, and the value recorded by the shift counter is updated to the first value; Read the second parameter value corresponding to the second bit and determine the second left shift number corresponding to the second parameter value, wherein the second bit is the next bit after the first bit; The message register is filled with a second preset value according to the second left shift number, and the value recorded by the shift counter is updated to the second value, wherein the second value is greater than the first value; Read the third parameter value corresponding to the third bit, and determine the third left shift number corresponding to the third parameter value, wherein the third bit is the bit following the second bit; The message register is filled with a second preset value according to the third left shift number, and the value recorded by the shift counter is updated to a third value, wherein the third value is greater than the first value; Detect whether the third bit is the last bit in the message register; When the third bit is the last bit in the message register, padding data is constructed based on a first preset value of 1 bit, a second preset value of the total padding bit length, and other message words, wherein the total padding bit length is the sum of the left shift bits corresponding to each bit.

3. The method according to claim 1, characterized in that, The method further includes: If it is confirmed that the currently written message word is not the last group of message words of the target data, a hash operation is performed based on the currently written message word.

4. The method according to claim 2, characterized in that, After constructing the padding data based on a first preset value of 1 bit, a second preset value of the total padding bits, and other message words, the method further includes: The parameter values ​​of the set bits in the filling data are replaced with the parameter values ​​of the set bits in the data length register to obtain the replaced filling data; Hash calculation is performed based on the replaced padding data.

5. A data filling device, characterized in that, The device includes: The acquisition module is used to acquire a message filling instruction, wherein the message filling instruction carries the target data to be written; The response module is used to respond to the message filling instruction, store the target data into the message register in sequence, and determine the most significant bit of the message register; The determination module is used to determine the padding length corresponding to the last group of message words in the target data based on the highest bit of the message register and a specific bit of the data length register. The control module is used to control the last group of message words to shift left in the message register using the padding length, so as to complete the padding of the last group of message words; The determining module is used to calculate the difference between the highest bit of the message register and a specific bit of the data length register; and to determine the difference as the padding length corresponding to the last group of message words in the target data. The data filling device further includes: a storage module for storing the filling length in a shift register, wherein the storage length of the shift register is consistent with the filling length; The control module is used to detect whether the currently written message word is the last group of message words of the target data; if it is confirmed that the currently written message word is the last group of message words of the target data, a first preset value of 1 bit is filled at the end of the last group of message words; the shift counter is controlled to read the parameter values ​​of each bit of the shift register in sequence, and the parameter values ​​of each bit in the shift register are used to control the left shift of the last group of message words.

6. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method of any one of claims 1 to 4.

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