A register transfer level code generation method and system for a combinational logic circuit

Abstract

The application discloses a register transfer level code generation method and system of a combinational logic circuit, which comprises taking the check rule used for function verification of the combinational logic circuit as a constraint condition, traversing each input combination of the combinational logic circuit to check whether the output of the combinational logic circuit takes a specific value and filling in a truth table according to the check result; and generating register transfer level code of the combinational logic circuit according to the truth table, wherein the traversal is performed by taking the check rule rule1-ruleK as a constraint condition, and the traversal is performed on 2 N An input combination composed of N inputs in1-inN, and the value of each output of M outputs out1-outM is determined under each input combination. The application aims to support larger scale inputs when generating register transfer level code of the combinational logic circuit by constructing a truth table, and the generated RTL code does not need to be functionally verified and is beneficial to generation of a timing-optimized circuit by a synthesis tool.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and specifically to a method and system for generating register-transfer level (RTL) code for combinational logic circuits. Background Technology

[0002] A crucial part of integrated circuit design is writing RTL (Register Transfer Level) code, which is essentially logic design. An integrated circuit mainly consists of two parts: sequential logic circuits and combinational logic circuits. Sequential logic circuits are typically a set of registers that operate sequentially according to a given clock pulse, giving them memory capabilities. Combinational logic circuits, on the other hand, consist of logic gates that provide the circuit's logical functions.

[0003] Any combinational logic circuit, no matter how complex, can be abstracted as a function with N inputs and M outputs, denoted as (out1, out2, ..., outM) = f(in1, in2, ..., inN), where each input and output is a one-bit digital signal. Each input signal is either 0 or 1. Therefore, for a combinational logic circuit with N inputs, there are a total of 2... N There are multiple input combinations. When writing code for a combinational logic circuit with N inputs and M outputs, a complete truth table can be constructed. For example... Figure 2 As shown, the truth table has 2 N Rows and (N+M) columns, where columns 1 to N correspond to inputs in1 to inN, and columns (N+1) to (N+1+M) correspond to outputs out1 to outM, 1 to 2 N The rows correspond to 2 respectively N Given a set of input combinations, for example, the first line corresponds to {in1,in2,…,inN}=0, the second line corresponds to {in1,in2,…,inN}=1, and so on, the second... N The row corresponds to {in1,in2,…,inN}=2 N -1. Under each input combination, an output signal can have three values: 1, 0, or "-". "-" indicates that the logic circuit does not care about the value of the output signal under this input combination; whether it is 0 or 1 does not affect the circuit's function. After filling in the complete truth table according to the function to be implemented by the combinational logic circuit, the RTL code for this combinational logic circuit can be written using AND, OR, NOT, and other logic gates.

[0004] Generating RTL code using a complete truth table has several advantages: the truth table is very intuitive to construct, requiring no high-level abstraction and considering all possible cases, thus reducing the probability of errors; the process of generating RTL code from the truth table can be automated by tools, and the correctness of the RTL code is guaranteed as long as the truth table is constructed correctly; the generated RTL code is very close to the underlying implementation, which is beneficial for synthesis tools to generate timing-optimized circuits. However, the biggest problem with this method is the limited scale of input signals it can handle. Assuming there are 10 input signals, there are 1024 input combinations, requiring 1024 rows of information to construct a complete truth table; however, when there are 20 input signals, there are over 1 million input combinations, requiring over 1 million rows of information to construct a complete truth table, which is extremely difficult to manually fill out manually. When there are many input signals, it is usually necessary to perform high-level abstraction based on the function to be implemented by the combinational logic circuit or to merge the input scenarios to reduce the size of the truth table. Compared with building a complete truth table, the code written by these methods has a relatively high probability of error, requires sufficient functional verification, and the timing may be poor. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method and system for generating register-transfer level code for combinational logic circuits, which addresses the above-mentioned problems in the prior art. The present invention aims to achieve support for larger-scale inputs when generating register-transfer level code for combinational logic circuits by constructing truth tables. The generated RTL code does not require functional verification and is beneficial for synthesis tools to generate timing-optimized circuits.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A register-transfer level code generation method for combinational logic circuits includes:

[0008] S101, take the checking rules used to perform functional verification of combinational logic circuits as constraints, iterate through the combinational logic circuit outputs for each input combination to see if the checking rules are violated when they take a specific value, and fill in the truth table accordingly.

[0009] S102 generates register transfer level code for combinational logic circuits based on the truth table.

[0010] Optionally, step S101 includes:

[0011] S201, determine the N inputs in1 to inN, the M outputs out1 to outM, and the K check rules rule1 to ruleK used for functional verification of the combinational logic circuit;

[0012] S202, using rules 1 to 1K as constraints, iterate through 2... N Given N input combinations in1 to inN, determine the value of each of the M outputs out1 to outM as 0, 1, or "-" for each input combination, where "-" indicates that it can be either 0 or 1. This results in a truth table consisting of the values ​​of each of the M outputs out1 to outM as 0, 1, or "-".

[0013] Optionally, step S202 includes:

[0014] S301, Initialize row variable I to 0, proceed to step S302;

[0015] S302, Determine if row variable I is less than 2 N If yes, proceed to step S303; otherwise, it means that all input combinations consisting of N inputs in1 to inN have been traversed, and a truth table consisting of M outputs out1 to outM in which each output is 0, 1 or "-" has been obtained, and jump to step S102.

[0016] S303, Initialize column variable J to 1, proceed to step S304;

[0017] S304, determine whether column variable J is greater than M. If yes, it means that under the current input combination, the corresponding bits of all output signals in the truth table have been filled. Jump to step S313; otherwise, proceed to step S305.

[0018] S305, Generate a non-repeating input combination based on N inputs in1 to inN as the current input combination, and proceed to step 306;

[0019] S306, set the value of the Jth output outJ to 0, and determine whether the input combination is the current input combination and the Jth output outJ is 0, and whether there is a violation of the checking rules in rule1 to ruleK. If so, it means that the Jth output outJ under the current input combination cannot be 0, and proceed to step S307; otherwise, jump to step S309.

[0020] S307, set the value of the Jth output outJ to 1, and determine whether the input combination is the current input combination and the Jth output outJ is 1, which violates any of the checking rules in rules1 to ruleK. If yes, it means that the Jth output outJ cannot be 1 under the current input combination, and the Jth output outJ cannot be 0 or 1, indicating that the checking rule definition is wrong and needs to be redefined. Then, end and exit; otherwise, it means that the Jth output outJ cannot be 0 under the current input combination but can be 1, and proceed to step S308.

[0021] S308, fill the corresponding bit of the Jth output outJ in the I-th row of the truth table with 1, and jump to step S312;

[0022] S309, set the value of the Jth output outJ to 1, and determine whether the input combination is the current input combination and the Jth output outJ is 1, and whether there is a violation of the checking rules in rule1 to ruleK. If yes, it means that the Jth output outJ under the current input combination cannot be 1 but can be 0, and proceed to step S310; otherwise, it means that the Jth output outJ under the current input combination can be either 0 or 1, and jump to step S311.

[0023] S310, fill the corresponding bit of the Jth output in the I-th row of the truth table with 0, and jump to step S312;

[0024] S311, fill the corresponding bit of the Jth output in the I-th row of the truth table with "-", and proceed to step S312;

[0025] S312, let J = J + 1, then jump back to step S304;

[0026] S313, let I = I + 1, then jump back to step S302.

[0027] Optionally, step S202 is performed using a formal verification tool.

[0028] Optionally, after step S102, the method further includes register-transfer level code for combinational logic circuits generated from the truth table, skipping functional verification of the register-transfer level code and directly using synthesis tools to generate the circuit.

[0029] Furthermore, the present invention also provides a register-transfer level code generation system for combinational logic circuits, comprising:

[0030] The truth table generation program unit is used to take the checking rules used to perform functional verification of combinational logic circuits as constraints, traverse the combinational logic circuit output to take a specific value under each input combination to see if the checking rules are violated and fill in the truth table accordingly.

[0031] The code generation unit is used to generate register-transfer level code for combinational logic circuits based on the truth table.

[0032] Optionally, the truth table generation program unit includes:

[0033] The initialization program module is used to determine the N inputs in1 to inN, the M outputs out1 to outM, and the K check rules rule1 to ruleK used for functional verification of the combinational logic circuit.

[0034] The input combination truth value loop constructs a program module, which is used to iterate through 2 rules, using rule1 to ruleK as constraints. N Given N input combinations in1 to inN, determine the value of each of the M outputs out1 to outM as 0, 1, or "-" for each input combination, where "-" indicates that it can be either 0 or 1. This results in a truth table consisting of the values ​​of each of the M outputs out1 to outM as 0, 1, or "-".

[0035] Furthermore, the present invention also provides a register-transfer level code generation system for combinational logic circuits, including a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the register-transfer level code generation method for the combinational logic circuits.

[0036] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute a register-transfer level code generation method for the combinational logic circuit.

[0037] Furthermore, the present invention also provides a computer program product comprising a computer program or instructions for being programmed or configured by a microprocessor to execute a register-transfer level code generation method for the combinational logic circuit.

[0038] Compared with the prior art, the present invention has the following main advantages:

[0039] 1. This invention can handle larger-scale inputs. This invention proposes a method for generating RTL code. In this method, the operator only needs to define the checking rules, and the formal verification tool judges the legal values ​​of the output signal under each combination of inputs according to the checking rules, thereby constructing a complete truth table. Compared with manually filling in the truth table, the tool can handle larger-scale inputs.

[0040] 2. The RTL code generated by this invention does not require functional verification. This invention uses the checking rules used for functional verification as constraints, iterating through each input combination to check for violations of the checking rules when the output takes a specific value, filling in a truth table accordingly, and then generating RTL code based on the truth table. The process of generating RTL from the truth table can be automated by tools; as long as the truth table is constructed correctly, the correctness of the RTL code is guaranteed. The truth table is generated by the tool based on the checking rules; as long as the checking rule definitions are complete, the generated truth table will meet the design expectations. Therefore, once the RTL is generated, it is code that does not violate the defined checking rules and does not require further functional verification.

[0041] 3. The RTL code generated by this invention facilitates the generation of timing-optimized circuits by synthesis tools. This invention also generates RTL code by constructing a complete truth table. The RTL code is very close to the underlying implementation, which is beneficial for synthesis tools to generate timing-optimized circuits. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention.

[0043] Figure 2 This is an example of a truth representation constructed in an embodiment of the present invention.

[0044] Figure 3 This is a detailed flowchart illustrating the method of an embodiment of the present invention. Detailed Implementation

[0045] The basic principle of this invention is as follows: When performing functional verification on combinational logic code, either simulation verification or formal verification methods can be used. Regardless of the method used, a series of checking rules are typically defined. If the code does not violate these rules, it is considered to meet the design expectations. Assuming the defined checking rules are complete and cover all functional scenarios of combinational logic circuits, then code that does not violate the defined checking rules is functionally correct. Based on this, such as Figure 1 As shown, this embodiment provides a method for generating register-transfer-level (RTL) code for combinational logic circuits, including:

[0046] S101, take the checking rules used to perform functional verification of combinational logic circuits as constraints, iterate through the combinational logic circuit outputs for each input combination to see if the checking rules are violated when they take a specific value, and fill in the truth table accordingly.

[0047] S102 generates register transfer level code for combinational logic circuits based on the truth table.

[0048] In this embodiment, step S101 includes:

[0049] S201, determine the N inputs in1 to inN, the M outputs out1 to outM, and the K check rules rule1 to ruleK used for functional verification of the combinational logic circuit;

[0050] S202, using rules 1 to 1K as constraints, iterate through 2... NGiven N input combinations in1 to inN, determine the value of each of the M outputs out1 to outM as 0, 1, or "-" for each input combination, where "-" indicates that it can be either 0 or 1. This results in a truth table consisting of the values ​​of each of the M outputs out1 to outM as 0, 1, or "-". Figure 2 For an example of the truth representation constructed in this embodiment, see [link to example]. Figure 2 It can be seen that the N inputs of this combinational logic circuit are in1, in2, ..., inN, and the M outputs are out1, out2, ..., outM; the N inputs constitute 2 N There are N input combinations consisting of inputs in1 to inN. Under each input combination, the value of each of the M outputs out1 to outM is 0, 1 or "-", where "-" means that it can be either 0 or 1.

[0051] like Figure 3 As shown, step S202 in this embodiment includes:

[0052] S301, Initialize row variable I to 0, proceed to step S302;

[0053] S302, Determine if row variable I is less than 2 N If yes, proceed to step S303; otherwise, it means that all input combinations consisting of N inputs in1 to inN have been traversed, and a truth table consisting of M outputs out1 to outM in which each output is 0, 1 or "-" has been obtained, and jump to step S102.

[0054] S303, Initialize column variable J to 1, proceed to step S304;

[0055] S304, determine whether column variable J is greater than M. If yes, it means that under the current input combination, the corresponding bits of all output signals in the truth table have been filled. Jump to step S313; otherwise, proceed to step S305.

[0056] S305, Generate a non-repeating input combination based on N inputs in1 to inN as the current input combination, and proceed to step 306;

[0057] S306, set the value of the Jth output outJ to 0, and determine whether the input combination is the current input combination and the Jth output outJ is 0, and whether there is a violation of the checking rules in rule1 to ruleK. If so, it means that the Jth output outJ under the current input combination cannot be 0, and proceed to step S307; otherwise, jump to step S309.

[0058] S307, set the value of the Jth output outJ to 1, and determine whether the input combination is the current input combination and the Jth output outJ is 1, which violates any of the checking rules in rules1 to ruleK. If yes, it means that the Jth output outJ cannot be 1 under the current input combination, and the Jth output outJ cannot be 0 or 1, indicating that the checking rule definition is wrong and needs to be redefined. Then, end and exit; otherwise, it means that the Jth output outJ cannot be 0 under the current input combination but can be 1, and proceed to step S308.

[0059] S308, fill the corresponding bit of the Jth output outJ in the I-th row of the truth table with 1, and jump to step S312;

[0060] S309, set the value of the Jth output outJ to 1, and determine whether the input combination is the current input combination and the Jth output outJ is 1, and whether there is a violation of the checking rules in rule1 to ruleK. If yes, it means that the Jth output outJ under the current input combination cannot be 1 but can be 0, and proceed to step S310; otherwise, it means that the Jth output outJ under the current input combination can be either 0 or 1, and jump to step S311.

[0061] S310, fill the corresponding bit of the Jth output in the I-th row of the truth table with 0, and jump to step S312;

[0062] S311, fill the corresponding bit of the Jth output in the I-th row of the truth table with "-", and proceed to step S312;

[0063] S312, let J = J + 1, then jump back to step S304;

[0064] S313, let I = I + 1, then jump back to step S302.

[0065] In this embodiment, step S202 is performed using a formal verification tool. Furthermore, step S102, which generates register-transfer level code for the combinational logic circuit based on the truth table, is an existing method that can be implemented using existing tools; therefore, its implementation details will not be elaborated here. In this embodiment, after step S102, the method further includes generating register-transfer level code for the combinational logic circuit based on the truth table. Functional verification of the register-transfer level code is skipped, and the circuit is directly generated using synthesis tools, thereby enabling rapid generation of timing-optimized circuits.

[0066] In summary, compared to the traditional method of manually filling in truth tables, the method of this embodiment uses formal verification tools to generate truth tables based on the checking rules used for functional verification of combinational logic circuits. This allows the method of this embodiment to handle larger-scale inputs. Moreover, since the RTL code is directly based on the checking rules used for functional verification of combinational logic circuits, the generated RTL code does not need to be functionally verified and is beneficial for synthesis tools to generate timing-optimized circuits.

[0067] Furthermore, this embodiment also provides a register-transfer level code generation system for combinational logic circuits, including: a truth table generation program unit, used to take the checking rules used for functional verification of combinational logic circuits as constraints, traverse whether the checking rules are violated when the output of the combinational logic circuit takes a specific value under each input combination, and fill in the truth table accordingly; and a code generation program unit, used to generate register-transfer level code for combinational logic circuits based on the truth table.

[0068] In this embodiment, the truth table generation program unit includes: an initialization program module, used to determine the N inputs in1 to inN, the M outputs out1 to outM, and the K checking rules rule1 to ruleK used for functional verification of the combinational logic circuit; and an input combinational truth table loop construction program module, used to traverse 2 using the checking rules rule1 to ruleK as constraints. N Given N input combinations in1 to inN, determine the value of each of the M outputs out1 to outM as 0, 1, or "-" for each input combination, where "-" indicates that it can be either 0 or 1. This results in a truth table consisting of the values ​​of each of the M outputs out1 to outM as 0, 1, or "-".

[0069] Furthermore, this embodiment also provides a register-transfer-level code generation system for combinational logic circuits, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute a register-transfer-level code generation method for the combinational logic circuits. Additionally, this embodiment provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute the register-transfer-level code generation method for the combinational logic circuits. Furthermore, this embodiment also provides a computer program product comprising a computer program or instructions for being programmed or configured by a microprocessor to execute the register-transfer-level code generation method for the combinational logic circuits.

[0070] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0071] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for generating register-transfer level code for combinational logic circuits, characterized in that, include: S101, take the checking rules used to perform functional verification of combinational logic circuits as constraints, iterate through the combinational logic circuit outputs for each input combination to see if the checking rules are violated when they take a specific value, and fill in the truth table accordingly. S102, Generate register transfer level code for combinational logic circuits based on the truth table; Step S101 includes: S201, determine the N inputs in1 to inN, the M outputs out1 to outM, and the K check rules rule1 to ruleK used for functional verification of the combinational logic circuit; S202, using rules 1 to 1K as constraints, iterate through 2... N Given N input combinations from in1 to inN, determine the value of each of the M outputs out1 to outM as 0, 1, or "-" for each input combination, where "-" indicates that it can be either 0 or 1, thus obtaining a truth table consisting of the values ​​of each of the M outputs out1 to outM as 0, 1, or "-". Step S202 includes: S301, Initialize row variable I to 0, proceed to step S302; S302, Determine if row variable I is less than 2 N If yes, proceed to step S303; otherwise, it means that all input combinations consisting of N inputs in1 to inN have been traversed, and a truth table consisting of M outputs out1 to outM in which each output is 0, 1 or "-" has been obtained, and jump to step S102. S303, Initialize column variable J to 1, proceed to step S304; S304, determine whether column variable J is greater than M. If yes, it means that under the current input combination, the corresponding bits of all output signals in the truth table have been filled. Jump to step S313; otherwise, proceed to step S305. S305, Generate a non-repeating input combination based on N inputs in1 to inN as the current input combination, and proceed to step 306; S306, set the value of the Jth output outJ to 0, and determine whether the input combination is the current input combination and the Jth output outJ is 0, and whether there is a violation of the checking rules in rule1 to ruleK. If so, it means that the Jth output outJ under the current input combination cannot be 0, and proceed to step S307; otherwise, jump to step S309. S307, set the value of the Jth output outJ to 1, and determine whether the input combination is the current input combination and the Jth output outJ is 1, which violates any of the checking rules in rules1 to ruleK. If yes, it means that the Jth output outJ cannot be 1 under the current input combination, and the Jth output outJ cannot be 0 or 1, indicating that the checking rule definition is wrong and needs to be redefined. Then, end and exit; otherwise, it means that the Jth output outJ cannot be 0 under the current input combination but can be 1, and proceed to step S308. S308, fill the corresponding bit of the Jth output outJ in the I-th row of the truth table with 1, and jump to step S312; S309, set the value of the Jth output outJ to 1, and determine whether the input combination is the current input combination and the Jth output outJ is 1, and whether there is a violation of the checking rules in rule1 to ruleK. If yes, it means that the Jth output outJ under the current input combination cannot be 1 but can be 0, and proceed to step S310; otherwise, it means that the Jth output outJ under the current input combination can be either 0 or 1, and jump to step S311. S310, fill the corresponding bit of the Jth output in the I-th row of the truth table with 0, and jump to step S312; S311, fill the corresponding bit of the Jth output in the I-th row of the truth table with "-", and proceed to step S312; S312, let J = J + 1, then jump back to step S304; S313, let I = I + 1, then jump back to step S302.

2. The register-transfer level code generation method for combinational logic circuits according to claim 1, characterized in that, Step S202 is completed using formal verification tools.

3. The register-transfer level code generation method for combinational logic circuits according to claim 1, characterized in that, After step S102, the method also includes register-transfer level code for combinational logic circuits generated from the truth table. Functional verification of the register-transfer level code is skipped, and the circuit is directly generated using synthesis tools.

4. A register-transfer-level code generation system for using the register-transfer-level code generation method for combinational logic circuits according to any one of claims 1 to 3, characterized in that, include: The truth table generation program unit is used to take the checking rules used to perform functional verification of combinational logic circuits as constraints, traverse the combinational logic circuit output to take a specific value under each input combination to see if the checking rules are violated and fill in the truth table accordingly. The code generation unit is used to generate register-transfer level code for combinational logic circuits based on the truth table. The truth table generation program unit includes: The initialization program module is used to determine the N inputs in1 to inN, the M outputs out1 to outM, and the K check rules rule1 to ruleK used for functional verification of the combinational logic circuit. The input combination truth value loop constructs a program module, which is used to iterate through 2 rules, using rule1 to ruleK as constraints. N Given N input combinations in1 to inN, determine the value of each of the M outputs out1 to outM as 0, 1, or "-" for each input combination, where "-" indicates that it can be either 0 or 1. This results in a truth table consisting of the values ​​of each of the M outputs out1 to outM as 0, 1, or "-".

5. A register-transfer level code generation system for combinational logic circuits, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to execute the register-transfer level code generation method for the combinational logic circuit according to any one of claims 1 to 3.

6. A computer-readable storage medium storing a computer program, characterized in that, The computer program is used to be programmed or configured by a microprocessor to execute the register-transfer level code generation method for the combinational logic circuit according to any one of claims 1 to 3.

7. A computer program product, said computer program product comprising a computer program or instructions, characterized in that, The computer program or instructions are used to be programmed or configured by a microprocessor to execute the register-transfer level code generation method for the combinational logic circuit according to any one of claims 1 to 3.

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