Netlist processing method and apparatus, electronic device, and computer-readable storage medium

Abstract

The present disclosure provides a netlist processing method and device, electronic equipment and computer readable storage medium, and belongs to the technical field of chip design. The netlist processing method comprises: determining, from standard cells included in a target netlist, standard cells other than hardware macro cells as to-be-modified standard cells; and deleting redundant information of the to-be-modified standard cells from the target netlist to obtain a first to-be-loaded file for input in a layout planning stage of chip back-end design, wherein the redundant information comprises interface information and connection objects, and / or hierarchical information. When top-down partitioning is performed in the layout planning stage of chip back-end design, the time length of initialization and interface change delay can be reduced, and the top layer does not need to obtain required information from each module.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and in particular to a netlist processing method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] When performing top-down partitioning during the layout planning phase of chip backend design, it is necessary to load all netlists, including the top-level netlist and the netlists of each module. However, existing chips are quite large, with hundreds of millions of included units, and the corresponding netlists are also gigabytes in size. Loading all netlists and initializing can take more than ten hours. Furthermore, every modification to the partitioning on the interface also introduces significant delays.

[0003] Related technologies aim to reduce the problems of excessively long initialization times and significant delays in subsequent modifications caused by large netlists by clearing all content from them. However, clearing all netlists can lead to the loss of important information. When performing top-down partitioning, the top layer needs to frequently interact with each module to obtain relevant information. After the top layer summarizes the obtained information, it continues to partition, which increases the iteration process and interaction costs. Summary of the Invention

[0004] This disclosure provides a netlist processing method, apparatus, electronic device, and computer-readable storage medium; it can reduce initialization time and interface modification delay when performing top-down partitioning during the layout planning stage of chip back-end design, and eliminates the need for the top layer to obtain the required information from each module.

[0005] In a first aspect, this disclosure provides a netlist processing method, which includes: identifying standard cells other than hardware macrocells from the standard cells included in the target netlist as standard cells to be modified; deleting redundant information of the standard cells to be modified from the target netlist to obtain a first file to be loaded for input in the layout planning stage of chip back-end design, wherein the redundant information includes: interface information and connection objects, and / or, hierarchy information.

[0006] Secondly, this disclosure provides a netlist processing apparatus, which includes: a determining part and a deleting part; the determining part is used to determine, from the standard cells included in the target netlist, standard cells other than hardware macrocells as standard cells to be modified; the deleting part is used to delete redundant information of the standard cells to be modified from the target netlist to obtain a first file to be loaded for input in the layout planning stage of chip back-end design, wherein the redundant information includes: interface information and connection objects, and / or, hierarchy information.

[0007] Thirdly, this disclosure provides an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the netlist processing method as described in the first aspect.

[0008] Fourthly, this disclosure provides a computer-readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the netlist processing method as described in the first aspect.

[0009] Fifthly, this disclosure provides a computer program product, wherein the computer program product includes a computer program or instructions, which, when run on a processor, cause the processor to execute the computer program or instructions to implement the steps of the netlist processing method as described in the first aspect.

[0010] In a sixth aspect, this disclosure provides a chip including a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the netlist processing method as described in the first aspect.

[0011] This disclosure provides a netlist processing method, which includes, during the top-down partitioning stage of chip back-end design layout planning, identifying standard cells (excluding hardware macrocells) from the standard cells included in the target netlist as standard cells to be modified based on the characteristics of the input files relied upon by this stage; deleting redundant information of the standard cells to be modified from the target netlist to obtain a first file to be loaded. Since the first file to be loaded removes redundant information, it is much smaller than the target netlist, significantly reducing the time required for the chip placement and routing layout design tool to load and initialize the first file to be loaded. After initialization, the latency for user operations on the module layout in the interface is also greatly reduced. Furthermore, the first file to be loaded retains the identification information of each standard cell and the information of the hardware macrocells, which can be directly used during layout planning. The top layer does not need to obtain the required information from the modules, reducing the interaction between the top layer and the modules and improving the efficiency of layout planning. Attached Figure Description

[0012] Figure 1 This is one of the flowcharts illustrating the netlist processing method provided in this disclosure;

[0013] Figure 2 A schematic diagram of the information provided for the standard unit in this disclosure;

[0014] Figure 3 This is one of the schematic diagrams of chip layout planning provided in this disclosure;

[0015] Figure 4This is the second schematic diagram of the chip layout provided in this disclosure;

[0016] Figure 5 This is the third schematic diagram of the chip layout provided in this disclosure;

[0017] Figure 6 This is the fourth schematic diagram of the chip layout provided in this disclosure;

[0018] Figure 7 This is the second flowchart illustrating the netlist processing method provided in this disclosure;

[0019] Figure 8 The third flowchart illustrating the netlist processing method provided in this disclosure;

[0020] Figure 9 The fourth flowchart illustrating the netlist processing method provided in this disclosure;

[0021] Figure 10 This is a structural block diagram of a netlist processing device provided in this disclosure;

[0022] Figure 11 This is a schematic diagram of the hardware structure of an electronic device provided in this disclosure. Detailed Implementation

[0023] The technical solutions in the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0024] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that this disclosure can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0025] The following is an explanation of some of the terms or concepts used in the claims and description of this invention.

[0026] Chip layout: includes top layer, modules and standard units; where the top layer is the base of the chip layout, including modules and standard units, or only modules, and modules include multiple standard units.

[0027] Standard cell: A standardized basic unit in chip design, such as flip-flops, logic gates, latches, registers, selectors, adders, etc.

[0028] A netlist is used to describe the connections between standard units, modules, layers, etc., and is usually a text file that follows a relatively simple markup syntax. Netlists are generally divided into block netlists and top netlists. Block netlists describe the connections between standard units within a module and the connections between the layers to which each standard unit belongs. Top netlists describe the connections between standard units and modules within the top netlist (e.g., between standard units and modules, modules and modules, and between standard units), and the connections between the layers to which each standard unit belongs.

[0029] Hardware macro: A special type of unit in the standard unit, which is a hardware circuit module, such as an analog-to-digital converter, memory, etc.

[0030] Standard cell information database: Used to store information about standard cells, including the size, area, and interface information of the standard cells.

[0031] During the layout planning stage of chip back-end design, all netlists and other dependent files are loaded and initialized using chip placement and routing layout design tools (such as Innovus) to transform the logical view described by the files into a visual view displayed on the interface. However, if the netlist is large (the size of netlists in existing chip designs is in the gigabyte range), initialization takes a long time, and every subsequent operation on the interface will cause a significant delay.

[0032] If the information in the netlist is removed and initialization is complete, when planning various modules in the top layer (assuming the top layer includes module A, module B, and module C), the top layer interacts with module A to obtain its information (e.g., total area, number of hardware macrocells, and their location) when planning module A's position in the layout. Similarly, it interacts with module B and module C sequentially. In current chip designs, the top layer contains many modules, and interacting with each module increases the iterative process and the time cost of frequent interactions also increases.

[0033] Therefore, this disclosure aims to remove redundant information in the netlist during the initialization process, so as to reduce the size of the netlist while retaining important information, thereby avoiding increased interaction between the top layer and the modules.

[0034] The netlist processing method provided in this disclosure will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0035] like Figure 1 As shown, this disclosure provides a netlist processing method. The following example, using an electronic device as the execution subject, provides an exemplary description of the netlist processing method provided by this disclosure. This method may include steps 101 to 104 as described below.

[0036] 101. From the standard cells included in the target netlist, identify the standard cells other than hardware macrocells as the standard cells to be modified.

[0037] In this example, the target netlist may be a top-level netlist or a module netlist.

[0038] Each target netlist includes: identification information, interface information, connection objects, hierarchy information, and hierarchy connection information. Based on the aforementioned definition of the top layer, since the top layer includes standard units and modules, the top-level netlist can include identification information, which includes the identifiers of the standard units and modules included in the top layer. For each standard unit or module, the top-level netlist also includes interface information, which indicates the interfaces included in a standard unit or a module. For each interface, the top-level netlist also includes the corresponding connection object, which indicates the object interconnected with that interface. For each standard unit, the top-level netlist also includes hierarchy information, which indicates the hierarchy of a standard unit in the chip and its position at the top layer. For each hierarchy, the top-level netlist also includes the corresponding connection relationships for that hierarchy.

[0039] Based on the aforementioned module definition, since a module comprises multiple standard units, the module netlist includes identification information, which includes the identifiers of the standard units included in the module. For each standard unit, the module netlist also includes interface information, which indicates the interfaces included in a standard unit. For each interface, the module netlist also includes the corresponding connection object, which indicates the object interconnected with that interface. For each standard unit, the module netlist also includes hierarchy information, which indicates the hierarchy of a standard unit within the chip and its location within the module. For each hierarchy, the module netlist also includes the corresponding connection relationships.

[0040] For example, such as Figure 2The diagram shows an example of standard units included in a module netlist. This module netlist includes: standard unit 1 and standard unit 2. Standard unit 1 includes two interfaces, A1 and A2, and standard unit 2 includes two interfaces, B1 and B2. Interface A1 of standard unit 1 is connected to interface B1 of standard unit 2, and interface A2 of standard unit 1 is connected to interface B2 of standard unit 2. Standard unit 1 is located in the third layer, at the upper left of the module, and standard unit 2 is located in the second layer, at the lower right of the module. The connection between the layers is that the second layer and the third layer are connected.

[0041] In this embodiment, the information of the hardware macrocell is retained because the area of ​​the hardware macrocell is relatively large, and the position of the hardware macrocell will affect the layout of the module. If the information of the hardware macrocell is deleted, it may lead to an unreasonable layout, which will require a re-layout.

[0042] For example, such as Figure 3 As shown, if the information of the hardware macro unit is deleted, module 4 includes hardware macro unit 1 located in the upper left corner of the module. Figure 3 Due to insufficient area, the upper left corner of module 4 in the design cannot accommodate hardware macrounit 1. Figure 3 The layout of each module needs to be redesigned. However, if the information of hardware macro unit 1 in module 4 is retained, and the hardware macro unit is determined to be located in the upper left position of module 4 before layout design, then sufficient space can be reserved for hardware macro unit 1 in the upper left position of module 4 during layout design. Figure 4 As shown.

[0043] 102. Delete redundant information of the standard cells to be modified from the target netlist to obtain the first file to be loaded for the layout planning stage of chip back-end design.

[0044] The redundant information includes: interface information and connection objects, and / or, hierarchy information.

[0045] Specifically, removing redundant information from the target netlist for the standard unit to be modified can include deleting the interface information and connection objects of the standard unit, deleting its hierarchical information, or deleting all three. In practice, to minimize the size of the resulting first file to be loaded, it is common practice to delete all interface information, connection objects, and hierarchical information of the standard unit from the target netlist.

[0046] During the layout planning phase of chip back-end design, it is necessary to define the approximate location of each module at the top layer. Therefore, the area information of each module is quite important. The area of ​​each standard cell is defined in the standard cell information database. Therefore, the identification information of each standard cell is retained in the netlist so that the area of ​​each standard cell can be retrieved from the standard cell information database based on the identification information, and thus the area of ​​a part can be determined based on the area of ​​each standard cell.

[0047] For example, such as Figure 5 The diagram shows the approximate locations of the various modules included in the top-level 20 design. However, due to unreasonable design of modules 1 and 5, adjustments and swaps are necessary. Figure 5 The positions of modules 1 and 5 are used to obtain the adjusted layout as follows: Figure 6 As shown. The existing netlist, loaded without pruning, in... Figure 5 After performing the swap operation, the following will be displayed. Figure 6 It would require a delay of tens of seconds or even several minutes, but with the solution disclosed in this paper, the display... Figure 6 The required latency is in the millisecond range, meaning it is imperceptible to the user.

[0048] It should be noted that the target netlist is any netlist in the entire netlist, that is, steps 101 and 102 are performed on each netlist in the entire netlist to remove redundant information of the standard cells in each netlist.

[0049] In this embodiment, during the top-down partitioning of the chip back-end design layout planning stage, based on the characteristics of the input files relied upon by this stage, standard cells other than hardware macrocells are identified as standard cells to be modified from the standard cells included in the target netlist. Redundant information of the standard cells to be modified is deleted from the target netlist to obtain a first file to be loaded. Since the first file to be loaded removes redundant information, it is much smaller than the target netlist. This significantly reduces the time required for the chip placement and routing layout design tool to load the first file to be loaded for initialization, and greatly reduces the latency for user operations on the module layout in the interface after initialization. Furthermore, the first file to be loaded retains the identification information of each standard cell and the information of the hardware macrocells, which can be directly used during layout planning. The top layer does not need to obtain the required information from the modules, reducing the interaction between the top layer and the modules and improving the efficiency of layout planning.

[0050] Since the area and location of hardware macrocells affect the top-level layout planning of modules, it is necessary to retain the area-related identification and location information of hardware macrocells. To further reduce the size of the input file during the top-down partitioning stage of chip back-end design layout planning, some embodiments of this disclosure combine... Figure 1 ,like Figure 7As shown, after step 102 above, the netlist processing method further includes the following step 103.

[0051] 103. Delete the interface information and connection objects of the hardware macrocells included in the first file to be loaded, and obtain the second file to be loaded for input in the layout planning stage of chip back-end design.

[0052] In this embodiment, the hardware macrocell information included in the first file to be loaded is: identification information, interface information, connection object, hierarchy information, and hierarchy connection information. During top-down partitioning in the layout planning stage, the area and position information of the hardware macrocells affect the module's layout design, while the interface information, connection object, and hierarchy connection information do not affect the module's layout design, but they occupy most of the space in the netlist and can be considered redundant information. Therefore, this embodiment removes this redundant information, retaining only the area-related identification information of the hardware macrocells (the area corresponding to the identification information can be determined from the standard cell information library based on the identification information) and the position-related hierarchy information, resulting in the second file to be loaded. This further reduces the size of the input file during top-down partitioning in the layout planning stage, thereby reducing the time for the tool to load and initialize the second file to be loaded, and reducing the latency of interface operations during layout planning.

[0053] When partitioning from top to bottom during the layout planning phase, the key information in the netlist is the area of ​​the modules. The area of ​​a module is determined by the sum of the areas of the individual units it comprises. To further reduce the size of the input file, this embodiment combines... Figure 1 ,like Figure 8 As shown, after step 102 above, the netlist processing method further includes steps 104 and 105 below.

[0054] The number of units to be modified is M, and the redundant information includes interface information, connection objects, and hierarchy information; the redundant information of the standard units to be modified is deleted from the target netlist.

[0055] 104. Determine the area of ​​the standard unit to be modified from the standard unit information database.

[0056] The standard unit information database includes information on multiple standard units. The information of each standard unit includes the identification information and area information of the standard unit. Based on the identification information of the standard unit to be modified, the area of ​​the standard unit to be modified is retrieved from the standard unit information database.

[0057] 105. Modify the M standard cells to be modified in the first file to be loaded into N target cells to obtain the third file to be loaded, which is used as input in the layout planning stage of chip back-end design.

[0058] Among them, the area of ​​the target cell is greater than or equal to the area of ​​any one of the M standard cells to be modified, the difference between the sum of the areas of the M standard cells to be modified and the sum of the areas of the N target cells is within a preset range, N is an integer greater than 1, and M is greater than N, and the third file to be loaded is the input file of the layout planning stage of the chip back-end design.

[0059] Optionally, the target element can be determined from the standard element information database by selecting the standard element with the largest area; or, the target element can be determined from the target netlist by selecting the standard element to be modified with the largest area.

[0060] Specifically, the process for determining N is as follows: the sum of the areas of the M standard units to be modified is Sum, the area of ​​the target unit is S, N1 is the quotient of Sum divided by S, N2 is the quotient of Sum divided by S plus 1, the product of N1 and S is P1, the product of N2 and S is P2, the absolute value of the difference between P1 and Sum is less than the absolute value of the difference between P2 and Sum, then the number of target units is determined to be N1, the absolute value of the difference between P1 and Sum is greater than the absolute value of the difference between P2 and Sum, then the number of target units is determined to be N2.

[0061] For example, the first file to be loaded includes eight standard units to be modified: standard unit 1 to standard unit 8. The areas of standard unit 1 to standard unit 8 are determined from the standard unit information database to be 20, 5, 2, 5, 8, 7, 8, and 5, respectively, and the sum of the areas of standard unit 1 to standard unit 8 is 60.

[0062] In one scenario, the standard unit with the largest area is determined from the standard unit information database to be standard unit 10, with an area of ​​31. The quotient of 31 divided by 60 is 1. When N is 1, the product of 1 and 31 is 31, and the absolute value of the difference between 31 and 60 is 29. When N is 1 plus 1, which is 2, the product of 2 and 31 is 62, and the absolute value of the difference between 62 and 60 is 2. Since 2 is less than 29, N is determined to be 2. Therefore, the standard unit included in the third file to be loaded is: standard unit 10.

[0063] In another scenario, the standard cell with the largest area is determined from the target netlist as standard cell 1, with an area of ​​20. The quotient of 60 divided by 20 is 3. Therefore, the standard cells included in the third file to be loaded are: standard cell 1, standard cell 1, and standard cell 1.

[0064] As can be seen, the first file to be loaded contains 8 standard cells, while the third file to be loaded contains 2 or 3 standard cells. The number of standard cells is greatly reduced, which further reduces the size of the input file. In addition, the total area information is preserved, and the important information that is relied upon when performing top-down partitioning in the layout planning stage is not lost.

[0065] In this embodiment, the area of ​​the standard unit to be modified is determined from the standard unit information library; the M standard units to be modified in the first file to be loaded are modified into N target units to obtain a third file to be loaded, where N is less than M, and the sum of the areas of the N target units and the sum of the areas of the M standard units to be modified are within a preset range. Thus, the third file to be loaded contains fewer standard units than the first file to be loaded, but the change in the total area is within the preset range. This means that while further reducing the input file size in the layout planning stage, the area information of each module is not lost, thereby further reducing the initialization time, and the top layer does not need to obtain the area information corresponding to each module.

[0066] In some embodiments of this disclosure, in order to further reduce the size of the input file in the layout planning stage, combined with Figure 8 ,like Figure 9 As shown, step 106 can be performed after step 105.

[0067] 106. Delete the interface information and connection objects of the hardware macrocells included in the third file to be loaded, and obtain the fourth file to be loaded for the layout planning stage of the chip back-end design.

[0068] For details on deleting the interface information and connection object descriptions of the hardware macrocells included in the third file to be loaded, please refer to step 103 above, which will not be repeated here.

[0069] For example, the information included in the third file to be loaded is: Standard Unit 1, Standard Unit 1, Standard Unit 1, Hardware Macro Unit 2 - Interface A (Connection Object) - Hierarchical Information; the information included in the fourth file to be loaded is: Standard Unit 1, Standard Unit 1, Standard Unit 1, Hardware Macro Unit 2 - Hierarchical Information.

[0070] In this embodiment of the disclosure, the interface information and connection objects of the hardware macrocells included in the third file to be loaded are deleted to obtain the fourth file to be loaded, which can further reduce the size of the input file in the layout planning stage, thereby further reducing the initialization time.

[0071] Optionally, after steps 102, 103, 105 and 106 above, in order to further reduce the size of the input files in the layout planning stage, the hierarchical connection information in the first file to be loaded, the second file to be loaded, the third file to be loaded and the fourth file to be loaded is deleted.

[0072] Figure 10 This is a structural block diagram of a netlist processing apparatus disclosed herein, such as... Figure 10As shown, it includes: a determination part and a deletion part; the determination part 1001 is used to determine the standard cells other than hardware macro cells from the standard cells included in the target netlist as the standard cells to be modified; the deletion part 1002 is used to delete redundant information of the standard cells to be modified from the target netlist to obtain the first file to be loaded for the layout planning stage of the chip back-end design, wherein the redundant information includes: interface information and connection objects, and / or, hierarchy information.

[0073] In some embodiments of this disclosure, the deletion portion 1002 is further used to delete the redundant information of the standard cell to be modified from the target netlist to obtain the first file to be loaded for the layout planning stage of the chip back-end design, and then delete the interface information and connection objects of the hardware macrocells included in the first file to be loaded to obtain the second file to be loaded for the layout planning stage of the chip back-end design.

[0074] In some embodiments of this disclosure, the number of units to be modified is M, and the redundant information includes interface information, connection objects, and hierarchy information. The device further includes a modification part. The determining part 1001 is further configured to, after deleting the redundant information of the standard units to be modified from the target netlist to obtain a first file to be loaded for the layout planning stage of chip back-end design, determine the area of ​​the standard units to be modified from the standard unit information library, which includes the areas of multiple standard units. The modification part is configured to modify the M standard units to be modified included in the first file to be loaded into N target units to obtain a third file to be loaded for the layout planning stage of chip back-end design. The area of ​​the target units is greater than or equal to the area of ​​any one of the M standard units to be modified, and the difference between the sum of the areas of the M standard units to be modified and the sum of the areas of the N target units is within a preset range, where N is an integer greater than 1, and M is greater than N.

[0075] In some embodiments of this disclosure, the determining part 1001 is further configured to determine the standard unit with the largest area as the target unit from the standard unit information library before modifying the M standard units to be modified in the first file to be loaded into N target units to obtain the third file to be loaded for input in the layout planning stage of the chip back-end design.

[0076] In some embodiments of this disclosure, the determining portion 1001 is further configured to determine the standard unit to be modified with the largest area as the target unit from the target netlist before modifying the M standard units to be modified included in the first file to be loaded into N target units to obtain the third file to be loaded for the layout planning stage of the chip back-end design.

[0077] In some embodiments of this disclosure, the deletion portion 902 is further configured to, after modifying the M standard units to be modified in the first file to be loaded into N target units to obtain a third file to be loaded for input in the layout planning stage of chip back-end design, delete the interface information and connection objects of the hardware macrocells included in the third file to be loaded, thereby obtaining a fourth file to be loaded for input in the layout planning stage of chip back-end design.

[0078] It should be noted that the above-mentioned netlist processing device can be the electronic device in the above method embodiment of this application, or it can be a functional module and / or functional entity in the electronic device that can realize the function of the device embodiment. This application embodiment does not limit it.

[0079] In this embodiment, each module can implement the netlist processing method provided in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0080] Please refer to Figure 11 This illustration shows a structural block diagram of an electronic device provided in an exemplary embodiment of this disclosure. In some examples, the electronic device may be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The electronic device has communication functions and can access wired or wireless networks. The term "electronic device" can refer to one of multiple terminals; those skilled in the art will understand that the number of such terminals may be more or less. It is understood that the electronic device undertakes the computational and processing work of the technical solution of this disclosure, and this disclosure does not limit this aspect.

[0081] like Figure 11 As shown, the electronic device in this disclosure may include one or more of the following components: processor 1110 and memory 10120.

[0082] Optionally, the processor 1110 connects various parts within the electronic device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1120, and by calling data stored in the memory 1120. Optionally, the processor 1110 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 1010 can integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required to be displayed on the touch screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the baseband chip is used to handle wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 1110, but may be implemented using a separate chip.

[0083] The memory 1120 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 1120 may include a non-transitory computer-readable storage medium. The memory 1120 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created according to the use of the electronic device, etc.

[0084] In addition, those skilled in the art will understand that the structure of the electronic device shown in the above figures does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the electronic device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0085] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the netlist processing method as described in the above embodiments.

[0086] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the netlist processing method described in the above embodiments.

[0087] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described netlist processing method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0088] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0089] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0090] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0091] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A netlist processing method, characterized in that, The method includes: From the standard cells included in the target netlist, the standard cells other than hardware macro cells are identified as the standard cells to be modified; The redundant information of the standard cell to be modified is removed from the target netlist to obtain the first file to be loaded for the layout planning stage of the chip back-end design. The redundant information includes: interface information and connection objects, and / or, hierarchy information. Delete the interface information and connection objects of the hardware macrocells included in the first file to be loaded to obtain a second file to be loaded for input in the layout planning stage of chip back-end design; The area of ​​the standard unit to be modified is determined from the standard unit information database, which includes the areas of multiple standard units; The M standard units to be modified included in the first file to be loaded are modified into N target units to obtain a third file to be loaded for input in the layout planning stage of chip back-end design. The area of ​​the target unit is greater than or equal to the area of ​​any one of the M standard units to be modified. The difference between the sum of the areas of the M standard units to be modified and the sum of the areas of the N target units is within a preset range, where N is an integer greater than 1 and M is greater than N. The interface information and connection objects of the hardware macrocells included in the third file to be loaded are deleted to obtain the fourth file to be loaded, which is used for the layout planning stage of chip back-end design.

2. The method according to claim 1, characterized in that, Before modifying the M standard units to be modified in the first file to be loaded into N target units to obtain the third file to be loaded for input in the layout planning stage of chip back-end design, the method further includes: From the standard unit information database, the standard unit with the largest area is determined as the target unit.

3. The method according to claim 1, characterized in that, Before modifying the M standard units to be modified in the first file to be loaded into N target units to obtain the third file to be loaded for input in the layout planning stage of chip back-end design, the method further includes: From the target netlist, the standard cell with the largest area to be modified is determined as the target cell.

4. A netlist processing device, characterized in that, The device includes: a determining part, a deleting part, and a modifying part; The determining part is used to determine the standard units other than hardware macro units from the standard units included in the target netlist as the standard units to be modified. The deletion section is used to remove redundant information of the standard cell to be modified from the target netlist, obtaining a first file to be loaded for input during the layout planning stage of chip back-end design. The redundant information includes: interface information and connection objects, and / or, hierarchy information; and Delete the interface information and connection objects of the hardware macrocells included in the first file to be loaded to obtain a second file to be loaded for input in the layout planning stage of chip back-end design; The determining part determines the area of ​​the standard unit to be modified from the standard unit information database, which includes the areas of multiple standard units; The modification part is used to modify the M standard units to be modified included in the first file to be loaded into N target units to obtain a third file to be loaded for input in the layout planning stage of chip back-end design. The area of ​​the target unit is greater than or equal to the area of ​​any one of the M standard units to be modified. The difference between the sum of the areas of the M standard units to be modified and the sum of the areas of the N target units is within a preset range, where N is an integer greater than 1 and M is greater than N. The deletion part is also used to delete the interface information and connection objects of the hardware macrocells included in the third file to be loaded, so as to obtain the fourth file to be loaded for input in the layout planning stage of chip back-end design.

5. The apparatus according to claim 4, characterized in that, The determining part is further configured to, before modifying the M standard units to be modified in the first file to be loaded into N target units to obtain the third file to be loaded for input in the layout planning stage of chip back-end design, determine the standard unit with the largest area as the target unit from the standard unit information library.

6. The apparatus according to claim 4, characterized in that, The determining part is further configured to, before modifying the M standard units to be modified included in the first file to be loaded into N target units to obtain the third file to be loaded for input in the layout planning stage of chip back-end design, determine the standard unit to be modified with the largest area as the target unit from the target netlist.

7. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the netlist processing method as described in any one of claims 1 to 3.

8. A computer-readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the netlist processing method as described in any one of claims 1 to 3.

Images