A timing violation processing method and device, and a medium

Abstract

The application relates to the technical field of integrated circuit design, and discloses a timing violation processing method and device and a medium. Compared with the problem that in the related art, when the timing problem is solved by limiting the register position, the position of the constraint frame needs to be adjusted for many times, thereby consuming time and energy, in the application, different timing convergence distances are set for different clock sizes, after the target repair path is confirmed, the timing convergence distance between the transmitting point register and the receiving point register corresponding to the clock size of the target repair path is determined based on the corresponding relationship between the clock size and the timing convergence distance, thereby a constraint frame is created at the position where the distance between the transmitting point register and the receiving point register is less than the timing convergence distance, and the timing violation processing is realized. In the application, the position of the constraint frame does not need to be tried for many times, the distance relationship between the constraint frame and the register for different clock sizes is confirmed according to the corresponding relationship table, the experiment and debugging process are reduced, and the processing efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a timing violation handling method, apparatus, and medium. Background Technology

[0002] Logic synthesis is the process of transforming a circuit's behavioral-level description, particularly a Register Transfer Level (RTL) description, into a gate-level representation. Logic synthesis is driven by various constraints, including operating environment, time, area, and power consumption. The ultimate goal of synthesis is to produce results that satisfy these constraints, the most important of which is timing constraint. Satisfying timing constraints is commonly referred to as timing convergence, which is the most crucial objective of synthesis.

[0003] In related technologies, timing violations are resolved by placing specified logic cells within a created cell constraint frame using instructions in the accompanying Electronic Design Automation (EDA) tools. This optimizes the layout and resolves timing issues. However, due to the distance between the emitter and receiver registers, setting the cell constraint frame requires gradually adjusting the distance between the cell constraint frame and both registers. This method demands extensive experimentation and debugging, consuming significant time and effort.

[0004] Therefore, it is evident that how to implement a simpler solution to timing violation is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a timing violation handling method, apparatus, and medium to solve the problem in related technologies where multiple adjustments to the constraint box position are required to resolve timing problems by restricting register positions, resulting in time and effort consumption.

[0006] To solve the above-mentioned technical problems, the present invention provides a timing violation handling method, comprising:

[0007] Obtain the timing path of each timing unit;

[0008] The target repair path is identified from each of the aforementioned time-series paths;

[0009] Obtain the correspondence between the clock size of the target repair path and the distance between the transmit point register and the receive point register, and determine the timing convergence distance between the transmit point register and the receive point register corresponding to the clock size of the target repair path based on the correspondence.

[0010] Based on the timing convergence distance, a binding box is created where the distance between the transmitter register and the receiver register is less than the timing convergence distance;

[0011] The distance between the transmit point register and the receive point register includes: the direct distance between the transmit point register and the receive point register, or the sum of the distances between the transmit point register and the receive point register and the logical unit that the transmit point register passes through.

[0012] In some implementations, the constraint frame includes a cell constraint frame and a logic cell constraint frame;

[0013] Furthermore, the step of creating a binding box where the distance between the transmit point register and the receive point register is less than the timing convergence distance, based on the timing convergence distance, includes:

[0014] Determine whether the direct distance between the transmit point register and the receive point register exceeds the timing convergence distance;

[0015] If the distance is exceeded, the cell binding frame is created within the time convergence distance to place the receiver point register;

[0016] If not, determine whether the sum of the distances between the logic unit that passes through the transmitter register and the receiver register and the transmitter register and the receiver register exceeds the timing convergence distance; if so, create a logic unit constraint box at the location where the sum of the distances does not exceed the timing convergence distance to place the target logic unit.

[0017] On the one hand, it is confirmed that the target repair path includes:

[0018] Obtain the violation value corresponding to each of the aforementioned timing units;

[0019] Sort the aforementioned violation values;

[0020] The timing unit with the largest violation value is identified as the target timing unit.

[0021] The path in the target timing unit is confirmed to be the target repair path.

[0022] On the other hand, placing the target logic unit within the logic unit constraint frame includes:

[0023] Confirm the hierarchical name of the target level in the logic unit between the transmit point register and the receive point register;

[0024] Place logical units with the same hierarchical name as the target logical unit within the logical unit constraint box.

[0025] In some implementations, the size of the unit constraint frame is a first preset multiple of the area of ​​the receiving point register;

[0026] The size of the logic unit constraint frame is a second preset multiple of the area size of the target logic unit; the values ​​of the first preset multiple and the second preset multiple are both greater than or equal to 1.

[0027] In other implementations, after the step of creating a binding box where the distance between the transmit point register and the receive point register is less than the timing convergence distance, the method further includes:

[0028] Determine whether the timing of the target repair path converges;

[0029] If not, move the unit constraint box toward the emission point register by the minimum moving distance, and return to the step of determining whether the timing of the target repair path has converged;

[0030] If so, then the creation position of the constraint box is determined to meet the requirements.

[0031] On one hand, after the step of creating a binding box where the distance between the transmit point register and the receive point register is less than the timing convergence distance, the method further includes:

[0032] Determine whether there is a violation between the transmit point register and the logic unit constraint frame, or between the logic unit constraint frame and the receive point register;

[0033] If so, the logic unit constraint frame is moved to the side with more buffers by the minimum moving distance, and the process returns to the step of determining whether there is a violation between the transmit point register and the logic unit constraint frame, or between the logic unit constraint frame and the receive point register;

[0034] If not, then the creation position of the constraint box is determined to meet the requirements.

[0035] On the other hand, if violations still exist in the timing path through the logic unit constraint box, the following is also included:

[0036] Determine whether the timing of the path opposite to the timing path of the violation is positive;

[0037] If positive, move the logic unit constraint box toward the emitter register by the minimum moving distance; return to the step of determining whether the timing of the path opposite to the timing path of the violation is positive, until the violation is cleared;

[0038] If the result is negative, the layout plan will be readjusted.

[0039] In some embodiments, the timing path includes an establishment timing path and a hold timing path;

[0040] The formula for the time required for data to arrive in the established time path is:

[0041] T arrive =T launch +T ck2q +T dp ;

[0042] Among them, T arrive T represents the data arrival time. launch T is the time required for the clock source to reach the first register. ck2q T is the time it takes for data to be transferred within the first register. dp This is the time required for data to be sent from the first register to the second register;

[0043] The time required to establish a time path is:

[0044] T require =T capture +T cycle -T setup ;

[0045] Among them, T require To meet the time requirement, T capture T represents the data capture time. cycle T is the cycle time. setup Set the time for the data;

[0046] The establishment time formula is:

[0047] T launch +T ck2q +T dp =T capure +T cycle -T setup ;

[0048] T setup slack =T require -T arrive >0;

[0049] The time required to maintain the time path is:

[0050] T arrive =T launch +T ck2q +T dp ;

[0051] T require =T capture +Thold ;

[0052] T hold_slack =T arrive -T require >0;

[0053] Among them, T setup slack To establish a time margin, T hold For the data retention time, T hold_slack To maintain a time margin.

[0054] To address the aforementioned technical problems, the present invention also provides a timing violation processing apparatus, comprising:

[0055] The acquisition module is used to acquire the timing path of each timing unit;

[0056] The confirmation module is used to confirm the target repair path from each of the aforementioned timing paths;

[0057] The processing module is used to obtain the correspondence between the clock size of the target repair path and the distance between the transmit point register and the receive point register, and to determine the timing convergence distance between the transmit point register and the receive point register corresponding to the clock size of the target repair path based on the correspondence; wherein, the distance between the transmit point register and the receive point register includes: the direct distance between the transmit point register and the receive point register, or the sum of the distances between the logic unit passed between the transmit point register and the receive point register and the distance between the transmit point register and the receive point register;

[0058] A module is created to create a bounding box where the distance between the transmitter register and the receiver register is less than the timing convergence distance, based on the timing convergence distance.

[0059] To solve the above-mentioned technical problems, the present invention also provides another timing violation processing apparatus, including a memory for storing computer programs;

[0060] A processor, configured to implement the timing violation handling method described above when executing the computer program.

[0061] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the timing violation handling method described above.

[0062] The timing violation handling method provided by this invention includes: obtaining the timing path of each timing unit; identifying the target repair path from each timing path; obtaining the correspondence between the clock size of the target repair path and the distance between the transmit point register and the receive point register; determining the timing convergence distance between the transmit point register and the receive point register corresponding to the clock size of the target repair path based on the correspondence; creating a binding box where the distance between the transmit point register and the receive point register is less than the timing convergence distance, according to the timing convergence distance; wherein, the distance between the transmit point register and the receive point register includes: the direct distance between the transmit point register and the receive point register, or the sum of the distances between the logic unit passed through between the transmit point register and the receive point register and the distance between the transmit point register and the receive point register.

[0063] Compared to related technologies, the advantages of this invention are as follows: This invention sets different timing convergence distances for different clock sizes. After identifying the target repair path, the timing convergence distance between the transmit and receive registers corresponding to the clock size of the target repair path is determined based on the correspondence between clock size and timing convergence distance. This allows for the creation of a constraint box where the distance between the transmit and receive registers is less than the timing convergence distance, thus achieving timing violation handling. This invention eliminates the need for multiple attempts to determine the position of the constraint box. The distance relationship between the constraint box and registers for different clock sizes is confirmed based on the correspondence table, reducing experimental and debugging processes, decreasing data processing volume, and improving processing efficiency.

[0064] Furthermore, the timing violation processing apparatus and medium provided by the present invention correspond to the timing violation processing method described above and have the same effect. Attached Figure Description

[0065] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 A flowchart of a timing violation handling method provided in an embodiment of the present invention;

[0067] Figure 2 A path diagram provided for an embodiment of the present invention;

[0068] Figure 3 A schematic diagram of an illegal path provided in an embodiment of the present invention;

[0069] Figure 4 for Figure 3 A schematic diagram showing the location of the constraint box for the path shown;

[0070] Figure 5 This is a schematic diagram of another violation path provided by an embodiment of the present invention;

[0071] Figure 6 for Figure 5 A schematic diagram showing the location of the constraint box for the path shown;

[0072] Figure 7 A structural diagram of a timing violation processing device provided in an embodiment of the present invention;

[0073] Figure 8 This is a structural diagram of another timing violation processing device provided in an embodiment of the present invention. Detailed Implementation

[0074] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0075] Logic synthesis is the process of using a synthesis tool like Design Compiler to convert RTL-level circuits in a Hardware Description Language (HDL) into a circuit-level netlist based on a basic circuit cell library provided by the chip manufacturer. Logic synthesis is driven by various constraints, including operating environment, time, area, and power consumption. The ultimate goal of synthesis is to produce results that satisfy these constraints, the most important of which is timing constraint. Satisfying timing constraints is often referred to as timing convergence, which is the most important objective of synthesis. The quality of logic synthesis directly affects the performance, area, and power consumption of a digital system.

[0076] Throughout the digital back-end implementation process, various verifications are required to ensure the chip's proper functioning. Timing closure is a crucial step, ensuring that the chip achieves its defined performance specifications under specific process, voltage, and temperature (PVT) conditions. For synchronous digital circuits, ensuring the clock path and delay to each timing unit are consistent is paramount. Therefore, timing issues are critical in the back-end design, and this stage primarily involves checking the setup and hold times.

[0077] In related technologies, timing issues arising during logic synthesis for digital back-end layout planning due to excessive distances between the registers at the origin of transmitted data and the registers at the destination of received data can be resolved by using the `create_bound` command in the DesignCompiler tool to restrict register positions. However, a set of timing issues may involve multiple different timing path violations, which can be categorized into two cases. Case 1 involves the transmitter and receiver registers being located in the same location, while the intermediate logic is located far away, resulting in an excessively long path for the transmitter register to transmit to the intermediate logic and then return to the receiver register. Case 2 involves the transmitter and receiver registers being far apart, and the receiver register having data transmission relationships with even more distant locations, thus requiring the timing requirements of both sides to be met. Considering these situations, resolving all path violations with a single `create_bound` is difficult. Designers often need to adjust the cell constraint box position and size multiple times to resolve timing issues. Analyzing the timing results after each adjustment to optimize the cell constraint box position and size for the next iteration is a very time-consuming and labor-intensive process for designers.

[0078] The core of this invention is to provide a timing violation handling method, apparatus, and medium to solve the problem in related technologies where multiple adjustments to the constraint box position are required to resolve timing issues by restricting register positions, resulting in wasted time and effort.

[0079] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0080] Figure 1 A flowchart of a timing violation handling method provided in an embodiment of the present invention is shown below. Figure 1 As shown, the method includes:

[0081] S10: Obtain the timing path of each timing unit;

[0082] S11: Confirm the target repair path from each timeline path;

[0083] S12: Obtain the correspondence between the clock size of the target repair path and the distance between the transmit point register and the receive point register, and determine the timing convergence distance between the transmit point register and the receive point register corresponding to the clock size of the target repair path based on the correspondence.

[0084] S13: Based on the timing convergence distance, create a bounding box where the distance between the transmitter register and the receiver register is less than the timing convergence distance;

[0085] The distance between the transmitter register and the receiver register includes: the direct distance between the transmitter register and the receiver register, or the sum of the distances between the transmitter register and the receiver register and the logical unit that the transmitter register passes through.

[0086] The timing violation handling method provided by this invention is applied in a timing violation handling device, specifically a processor, for implementing integrated circuit design. This method can be applied in the inspection stage of integrated circuits, such as chips, to check and correct timing problems. The above embodiments describe that timing problem checking is achieved by checking two timing parameters: setup time and hold time. Setup time is defined as the minimum time that data must remain stable before the clock trigger edge arrives for a timing analysis unit. Checking setup time ensures that the timing unit can stably acquire data emitted by the previous timing unit. The setup time check path is divided into a transmit path and a capture path. The transmit path is from the clock source to the D terminal of the second-level register, and the capture path is from the clock source to the clock terminal of the second-level register. The timing check only needs to ensure that the capture path delay of this second-level register is longer than the transmit path delay; the setup time is subtracted from the capture path delay. Hold time checking refers to the shortest time that the data input signal must remain stable after the effective clock edge. That is, after the clock signal arrives, the data signal needs to remain stable for a certain period of time. The hold time check is to ensure that new data does not arrive at the D terminal of the receive register too early before the trigger stabilizes and outputs the initial data, thus overwriting the initial data.

[0087] Figure 2 A path diagram provided in this embodiment of the invention is shown in the figure. For establishing a time path, the formula for the time required for data arrival is:

[0088] T arrive =T launch +T ck2q +T dp ;

[0089] Among them, T arrive T represents the data arrival time. launch T is the time required for the clock source to reach the first register. ck2q T is the time it takes for data to be transferred within the first register. dp This is the time required for data to be sent from the first register to the second register;

[0090] The time required to establish a time path is:

[0091] T require =T capture +Tcycle -T setup ;

[0092] Among them, T require To meet the time requirement, T capture T represents the data capture time. cycle T is the cycle time. setup Set the time for the data.

[0093] The establishment time formula is:

[0094] T launch +T ck2q +T dp =T capture +T chcle -T setup ;

[0095] T setup slack =T require -T arrive >0;

[0096] For the hold time check, the required hold time path is:

[0097] T arrive =T launch +T ck2q +T dp ;

[0098] T require =T capture +T hold ;

[0099] T hold_slack =T arrive -T require >0;

[0100] Among them, T setup slack To establish a time margin, T hold For the data retention time, T hold_slack To maintain a time margin.

[0101] As can be seen from the above formula, when the setup time margin and hold time margin are negative, timing violations will occur, which will affect the chip performance and may cause problems in the actual operation of the chip.

[0102] Setup time violations are typically caused by excessively long combinational logic or excessive distance between the transmit register and the receive register. To evaluate whether the path meets setup time requirements, the time slack can be calculated. The time slack includes setup slack and hold slack. A positive time slack indicates timing closure, while a negative time slack indicates a timing violation. Although individual violations do not necessarily indicate a fatal problem with the chip, they represent a risk. A higher number of violations means a greater probability of design issues in real-world environments.

[0103] In this embodiment, the target repair path is the path where a timing violation occurs. It is understood that a chip includes multiple timing units, each containing multiple paths. These paths may intersect with those in other timing units, and a timing violation in one path can affect the operation of other units. Therefore, in practical implementation, when eliminating chip violations, the timing unit with the most violations can be repaired first, processing violations sequentially from most to least numerous violations, thereby reducing the impact on other paths during violation elimination. Specifically, before processing, the violation situation in each timing unit needs to be statistically analyzed and sorted to identify the timing unit to be processed first. In this embodiment, the timing violation processing method further includes: obtaining the violation value corresponding to each timing unit; sorting the violation values; identifying the timing unit with the largest violation value as the target timing unit; and identifying the path in the target timing unit as the target repair path. In this embodiment, the violation value can represent the number of violation paths occurring in the timing unit, and sorting is achieved by comparing this value. Once the target timing unit is identified, the violation path within it becomes the target repair path. In specific implementations, the target repair paths can also be sorted according to the specific circumstances of the violation path, such as path length and the number of logic units traversed.

[0104] The timing violation handling method provided in this invention addresses the problem in related technologies where resolving timing issues by restricting register positions requires multiple adjustments to the binding box position, resulting in wasted time and effort. This invention sets different timing convergence distances for different clock sizes. After identifying the target repair path, it determines the timing convergence distance between the transmit and receive registers corresponding to the clock size of the target repair path based on the correspondence between clock size and timing convergence distance. A binding box is then created where the distance between the transmit and receive registers is less than the timing convergence distance, thus achieving timing violation handling. This invention eliminates the need for multiple attempts at binding box placement; the distance relationship between the binding box and registers for different clock sizes is determined based on a correspondence table, reducing experimental and debugging processes, decreasing data processing volume, and improving processing efficiency.

[0105] As can be seen from the above embodiments, the cause of timing violations in specific implementations may be that the direct distance between the transmitter register and the receiver register is too large, or that the path required by the logic unit passing through the transmitter register and the receiver register is too long. Therefore, the position setting needs to be adjusted according to different situations when creating the binding frame. This embodiment provides a specific creation method. In this embodiment, the binding frame includes a cell binding frame and a logic unit binding frame. Further, creating a binding frame where the distance between the transmitter register and the receiver register is less than the timing convergence distance, based on the timing convergence distance, includes: determining whether the direct distance between the transmitter register and the receiver register exceeds the timing convergence distance; if it does, creating a cell binding frame within the timing convergence distance to place the receiver register; if it does not exceed the timing convergence distance, determining whether the sum of the distances between the logic unit passing through the transmitter register and the receiver register and the transmitter register and the receiver register exceeds the timing convergence distance; if so, creating a logic unit binding frame where the sum of the distances does not exceed the timing convergence distance to place the target logic unit.

[0106] In this embodiment, after the target repair path is identified, its corresponding clock size can also be determined. Based on the correspondence between the clock size and the distance between the transmit point register and the receive point register, the timing convergence distance between the transmit point register and the receive point register can be determined. Setting the constraint box within the timing convergence distance can eliminate timing violations. The distance between the transmit point register and the receive point register includes: the direct distance between the transmit point register and the receive point register, or the sum of the distances between the logic units traversed between the transmit point register and the receive point register and the distances between the transmit point register and the receive point register. Figure 3 A schematic diagram of an illegal path provided for an embodiment of the present invention, such as Figure 3 As shown, for example, if the clock corresponding to the path between the transmitter register and the receiver register is 500MHz, the timing convergence distance between them should be 2000 micrometers. Therefore, when creating the bounding box, it should be created within 2000 micrometers to place the receiver register. Figure 4 for Figure 3 The diagram shows the location of the constraint box for the path shown. Figure 5 Another violation path diagram provided by an embodiment of the present invention shows that the logic unit passing between the transmitter point register and the receiver point register has a total distance from the transmitter point register and the receiver point register that exceeds 2000 micrometers. Similarly, when creating the binding frame, the distance is then created within 2000 micrometers to place the logic unit. Figure 6 for Figure 5 The diagram shows the location of the constraint box for the path shown.

[0107] It is understandable that there may be multiple logical units between the transmit point register and the receive point register, and these different logical units constitute different logical levels. Some of these logical units are lower-level units that must be passed between the transmit point register and the receive point register. When setting the logical unit constraint frame, these units need to be placed within the logical unit constraint frame. Specifically, based on the above embodiment, in this embodiment, placing the target logical unit within the logical unit constraint frame includes: confirming the level name of the target level among the logical units passed between the transmit point register and the receive point register; and placing the logical units with the same level name as the target logical units within the logical unit constraint frame.

[0108] In this embodiment, the underlying logic units are placed within the logic unit constraint frame instead of all logic units, thus reducing the area required within the constraint frame. When actually setting the size of the constraint frame, the size of the unit constraint frame is a first preset multiple of the area of ​​the receiver point register; the size of the logic unit constraint frame is a second preset multiple of the area of ​​the target logic unit; both the first and second preset multiples are greater than or equal to 1.

[0109] After setting the binding box, since the register may still have violations with other paths, after the step of creating the binding box where the distance between the transmitter register and the receiver register is less than the timing convergence distance, the process also includes: determining whether the timing of the target repair path has converged; if not, moving the cell binding box towards the transmitter register with the minimum moving distance and returning to the step of determining whether the timing of the target repair path has converged; if yes, determining that the creation position of the binding box meets the requirements.

[0110] For the path from the transmitter register through the logic unit and the receiver register, setting the position of the logic unit constraint frame may lead to violations between the transmitter register and the logic unit constraint frame, or between the logic unit constraint frame and the receiver register. In this case, the position of the logic unit constraint frame needs to be adjusted to eliminate violations in both directions. Specifically, after the step of creating a constraint frame where the distance between the transmitter register and the receiver register is less than the timing convergence distance, the process includes: determining whether there is a violation between the transmitter register and the logic unit constraint frame, or between the logic unit constraint frame and the receiver register; if so, moving the logic unit constraint frame to the side with more buffers by the minimum moving distance, and returning to the step of determining whether there is a violation between the transmitter register and the logic unit constraint frame, or between the logic unit constraint frame and the receiver register; if not, determining that the creation position of the constraint frame meets the requirements.

[0111] Understandably, the presence of buffers increases the time of the data transmission path, which can cause timing violations. Therefore, after a violation occurs, the logic unit binding box is moved to the side with more buffers to eliminate the violation.

[0112] If violations still exist in the timing path through the logic unit constraint box, the process further includes: determining whether the timing of the path opposite to the timing path of the violation is positive; if positive, moving the logic unit constraint box towards the emitter register by the minimum moving distance; returning to the step of determining whether the timing of the path opposite to the timing path of the violation is positive, until the violation is cleared; if negative, readjusting the layout plan.

[0113] In the above embodiments, the timing violation handling method has been described in detail. This invention also provides embodiments corresponding to the timing violation handling apparatus. It should be noted that this invention describes the apparatus embodiments from two perspectives: one based on functional modules, and the other based on hardware.

[0114] Figure 7 A structural diagram of a timing violation processing device provided in an embodiment of the present invention is shown below. Figure 7 As shown, the timing violation handling device includes:

[0115] The acquisition module 10 is used to acquire the timing path of each timing unit;

[0116] The confirmation module 11 is used to confirm the target repair path from each timing path;

[0117] Processing module 12 is used to obtain the correspondence between the clock size of the target repair path and the distance between the transmit point register and the receive point register, and to determine the timing convergence distance between the transmit point register and the receive point register corresponding to the clock size of the target repair path based on the correspondence; wherein, the distance between the transmit point register and the receive point register includes: the direct distance between the transmit point register and the receive point register, or the sum of the distance between the logic unit passed through between the transmit point register and the receive point register and the distance between the transmit point register and the receive point register;

[0118] Create module 13 to create a bounding box where the distance between the transmitter register and the receiver register is less than the timing convergence distance, based on the timing convergence distance.

[0119] In some embodiments, the creation module includes:

[0120] The first judgment module is used to determine whether the direct distance between the transmit point register and the receive point register exceeds the timing convergence distance; if it does, a cell binding frame is created within the timing convergence distance to place the receive point register; if it does not exceed the distance, the process proceeds to the second judgment module.

[0121] The second judgment module is used to determine whether the sum of the distances between the logic unit passing through the transmitter point register and the receiver point register and the transmitter point register exceeds the timing convergence distance; if so, a logic unit constraint box is created at the point where the sum of the distances does not exceed the timing convergence distance to place the target logic unit.

[0122] In other embodiments, the confirmation module includes:

[0123] The violation value acquisition module is used to acquire the violation value corresponding to each timing unit;

[0124] The sorting module is used to sort the violation values.

[0125] The target timing unit confirmation module is used to confirm the timing unit with the largest violation value as the target timing unit.

[0126] The target repair path confirmation module is used to confirm that the path in the target timing unit is the target repair path.

[0127] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0128] The timing violation handling apparatus provided in this invention addresses the problem in related technologies where resolving timing issues by restricting register positions requires multiple adjustments to the binding box position, resulting in wasted time and effort. This invention sets different timing convergence distances for different clock sizes. After identifying the target repair path, it determines the timing convergence distance between the transmit and receive registers corresponding to the clock size of the target repair path based on the correspondence between clock size and timing convergence distance. A binding box is then created where the distance between the transmit and receive registers is less than the timing convergence distance, thus achieving timing violation handling. This invention eliminates the need for multiple attempts to determine the binding box position; the distance relationship between the binding box and registers for different clock sizes is confirmed using a correspondence table, reducing experimentation and debugging processes, decreasing data processing volume, and improving processing efficiency.

[0129] Figure 8 A structural diagram of another timing violation processing device provided in an embodiment of the present invention is shown below. Figure 8 As shown, the device includes: a memory 20 for storing computer programs;

[0130] The processor 21 is configured to implement the steps of the timing violation handling method as described in the above embodiments when executing a computer program.

[0131] The timing violation processing device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0132] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0133] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the timing violation handling method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, timing convergence distance.

[0134] In some embodiments, the timing violation processing apparatus may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0135] Those skilled in the art will understand that Figure 8 The structure shown does not constitute a limitation on the timing violation handling apparatus and may include more or fewer components than shown.

[0136] The timing violation processing apparatus provided in this embodiment of the invention includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: obtaining the timing path of each timing unit; identifying a target repair path from each timing path; obtaining the correspondence between the clock size of the target repair path and the distance between the transmit point register and the receive point register; determining the timing convergence distance between the transmit point register and the receive point register corresponding to the clock size of the target repair path based on the correspondence; creating a binding box where the distance between the transmit point register and the receive point register is less than the timing convergence distance, according to the timing convergence distance; wherein, the distance between the transmit point register and the receive point register includes: the direct distance between the transmit point register and the receive point register, or the sum of the distances between the logic unit passed through between the transmit point register and the receive point register and the distance between the transmit point register and the receive point register.

[0137] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps described in the above method embodiments.

[0138] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0139] The timing violation handling method, apparatus, and medium provided by this invention have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

[0140] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for handling timing violations, characterized in that, include: Obtain the timing path of each timing unit; The target repair path is identified from each of the aforementioned time-series paths; Obtain the correspondence between the clock size of the target repair path and the distance between the transmit point register and the receive point register, and determine the timing convergence distance between the transmit point register and the receive point register corresponding to the clock size of the target repair path based on the correspondence. Based on the timing convergence distance, a binding box is created where the distance between the transmitter register and the receiver register is less than the timing convergence distance; The constraint frame includes a unit constraint frame and a logic unit constraint frame; The step of creating a binding box where the distance between the transmit point register and the receive point register is less than the timing convergence distance, based on the timing convergence distance, includes: Determine whether the direct distance between the transmit point register and the receive point register exceeds the timing convergence distance; If the direct distance exceeds the timing convergence distance, then the unit constraint box is created within the timing convergence distance to place the receiver point register; it is determined whether the timing of the target repair path has converged; if the timing of the target repair path has not converged, then the unit constraint box is moved towards the transmitter point register by the minimum moving distance, and the process returns to the step of determining whether the timing of the target repair path has converged; if the timing of the target repair path has converged, then it is determined that the creation position of the unit constraint box meets the requirements. If the direct distance does not exceed the timing convergence distance, then determine whether the sum of the distances between the logic unit that the transmitter register and the receiver register pass through and the transmitter register and the receiver register exceeds the timing convergence distance. If the sum of the distances exceeds the timing convergence distance, a logic unit constraint frame is created at a location where the sum of the distances does not exceed the timing convergence distance to place the target logic unit; it is determined whether there are any violations between the emitter register and the logic unit constraint frame, and between the logic unit constraint frame and the receiver register; if at least one segment has a violation, the logic unit constraint frame is moved to the side with more buffers by the minimum moving distance, and the process returns to the step of determining whether there are any violations between the emitter register and the logic unit constraint frame, and between the logic unit constraint frame and the receiver register; if there are no violations, it is determined that the creation position of the logic unit constraint frame meets the requirements.

2. The timing violation handling method according to claim 1, characterized in that, The target repair path is confirmed to include: Obtain the violation value corresponding to each of the aforementioned timing units; Sort the aforementioned violation values; The timing unit with the largest violation value is identified as the target timing unit. The path in the target timing unit is confirmed to be the target repair path.

3. The timing violation handling method according to claim 1, characterized in that, Placing the target logic unit within the logic unit constraint frame includes: Confirm the hierarchical name of the target level in the logic unit between the transmit point register and the receive point register; Place logical units with the same hierarchical name as the target logical unit within the logical unit constraint box.

4. The timing violation handling method according to any one of claims 1 to 3, characterized in that, The size of the unit constraint frame is a first preset multiple of the area of ​​the receiving point register; The size of the logic unit constraint frame is a second preset multiple of the area size of the target logic unit; the values ​​of the first preset multiple and the second preset multiple are both greater than or equal to 1.

5. The timing violation handling method according to claim 1, characterized in that, If a violation still exists in the timing path through the logic unit constraint box, the following is also included: Determine whether the timing of the path opposite to the timing path of the violation is positive; If positive, move the logic unit constraint box toward the emitter register by the minimum moving distance; return to the step of determining whether the timing of the path opposite to the timing path of the violation is positive, until the violation is cleared; If the result is negative, the layout plan will be readjusted.

6. The timing violation handling method according to claim 1, characterized in that, The timing path includes an establishment timing path and a hold timing path; The formula for the time required for data to arrive in the established time path is: ； in, For data arrival time, The time required for the clock source to reach the first register. For the time it takes for data to be transferred in the first register, This is the time required for data to be sent from the first register to the second register; The time required to establish a time path is: ； in, In order to meet the time requirement, For data capture time, For the cycle time, Set the time for the data; The establishment time formula is: ； ； The time required to maintain the time path is: ； ； ； in, To establish a time margin, For data retention time, To maintain a time margin.

7. A timing violation processing device, characterized in that, include: The acquisition module is used to acquire the timing path of each timing unit; The confirmation module is used to confirm the target repair path from each of the aforementioned timing paths; The processing module is used to obtain the correspondence between the clock size of the target repair path and the distance between the transmit point register and the receive point register, and to determine the timing convergence distance between the transmit point register and the receive point register corresponding to the clock size of the target repair path based on the correspondence. A module is created to create a bounding box where the distance between the transmitter register and the receiver register is less than the timing convergence distance, based on the timing convergence distance. The constraint frame includes a unit constraint frame and a logic unit constraint frame; The step of creating a binding box where the distance between the transmit point register and the receive point register is less than the timing convergence distance, based on the timing convergence distance, includes: Determine whether the direct distance between the transmit point register and the receive point register exceeds the timing convergence distance; If the direct distance exceeds the timing convergence distance, then the unit constraint box is created within the timing convergence distance to place the receiver point register; it is determined whether the timing of the target repair path has converged; if the timing of the target repair path has not converged, then the unit constraint box is moved towards the transmitter point register by the minimum moving distance, and the process returns to the step of determining whether the timing of the target repair path has converged; if the timing of the target repair path has converged, then it is determined that the creation position of the unit constraint box meets the requirements. If the direct distance does not exceed the timing convergence distance, then determine whether the sum of the distances between the logic unit that the transmitter register and the receiver register pass through and the transmitter register and the receiver register exceeds the timing convergence distance. If the sum of the distances exceeds the timing convergence distance, a logic unit constraint frame is created at a location where the sum of the distances does not exceed the timing convergence distance to place the target logic unit; it is determined whether there are any violations between the emitter register and the logic unit constraint frame, and between the logic unit constraint frame and the receiver register; if at least one segment has a violation, the logic unit constraint frame is moved to the side with more buffers by the minimum moving distance, and the process returns to the step of determining whether there are any violations between the emitter register and the logic unit constraint frame, and between the logic unit constraint frame and the receiver register; if there are no violations, it is determined that the creation position of the logic unit constraint frame meets the requirements.

8. A timing violation processing device, characterized in that, Includes memory used to store computer programs; A processor, configured to implement the timing violation handling method as described in any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the timing violation handling method as described in any one of claims 1 to 6.

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