Method and device for improving long-term temperature fluctuation resistance of digital circuit

Abstract

The application discloses a method for improving long-term temperature fluctuation resistance of a digital circuit, comprising the following steps: obtaining a first zero-temperature delay point of a first standard cell; performing aging simulation on the first standard cell to obtain aging information of the first standard cell; obtaining a target simulation netlist according to the first zero-temperature delay point and the aging information; obtaining a second zero-temperature delay point according to the target simulation netlist; obtaining a preset subset according to the first zero-temperature delay point and the second zero-temperature delay point; screening the preset subset according to a screening condition to obtain a target subset; inputting the target subset into a target tool to perform re-characterization processing, and obtaining a target library; and inputting the target library into a circuit synthesis tool to obtain a target circuit. The application can make the circuit have aging resistance at a zero-temperature delay point, enhance long-term temperature immunity of the circuit, and can be widely applied to the technical field of digital circuits.

Description

Technical Field

[0001] This invention relates to the field of digital circuit technology, and in particular to a method for improving the long-term resistance of digital circuits to temperature fluctuations. Background Technology

[0002] As transistor sizes continue to shrink, thermal issues in integrated circuits (ICs) become increasingly critical. The shrinking transistor size leads to increased power density, and the use of stacked structures and materials with low thermal conductivity presents challenges in heat dissipation, resulting in localized hot spots and temperature gradients within the chip. Furthermore, IC products may operate at varying temperatures, including self-heating temperatures and ambient temperature variations in different application scenarios. These temperature variations can cause significant performance instability, such as timing and frequency variations in digital circuits. To ensure reliable operation within the expected temperature range, thermally dependent timing guard bands are typically used, but this sacrifices performance. While guard bands can compensate for thermally induced timing variations, performance instability caused by temperature fluctuations still exists. Existing circuit-level temperature fluctuation mitigation design methods use temperature sensors to monitor the temperature on the chip. These sensors can be analog voltage output sensors or digital interface sensors, occupying a certain chip area. The sensor layout is highly dependent on hot spots on the chip, meaning that sensor temperature control is often localized and cannot address global temperature fluctuations. To maximize the temperature control range, the number of sensors also increases, further increasing the chip area. Furthermore, to improve the temperature stability of digital circuits, a design strategy based on Zero Temperature Delay (ZTD) has been developed, utilizing the mutual compensation effect between device mobility and threshold voltage temperature characteristics. The ZTD method aims to find the optimal supply voltage that minimizes the circuit's delay temperature sensitivity along the critical path. However, the effectiveness of the ZTD method can be challenged by aging effects, such as bias temperature instability (BTI). Under the influence of aging effects, ZTD can shift significantly, therefore, relying solely on ZTD cannot provide long-term temperature immunity for the circuit. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a method for improving the long-term resistance to temperature fluctuations of digital circuits, thereby enhancing the long-term temperature immunity of the circuits.

[0004] One aspect of this invention provides a method for improving the long-term temperature fluctuation resistance of digital circuits, the method comprising:

[0005] Obtain the first zero-temperature delay point of the first standard cell;

[0006] Aging simulation is performed on the first standard unit to obtain aging information of the first standard unit;

[0007] Based on the first zero-temperature delay point and the aging information, obtain the target simulation netlist;

[0008] Based on the target simulation netlist, obtain the second zero-temperature delay point;

[0009] A preset subset is obtained based on the first zero-temperature delay point and the second zero-temperature delay point;

[0010] The preset subset is filtered according to the filtering criteria to obtain the target subset;

[0011] The target subset is input into the target tool and re-featured to obtain the target library;

[0012] The target library is input into a circuit synthesis tool to obtain the target circuit.

[0013] Optionally, obtaining the first zero-temperature delay point of the first standard cell includes:

[0014] A delay operation is performed on the first standard unit to obtain various curves of the first standard unit changing with the power supply voltage at various temperatures;

[0015] The intersection of the curves is taken as the first zero-temperature delay point of the first standard unit.

[0016] Optionally, the step of performing aging simulation on the first standard cell to obtain aging information of the first standard cell includes:

[0017] An aging simulation is performed on the first standard unit to obtain the threshold voltage degradation value of each device in the first standard unit at each aging time, thereby obtaining the aging information of the first standard unit.

[0018] Optionally, obtaining the target simulation netlist based on the first zero-temperature delay point and the aging information includes:

[0019] The aging information of the first standard cell is input into the simulation netlist corresponding to the first zero temperature delay point to obtain the target simulation netlist.

[0020] Optionally, obtaining the second zero-temperature delay point based on the target simulation netlist includes:

[0021] Based on the target simulation netlist, SPICE simulation is performed, various aging times are set, and the second zero temperature delay point corresponding to each aging time is obtained.

[0022] Optionally, obtaining a preset subset based on the first zero-temperature delay point and the second zero-temperature delay point includes:

[0023] Obtain the change values ​​at each preset zero-temperature delay point;

[0024] The set of changes in each preset zero-temperature delay point is taken as a preset subset;

[0025] The change values ​​of each preset zero-temperature delay point are:

[0026] ΔV ZTD = V ZTD (aged)- V ZTD (fresh)

[0027] Where, ΔV ZTD V represents the change value at each preset zero-temperature delay point. ZTD (fresh) represents the first zero-temperature delay point, V ZTD (aged) represents the second zero temperature delay point.

[0028] Optionally, the filtering conditions include: a first preset condition and a second preset condition, and the step of filtering the preset subset according to the filtering conditions to obtain the target subset includes:

[0029] Determine whether the change value of each preset zero-temperature delay point is less than the first preset condition;

[0030] When the change value of each preset zero temperature delay point is less than the first preset condition, the second standard unit corresponding to the change value of each preset zero temperature delay point that is less than the first preset condition is obtained, and it is determined whether the number of the second standard units meets the second preset condition.

[0031] The second standard unit that meets the second preset condition is input into the target subset to obtain the third standard unit;

[0032] The first preset condition is a standard value set according to the current circuit design's requirements for temperature immunity.

[0033] The second preset condition is the minimum quantity requirement of the integrated circuit.

[0034] Optionally, the step of inputting the target subset into the target tool for re-featureization processing to obtain the target library includes:

[0035] Obtain the third standard unit in the target subset;

[0036] The third standard unit is input into the target tool, so that the third standard unit is re-characterized in the standard unit library at various temperatures and power supply voltages.

[0037] The target tool is a standard cell library re-featureization tool.

[0038] This invention also provides an apparatus for improving the long-term temperature fluctuation resistance of digital circuits, comprising:

[0039] The first module is used to obtain the first zero-temperature delay point of the first standard unit;

[0040] The second module is used to perform aging simulation on the first standard unit to obtain the aging information of the first standard unit.

[0041] The third module is used to obtain the target simulation netlist based on the first zero-temperature delay point and the aging information;

[0042] The fourth module is used to obtain the second zero-temperature delay point based on the target simulation netlist;

[0043] The fifth module is used to obtain a preset subset based on the first zero-temperature delay point and the second zero-temperature delay point;

[0044] The sixth module is used to filter the preset subset according to the filtering conditions to obtain the target subset;

[0045] The seventh module is used to input the target subset into the target tool, perform re-featureization processing, and obtain the target library;

[0046] The eighth module is used to input the target library into the circuit synthesis tool to obtain the target circuit.

[0047] This invention also provides an electronic device, which includes a processor and a memory; the memory stores a program; the processor executes the program to perform the aforementioned method for improving the long-term temperature fluctuation resistance of digital circuits; the electronic device has the function of carrying and running the business data processing software system provided in this invention, such as a personal computer (PC), mobile phone, smartphone, personal digital assistant (PDA), wearable device, handheld PC (PPC), tablet computer, vehicle terminal, etc.

[0048] This invention also provides a computer-readable storage medium storing a program that is executed by a processor to implement the aforementioned method for improving the long-term resistance to temperature fluctuations of digital circuits.

[0049] This invention also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the aforementioned method for improving the long-term temperature fluctuation resistance of digital circuits.

[0050] An embodiment of the present invention obtains a first zero-temperature delay point of a first standard cell; performs aging simulation on the first standard cell to obtain aging information of the first standard cell; obtains a target simulation netlist based on the first zero-temperature delay point and the aging information; obtains a second zero-temperature delay point based on the target simulation netlist; obtains a preset subset based on the first zero-temperature delay point and the second zero-temperature delay point; filters the preset subset according to filtering conditions to obtain a target subset; inputs the target subset into a target tool for re-characterization processing to obtain a target library; and inputs the target library into a circuit synthesis tool to obtain a target circuit. This embodiment of the present invention enables the circuit to have anti-aging capability at a zero-temperature delay point, enhancing the long-term temperature immunity of the circuit. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A flowchart illustrating the steps involved in improving the long-term temperature fluctuation resistance of digital circuits.

[0053] Figure 2 This is a schematic diagram of the overall process of a method for improving the long-term resistance to temperature fluctuations of digital circuits provided in an embodiment of the present invention;

[0054] Figure 3 This is a schematic diagram of the zero-temperature delay point of the unit. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0056] To improve the temperature stability of digital circuits, a design strategy based on Zero Temperature Delay (ZTD) has been developed, leveraging the mutual compensation effect between device mobility and threshold voltage temperature characteristics. The ZTD method aims to find the optimal supply voltage that minimizes the circuit's delay temperature sensitivity along the critical path. However, the effectiveness of the ZTD method can be challenged by aging effects, such as bias temperature instability (BTI). Under the influence of aging effects, ZTD can shift significantly, therefore relying solely on ZTD cannot provide long-term temperature immunity to the circuit.

[0057] In response to the problems existing in the current technology, such as Figure 1 as well as Figure 2 As shown, the present invention provides a method for improving the long-term temperature fluctuation resistance of digital circuits, the method specifically including but not limited to steps S100-S800:

[0058] S100, Obtain the first zero-temperature delay point of the first standard unit;

[0059] Specifically, using circuit simulation tools, transient simulations are performed on all standard cells in the standard cell library to obtain the first zero-temperature delay point of the standard cell. The first zero-temperature delay point is the zero-temperature delay point of the standard cell before it ages.

[0060] S200. Perform aging simulation on the first standard cell to obtain the aging information of the first standard cell;

[0061] Specifically, the HSPICE circuit simulator containing the device BTI aging model is used to perform aging simulation on the standard cell. The voltage information of each device in the circuit cell is collected by the HSPICE simulator, and the voltage information is converted into the threshold voltage degradation value of the device in the cell using the BTI aging model. The threshold voltage degradation value is then updated to the model card and called by the simulator to complete the aging simulation.

[0062] S300. Based on the first zero-temperature delay point and aging information, obtain the target simulation netlist.

[0063] S400. Based on the target simulation netlist, obtain the second zero-temperature delay point.

[0064] S500: Obtain a preset subset based on the first zero-temperature delay point and the second zero-temperature delay point.

[0065] S600. Based on the filtering criteria, the preset subset is filtered to obtain the target subset;

[0066] Specifically, the screening conditions include: a first preset condition and a second preset condition. The first preset condition is a standard value set according to the temperature immunity effect requirements of the current circuit design. The second preset condition is the minimum number of units required for the integrated circuit. In different application scenarios, the required chip operating temperature range varies. The typical temperature range for industrial chips is -40℃ to 125℃, while military and aerospace applications require a wider temperature range of -50℃ to 150℃, meaning the requirement for temperature immunity is more stringent. Therefore, based on the screening conditions, various target circuits suitable for different application scenarios can be designed. The minimum number of units required for the integrated circuit, i.e., the minimum number of units in the integrated circuit, depends on the complexity of the logic circuit, the constraints, and the selected synthesis algorithm. The circuit can be synthesized using synthesis tools starting with a few typical units such as AND gates and NOT gates to test whether a circuit that meets the requirements can be synthesized with a certain number of units. If a circuit that meets the requirements can be synthesized, then that certain number of units is the minimum number of units required for the integrated circuit.

[0067] S700. Input the target subset into the target tool and perform re-featureization processing to obtain the target library.

[0068] S800: Input the target library into the circuit synthesis tool to obtain the target circuit;

[0069] Specifically, the target library obtained by re-characterization at room temperature is input into the circuit synthesis tool, and a new circuit is synthesized by the circuit synthesis tool to obtain a target circuit with enhanced temperature immunity.

[0070] Optionally, in some embodiments, step S100 specifically includes the following steps:

[0071] S101. Perform a delay operation on the first standard unit to obtain various curves of the first standard unit changing with the power supply voltage at various temperatures.

[0072] S102. The intersection of the curves is taken as the first zero-temperature delay point of the first standard unit;

[0073] Specifically, refer to Figure 3 The propagation delay of the inverter circuit decreases as the power supply voltage increases. At different temperatures, the curves corresponding to each delay value intersect at a certain power supply voltage. This intersection point is taken as the first zero-temperature delay point. To the left of the intersection point, the propagation delay of the circuit decreases as the temperature increases; to the right of the intersection point, the propagation delay of the circuit increases as the temperature increases.

[0074] Among them, such as Figure 3 As shown, t p The value represents the propagation delay of the circuit, where T represents temperature and V represents temperature. DD Represents the power supply voltage, VZTD This is the zero-temperature delay point; additionally, Figure 3 The circuit shown is an inverter, a basic unit structure in digital circuit design. V in Indicates circuit input, V out Indicates the circuit output, C m C represents the coupling capacitance between the input and output ports. l Indicates the load capacitance; when V in When it is high, V out When V is low level in When it is low, V out The input level is high, therefore the circuit function is to invert the input.

[0075] Optionally, in some embodiments, step S200 specifically includes the following steps:

[0076] S201. Perform aging simulation on the first standard unit to obtain the threshold voltage degradation value of each device in the first standard unit at each aging time, and obtain the aging information of the first standard unit.

[0077] Specifically, through aging simulation, the threshold voltage degradation value of each device in the standard cell at each aging time can be obtained. For example, taking the threshold voltage of the device as an example, for an inverter, the degradation value of NMOS after the first set aging time can be obtained through aging simulation: ΔVth1. Similarly, the degradation value of PMOS after the first set aging time can be obtained through aging simulation: ΔVth2. Then ΔVth1 and ΔVth2 are the aging information of the cell corresponding to the inverter.

[0078] NMOS is a metal-oxide-semiconductor field-effect transistor with an N-type channel, and the charge carrier is electron; PMOS refers to a metal-oxide-semiconductor field-effect transistor with a P-type channel, and the charge carrier is hole.

[0079] Optionally, in some embodiments, step S300 specifically includes the following steps:

[0080] S301. Input the aging information of the first standard cell into the simulation netlist corresponding to the first zero temperature delay point to obtain the target simulation netlist.

[0081] Specifically, the aging status (ΔVthx, x = 1, 2, 3, ..., n) of each device in the standard cell is written into the simulation netlist corresponding to the first zero-temperature delay point to obtain the aging simulation netlist corresponding to the first zero-temperature delay point, i.e., the target simulation netlist. For example, for the inverter INV, the aging information of the NMOS device is ΔVth1, and the aging information of the PMOS device is ΔVth2. In the simulation netlist corresponding to the first zero-temperature delay point, ΔVth1 and ΔVth2 are written into the device model card used by the simulation netlist respectively.

[0082] The netlist is a SPICE netlist, which is a transistor-level circuit simulation file in .sp format.

[0083] Optionally, in some embodiments, step S400 specifically includes the following steps:

[0084] S401. Perform SPICE simulation based on the target simulation netlist, set each aging time, and obtain the second zero temperature delay point corresponding to each aging time.

[0085] Specifically, SPICE simulation is performed on the target simulation netlist. Based on different aging times, the zero-temperature delay point after aging, i.e., the second zero-temperature delay point, can be obtained for different aging times; for example, when t age When the temperature is 0, the standard element is not aged. By performing SPICE simulation on the target simulation netlist, the zero-temperature delay point of the standard element before aging can be obtained; the aging time is set to 10. 6 seconds, that is, when t age =10 6 At a given time, by performing SPICE simulation on the target simulation netlist, the zero-temperature delay point of the standard element after aging can be obtained after the set aging time.

[0086] SPICE (Simulation Program with Integrated Circuit Emphasis) is a powerful general-purpose circuit simulator developed in 1975 by the Research Laboratory of Electronics at the University of California, Berkeley. Initially, it was mainly used to verify circuit designs in integrated circuits and predict circuit performance. Now, SPICE models are widely used in electronic design and can perform nonlinear DC analysis, nonlinear transient analysis, and linear AC analysis on circuits.

[0087] Optionally, in some embodiments, step S500 specifically includes the following steps:

[0088] S501. Obtain the change values ​​of each preset zero-temperature delay point;

[0089] Specifically, the change values ​​of each preset zero-temperature delay point are:

[0090] ΔV ZTD = V ZTD (aged)- V ZTD (fresh)

[0091] Where, ΔV ZTD V represents the change value at each preset zero-temperature delay point. ZTD (fresh) represents the first zero-temperature delay point, V ZTD (aged) represents the second zero temperature delay point.

[0092] S502, take the set of change values ​​of each preset zero temperature delay point as a preset subset.

[0093] Optionally, in some embodiments, step S600 specifically includes the following steps:

[0094] S601. Determine whether the change value of each preset zero temperature delay point is less than the first preset condition;

[0095] Specifically, the first preset condition is a standard value set according to the temperature immunity effect requirements of the current circuit design. The standard value can be a single value or multiple values, such as 0.01V, 0.02V, and 0.03V. Therefore, when 0.01V is set as the standard value, the first preset condition ΔV is established. ZTD <0.01V; When setting 0.01V, 0.02V, and 0.03V as standard values, there are corresponding first preset conditions of ΔV. ZTD <0.01V, ΔV ZTD <0.02V and ΔV ZTD If the value is less than 0.03V, the judgment results are obtained according to the corresponding first preset conditions.

[0096] S602. When the change value of each preset zero temperature delay point is less than the first preset condition, obtain the second standard unit corresponding to the change value of each preset zero temperature delay point that is less than the first preset condition, and determine whether the number of the second standard units meets the second preset condition.

[0097] Specifically, the second preset condition is the minimum number requirement of the integrated circuit. Among them, the smaller the variation value of each preset zero-temperature delay point of a unit before and after aging, the better; the smaller the selected standard value, the better the immunity to temperature fluctuations. Therefore, when the number of all second standard units meets the minimum number requirement of the integrated circuit, selecting the smallest standard value is optimal. For example, there are x second standard units whose variation values of preset zero-temperature delay points are less than the standard value of 0.01V, there are y second standard units whose variation values of preset zero-temperature delay points are less than the standard value of 0.02V, there are z second standard units whose variation values of preset zero-temperature delay points are less than the standard value of 0.03V, and the minimum number requirement of the integrated circuit is k; if k<x<y<z, the second standard units corresponding to the variation values of preset zero-temperature delay points less than the standard value of 0.01V, 0.02V or 0.03V can be selected; if x<k<y<z, the second standard units corresponding to the variation values of preset zero-temperature delay points less than the standard value of 0.02V or 0.03V are selected, and so on.

[0098] S603, inputting the second standard units that satisfy the second preset condition into the target subset to obtain third standard units.

[0099] Optionally, in some embodiments, said step S700 specifically includes the following steps:

[0100] S701, acquiring the third standard units in the target subset.

[0101] S702, inputting said third standard units into a target tool, and performing re-characterization of the standard cell library on said third standard units at various temperatures and various power supply voltages;

[0102] Specifically, said target tool is a standard cell library re-characterization tool, and said various temperatures include normal temperature (25°C) and extreme temperatures (e.g., -30°C, 120°C, etc.). Among them, performing re-characterization of the standard cell library at extreme temperatures can be used for subsequent timing analysis to determine whether the delay fluctuation of the new circuit within a wide temperature range has been reduced;

[0103] Wherein, standard cell library re-characterization tools include Siliconsmart, liberty, encounter, etc.; the standard cell library re-characterization tool can re-extract the characteristic information of the standard cell timing library of standard cells under specified conditions, including power consumption, delay, area, function, pin attributes, etc. Said specified conditions include but are not limited to special working environments such as high temperature and high voltage.

[0104] An embodiment of the present invention also provides an apparatus for improving the long-term resistance to temperature fluctuation of digital circuits, comprising:

[0105] The first module is used to obtain the first zero-temperature delay point of the first standard unit;

[0106] The second module is used to perform aging simulation on the first standard unit to obtain the aging information of the first standard unit.

[0107] The third module is used to obtain the target simulation netlist based on the first zero-temperature delay point and the aging information;

[0108] The fourth module is used to obtain the second zero-temperature delay point based on the target simulation netlist;

[0109] The fifth module is used to obtain a preset subset based on the first zero-temperature delay point and the second zero-temperature delay point;

[0110] The sixth module is used to filter the preset subset according to the filtering conditions to obtain the target subset;

[0111] The seventh module is used to input the target subset into the target tool, perform re-featureization processing, and obtain the target library;

[0112] The eighth module is used to input the target library into the circuit synthesis tool to obtain the target circuit.

[0113] This invention also provides an electronic device, which includes a processor and a memory; the memory stores a program; the processor executes the program to perform the aforementioned method for improving the long-term temperature fluctuation resistance of digital circuits; the electronic device has the function of carrying and running the business data processing software system provided in this invention, such as a personal computer (PC), mobile phone, smartphone, personal digital assistant (PDA), wearable device, handheld PC (PPC), tablet computer, vehicle terminal, etc.

[0114] This invention also provides a computer-readable storage medium storing a program that is executed by a processor to implement the aforementioned method for improving the long-term resistance to temperature fluctuations of digital circuits.

[0115] This invention also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the aforementioned method for improving the long-term temperature fluctuation resistance of digital circuits.

[0116] In summary, the method for improving the long-term temperature fluctuation resistance of digital circuits according to embodiments of the present invention has the following advantages:

[0117] 1. This invention improves the circuit's immunity to temperature fluctuations by setting standard values ​​based on the current circuit design's requirements for temperature immunity and selecting standard units based on the minimum quantity requirements of the integrated circuit.

[0118] 2. This invention selects standard units by setting standard values ​​based on the current circuit design's requirements for temperature immunity, which can design various target circuits suitable for different application scenarios. The method of this invention can be widely applied to circuit design in various application scenarios to meet the requirements of different circuit chip operating temperature ranges.

[0119] 3. This invention extracts a subset of standard cells from a standard cell library that exhibit minimal changes in the zero-temperature delay point before and after aging. The aged subset is then used to synthesize a new circuit. A cell library featureization tool is used for re-featureization to obtain a standard cell subset library under different conditions. This allows the circuit to achieve good temperature immunity not only under normal conditions but also under aging conditions, thus possessing anti-aging capabilities at the zero-temperature delay point and enhancing the circuit's long-term resistance to temperature fluctuations.

[0120] 4. The principle of this invention is simple, easy to implement, highly versatile, and low in cost. It does not require increasing the chip area or power consumption, has no additional area consumption, and has high robustness in temperature immunity.

[0121] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0122] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the described functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0123] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0124] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0125] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0126] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0127] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0128] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0129] The above is a detailed description of the preferred embodiments of the present invention, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A method for improving the long-term resistance to temperature fluctuations of digital circuits, characterized in that, include: Obtain the first zero-temperature delay point of the first standard cell; Aging simulation is performed on the first standard unit to obtain aging information of the first standard unit; Based on the first zero-temperature delay point and the aging information, obtain the target simulation netlist; Based on the target simulation netlist, obtain the second zero-temperature delay point; Based on the first zero-temperature delay point and the second zero-temperature delay point, a preset subset is obtained, including: Obtain the change value at each preset zero-temperature delay point; take the set of change values ​​at each preset zero-temperature delay point as a preset subset; the change value at each preset zero-temperature delay point is: ΔV ZTD = V ZTD (aged)- V ZTD (fresh); where ΔV ZTD V represents the change value at each preset zero-temperature delay point. ZTD (fresh) represents the first zero-temperature delay point, V ZTD (aged) represents the second zero temperature delay point; The preset subset is filtered according to the filtering criteria to obtain the target subset, including: Determine whether the change value of each preset zero-temperature delay point is less than a first preset condition; when the change value of each preset zero-temperature delay point is less than the first preset condition, obtain the second standard unit corresponding to the change value of each preset zero-temperature delay point that is less than the first preset condition, and determine whether the number of the second standard units meets the second preset condition; input the second standard units that meet the second preset condition into the target subset to obtain the third standard unit; the first preset condition is a standard value set according to the temperature immunity effect requirements of the current circuit design; the second preset condition is the minimum quantity requirement of the integrated circuit; the screening conditions include the first preset condition and the second preset condition; The target subset is input into the target tool and re-featured to obtain the target library; The target library is input into a circuit synthesis tool to obtain the target circuit.

2. The method for improving the long-term resistance to temperature fluctuations of digital circuits according to claim 1, characterized in that, The process of obtaining the first zero-temperature delay point of the first standard unit includes: A delay operation is performed on the first standard unit to obtain various curves of the first standard unit changing with the power supply voltage at various temperatures; The intersection of the curves is taken as the first zero-temperature delay point of the first standard unit.

3. The method for improving the long-term resistance to temperature fluctuations of digital circuits according to claim 1, characterized in that, The step of performing aging simulation on the first standard unit to obtain aging information of the first standard unit includes: An aging simulation is performed on the first standard unit to obtain the threshold voltage degradation value of each device in the first standard unit at each aging time, thereby obtaining the aging information of the first standard unit.

4. The method for improving the long-term resistance to temperature fluctuations of digital circuits according to claim 1, characterized in that, The step of obtaining the target simulation netlist based on the first zero-temperature delay point and the aging information includes: The aging information of the first standard cell is input into the simulation netlist corresponding to the first zero temperature delay point to obtain the target simulation netlist.

5. The method for improving the long-term resistance to temperature fluctuations of digital circuits according to claim 1, characterized in that, The step of obtaining the second zero-temperature delay point based on the target simulation netlist includes: Based on the target simulation netlist, SPICE simulation is performed, various aging times are set, and the second zero temperature delay point corresponding to each aging time is obtained.

6. The method for improving the long-term resistance to temperature fluctuations of digital circuits according to claim 1, characterized in that, The step of inputting the target subset into the target tool and performing re-featureization processing to obtain the target library includes: Obtain the third standard unit in the target subset; The third standard unit is input into the target tool, so that the third standard unit is re-characterized in the standard unit library at various temperatures and power supply voltages. The target tool is a standard cell library re-featureization tool.

7. An apparatus for improving the long-term resistance to temperature fluctuations of digital circuits, used to implement the method as described in any one of claims 1 to 6, characterized in that, include: The first module is used to obtain the first zero-temperature delay point of the first standard unit; The second module is used to perform aging simulation on the first standard unit to obtain the aging information of the first standard unit. The third module is used to obtain the target simulation netlist based on the first zero-temperature delay point and the aging information; The fourth module is used to obtain the second zero-temperature delay point based on the target simulation netlist; The fifth module is used to obtain a preset subset based on the first zero-temperature delay point and the second zero-temperature delay point; The sixth module is used to filter the preset subset according to the filtering conditions to obtain the target subset; The seventh module is used to input the target subset into the target tool, perform re-featureization processing, and obtain the target library; The eighth module is used to input the target library into the circuit synthesis tool to obtain the target circuit.

8. An electronic device, characterized in that, Including the processor and memory; The memory is used to store programs; The processor executes the program to implement the method as described in any one of claims 1 to 6.

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