A method, device and medium for constructing a clock tree based on an improved structure algorithm

Abstract

A method, device and medium for constructing a clock tree based on an improved structure algorithm, comprising: step 1, generating a lookup table according to chip parameters and design constraints; step 2, sampling the attributes of each line segment in the lookup table; step 3, splicing the line segments in the lookup table, and generating a standard tree by dynamic programming; step 4, judging whether the standard tree meets the constraints, if yes, clustering the clock tree nodes from top to bottom, moving the buffers in the standard tree to the cluster center, and entering step 5, otherwise, backtracking one layer, reducing the width, and returning to step 3; and step 5, inserting the buffers for correcting the violations symmetrically at the branch nodes from bottom to top. The improved structure algorithm is used to optimize the total delay and clock skew, so that the running time is reduced, and the chip layout with a large number of nodes and complex structure is suitable. Moreover, the tree is built with a smaller width interval only when the tree building fails, so that the tree building speed is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of clock trees, and more specifically, the embodiments of the present invention relate to a method, apparatus and medium for constructing clock trees based on an improved structural algorithm. Background Technology

[0002] The construction of a clock tree with an upper-level structure is divided into two stages. The first stage requires generating a low-clock-skew and highly robust upper-level clock network topology based on design constraints such as chip layout, maximum capacitance, and maximum transition time input by the user. This transforms the large-scale, complex original layout into multiple simpler layouts with fewer triggers. The second stage involves routing in sub-regions based on the topology of the first stage, which is a traditional clock tree construction process.

[0003] The clock network topology built in the first phase is called the top-level structure of the clock tree, which includes branch nodes, buffer nodes, and leaf nodes (tap points) of the top-level structure.

[0004] Existing technologies can implement three topology establishment algorithms for the first stage of functionality:

[0005] The first type is the H-tree structure. This method can theoretically guarantee zero clock skew. However, this topology has a large winding length, resulting in a large maximum delay; and it is greatly affected by chip layout, resulting in low routing flexibility.

[0006] The second type is the fishbone tree structure. This method has a shorter line length than the H-shaped tree structure, reducing maximum latency, power consumption, and area. However, because the distances to the leaf nodes of different groups from the center point are different, the clock skew cannot be equal to 0.

[0007] The third type is the general-purpose H-tree structure. This method combines the first two structures, making the H-tree structure widely applicable to most chip layouts with relatively uniform leaf node distribution. It offers better latency, power consumption, and area compared to the traditional H-tree structure, and its clock skew is smaller than that of the fishbone structure. However, the method described in the original paper is time-consuming to construct, consumes a lot of memory, and has a relatively long trace length when applied to complex chip layouts in practice.

[0008] The above solution has the following drawbacks:

[0009] The H-shaped tree structure can only expand in two branches, while the fishbone structure has only two layers. Faced with complex chip layouts, the former has a longer winding length, resulting in higher power consumption and longer latency; while the latter has more branch nodes on the same layer, resulting in greater clock skew.

[0010] The general-purpose H-tree structure balances the latency and clock skew of the previous two methods, but the generated lookup table is large, and the complexity of building a standard clock tree is high, resulting in excessive runtime and memory consumption, making it difficult to apply in VLSI design. The leaf node positions and the number of branches at each level are automatically generated by the algorithm, lacking flexibility and failing to effectively utilize user-provided information for heuristic construction. It is not optimized for netlists containing logic gates; if downstream nodes of logic gates are assigned to different leaf nodes in the top-level structure, it will affect the correctness of the function. When there are more than two branch nodes, tap points will appear in networks with a large fan-out number, leading to increased latency. The unfolding method is not adjusted according to the chip layout, only allowing horizontal unfolding, which will lead to an increase in the number of layers and greater clock skew in vertical layouts. Summary of the Invention

[0011] In this context, embodiments of the present invention aim to provide a method, apparatus, and medium for constructing a clock tree based on an improved structural algorithm.

[0012] In a first aspect of the present invention, a method for constructing a clock tree based on an improved structural algorithm is provided, comprising:

[0013] Step 1: Generate a lookup table based on chip parameters and design constraints;

[0014] Step 2: Sample the attributes of each line segment in the lookup table;

[0015] Step 3: Concatenate the line segments in the lookup table and generate a standard tree using dynamic programming;

[0016] Step 4: Determine whether the standard tree meets the constraints. If it does, cluster the clock tree nodes from top to bottom, move the buffer in the standard tree towards the cluster center, and proceed to Step 5. Otherwise, backtrack one level, reduce the width, and return to Step 3.

[0017] Step 5: Insert buffers to correct violations symmetrically at the branch nodes from bottom to top.

[0018] In one embodiment of this implementation, step 1, generating a lookup table based on chip parameters and design constraints, includes:

[0019] Calculate the length of the lookup table, the range of output capacitance and input conversion rate, and the interval based on the chip layout and capacitance and conversion rate parameters.

[0020] For each [length, output capacitance, input slew rate] triplet, calculate the delay, area, input capacitance, and output slew rate for all buffer insertion schemes, and sample the input capacitance and output slew rate according to the interval calculated in the previous step;

[0021] For each [length, output capacitance, output conversion rate, input capacitance] quadruple, the worse segments are deleted with a delay.

[0022] In one embodiment of this implementation, line segments in the splicing lookup table are provided, and a standard tree is generated through dynamic programming, including:

[0023] The connection direction between the clock source and the root node of the upper tree is determined based on the length and width of the input layout.

[0024] The general H-tree algorithm is used to generate solutions for each level from bottom to top, and then to build a standard clock tree from top to bottom level by level.

[0025] In one embodiment of this implementation, the method of determining the connection direction between the clock source and the upper-level tree root node based on the length and width of the input layout includes:

[0026] If the length of the input layout is greater than or equal to its width, the top layer of the upper-level tree will expand horizontally; otherwise, the root node of the upper-level tree will expand vertically.

[0027] In one embodiment of this implementation, the method of first generating solutions for each layer from bottom to top using a general H-tree algorithm, and then constructing a standard clock tree from top to bottom, includes:

[0028] First, construct a structure with depth P. During dynamic programming, the width range is from twice the minimum length of the lookup table to the width of the chip layout, the width interval is twice the length of the lookup table, the height range is from the specified minimum height to the width of the chip layout, and the interval is the specified minimum interval.

[0029] For each [width and height], it is necessary to traverse all possibilities of [number of nodes and branches], generate the corresponding line segment, prune it, and store it in the solution container;

[0030] Then, using the solution at depth P as a subtree, construct a tree at depth P-1. If the target tree cannot be constructed, backtrack to depth P, reduce the dynamic programming interval, and regenerate the solution until the depth reaches the set upper limit.

[0031] In one embodiment of this implementation, a method for constructing a clock tree based on an improved structural algorithm further includes: manually specifying the distribution or specific location of tap points and controlling the number of branches through corresponding instructions.

[0032] In one embodiment of this implementation, the method of manually specifying the distribution or specific location of tap points and controlling the number of branches through corresponding instructions includes:

[0033] Based on the {row, column} values ​​given by the user, obtain the sequence of branches that satisfy the rxc distribution for the tap point;

[0034] The coordinates of the tap point are determined based on whether the final coordinates of the tap point specified by the user are a specific point or a range of coordinates.

[0035] Specify whether the number of branches at the lowest level is 2;

[0036] Specify that the number of branches for all layers is 2.

[0037] In one embodiment of this implementation, a method for constructing a clock tree based on an improved structural algorithm further includes: adjusting the position of the internal nodes of the clock tree from top to bottom through clustering.

[0038] In one embodiment of this implementation, the top-down adjustment of the position of nodes within the clock tree through clustering includes:

[0039] When a buffer that is directly connected between different layers violates the design constraints, a buffer to correct the violation is symmetrically inserted at a suitable branch node in the middle.

[0040] When a tap point directly connects to the next tap point and a leaf node within its own cluster, the network with a large number of fan-out nodes will be split.

[0041] When the tap point is directly connected to the root node of the clock tree, the buffer is inserted at the branch node between the tap point and the root node.

[0042] In a second aspect of the present invention, an apparatus for constructing a clock tree based on an improved structural algorithm is provided, comprising:

[0043] The table generation module is used to generate lookup tables based on chip parameters and design constraints.

[0044] The sampling module is used to sample the attributes of each line segment in the lookup table;

[0045] The dynamic programming module is used to concatenate line segments in the lookup table and generate a standard tree using dynamic programming.

[0046] The judgment module is used to determine whether the standard tree meets the constraints. If it does, the clock tree nodes are clustered from top to bottom, and the buffer in the standard tree is moved towards the cluster center. Otherwise, it backtracks one layer, reduces the width, and sends the data after the width reduction to the sampling module.

[0047] Insertion module, used to insert buffers that correct violations symmetrically at branch nodes from bottom to top.

[0048] In one embodiment of this implementation, the table generation module is specifically used for:

[0049] Calculate the length of the lookup table, the range of output capacitance and input conversion rate, and the interval based on the chip layout and capacitance and conversion rate parameters.

[0050] For each [length, output capacitance, input slew rate] triplet, calculate the delay, area, input capacitance, and output slew rate for all buffer insertion schemes, and sample the input capacitance and output slew rate according to the interval calculated in the previous step;

[0051] For each [length, output capacitance, output conversion rate, input capacitance] quadruple, the worse segments are deleted with a delay.

[0052] In one embodiment of this implementation, the dynamic programming module includes:

[0053] The direction determination submodule is used to determine the connection direction between the clock source and the upper-level tree root node based on the length and width of the input layout.

[0054] The sub-modules are built level by level to generate the solution for each level from bottom to top using a general H-tree algorithm, and then build the standard clock tree from top to bottom.

[0055] In one embodiment of this implementation, the direction determination submodule is specifically used for:

[0056] If the length of the input layout is greater than or equal to its width, the connection direction of the upper-level root node is horizontal expansion; otherwise, the connection direction of the upper-level root node is vertical expansion.

[0057] In one embodiment of this implementation, the hierarchical construction submodule is specifically used for:

[0058] First, construct a structure with depth P. During dynamic programming, the width range is from twice the minimum length of the lookup table to the width of the chip layout, the width interval is twice the length of the lookup table, the height range is from the specified minimum height to the width of the chip layout, and the interval is the specified minimum interval.

[0059] For each [width and height], it is necessary to traverse all possibilities of [number of nodes and branches], generate the corresponding line segment, prune it, and store it in the solution container;

[0060] Then, using the solution at depth P as a subtree, construct a tree at depth P-1. If the target tree cannot be constructed, backtrack to depth P, reduce the dynamic programming interval, and regenerate the solution until the depth reaches the set upper limit.

[0061] In one embodiment of this implementation, an apparatus for constructing a clock tree based on an improved structural algorithm further includes: an instruction control module, used to manually specify the distribution or specific location of tap points and control the number of branches through corresponding instructions.

[0062] In one embodiment of this implementation, the instruction control module is specifically used for:

[0063] Based on the {row, column} values ​​given by the user, obtain the sequence of branches that satisfy the rxc distribution for the tap point;

[0064] The coordinates of the tap point are determined based on whether the final coordinates of the tap point specified by the user are a specific point or a range of coordinates.

[0065] Specify whether the number of branches at the lowest level is 2;

[0066] Specify that the number of branches for all layers is 2.

[0067] In one embodiment of this implementation, an apparatus for constructing a clock tree based on an improved structural algorithm further includes: an adjustment module for adjusting the position of internal nodes of the clock tree from top to bottom through clustering.

[0068] In one embodiment of this implementation, the adjustment module is specifically used for:

[0069] When a buffer that is directly connected between different layers violates the design constraints, a buffer to correct the violation is symmetrically inserted at a suitable branch node in the middle.

[0070] When a tap point directly connects to the next tap point and a leaf node within its own cluster, the network with a large number of fan-out nodes will be split.

[0071] When the tap point is directly connected to the root node of the clock tree, the buffer is inserted at the branch node between the tap point and the root node.

[0072] In a third aspect of the present invention, a computing device is provided, the computing device comprising: at least one processor, a memory, and an input / output unit; wherein the memory is used to store a computer program, and the processor is used to invoke the computer program stored in the memory to execute a method for constructing a clock tree based on an improved structural algorithm as described in any one aspect of the first aspect.

[0073] In a fourth aspect of the present invention, a computer-readable storage medium is provided, comprising instructions which, when executed on a computer, cause the computer to perform a method for constructing a clock tree based on an improved structural algorithm as described in any of the first aspects.

[0074] (1) According to an embodiment of the present invention, a method, apparatus and medium for constructing a clock tree based on an improved structure algorithm are provided. The improved structure algorithm of the present invention has a reduced running time compared with the original algorithm and is applicable to chip layouts with a large number of nodes and complex structures. The backtracking operation when establishing a standard tree structure ensures that a tree structure with key indicators can be established even when using a larger width interval during dynamic programming. Backtracking to the bottom layer is only performed when tree construction fails, and a smaller width interval is used to build the tree, which further accelerates the tree construction speed.

[0075] (2) The present invention allows users to specify the node distribution or coordinates of the upper structure, as well as the number of branch factors, which increases the adaptability of the tree structure to complex chip layouts, so as to obtain results with lower maximum latency and smaller clock skew compared to automatic planning indicators, and is more flexible than the prior art.

[0076] (3) Compared with existing algorithms, the algorithm in this invention adjusts the underlying branch structure. In order to avoid the situation where the tap point is directly connected to the next tap point and the fan-out number caused by its own leaf node is too large, the clock network is appropriately split, so that the total delay and clock skew are reduced. Attached Figure Description

[0077] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein:

[0078] Figure 1 A flowchart illustrating a method for constructing a clock tree based on an improved structural algorithm, as provided in an embodiment of the present invention;

[0079] Figure 2 A flowchart of an improved H-shaped structure algorithm provided in an embodiment of the present invention;

[0080] Figure 3 The flowchart illustrates the construction of a lookup table according to an embodiment of the present invention.

[0081] Figure 4 This is a standard tree structure construction process provided in an embodiment of the present invention;

[0082] Figure 5 This is a flowchart of a clustering-based node position adjustment method provided in an embodiment of the present invention.

[0083] Figure 6 A schematic diagram of the structure of a medium according to an embodiment of the present invention is shown.

[0084] Figure 7 A schematic diagram of the structure of a computing device according to an embodiment of the present invention is shown.

[0085] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0086] The principles and spirit of the invention will now be described with reference to several exemplary embodiments. It should be understood that these embodiments are given merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way. Rather, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0087] Those skilled in the art will recognize that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, this disclosure can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0088] According to an embodiment of the present invention, a method, apparatus and medium for constructing a clock tree based on an improved structural algorithm are proposed.

[0089] It should be noted that the number of any elements in the accompanying drawings is for illustrative purposes only and not as a limitation, and any naming is for distinction only and has no limiting meaning.

[0090] The principles and spirit of the present invention will be explained in detail below with reference to several representative embodiments.

[0091] Exemplary methods

[0092] The following is for reference. Figure 1 , Figure 1 This is a flowchart illustrating a method for constructing a clock tree based on an improved structural algorithm, as provided in one embodiment of the present invention. It should be noted that the embodiments of the present invention can be applied to any applicable scenario.

[0093] The improved H-type structure algorithm proposed in the patent can solve the above problems by constructing a clock tree. The new algorithm consists of four steps: First, based on the chip parameters input by the user and design constraints, the algorithm calculates the input and output attributes of line segments of different lengths after sampling at certain intervals, prunes the branches, and generates a lookup table to reduce the running time of the algorithm for constructing the standard tree structure. Second, the algorithm traverses reasonable widths, heights, leaf node regions, and branch factors to generate a standard tree structure from bottom to top through dynamic programming. Third, from top to bottom, the algorithm clusters leaf nodes according to the number of branch factors in each level of the tree structure, moves the buffers towards the cluster center, and reduces the clock skew from each leaf node in the cluster to its connected buffer.

[0094] Figure 1 The flowchart shown in this embodiment of the present invention provides a method, apparatus, and medium for constructing a clock tree based on an improved structural algorithm, including:

[0095] Step 1: Generate a lookup table based on chip parameters and design constraints;

[0096] Step 2: Sample the attributes of each line segment in the lookup table;

[0097] Step 3: Concatenate the line segments in the lookup table and generate a standard tree using dynamic programming;

[0098] Step 4: Determine whether the standard tree meets the constraints. If it does, cluster the clock tree nodes from top to bottom, move the buffer in the standard tree towards the cluster center, and proceed to Step 5. Otherwise, backtrack one level, reduce the width, and return to Step 3.

[0099] Step 5: Insert buffers to correct violations symmetrically at the branch nodes from bottom to top.

[0100] In another embodiment of the present invention, in order to accurately generate a lookup table based on chip parameters and design constraints, such as... Figure 3 As shown, step 1 above is replaced by steps 101 to 103:

[0101] Perform steps 101 to 103 as described above.

[0102] Step 101: Calculate the length of the lookup table, the range of output capacitance and input conversion rate, and the interval based on the chip layout and capacitance and conversion rate parameters;

[0103] Step 102: Calculate the delay, area, input capacitance, and output conversion rate for all buffer insertion schemes corresponding to each [length, output capacitance, input conversion rate] triplet, and sample the input capacitance and output conversion rate according to the interval calculated in the previous step;

[0104] Step 103: For each [length, output capacitor, output conversion rate, input capacitor] quadruple, delete the worse segments according to the delay.

[0105] The specific implementation process of steps 101 to 103 is as follows:

[0106] The lookup table stores pre-generated candidate wires that are pruned based on metrics such as area and latency when building the top-level structure. The purpose is to avoid repeatedly generating wires during the tree-building phase and to ensure that all possible wires are considered during pruning to find the globally optimal result.

[0107] To create the lookup table, the user first needs to input the chip layout, maximum capacitance, maximum conversion time, and a list of available buffers. Based on the triplet [length, output capacitance, input conversion rate] for each type of buffer insertion scheme, a quadtt [length, input capacitance, output conversion rate, output capacitance] is calculated. Then, for each quadttt, redundant segments in the table are pruned.

[0108] In practice, building a lookup table according to this scheme leads to long program execution time and potential failures in subsequent tree construction. In the subsequent dynamic programming steps for constructing the standard tree structure, the program traverses all wires in the lookup table, concatenating wires with matching input and output attributes to the target length. Therefore, the probability of successful tree construction is related to the sampling interval of the output capacitance and input conversion rate when building the lookup table ([input capacitance, output conversion rate] are calculated results, and their density affects the probability of a matching [output capacitance, input conversion rate] in the lookup table). A smaller sampling interval results in longer program execution time and higher memory consumption.

[0109] To address this issue, this patent samples the attributes calculated from the wires at intervals equal to the original attributes, eliminating the impact of sampling intervals on the probability of successful tree construction. Sampling the calculation results amplifies the error caused by the precision of the original scheme; therefore, after the third embedding operation, buffers are inserted into the branch nodes of the nets with design constraint violations to correct the violations, and similar buffers are inserted at symmetrical positions to ensure symmetry. The delayed insertion of the design constraint correction buffers (i.e., the design constraint correction buffers are not reflected in the lookup table scheme but are inserted additionally after tree construction) makes the program runtime controllable and guarantees successful tree construction.

[0110] The following is combined with Figure 3 Here is a brief description of the process for constructing a lookup table:

[0111] First, the length of the lookup table, the range of output capacitance and input conversion rate, and the interval are determined based on the chip layout and the capacitance and conversion rate parameters input by the user (a). Then, the delay, area, input capacitance, and output conversion rate are calculated for all buffer insertion schemes corresponding to each [length, output capacitance, input conversion rate] triplet (b), and the input capacitance and output conversion rate are sampled according to the interval calculated in the previous step (c). Finally, for each [length, output capacitance, output conversion rate, input capacitance] quadruplet, the worse segments are deleted according to the delay (d).

[0112] In another embodiment of the present invention, a standard tree is dynamically generated to accurately connect the line segments in the lookup table; such as... Figure 4 As shown, step 3 above is replaced by steps 301 to 302:

[0113] The steps 301 to 302 described above are as follows:

[0114] Step 301: Determine the connection direction between the clock source and the root node of the upper tree based on the length and width of the input layout;

[0115] Step 302: Using the Gh-tree (general H-tree) algorithm, first generate the solution for each level from bottom to top, and then build the standard clock tree from top to bottom level by level.

[0116] Step 301 above is replaced by step 3011.

[0117] Step 3011: If the length of the input layout is greater than or equal to the width, the connection direction of the upper-level root node is horizontal expansion; otherwise, the connection direction of the upper-level root node is vertical expansion.

[0118] Step 302 above is replaced by steps 3021 to 3023.

[0119] Step 3021: First, construct a structure with depth P. During dynamic programming, the width range is twice the minimum length of the lookup table to the width of the chip layout, the width interval is twice the length of the lookup table, the height range is the specified minimum height to the width of the chip layout, and the interval is the specified minimum interval.

[0120] Step 3022: For each [width and height], it is necessary to traverse all possibilities of [number of nodes and branches], generate the corresponding line segment, prune it, and store it in the solution container;

[0121] Step 3023: Then, using the scheme at depth P as a subtree, construct a tree at depth P-1. If the target tree cannot be constructed, backtrack to depth P, reduce the dynamic programming interval, and regenerate the scheme until the depth reaches the set upper limit.

[0122] The following is combined with Figure 4 A detailed explanation of step 3:

[0123] This patent refers to the leaf nodes of the upper-level clock tree as tap points.

[0124] First, determine the connection direction between the clock source and the root node of the upper-level tree, which is also the expansion direction of the top level. If the length of the input layout is greater than or equal to the width, the top level expands horizontally; otherwise, it expands vertically, thus enhancing the algorithm's adaptability to different layouts. Then, using a general H-tree algorithm, generate solutions for each level from bottom to top, and then build a standard clock tree from top to bottom.

[0125] Figure 4The upper and middle layers are horizontally expanded. First, a tree of depth P, the lowest level, is constructed. During dynamic programming, the width range is twice the minimum length of the lookup table (due to the symmetry of the tree structure) to the width of the chip layout, with a width interval of twice the lookup table length. The height range is a specified minimum height (usually 2; the smaller this value, the higher the probability of building the tree, but also the higher the time cost) to the width of the chip layout (expansion direction alternates between vertical and horizontal according to the number of layers), with an interval of a specified minimum interval (a). For each [width and height], all possibilities of [number of node regions and number of branches] need to be traversed, generating corresponding line segments, pruning them, and storing them in the solution container (b). Then, using the solution at depth P as a subtree, a tree of depth P-1 is constructed. If the target tree cannot be constructed (the number of node regions and performance indicators meet the requirements), it is necessary to backtrack to the previous depth, reduce the dynamic programming interval, and regenerate the solution (c). These operations will be repeated until the depth reaches the upper limit (d).

[0126] This patent also includes the following optimizations:

[0127] When traversing the length, if the initial step size is set too small, it will take a lot of time to generate a large number of solutions, most of which will not be used. Therefore, to reduce the algorithm's running time and memory consumption, the initial step size is the sampling interval (lut_interval) from the first step's lookup table, and a backtracking strategy is used to ensure that a valid solution is found as much as possible. When a round of construction ends without finding a solution that meets the constraints, a backtracking operation is performed: the step size of the next layer is halved and a new solution is generated, until a solution that meets the constraints is generated at a certain layer or the lowest layer is also generated, and then the process returns layer by layer.

[0128] In another embodiment of the present invention, to accurately describe the determination of the top-level structure of the clock tree based on the buffer position and winding method after chip layout optimization, the following is combined with... Figure 5 The process is described below:

[0129] The process executes from top to bottom. Based on the number of branches in the current layer, the clock tree nodes are clustered. Then, while keeping the line length fixed, the buffers and branch nodes are moved closer to the corresponding cluster centroids. Subsequently, layer by layer downwards, the nodes are re-clustered and the branch nodes and buffers are moved according to the number of branch nodes in the subtrees within the upper-level cluster. Finally, the branch nodes are traversed from bottom to top. If there is a violation between its child node and the upper-level buffer, a buffer is inserted to correct it.

[0130] In another embodiment of the present invention, the method may further include the following steps: manually specifying the distribution or specific location of tap points and controlling the number of branches through corresponding instructions.

[0131] In another embodiment of the present invention, the distribution or specific location of tap points and the number of branches are manually specified by corresponding instructions. Specific steps include:

[0132] Based on the {row, column} values ​​given by the user, obtain the sequence of branches that satisfy the rxc distribution for the tap point;

[0133] The coordinates of the tap point are determined based on whether the final coordinates of the tap point specified by the user are a specific point or a range of coordinates.

[0134] Specify whether the number of branches at the lowest level is 2;

[0135] Specify that the number of branches for all layers is 2.

[0136] By manually specifying the distribution or specific location of tap points and controlling the number of branches through corresponding instructions, a more flexible and instructive standard clock tree can be generated.

[0137] In another embodiment of the present invention, the specific implementation method for manually specifying the distribution or specific location of tap points and controlling the number of branches through corresponding instructions is as follows:

[0138] Users can manually specify the distribution or specific location of tap points and control the number of branches through corresponding commands, thereby generating a more flexible and instructive standard clock tree.

[0139] ① Specify the distribution of tap points. Users can provide input of the form {r, c}, specifying that the tap points will ultimately be distributed in r rows and c columns. The algorithm obtains the sequence of branches where the tap points satisfy an rxc distribution based on the values ​​of r and c (taking r = 8, c = 4, and top-level horizontal expansion as an example):

[0140] • The factor sequences of r and c are obtained respectively: the factor sequence of r is {{8}, {2 4}, {4 2}, {2 2 2}}, and the factor sequence of c is {{4}, {2 2}};

[0141] For each sequence cn in c, select the corresponding r sequence rn (which must satisfy size(cn) == size(rn)||

[0142] `size(cn) == size(rn) + 1)`, starting from `cn`, alternately select one factor from `cn` and `rn` to form a feasible sequence. For example: `cn = {2 2}`, then `rn` can take the values ​​{8}, {2 4}, and {4 2}. Therefore, the feasible sequence obtained by combining these factors is...

[0143] {2 8 2}, {2 2 2 4}, and {2 4 2 2} all conform to the distribution of 8x 4.

[0144] ② Specify the coordinates of the tap point. Users can specify the final coordinates of the tap point. If the coordinates are a specific point, they will be used directly as the coordinates of the tap point; otherwise, the midpoint of the coordinate range will be used as the coordinates of the tap point.

[0145] ③ Specify whether the number of branches at the lowest level is 2. The number of branches at the lowest level has a significant impact on the result. By default, it is binary, but users can specify that it should be automatically generated by the algorithm.

[0146] ④ Specify that the number of branches for all layers is 2. Users can specify that a standard H-tree will be generated.

[0147] In another embodiment of the present invention, in order to ensure the accuracy of the node positions inside the clock tree, the clock tree is adjusted from top to bottom through clustering. The specific implementation steps are as follows:

[0148] When a buffer that is directly connected between different layers violates the design constraints, a buffer to correct the violation is symmetrically inserted at a suitable branch node in the middle.

[0149] When a tap point directly connects to the next tap point and a leaf node within its own cluster, the network with a large number of fan-out nodes will be split.

[0150] When the tap point is directly connected to the root node of the clock tree, the buffer is inserted at the branch node between the tap point and the root node.

[0151] The following is a detailed explanation of the specific implementation process for adjusting the clock tree:

[0152] Then, the nodes in the top-level structure are optimized. When a buffer directly connected between different layers violates design constraints, a buffer to correct the violation is symmetrically inserted at a suitable branch node in the middle. When a tap point is directly connected to the next tap point and a leaf node within its own cluster, the network with a large fan-out number is split to reduce the insertion delay of the next tap point. When a tap point is directly connected to the root node of the clock tree, since the position and size of the tap point cannot be changed, a buffer is inserted at a branch node between the tap point and the root node when necessary (the branch node may not only connect to the tap point but also to other nodes, so the buffer will be placed on the branch node that has a smaller impact on other nodes).

[0153] Figure 2The flowchart of the improved H-shaped structure algorithm provided in this patent consists of three main steps: constructing a lookup table, constructing a standard tree structure, and embedding the structure to the layout. Each step can be further subdivided into multiple smaller steps, which are executed sequentially. In the clock tree synthesis and tree construction stage, the algorithm takes chip layout, maximum capacitance, maximum conversion rate, process library, and required and / or optional user parameters as input, and outputs the upper-level structure of the clock tree determined by the buffer position and routing method after optimization of the chip layout. In the clock tree synthesis and optimization stage, the algorithm takes the netlist after the clock tree construction stage as input, and outputs the clock tree optimized according to the subtrees corresponding to the nodes in the upper-level structure.

[0154] The improved H-type structure algorithm provided by this invention significantly reduces the running time compared to the original algorithm, making it suitable for chip layouts with more nodes and more complex structures. It also achieves significant advantages in key clock tree quality indicators such as area, maximum latency, and clock skew. Specifically:

[0155] 1. Reduced runtime. In the first step of the algorithm, when building the lookup table, the algorithm samples the results of the line segment attribute calculation, which reduces the coupling between the probability of successful tree construction and the sampling interval of the input data, thereby reducing the time and memory overhead for generating the lookup table;

[0156] This also increases the probability of successful line segment splicing in the second step, allowing only the optimal few solutions to be retained during the second step of dynamic programming, thus reducing the time cost of splicing the current layer with all subtrees.

[0157] The backtracking operation in the second step of the algorithm when building the standard tree structure ensures that a tree structure with the expected key indicators can be built even when using a larger width interval during dynamic programming. Backtracking to the bottom layer is only performed when tree building fails, and a smaller width interval is used to build the tree, which further speeds up the tree building process.

[0158] 2. Greater flexibility. The algorithm in this patent allows users to specify the node distribution or coordinates of the upper-level structure, as well as the number of branch factors, increasing the adaptability of the tree structure to complex chip layouts and achieving results with lower maximum latency and smaller clock skew compared to automatic planning.

[0159] Total latency and clock skew are reduced. Compared with existing algorithms, the algorithm in this patent adjusts the underlying branch structure. To avoid excessive fan-out caused by tap points directly connecting to the next tap point and their own leaf nodes, the clock network is appropriately split.

[0160] The algorithm proposed in this patent can be used for advanced process sizes such as 7nm, as well as 14nm and above, and can support clock tree construction with up to millions of original nodes. There are no restrictions on the types of nodes included within the clock tree, including but not limited to logic units, clock gating units, multiplexers, etc.

[0161] Users need to provide all parameters before the algorithm starts, such as Figure 1 As shown, optional parameters include tap point distribution / tap point coordinates, number of branch factors, etc., while required parameters include maximum conversion time, maximum capacitance, etc.

[0162] The intermediate file output by the algorithm, "Top-level structure of the clock tree construction phase", should satisfy the clustering constraints.

[0163] In the second step of the algorithm, when building the standard tree structure, there may be cases where the leaf nodes of the clock tree are much smaller than the user-specified tappoint. In such cases, the algorithm will choose not to build the top-level structure.

[0164] Exemplary device

[0165] After introducing the method of exemplary embodiments of the present invention, the following references are made. Figure 5 An apparatus for constructing a clock tree based on an improved structural algorithm according to an exemplary embodiment of the present invention will be described. The apparatus includes:

[0166] The table generation module is used to generate lookup tables based on chip parameters and design constraints.

[0167] The sampling module is used to sample the attributes of each line segment in the lookup table;

[0168] The dynamic programming module is used to concatenate line segments in the lookup table and generate a standard tree using dynamic programming.

[0169] The judgment module is used to determine whether the standard tree meets the constraints. If it does, the clock tree nodes are clustered from top to bottom, and the buffer in the standard tree is moved towards the cluster center. Otherwise, it backtracks one layer, reduces the width, and sends the data after the width reduction to the sampling module.

[0170] Insertion module, used to insert buffers that correct violations symmetrically at branch nodes from bottom to top.

[0171] As an optional implementation, the table generation module is specifically used for:

[0172] Calculate the length of the lookup table, the range of output capacitance and input conversion rate, and the interval based on the chip layout and capacitance and conversion rate parameters.

[0173] For each [length, output capacitance, input slew rate] triplet, calculate the delay, area, input capacitance, and output slew rate for all buffer insertion schemes, and sample the input capacitance and output slew rate according to the interval calculated in the previous step;

[0174] For each [length, output capacitance, output conversion rate, input capacitance] quadruple, the worse segments are deleted with a delay.

[0175] As an optional implementation, the dynamic programming module includes:

[0176] The direction determination submodule is used to determine the connection direction between the clock source and the upper-level tree root node based on the length and width of the input layout.

[0177] The sub-modules are built level by level to generate the solution for each level from bottom to top using a general H-tree algorithm, and then build the standard clock tree from top to bottom.

[0178] As an optional implementation, the direction determination submodule is specifically used for:

[0179] If the length of the input layout is greater than or equal to its width, the connection direction of the upper-level root node is horizontal expansion; otherwise, the connection direction of the upper-level root node is vertical expansion.

[0180] As an optional implementation, the hierarchical construction of sub-modules is specifically used for:

[0181] First, construct a scheme with depth P. During dynamic programming, the width range is from twice the minimum length of the lookup table to the width of the chip layout, the width interval is twice the length of the lookup table, the height range is from the specified minimum height to the width of the chip layout, and the interval is the specified minimum interval.

[0182] For each [width and height], it is necessary to traverse all possibilities of [number of nodes and branches], generate the corresponding line segment, prune it, and store it in the solution container;

[0183] Then, using the solution at depth P as a subtree, construct a tree at depth P-1. If the target tree cannot be constructed, backtrack to depth P, reduce the dynamic programming interval, and regenerate the solution until the depth reaches the set upper limit.

[0184] As an optional implementation, an apparatus for constructing a clock tree based on an improved structural algorithm further includes: an instruction control module, used to manually specify the distribution or specific location of tap points and control the number of branches through corresponding instructions.

[0185] As an optional implementation, the instruction control module is specifically used for:

[0186] Based on the {row, column} values ​​given by the user, obtain the sequence of branches that satisfy the rxc distribution for the tap point;

[0187] The coordinates of the tap point are determined based on whether the final coordinates of the tap point specified by the user are a specific point or a range of coordinates.

[0188] Specify whether the lowest-level branch data is 2;

[0189] Specify that the number of branches for all layers is 2.

[0190] As an alternative implementation, an apparatus for constructing a clock tree based on an improved structural algorithm further includes: an adjustment module for adjusting the position of internal nodes of the clock tree from top to bottom through clustering.

[0191] As an optional implementation, the adjustment module is specifically used for:

[0192] When a buffer that is directly connected between different layers violates the design constraints, a buffer to correct the violation is symmetrically inserted at a suitable branch node in the middle.

[0193] When a tap point directly connects to the next tap point and a leaf node within its own cluster, the network with a large number of fan-out nodes will be split.

[0194] When the tap point is directly connected to the root node of the clock tree, the buffer is inserted at the branch node between the tap point and the root node.

[0195] Exemplary media

[0196] After introducing the methods and apparatus of exemplary embodiments of the present invention, the following references are made. Figure 6 A computer-readable storage medium according to exemplary embodiments of the present invention will be described, please refer to... Figure 6 The computer-readable storage medium shown is an optical disc 80, on which a computer program (i.e., a program product) is stored. When the computer program is run by the processor, it implements the steps described in the above method implementation, for example: Step 1: Generate a lookup table based on chip parameters and design constraints; Step 2: Sample the attributes of each line segment in the lookup table; Step 3: Concatenate the line segments in the lookup table and dynamically program to generate a standard tree; Step 4: Determine whether the standard tree meets the constraints. If it does, cluster the clock tree nodes from top to bottom, move the buffer in the standard tree towards the cluster center, and proceed to Step 5. Otherwise, backtrack one level, reduce the width, and return to Step 3; Step 5: Insert buffers to correct violations symmetrically at the branch nodes from bottom to top. The specific implementation of each step will not be repeated here.

[0197] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0198] Exemplary computing device

[0199] After introducing the methods, apparatus, and media of exemplary embodiments of the present invention, the following references are made. Figure 7 A computing device for constructing a clock tree based on an improved structural algorithm, according to an exemplary embodiment of the present invention.

[0200] Figure 7 A block diagram is shown of an exemplary computing device 90 suitable for implementing embodiments of the present invention, which may be a computer system or a server. Figure 7 The computing device 90 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of the present invention.

[0201] like Figure 7 As shown, the components of the computing device 90 may include, but are not limited to: one or more processors or processing units 901, system memory 902, and bus 903 connecting different system components (including system memory 902 and processing unit 901).

[0202] The computing device 90 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computing device 90, including volatile and non-volatile media, removable and non-removable media.

[0203] System memory 902 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 9021 and / or cache memory 9022. Computing device 90 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, ROM 9023 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 7 Not shown in the image (usually referred to as a "hard drive"). Although not shown in Figure 7The diagram illustrates that disk drives for reading and writing to removable non-volatile disks (e.g., "floppy disks") and optical disc drives for reading and writing to removable non-volatile optical discs (e.g., CD-ROMs, DVD-ROMs, or other optical media) can be provided. In these cases, each drive can be connected to bus 903 via one or more data media interfaces. System memory 902 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0204] A program / utility 9025 having a set (at least one) of program modules 9024 may be stored, for example, in system memory 902, and such program modules 9024 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment. Program modules 9024 typically perform the functions and / or methods described in the embodiments of the present invention.

[0205] The computing device 90 can also communicate with one or more external devices 904 (such as a keyboard, pointing device, display, etc.). This communication can be performed through the input / output (I / O) interface 905. Furthermore, the computing device 90 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 906. Figure 7 As shown, network adapter 906 communicates with other modules of computing device 90 (such as processing unit 901) via bus 903. It should be understood that, although... Figure 7 As not shown, it can be used in conjunction with computing device 90 with other hardware and / or software modules.

[0206] The processing unit 901 executes various functional applications and data processing by running programs stored in the system memory 902. For example, step 1: generate a lookup table based on chip parameters and design constraints; step 2: sample the attributes of each line segment in the lookup table; step 3: concatenate the line segments in the lookup table and dynamically program to generate a standard tree; step 4: determine whether the standard tree meets the constraints. If it does, cluster the clock tree nodes from top to bottom, move the buffer in the standard tree towards the cluster center, and proceed to step 5. Otherwise, backtrack one level, reduce the width, and return to step 3.

[0207] Step 5: Insert buffers to correct violations symmetrically at the branch nodes from bottom to top. The specific implementation methods of each step will not be repeated here. It should be noted that although several units / modules or sub-units / sub-modules of a computer device constructing a clock tree based on the improved structural algorithm are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0208] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0209] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0210] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0211] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0212] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0213] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0214] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0215] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

Claims

1. A method for constructing a clock tree based on an improved structural algorithm, characterized in that, include: Step 1: Generate a lookup table based on chip parameters and design constraints; Step 2: Sample the attributes of each line segment in the lookup table; Step 3: Concatenate the line segments in the lookup table and generate a standard tree using dynamic programming; Step 4: Determine whether the standard tree meets the constraints. If it does, cluster the clock tree nodes from top to bottom, move the buffer in the standard tree towards the cluster center, and proceed to Step 5. Otherwise, backtrack one level, reduce the width, and return to Step 3. Step 5: Insert buffers to correct violations symmetrically at the branch nodes from bottom to top.

2. The method as described in claim 1, characterized in that, The step of generating a lookup table based on chip parameters and design constraints includes: Calculate the length of the lookup table, the range of output capacitance and input conversion rate, and the interval based on the chip layout and capacitance and conversion rate parameters. For each [length, output capacitance, input slew rate] triplet, calculate the delay, area, input capacitance, and output slew rate for all buffer insertion schemes, and sample the input capacitance and output slew rate according to the interval calculated in the previous step; For each [length, output capacitance, output conversion rate, input capacitance] quadruple, the worse segments are deleted with a delay.

3. The method as described in claim 1, characterized in that, The process of concatenating line segments in the lookup table and dynamically generating a standard tree includes: The connection direction between the clock source and the root node of the upper tree is determined based on the length and width of the input layout. The general H-tree algorithm is used to generate solutions for each level from bottom to top, and then the standard clock tree is built up from top to bottom level by level.

4. The method as described in claim 3, characterized in that, The method of determining the connection direction between the clock source and the upper-level tree root node based on the length and width of the input layout includes: If the length of the input layout is greater than or equal to its width, the top layer of the upper-level tree will expand horizontally; otherwise, the root node of the upper-level tree will expand vertically.

5. The method as described in claim 3, characterized in that, The method first generates solutions for each level from bottom to top using a general H-tree algorithm, and then constructs a standard clock tree from top to bottom, including: First, construct a scheme with depth P. During dynamic programming, the width range is from twice the minimum length of the lookup table to the width of the chip layout, the width interval is twice the length of the lookup table, the height range is from the specified minimum height to the width of the chip layout, and the interval is the specified minimum interval. For each [width and height], it is necessary to traverse all possibilities of [number of nodes and branches], generate the corresponding line segment, prune it, and store it in the solution container; Then, using the solution at depth P as a subtree, construct a tree at depth P-1. If the target tree cannot be constructed, backtrack to depth P, reduce the dynamic programming interval, and regenerate the solution until the depth reaches the set upper limit.

6. The method as described in claim 1, characterized in that, Also includes: The distribution or specific location of the leaf nodes of the upper-level clock tree and the number of branches can be manually specified through the corresponding instructions.

7. The method as described in claim 1, characterized in that, Also includes: The positions of nodes within the clock tree are adjusted from top to bottom through clustering.

8. The method as described in claim 7, characterized in that, The top-down clustering adjustment of the positions of nodes within the clock tree includes: When a buffer that is directly connected between different layers violates the design constraints, a buffer to correct the violation is symmetrically inserted at a suitable branch node in the middle. When a leaf node of an upper-level clock tree is directly connected to a leaf node of the next upper-level clock tree and a leaf node within its own cluster, the network with a large number of fan-outs formed by the direct connections is split. When a leaf node of the upper-level clock tree is directly connected to the root node of the clock tree, the buffer is inserted at the branch node between the leaf node and the root node of the upper-level clock tree.

9. A device for constructing a clock tree based on an improved structural algorithm, characterized in that, include: The table generation module is used to generate lookup tables based on chip parameters and design constraints. The sampling module is used to sample the attributes of each line segment in the lookup table; The dynamic programming module is used to concatenate line segments in the lookup table and generate a standard tree using dynamic programming. The judgment module is used to determine whether the standard tree meets the constraints. If it does, the clock tree nodes are clustered from top to bottom, and the buffer in the standard tree is moved towards the cluster center. Otherwise, it backtracks one layer, reduces the width, and sends the data after the width reduction to the sampling module. Insertion module, used to insert buffers that correct violations symmetrically at branch nodes from bottom to top.

10. A computing device, the computing device comprising: At least one processor, memory, and input / output unit; The memory is used to store computer programs, and the processor is used to call the computer programs stored in the memory to execute a method for constructing a clock tree based on an improved structural algorithm as described in any one of claims 1 to 8.

11. A computer-readable storage medium comprising instructions that, when executed on a computer, cause the computer to perform a method for constructing a clock tree based on an improved structural algorithm as described in any one of claims 1 to 8.

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