Photolithography mask generation model training method and device, equipment and storage medium

Abstract

Embodiments of the present application provide a photolithography mask generation model training method and device, equipment and a storage medium, relating to the chip and machine learning technical field. The method comprises: obtaining a plurality of chip layouts respectively corresponding to a predicted mask graph; based on the predicted mask graph corresponding to each chip layout, determining the predicted difficulty corresponding to each chip layout; selecting a chip layout with a predicted difficulty meeting a condition from the plurality of chip layouts as a difficult chip layout; and training a first photolithography mask generation model using the difficult chip layout to obtain a trained first photolithography mask generation model. The technical solution provided by the embodiments of the present application reduces the number of chip layouts required for training the photolithography mask generation model, and saves the training cost of the model.

Description

Technical Field

[0001] This application relates to the fields of chip and machine learning technology, and in particular to a training method, apparatus, device and storage medium for photolithography mask generation model. Background Technology

[0002] In the chip manufacturing process, it is necessary to obtain the mask images corresponding to each chip layout in order to perform photolithography exposure.

[0003] In related technologies, a large number of chip layouts are needed as training data to train the photomask generation model in order to obtain a high-precision photomask generation model.

[0004] In the aforementioned related technologies, a large number of chip layouts are required to train the photolithography mask generation model, and each chip layout requires a certain cost, so the training process of the model is costly. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for training a photolithography mask generation model, which can reduce the number of chip layouts required to train the model and save training costs. The technical solution is as follows:

[0006] According to one aspect of the embodiments of this application, a method for training a photolithographic mask generation model is provided, the method comprising:

[0007] Obtain the prediction mask images corresponding to multiple chip layouts;

[0008] Based on the prediction mask corresponding to each of the chip layouts, the prediction difficulty corresponding to each of the chip layouts is determined.

[0009] Select the chip layout that meets the predicted difficulty criteria from the plurality of chip layouts, and use it as the difficult chip layout;

[0010] The first photolithography mask generation model after initial training is updated and trained using the aforementioned difficult chip layout to obtain the first photolithography mask generation model after training and updating.

[0011] According to one aspect of the embodiments of this application, a training apparatus for a photolithographic mask generation model is provided, the apparatus comprising:

[0012] The mask acquisition module is used to acquire the predicted mask images corresponding to multiple chip layouts;

[0013] The difficulty determination module is used to determine the prediction difficulty corresponding to each of the chip layouts based on the prediction mask map corresponding to each of the chip layouts.

[0014] The layout selection module is used to select a chip layout that meets the predicted difficulty criteria from the plurality of chip layouts, and use it as the difficult chip layout.

[0015] The model update module is used to update and train the first photolithography mask generation model after preliminary training using the difficult chip layout, so as to obtain the first photolithography mask generation model after training and updating.

[0016] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described training method for photolithography mask generation model.

[0017] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, the computer program being loaded and executed by a processor to implement the above-described training method for the photolithographic mask generation model.

[0018] According to one aspect of the embodiments of this application, a computer program product is provided, comprising a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, causing the computer device to perform the training method for the photolithographic mask generation model described above.

[0019] The technical solutions provided in this application embodiment may have the following beneficial effects:

[0020] Since difficult chip layouts can quickly improve the model accuracy of photomask generation models, by selecting difficult chip layouts and using them to update photomask generation models, the number of chip layouts required to train photomask generation models can be reduced, thereby saving data annotation costs and thus saving model training costs.

[0021] In addition, training with complex chip layouts can quickly improve the model accuracy of the photolithography mask generation model, thereby saving the time required for model training and improving the training efficiency of the model.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0023] Figure 1 This is a flowchart of a training method for a photolithographic mask generation model provided in one embodiment of this application;

[0024] Figure 2 This is a schematic diagram of an implementation environment provided in one embodiment of this application;

[0025] Figure 3 This is a schematic diagram of a photolithographic mask generation model provided in one embodiment of this application;

[0026] Figure 4 This is a flowchart of a training method for a photolithographic mask generation model provided in another embodiment of this application;

[0027] Figure 5 This is a flowchart of a training method for a photolithographic mask generation model provided in another embodiment of this application;

[0028] Figure 6 This is a flowchart of a training method for a photolithographic mask generation model provided in another embodiment of this application;

[0029] Figure 7 This is a flowchart of a training method for a photolithographic mask generation model provided in another embodiment of this application;

[0030] Figure 8 This is a flowchart of a training method for a photolithographic mask generation model provided in another embodiment of this application;

[0031] Figure 9 This is a block diagram of a training apparatus for a photolithographic mask generation model provided in one embodiment of this application;

[0032] Figure 10 This is a block diagram of a training apparatus for a photolithographic mask generation model provided in one embodiment of this application;

[0033] Figure 11 This is a block diagram of a computer device provided in one embodiment of this application. Detailed Implementation

[0034] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of methods consistent with some aspects of this application as detailed in the appended claims.

[0035] First, let me introduce some of the terms used in this application.

[0036] Chip layout: Also known as integrated circuit layout, it is a planar geometric description of the actual physical state of an integrated circuit. The integrated circuit layout is the result of the physical design, the lowest-level step in integrated circuit design. Physical design uses placement and routing techniques to convert the results of logic synthesis into a layout file. This file contains the shape, area, and location information of each hardware unit on the chip.

[0037] Optical proximity correction (OPC) is a photolithography resolution enhancement technique that uses computational methods to correct the pattern on a photomask so that the pattern projected onto the photoresist closely matches the design requirements. In photolithography, the pattern on the mask is projected onto the photoresist through an exposure system. Due to imperfections in the optical system and diffraction effects, the pattern on the photoresist and the pattern on the mask are not perfectly identical. If these distortions are not corrected, they can significantly alter the electrical performance of the manufactured circuits. Optical proximity correction is a technique that adjusts the topology of the transparent areas on the photomask or adds small sub-resolution auxiliary patterns to the mask to make the image in the photoresist as close as possible to the mask pattern. OPC also compensates for the degradation in image quality of the photolithography system by changing the amplitude of the transmitted light from the mask. OPC is primarily used in the manufacturing process of semiconductor devices.

[0038] Photolithography mask: A photolithography mask is a light-masking film, similar in function to photography. Through a photolithography mask, a portion of the photoresist "underneath" the mask becomes photosensitive (and insoluble in organic chemicals), while another portion remains photosensitive (and readily soluble in organic chemicals), thus creating the desired pattern. In the manufacturing process of planar transistors and integrated circuits, multiple photolithography steps are required. Therefore, a set of photolithography masks with specific geometric patterns must be prepared. Photolithography mask preparation involves creating mask patterns of the required size and precision according to the geometric patterns required by the transistor and integrated circuit parameters, following a selected method. These patterns are then repeatedly arranged on a mask substrate at specific intervals and layouts, allowing for the mass production of photolithography masks for use in photolithography processes.

[0039] Artificial intelligence (AI) is the theory, methods, technology, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive technology within computer science that attempts to understand the essence of intelligence and produce a new kind of intelligent machine that can react in a way similar to human intelligence. AI studies the design principles and implementation methods of various intelligent machines, enabling them to possess the functions of perception, reasoning, and decision-making.

[0040] Artificial intelligence (AI) is a comprehensive discipline encompassing a wide range of fields, including both hardware and software technologies. Fundamental AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies primarily include computer vision, speech processing, natural language processing, and machine learning / deep learning.

[0041] Machine learning (ML) is a multidisciplinary field involving probability theory, statistics, approximation theory, convex analysis, and algorithm complexity theory. It specifically studies how computers can simulate or implement human learning behavior to acquire new knowledge or skills and reorganize existing knowledge structures to continuously improve their performance. Machine learning is the core of artificial intelligence and the fundamental way to endow computers with intelligence; its applications span all areas of artificial intelligence. Machine learning and deep learning typically include techniques such as artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and instructional learning.

[0042] This application employs machine learning technology to train a photolithography mask generation model, thereby enabling the model to generate highly accurate predicted mask images, providing a mask for subsequent chip lithography processes.

[0043] The methods provided in this application can also be extended to other stages of integrated circuit design, such as chip logic circuit simulation, chip thermal transport simulation, chip performance testing, chip defect detection, light source-mask co-optimization, and other EDA (Electronic Design Automation) fields.

[0044] This application Figure 1 Two training methods for photolithography mask generation models are provided respectively.

[0045] (1) Training methods based on error reduction sampling strategies, such as Figure 1 As shown in (a), the method includes at least the following steps (steps 11-13):

[0046] Step 11: First, use some labeled chip layouts as labeled datasets to perform preliminary training on the photolithography mask generation model. Then, use the pre-trained photolithography mask generation model to perform mask prediction on unlabeled chip layouts to obtain the predicted mask images of each unlabeled chip layout.

[0047] Step 12: Obtain the wafer pattern of the predicted mask through the photolithography physical model. Based on the difference between the wafer pattern of the predicted mask and the corresponding unlabeled chip layout, determine the prediction difficulty of each unlabeled chip layout and select the unlabeled chip layout with the highest prediction difficulty as the difficult chip layout.

[0048] Step 13: Obtain the standard mask image of the difficult chip layout, and add the difficult chip layout as an annotated chip layout to the annotated dataset to continue training the lithography mask generation model.

[0049] The above steps can be executed in multiple rounds to continuously improve the accuracy of the photolithography mask generation model.

[0050] (2) Training methods based on voting query sampling strategies, such as Figure 1 As shown in (b), the method includes at least the following steps (steps 14 to 16):

[0051] Step 14: First, use some labeled chip layouts as labeled datasets to perform preliminary training on several pre-trained photolithography mask generation models. Then, use the pre-trained photolithography mask generation models to perform mask prediction on unlabeled chip layouts.

[0052] Step 15: Based on the predicted mask generated by the multiple pre-trained photolithography mask generation models based on each unlabeled chip layout, calculate the uncertainty corresponding to each unlabeled chip layout, and select the unlabeled chip layout with the largest uncertainty as the difficult chip layout.

[0053] Step 16: Obtain the standard mask image of the difficult chip layout, and add the difficult chip layout as an annotated chip layout to the annotated dataset to continue training the lithography mask generation model.

[0054] The above steps can be executed in multiple rounds to continuously improve the accuracy of the photolithography mask generation model.

[0055] Please refer to Figure 2 The diagram illustrates an implementation environment provided in one embodiment of this application. This real-time environment can be implemented as a training system for generating models from photolithographic masks. The system 30 may include a model training device 31 and a model usage device 32.

[0056] The model training device 31 can be an electronic device such as a computer, server, or intelligent robot, or other electronic devices with strong computing power. The model training device 31 is used to train the photolithography mask generation model 33. In this embodiment, the photolithography mask generation model 33 is a neural network model used to generate predicted mask images. The model training device 31 can use machine learning to train the photolithography mask generation model 33 to achieve better performance.

[0057] The trained photolithography mask generation model 33 can be deployed on the model-using device 32 to provide image processing results (i.e., automatic counting results). The model-using device 32 can be a terminal device such as a PC (Personal Computer), tablet computer, smartphone, wearable device, intelligent robot, intelligent voice interaction device, smart home appliance, vehicle terminal, aircraft, medical device, etc., or it can be a server; this application does not limit it in this regard.

[0058] In some embodiments, such as Figure 2 As shown, the photolithography mask generation model 33 may include an encoder 34 and a decoder 35. (As...) Figure 3 As shown, encoder 34 is an encoder composed of convolutional neural networks. Taking an 8-layer convolutional network as an example, after the chip layout is input, it passes through multiple layers of two-dimensional convolutional neural networks. These 8 convolutional layers consist of 8, 16, 32, 64, 128, 256, 512, and 1024 3×3 filters 36, respectively. A batch normalization layer 37 is established after each convolutional layer, and the Corrected Linear Unit (ReLU) is used as the activation function. The final output of the above 8 convolutional layers (dimension (1,1,1024)) is used as the input of decoder 35, which is composed of multiple layers of deconvolutional neural networks. Taking an 8-layer deconvolution layer as an example, the first 7 convolutional layers consist of 1024, 512, 256, 128, 64, 32, and 16 3×3 filters 36, respectively. A batch normalization layer 37 is established after each deconvolutional layer, with Leaky-ReLU activated as the activation function. Finally, a deconvolutional layer consisting of a 3×3 filter 36 and a sigmoid activation function 38 provides a mask with dimensions (256, 256, 1) and values ​​from 0 to 1. The mask is then binarized to obtain the final prediction mask.

[0059] The embodiments of this application can be applied to various scenarios, including but not limited to chip design, cloud technology, artificial intelligence, chip manufacturing, smart transportation, and assisted driving.

[0060] The technical solution of this application will be described below through several embodiments.

[0061] Please refer to Figure 4 This document illustrates a flowchart of a method for training a photolithographic mask generation model according to another embodiment of this application. In this embodiment, the method is illustrated using the model training device described above. The method may include the following steps (401-404):

[0062] Step 401: Obtain the prediction mask images corresponding to the multiple chip layouts.

[0063] In some embodiments, multiple chip layouts include labeled chip layouts. A labeled chip layout refers to a chip layout for which a corresponding standard mask has been generated; the standard mask is the label on the labeled chip layout.

[0064] In some embodiments, multiple chip layouts include unlabeled chip layouts, which refer to chip layouts for which no corresponding standard mask has been generated.

[0065] It should be noted that multiple chip layouts can all be labeled chip layouts; multiple chip layouts can also all be unlabeled chip layouts; multiple chip layouts can also include both labeled chip layouts and unlabeled chip layouts, and this application embodiment does not specifically limit this.

[0066] In some embodiments, a second photolithography mask generation model is initially trained using multiple labeled chip layouts to obtain a pre-trained second photolithography mask generation model; wherein, a labeled chip layout refers to a chip layout that has already generated a corresponding standard mask image; the pre-trained second photolithography mask generation model is used to perform mask prediction on multiple chip layouts to obtain predicted mask images corresponding to each of the multiple chip layouts.

[0067] In some embodiments, the initial second lithography mask generation model is the same as the initial first lithography mask generation model, and the first lithography mask generation model is the second lithography mask generation model after preliminary training. The initial first lithography mask generation model is initially trained using multiple labeled chip layouts to obtain the first lithography mask generation model; then, the first lithography mask generation model is used to predict masks for the multiple chip layouts, obtaining predicted mask images corresponding to each chip layout. That is, the first lithography mask generation model is first initially trained using labeled chip layouts to obtain a pre-trained first lithography mask generation model; then, the pre-trained first lithography mask generation model is used to predict masks for the multiple chip layouts, obtaining predicted mask images corresponding to each chip layout. The model accuracy of the pre-trained first lithography mask generation model may be lower than the required model accuracy of the first lithography mask generation model.

[0068] In some embodiments, a second photolithography mask generation model, different from the first photolithography mask generation model, is used to generate predicted mask images corresponding to multiple chip layouts. The second photolithography mask generation model differs from the first photolithography mask generation model but is of the same type; it is also a model capable of generating corresponding predicted mask images based on chip layouts. In some embodiments, the second photolithography mask generation model is a pre-trained model, which can be directly used to generate predicted mask images corresponding to multiple chip layouts, and its model accuracy can be higher than that of the current first photolithography mask generation model.

[0069] In some embodiments, the two methods described above for generating prediction masks corresponding to multiple chip layouts can be combined. For example, if the model accuracy of the first photolithography mask generation model is low (such as the first photolithography mask generation model in the initial state), the second photolithography mask generation model is used to generate prediction masks corresponding to multiple chip layouts; if the model accuracy of the first photolithography mask generation model is high, the first photolithography mask generation model is used to generate prediction masks corresponding to multiple chip layouts.

[0070] In some embodiments, the model accuracy can be determined based on the loss of the photomask generation model, such as directly using the loss to represent the model accuracy of the photomask generation model. The smaller the loss, the higher the model accuracy of the photomask generation model; the larger the loss, the lower the model accuracy of the photomask generation model.

[0071] Step 402: Based on the prediction mask corresponding to each chip layout, determine the prediction difficulty corresponding to each chip layout.

[0072] In some embodiments, by analyzing and calculating the prediction masks corresponding to the chip layout, some calculation results can be obtained as indicators to measure the prediction difficulty. If there is a large (or strong) correlation between the indicator corresponding to the prediction mask and the prediction difficulty of the chip layout, the prediction difficulty corresponding to the chip layout can be indicated based on the indicator, or the indicator can be directly used as the prediction difficulty corresponding to the chip layout.

[0073] Step 403: Select the chip layout that meets the prediction difficulty criteria from multiple chip layouts as the difficult chip layout.

[0074] In some embodiments, a difficult chip layout can be understood as one that, compared to other chip layouts, is less likely / more difficult to predict high-quality and / or design-compliant mask patterns using a photolithography mask generation model.

[0075] In some embodiments, a chip layout whose predicted difficulty reaches a difficulty threshold is selected from multiple chip layouts as a difficult chip layout.

[0076] In some embodiments, multiple chip layouts are sorted from high to low according to prediction difficulty, and the first n chip layouts are selected as difficult chip layouts; or, multiple chip layouts are sorted from low to high according to prediction difficulty, and the last n chip layouts are selected as difficult chip layouts, where n is a positive integer.

[0077] In some embodiments, the chip layout with the greatest prediction difficulty is selected from the chip layouts as the difficult chip layout (i.e., the case where n is 1).

[0078] Step 404: The first photolithography mask generation model is trained using the difficult chip layout to obtain the trained first photolithography mask generation model.

[0079] In some embodiments, if the difficult chip layout is an annotated chip layout, the difficult chip layout can be directly used to train the first lithography mask generation model; if the difficult chip layout is an unannotated chip layout, the annotated mask image of the difficult chip layout is obtained first, and then the difficult chip layout is used to train the first lithography mask generation model.

[0080] In some embodiments, when multiple chip layouts include labeled chip layouts, the process of selecting the difficult chip layout is essentially a screening process for the labeled chip layouts. Optionally, the difficult chip layout is selected from the multiple labeled chip layouts, and the difficult chip layout is used primarily to train the first photolithography mask generation model. For example, the first photolithography mask generation model is trained using only the difficult chip layout; or, for example, the frequency of training the first photolithography mask generation model using the difficult chip layout is higher than the frequency of training the first photolithography mask generation model using other labeled chip layouts. That is, the first photolithography mask generation model is mainly trained using the difficult chip layout, supplemented by updating the first photolithography mask generation model locally on other chips, to avoid overfitting of the first photolithography mask generation model.

[0081] In some embodiments, after the difficult chip layout is determined, it is ensured that the proportion of the difficult chip layout in the labeled chip layout used to update the first lithography mask generation model is not less than a threshold value.

[0082] In some embodiments, when multiple chip layouts include unlabeled chip layouts, the process of selecting the difficult chip layout is the process of selecting a chip layout from the unlabeled chip layouts for training the first photomask generation model.

[0083] In summary, the technical solution provided by the embodiments of this application can quickly improve the model accuracy of the photomask generation model by selecting difficult chip layouts and using them to train the photomask generation model, thereby reducing the number of chip layouts required to train the photomask generation model, thus saving data annotation costs and model training costs.

[0084] Please refer to Figure 5 This document illustrates a flowchart of a method for training a photolithographic mask generation model according to another embodiment of this application. In this embodiment, the method is illustrated using the model training device described above. The method may include the following steps (501-505):

[0085] Step 501: The second photomask generation model is initially trained using multiple labeled chip layouts to obtain the initially trained second photomask generation model.

[0086] Among them, the labeled chip layout refers to the chip layout for which a corresponding standard mask has been generated.

[0087] In some embodiments, a labeled chip layout is obtained by acquiring standard mask images corresponding to multiple chip layouts; then, the second photolithography mask generation model is initially trained using the standard mask images corresponding to the multiple chip layouts. A standard mask image refers to a mask image that has undergone OPC and meets design requirements.

[0088] During the initial training phase, a relatively small number of labeled chip layouts are unnecessary. If we consider all labeled chip layouts as the labeled dataset for the second lithography mask generation model, new labeled chip layouts will be added to this dataset later. During the initial training phase, the second lithography mask generation model can undergo one or more rounds of training using the labeled dataset, and the parameters within the model can be optimized and adjusted accordingly.

[0089] In some embodiments, the second photolithographic mask generation model is a Unet (Unity Networking) deep learning model.

[0090] Step 502: The second photolithography mask generation model after preliminary training is used to perform mask prediction on multiple unlabeled chip layouts to obtain the predicted mask map corresponding to each unlabeled chip layout.

[0091] Unlabeled chip layout refers to a chip layout for which no corresponding standard mask has been generated.

[0092] In some embodiments, after initial training on labeled chip layouts, the photolithography mask generation model performs mask prediction on multiple unlabeled chip layouts to obtain the predicted mask corresponding to each unlabeled chip layout.

[0093] In some embodiments, since there is no standard mask reference during the execution of step 502, the second photolithography mask generation model has no optimization direction or optimization target, and therefore the parameters of the second photolithography mask generation model can remain fixed in this step.

[0094] Step 503: Based on the prediction mask corresponding to each unlabeled chip layout, determine the prediction difficulty corresponding to each unlabeled chip layout.

[0095] In some embodiments, by analyzing and calculating the prediction masks corresponding to the unlabeled chip layouts, some calculation results can be obtained as indicators to measure the prediction difficulty. If there is a large (or strong) correlation between the indicator corresponding to the prediction mask and the prediction difficulty of the chip layout, the prediction difficulty corresponding to the unlabeled chip layout can be indicated based on the indicator, or the indicator can be directly used as the prediction difficulty corresponding to the unlabeled chip layout.

[0096] Step 504: Select the unlabeled chip layout that meets the prediction difficulty criteria from multiple unlabeled chip layouts as the difficult chip layout.

[0097] The term "difficult chip layout" can be understood as a chip layout that is more difficult to predict using a photolithography mask generation model to obtain a high-quality and / or design-compliant mask pattern compared to other chip layouts.

[0098] In some embodiments, an unlabeled chip layout that has a predicted difficulty threshold is selected from multiple unlabeled chip layouts as a difficult chip layout.

[0099] In some embodiments, multiple unlabeled chip layouts are sorted from highest to lowest prediction difficulty, and the first n unlabeled chip layouts are selected as difficult chip layouts; or, multiple unlabeled chip layouts are sorted from lowest to highest prediction difficulty, and the last n unlabeled chip layouts are selected as difficult chip layouts, where n is a positive integer.

[0100] In some embodiments, the unlabeled chip layout with the highest prediction difficulty is selected as the difficult chip layout (i.e., the case where n is 1).

[0101] Step 505: The first photolithography mask generation model is trained using the difficult chip layout to obtain the trained first photolithography mask generation model.

[0102] In some embodiments, since predicting high-quality mask images for difficult chip layouts is challenging, training the first lithography mask generation model using the difficult chip layout can improve the prediction accuracy of the first lithography mask generation model in a shorter time. If the first lithography mask generation model can also generate high-quality predicted mask images for difficult chip layouts, then it can also generate high-quality predicted mask images for other chip layouts.

[0103] In some embodiments, a standard mask image corresponding to a difficult-to-identify chip layout is obtained, and the difficult-to-identify chip layout is added to an existing labeled dataset to obtain an updated labeled dataset; wherein, the existing labeled dataset includes multiple labeled chip layouts; the first lithography mask generation model is trained using the updated labeled dataset to obtain a trained first lithography mask generation model. In this embodiment, after determining the difficult-to-identify chip layout, the standard mask image corresponding to the difficult-to-identify chip layout is obtained, and the difficult-to-identify chip layout is added to the existing labeled dataset as a new labeled chip layout. The newly added labeled chip layout and the previously existing labeled chip layouts are then used to generate the first lithography mask generation model. Figure 1 The first lithographic mask generation model was trained.

[0104] In some embodiments, a lithography mask generation model is trained using publicly available lithography mask datasets (GAN-OPC: Mask optimization with lithography-guided generative adversarial nets and Bentian Jiang, et al. 2020. Neural-ILT: Migrating ILT to neural networks for mask printability and complexity co-optimization. In Proceedings of the IEEE / ACM International Conference on Computer-Aided Design (ICCA'20). IEEE, 1-9.). These two datasets contain a total of 10271 chip layouts and corresponding standard mask images. The chip layouts meet the 32nm process node and certain design rules. In some embodiments, the lithography masks in the above datasets are obtained through a reverse lithography mask optimization algorithm.

[0105] In summary, the technical solution provided in this application first trains the photomask generation model using labeled chip layouts, and then selects a difficult chip layout with higher prediction difficulty from the unlabeled chip layouts to update the photomask generation model. This allows for faster improvement of the model accuracy using fewer chip layouts, thereby reducing the number of labeled chip layouts required to train the photomask generation model and saving on model training costs.

[0106] Specifically, by reducing the number of labeled chip layouts required to train the photolithography mask generation model, the financial cost of model training can be saved. On the other hand, training with difficult chip layouts can quickly improve the model accuracy of the photolithography mask generation model, thereby saving the time required for model training and improving the training efficiency of the model.

[0107] like Figure 6 As shown above, Figure 5 Step 503 in the embodiment may include the following sub-steps (5031-5033):

[0108] Step 5031: For each chip layout, obtain the target wafer pattern corresponding to the chip layout based on the standard process parameters and the predicted mask map corresponding to the chip layout.

[0109] In some embodiments, the target wafer pattern of the predicted mask corresponding to the chip layout under standard process parameters is obtained. In some embodiments, the standard process parameters include: a reference exposure (e.g., 100% exposure) and a reference defocus (e.g., 100% defocus). In some embodiments, a model is used to generate the target wafer pattern of the predicted mask corresponding to the chip layout under standard process parameters.

[0110] In some embodiments, a lithography simulation (LS) model is used to generate a target wafer pattern corresponding to the chip layout based on the standard process parameters and the predicted mask image corresponding to the chip layout. The lithography simulation model is a mathematical physics simulation model based on optical principles. In some embodiments, the wafer pattern is generated based on the lithography simulation model. Optionally, the selected process parameters (such as standard process parameters) and the mask image are first input into the lithography simulation model, which generates a light intensity distribution corresponding to the process parameters and the chip layout; then, the light intensity distribution is converted into a wafer pattern corresponding to the process parameters and the chip layout using a sigmoid function.

[0111] The lithography physical model is a Hopkins diffraction lithography physical model for a partially coherent imaging system. This model obtains the light intensity distribution I imaged on the wafer. The light intensity distribution I is obtained by convolving a mask M with a kernel function h of the lithography system. The kernel function is obtained by singular value decomposition of the cross-transfer coefficients of the lithography system (such as a 193 nm ring light source or other sizes of ring light sources). In some embodiments, the lithography physical model is defined as follows:

[0112]

[0113] Among them, h k It is the k-th kernel function after singular value decomposition, ω k This refers to the weight coefficient corresponding to the k-th kernel function. In some embodiments, the first 24 kernel functions obtained through singular value decomposition and their corresponding weight coefficients are used, i.e., K = 24.

[0114] The final image pattern on the wafer is obtained by transforming the light intensity distribution on the wafer using the following distribution function (sigmoid function):

[0115] Z(x,y)=1,I(x,y)≥I th

[0116] Z(x,y)=0, I(x,y) th

[0117] Among them, I th It can be 0.225. In some embodiments, I th It can also take values ​​within other intervals [0, 1], I th The specific values ​​can be set by relevant technical personnel according to the actual situation, and this application embodiment does not impose specific limitations on them.

[0118] Since the photolithography physical model is a simulation model, although it contains a large number of parameters and involves a significant amount of computation during the simulation process, the wafer patterns generated based on the photolithography physical model have high precision. In some embodiments, the running efficiency of the photolithography physical model is optimized through methods such as GPU (Graphics Processing Unit) acceleration.

[0119] ​In some embodiments, a deep learning model can be used to generate the target wafer pattern corresponding to the chip layout based on the standard process parameters and the predicted mask corresponding to the chip layout. The deep learning model is a machine learning model built on a neural network and is trained using a labeled dataset of mask-wafer patterns. That is, it is entirely based on machine learning, enabling the deep learning model to predict the corresponding wafer pattern based on the mask. In this approach, compared to the photolithography physical model, the deep learning model has fewer parameters, lower requirements for the computing power of the device (such as a GPU), and a faster wafer pattern generation speed, resulting in higher efficiency.

[0120] Step 5032: Determine the first error corresponding to the chip layout based on the difference between the target wafer pattern and the chip layout.

[0121] In some embodiments, the higher the predicted mask quality, the smaller the difference between the corresponding wafer pattern and the chip layout; conversely, the lower the predicted mask quality, the greater the difference between the corresponding wafer pattern and the chip layout. Therefore, the prediction difficulty corresponding to the chip layout can be represented based on a first error.

[0122] Step 5033: Determine the prediction difficulty corresponding to the chip layout based on the first error corresponding to the chip layout.

[0123] In some embodiments, a larger first error indicates a lower quality of the prediction mask, which in turn indicates a greater difficulty in predicting the chip layout; a smaller first error indicates a higher quality of the prediction mask, which in turn indicates a less difficulty in predicting the chip layout.

[0124] In some embodiments, the method may further include the following steps (1.1 to 1.3):

[0125] 1.1 For each chip layout, obtain the predicted mask based on various process parameters and the chip layout, resulting in multiple wafer patterns corresponding to the chip layout;

[0126] 1.2 Determine the second error corresponding to the chip layout based on the differences between multiple wafer patterns corresponding to the chip layout;

[0127] 1.3 Determine the prediction difficulty corresponding to the chip layout based on the first error and the second error corresponding to the chip layout.

[0128] In some embodiments, the lower the complexity of the predictive mask, the smaller the difference between wafer patterns obtained under different process parameters; conversely, the higher the complexity of the predictive mask, the greater the difference between wafer patterns obtained under different process parameters. Therefore, the complexity of the predictive mask can be determined by the difference between wafer patterns obtained using the same predictive mask under different process parameter conditions, i.e., the second error corresponding to the chip layout can be determined. In some embodiments, the second error can be directly used as the prediction difficulty of the chip layout.

[0129] In some embodiments, the above-described photolithography physical model or deep learning model can also be used to generate multiple wafer patterns corresponding to the chip layout based on various different process parameters and the predicted mask map corresponding to the chip layout.

[0130] In some embodiments, a first wafer pattern and a second wafer pattern are obtained by using a predicted mask image corresponding to the chip layout through first process parameters and second process parameters; wherein the exposure amount of the first process parameters is less than the exposure amount of the second process parameters, and the defocus of the first process parameters is less than the defocus of the second process parameters. In some embodiments, a second error corresponding to the chip layout is determined based on the difference between the first wafer pattern and the second wafer pattern.

[0131] That is, a first wafer pattern is obtained by applying a predicted mask corresponding to the chip layout to a first process parameter, and a second wafer pattern is obtained by applying a predicted mask corresponding to the chip layout to a second process parameter. In some embodiments, the exposure of the first process parameter is less than the exposure of the standard process parameter, and the defocus of the first process parameter is less than the defocus of the standard process parameter. In some embodiments, the exposure of the second process parameter is higher than the exposure of the standard process parameter, and the defocus of the second process parameter is higher than the defocus of the standard process parameter. Therefore, the first process parameter can be referred to as low exposure and low defocus, and the second process parameter can be referred to as high exposure and high defocus.

[0132] Under low exposure and low defocus conditions, many microstructures of the mask (such as holes, protrusions, and serrations) will not be exposed on the wafer (i.e., the wafer corresponding to the first wafer pattern). Under high exposure and high defocus conditions, these microstructures will be exposed on the wafer (i.e., the wafer corresponding to the second wafer pattern). Therefore, the smaller the difference between the first and second wafer patterns (i.e., the smaller the second error), the fewer microstructures and the lower the complexity of the predicted mask pattern, and the easier it is to predict the chip layout. Conversely, the greater the difference between the first and second wafer patterns (i.e., the greater the second error), the more microstructures and the higher the complexity of the predicted mask pattern, and the more difficult it is to predict the chip layout.

[0133] In an exemplary embodiment, the first process parameters include: an exposure amount of 98% of the reference exposure amount and a defocusing value of 25 nanometers. In an exemplary embodiment, the second process parameters include: an exposure amount of 102% of the reference exposure amount.

[0134] Of course, the above data are merely illustrative. The specific values ​​of exposure and defocus in the first and second process parameters can be set by relevant technical personnel according to the actual situation. This application embodiment does not impose specific limitations on this.

[0135] In some embodiments, the prediction difficulty of the chip layout is obtained by weighted summation of the first error and the second error. For example, the prediction difficulty corresponding to the chip layout can be expressed by the following formula:

[0136] Target candidate

[0137] =argmax(|Target-LS(Mask) pred )| 2 +α×|LS(Mask pred ,Pmin)-LS(Mask pred ,Pmax)| 2 )

[0138] Among them, Target candidate The argmax(|Target-LSMaskpred2) represents the prediction difficulty corresponding to the chip layout, where Target represents the chip layout and LSMaskpred represents the target wafer pattern corresponding to the chip layout (under standard process parameters); |LS(Mask pred ,Pmin)-LSMaskpred,Pmax2 represents the second error, α represents the coefficient / weight of the second error, LS(Mask pred Pmin) represents the first wafer pattern, LS(Mask) pred ,Pmax) represents the second wafer pattern.

[0139] In the above implementation, the difference between the wafer pattern of the predicted mask and the chip layout (i.e., the first error) is used to represent the prediction difficulty. The calculation of the first error is relatively convenient and quick, thereby saving the time required to obtain the difficult chip layout and thus improving the training efficiency of the photolithography mask generation model.

[0140] In addition, in the above implementation, a second error is obtained based on the difference between the wafer patterns corresponding to the predicted mask under different process parameters. The second error can be regarded as the complexity of the predicted mask. The first error and the second error are combined to determine the prediction difficulty, thereby reducing the complexity of the predicted mask generated by the photolithography mask generation model.

[0141] like Figure 7 As shown above, Figure 5 Step 503 in the embodiment may further include the following sub-steps (5034-5036):

[0142] Step 5034: For each chip layout, determine the average predicted mask of the multiple predicted mask images generated by the multiple second lithography mask generation models for the chip layout.

[0143] In some embodiments, multiple initialized second lithography mask generation models are generated; wherein different initialized second lithography mask generation models have different model parameters; each initialized second lithography mask generation model is initially trained using multiple labeled chip layouts to obtain multiple initially trained second lithography mask generation models. Here, a labeled chip layout refers to a chip layout with a corresponding standard mask image already generated. The multiple initially trained second lithography mask generation models are used to generate multiple predicted mask images corresponding to the chip layout. Since the model parameters of different initialized second lithography mask generation models are different, it is ensured that after training on the same labeled chip layout, the model parameters of the multiple second lithography mask generation models differ, and the generated predicted mask images also differ, thus obtaining different predicted mask images for the same chip layout corresponding to different second lithography mask generation models. In some embodiments, the first lithography mask generation model is the initially trained second lithography mask generation model.

[0144] In some embodiments, multiple prediction masks are of the same size, and the average value of the element values ​​at the same position in the multiple prediction masks is used as the element value at the corresponding position in the average prediction mask, thereby obtaining the average prediction mask.

[0145] Step 5035: Determine the uncertainty corresponding to the chip layout based on the difference between the multiple predicted mask images and the average predicted mask image.

[0146] In some embodiments, for each chip layout, the difference between each predicted mask image and the average predicted mask image is calculated to obtain multiple mask image differences. The determinant of the multiple mask image differences is squared and then averaged to obtain the uncertainty corresponding to the chip layout.

[0147] In some embodiments, the uncertainty can be calculated using the following formula:

[0148]

[0149] Among them, Target candidate This indicates the uncertainty corresponding to the chip layout. It is the predicted mask of the i-th second lithographic mask generation model. It is the average value of the mask predicted by multiple second lithography mask generation models. The meaning of <> is to calculate the average.

[0150] It is evident that a layout with high uncertainty implies a large deviation between the prediction results of multiple second lithography mask generation models. Therefore, a chip layout with high uncertainty can be identified as a difficult chip layout, and the difficult chip layout can be used as an important data affecting the accuracy of the model.

[0151] Step 5036: Determine the prediction difficulty corresponding to the chip layout based on the uncertainty corresponding to the chip layout.

[0152] In some embodiments, the true error of the prediction result (i.e., the prediction map) of the photolithographic mask generation model can be expressed by the following formula:

[0153]

[0154] Where Mask represents the labeled mask image obtained from the chip layout using OPC, σ true This represents the actual error.

[0155] It can be seen that the uncertainty δ is less than the true error σ. true Uncertainty provides the lower bound of the true error; that is, when the uncertainty is large, the true error will be larger than the uncertainty. Therefore, uncertainty can be used to approximate the true error, and thus uncertainty can be directly used as the prediction difficulty corresponding to the chip layout.

[0156] In some embodiments, the prediction difficulty corresponding to the chip layout can be determined based on uncertainty and a first error (e.g., by weighted summation of uncertainty and first error); it can also be determined based on uncertainty and a second error (e.g., by weighted summation of uncertainty and second error); or it can be determined based on uncertainty, a first error, and a second error (e.g., by weighted summation of uncertainty, first error, and second error). Of course, the prediction difficulty corresponding to the chip layout can also be obtained by combining other parameters, and can be specifically set by those skilled in the art according to actual conditions. This application embodiment does not specifically limit this.

[0157] In the above implementation, the use of multiple second lithography mask generation models to "vote and sample" the chip layout largely avoids random occurrences, thus making the selected difficult chip layout more accurate.

[0158] In some possible implementations, such as Figure 8 As shown, after step 505 above, the following steps (506-510) are also included:

[0159] Step 506: Use the trained first lithography mask generation model to perform mask prediction on the labeled chip layout to obtain the predicted mask map corresponding to the labeled chip layout.

[0160] In some embodiments, the trained first lithography mask generation model is based on a model trained using a first loss. After obtaining the trained first lithography mask generation model, a predicted mask image of the labeled chip layout in the labeled dataset can also be generated using the first lithography mask generation model.

[0161] Step 507: Determine the first loss based on the predicted mask and the standard mask corresponding to the labeled chip layout.

[0162] The first loss measures the difference between the predicted mask and the standard mask corresponding to the labeled chip layout. Therefore, the first loss can be determined based on the difference between the predicted mask and the standard mask corresponding to the labeled chip layout.

[0163] In some embodiments, the formula for calculating the first loss can refer to the following formula:

[0164] L1 = |Mask - Mask pred | 2

[0165] Mask represents the standard mask image corresponding to the labeled chip layout. pred This represents the predicted mask image corresponding to the labeled chip layout, and L1 represents the first loss.

[0166] Step 508: Obtain multiple wafer patterns corresponding to the labeled chip layout based on various process parameters and the predicted mask map corresponding to the labeled chip layout.

[0167] In some embodiments, multiple wafer patterns for each predicted mask image are obtained based on a variety of different process parameters by using a photolithography physical model or a deep learning model.

[0168] Step 509: Determine the second loss based on the multiple wafer patterns corresponding to the labeled chip layout.

[0169] The second loss is used to measure the consistency between multiple wafer patterns corresponding to the labeled chip layout.

[0170] In some embodiments, the consistency between multiple wafer patterns is determined by the differences between the multiple wafer patterns corresponding to the labeled chip layout. The greater the difference between the multiple wafer patterns, the worse the consistency is determined; conversely, the smaller the difference between the multiple wafer patterns, the better the consistency is determined. For example, the formula for calculating the second loss can refer to the following formula:

[0171]

[0172] Where L2 represents the second loss, LS(Mask) pred ,P i ) indicates that the predicted mask map with labeled chip layout corresponds to the wafer pattern of the i-th group of process parameters, LS(Mask) pred ,P c The symbol ) represents the reference wafer pattern corresponding to the labeled chip layout; n represents the total number of process parameters, where n is a positive integer greater than 1 and i is a positive integer less than or equal to n. The reference wafer pattern can be a wafer pattern obtained based on standard process parameters, or it can be the average wafer pattern of i wafer patterns corresponding to i sets of process parameters from the predicted mask of the labeled chip layout. This application does not specifically limit this.

[0173] Step 510: Update the trained first lithography mask generation model according to the first loss and the second loss to obtain the trained first lithography mask generation model.

[0174] In some embodiments, the trained first lithography mask generation model is updated based on the total loss obtained by weighted summation of the first loss and the second loss, to obtain the trained first lithography mask generation model.

[0175] In the above implementation, after obtaining the first photolithography mask generation model after training based on the first loss, the consistency between wafer patterns obtained under different process parameter conditions corresponding to the chip layout is considered. The first photolithography mask generation model after training is updated based on the first loss and the second loss, thereby improving the robustness of the photolithography mask generation model.

[0176] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0177] Please refer to Figure 9This diagram illustrates a block diagram of a training apparatus for a photolithographic mask generation model according to an embodiment of this application. The apparatus has the functionality to implement the above-described method example for training the photolithographic mask generation model. This functionality can be implemented in hardware or by hardware executing corresponding software. The apparatus 900 can be the model training device described above, or it can be mounted on a model training device. The apparatus 900 may include: a mask acquisition module 990, a difficulty determination module 930, a layout selection module 940, and a model update module 950.

[0178] The mask acquisition module 990 is used to acquire the predicted mask images corresponding to multiple chip layouts.

[0179] The difficulty determination module 930 is used to determine the prediction difficulty corresponding to each of the unlabeled chip layouts based on the prediction mask corresponding to each of the unlabeled chip layouts.

[0180] The layout selection module 940 is used to select from the plurality of unlabeled chip layouts the unlabeled chip layout that meets the prediction difficulty condition, as the difficult chip layout.

[0181] The model update module 950 is used to train the first photolithography mask generation model using the difficult chip layout to obtain the trained first photolithography mask generation model.

[0182] In some embodiments, such as Figure 10 As shown, the difficulty determination module 930 includes: a pattern acquisition submodule 931, an error determination submodule 932, and a difficulty determination submodule 933.

[0183] The pattern acquisition submodule 931 is used to acquire, for each chip layout, the target wafer pattern corresponding to the chip layout based on standard process parameters and the predicted mask map corresponding to the chip layout.

[0184] The error determination submodule 932 is used to determine the first error corresponding to the chip layout based on the difference between the target wafer pattern corresponding to the chip layout and the chip layout.

[0185] The difficulty determination submodule 933 is used to determine the prediction difficulty corresponding to the chip layout based on the first error corresponding to the chip layout.

[0186] In some embodiments, such as Figure 10 As shown, the device 900 further includes a pattern acquisition module 960 and an error determination module 970.

[0187] The pattern acquisition module 960 is used to acquire, for each chip layout, multiple wafer patterns corresponding to the chip layout based on various process parameters and the predicted mask map corresponding to the chip layout.

[0188] The error determination module 970 is used to determine a second error corresponding to the chip layout based on the differences between multiple wafer patterns corresponding to the chip layout.

[0189] The difficulty determination submodule 933 is used to determine the prediction difficulty corresponding to the chip layout based on the first error and the second error corresponding to the chip layout.

[0190] In some embodiments, such as Figure 10 As shown, the pattern acquisition module 960 is used to acquire the first wafer pattern and the second wafer pattern obtained by the predicted mask pattern corresponding to the chip layout through the first process parameter and the second process parameter; wherein, the exposure of the first process parameter is less than the exposure of the second process parameter, and the defocus of the first process parameter is less than the defocus of the second process parameter.

[0191] The error determination module 970 is used to determine a second error corresponding to the chip layout based on the difference between the first wafer pattern and the second wafer pattern.

[0192] In some embodiments, the mask acquisition module 990 is used to generate a target wafer pattern corresponding to the chip layout based on the standard process parameters and the predicted mask image corresponding to the chip layout using a photolithography physical model, wherein the photolithography physical model is a mathematical physics simulation model based on optical principles; or to generate a target wafer pattern corresponding to the chip layout based on the standard process parameters and the predicted mask image corresponding to the chip layout using a deep learning model, wherein the deep learning model is a machine learning model built based on neural networks.

[0193] In some embodiments, the mask acquisition module 990 is configured to:

[0194] The second photolithography mask generation model is initially trained using multiple labeled chip layouts to obtain the initially trained second photolithography mask generation model; wherein, the labeled chip layout refers to the chip layout that has already generated corresponding standard mask images;

[0195] The second photolithography mask generation model, after initial training, is used to predict the mask for the multiple chip layouts, resulting in predicted mask images corresponding to the multiple chip layouts.

[0196] In some embodiments, the difficulty determination module 930 is used for:

[0197] For each chip layout, the average predicted mask is determined based on multiple predicted mask images generated by multiple pre-trained second lithography mask generation models for the chip layout.

[0198] The uncertainty corresponding to the chip layout is determined based on the difference between the multiple predicted mask images and the average predicted mask image;

[0199] The prediction difficulty corresponding to the chip layout is determined based on the uncertainty corresponding to the chip layout.

[0200] In some embodiments, the mask acquisition module 990 is used to generate multiple predicted mask images corresponding to each chip layout using multiple second lithography mask generation models.

[0201] In some embodiments, such as Figure 10 As shown, the device 900 further includes: a model generation module 910 and a model training module 920.

[0202] The model generation module 910 is used to generate multiple initialized second photolithography mask generation models; wherein, different initialized second photolithography mask generation models have different model parameters;

[0203] The model training module 920 is used to perform preliminary training on each of the initialized second lithography mask generation models using multiple labeled chip layouts to obtain multiple pre-trained second lithography mask generation models; wherein, the labeled chip layout refers to a chip layout that has generated corresponding standard mask images; wherein, the multiple pre-trained second lithography mask generation models are used to generate multiple predicted mask images corresponding to the chip layout.

[0204] In some embodiments, the first photolithography mask generation model is the second photolithography mask generation model after initial training. In some embodiments, the model update module 950 is configured to:

[0205] Obtain the standard mask image corresponding to the difficult chip layout, and add the difficult chip layout to the existing labeled dataset to obtain the updated labeled dataset; wherein, the existing labeled dataset includes multiple labeled chip layouts, and the labeled chip layouts refer to chip layouts that have generated corresponding standard mask images;

[0206] The first lithographic mask generation model is trained using the updated labeled dataset to obtain the trained first lithographic mask generation model.

[0207] In some embodiments, such as Figure 10 As shown, the device 900 further includes a mask prediction module 995 and a loss determination module 980.

[0208] The mask prediction module 995 is used to perform mask prediction on the labeled chip layout using the trained first lithography mask generation model to obtain the predicted mask map corresponding to the labeled chip layout.

[0209] The loss determination module 980 is used to determine a first loss based on the predicted mask and the standard mask corresponding to the labeled chip layout. The first loss is used to measure the difference between the predicted mask and the standard mask corresponding to the labeled chip layout.

[0210] The pattern acquisition module 960 is used to acquire multiple wafer patterns corresponding to the labeled chip layout based on various different process parameters and the predicted mask map corresponding to the labeled chip layout.

[0211] The loss determination module 980 is further configured to determine a second loss based on the multiple wafer patterns corresponding to the labeled chip layout, wherein the second loss is used to measure the consistency among the multiple wafer patterns corresponding to the labeled chip layout.

[0212] The model update module 950 is further configured to update the trained first lithography mask generation model based on the first loss and the second loss, so as to obtain the updated first lithography mask generation model.

[0213] In summary, the technical solution provided by the embodiments of this application can quickly improve the model accuracy of the photolithography mask generation model by selecting difficult chip layouts and using them to update the photolithography mask generation model, thereby reducing the number of chip layouts required to train the photolithography mask generation model, thus saving data annotation costs and model training costs.

[0214] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0215] Please refer to Figure 11 This diagram illustrates a structural block diagram of a computer device according to an embodiment of this application. The computer device is used to implement the training method for the photolithographic mask generation model provided in the above embodiments. Specifically:

[0216] The computer device 1100 includes a CPU (Central Processing Unit) 1101, a system memory 1104 including RAM (Random Access Memory) 1102 and ROM (Read-Only Memory) 1103, and a system bus 1105 connecting the system memory 1104 and the central processing unit 1101. The computer device 1100 also includes a basic I / O (Input / Output) system 1106 that facilitates information transfer between various components within the computer, and a mass storage device 1107 for storing the operating system 1113, application programs 1114, and other program modules 1115.

[0217] The basic input / output system 1106 includes a display 1108 for displaying information and an input device 1109 for user input, such as a mouse or keyboard. Both the display 1108 and the input device 1109 are connected to the central processing unit 1101 via an input / output controller 1110 connected to the system bus 1105. The basic input / output system 1106 may also include the input / output controller 1110 for receiving and processing input from multiple other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 1110 also provides output to a display screen, printer, or other types of output devices.

[0218] The mass storage device 1107 is connected to the central processing unit 1101 via a mass storage controller (not shown) connected to the system bus 1105. The mass storage device 1107 and its associated computer-readable media provide non-volatile storage for the computer device 1100. That is, the mass storage device 1107 may include computer-readable media (not shown) such as a hard disk or a CD-ROM (Compact Disc Read-Only Memory) drive.

[0219] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include RAM, ROM, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory or other solid-state storage, CD-ROM, DVD (Digital Video Disc) or other optical storage, magnetic tape cassettes, magnetic tape, disk storage, or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage media are not limited to the above-mentioned types. The system memory 1104 and the mass storage device 1107 described above can be collectively referred to as memory.

[0220] According to various embodiments of this application, the computer device 1100 can also be connected to a remote computer on a network, such as the Internet. That is, the computer device 1100 can be connected to the network 1112 via the network interface unit 1111 connected to the system bus 1105, or the network interface unit 1111 can be used to connect to other types of networks or remote computer systems (not shown).

[0221] In an exemplary embodiment, a computer-readable storage medium is also provided, wherein a computer program is stored therein, which, when executed by a processor, implements the above-described training method for the photolithographic mask generation model.

[0222] Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives), or optical disc, etc. The random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0223] In an exemplary embodiment, a computer program product is also provided, comprising a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the training method for the photolithographic mask generation model described above.

[0224] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0225] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A training method for a photolithographic mask generation model, characterized in that, The method includes: Obtain the prediction mask images corresponding to multiple chip layouts; For each chip layout, multiple wafer patterns corresponding to the chip layout are obtained based on various process parameters and a prediction mask corresponding to the chip layout; a second error corresponding to the chip layout is determined based on the differences between the multiple wafer patterns, the second error indicating the complexity of the prediction mask; and the prediction difficulty corresponding to the chip layout is determined based on the second error. Select the chip layout that meets the predicted difficulty criteria from the plurality of chip layouts, and use it as the difficult chip layout; The first photolithography mask generation model is trained using the aforementioned difficult chip layout to obtain the trained first photolithography mask generation model.

2. The method according to claim 1, characterized in that, The method further includes: For each chip layout, obtain the target wafer pattern corresponding to the chip layout based on standard process parameters and the predicted mask image corresponding to the chip layout; Based on the difference between the target wafer pattern corresponding to the chip layout and the chip layout, a first error corresponding to the chip layout is determined; The prediction difficulty corresponding to the chip layout is determined based on the first error corresponding to the chip layout.

3. The method according to claim 2, characterized in that, The method further includes: The step of determining the prediction difficulty corresponding to the chip layout based on the first error corresponding to the chip layout includes: The prediction difficulty corresponding to the chip layout is determined based on the first error and the second error corresponding to the chip layout.

4. The method according to claim 3, characterized in that, The process of obtaining multiple wafer patterns corresponding to the chip layout based on various process parameters and the predicted mask image corresponding to the chip layout includes: The first wafer pattern and the second wafer pattern are obtained by obtaining the predicted mask pattern corresponding to the chip layout through the first process parameters and the second process parameters; wherein, the exposure of the first process parameter is less than the exposure of the second process parameter, and the defocus of the first process parameter is less than the defocus of the second process parameter. The step of determining the second error corresponding to the chip layout based on the differences between the plurality of wafer patterns includes: The second error corresponding to the chip layout is determined based on the difference between the first wafer pattern and the second wafer pattern.

5. The method according to claim 2, characterized in that, The step of obtaining the target wafer pattern corresponding to the chip layout based on standard process parameters and the predicted mask image corresponding to the chip layout includes: The target wafer pattern corresponding to the chip layout is generated by using a photolithography physical model based on the standard process parameters and the predicted mask pattern corresponding to the chip layout. The photolithography physical model is a mathematical and physical simulation model based on optical principles. or, A deep learning model is used to generate a target wafer pattern corresponding to the chip layout based on the standard process parameters and the predicted mask map corresponding to the chip layout. The deep learning model is a machine learning model built on a neural network.

6. The method according to claim 2, characterized in that, The step of obtaining the prediction mask images corresponding to the multiple chip layouts includes: The second photolithography mask generation model is initially trained using multiple labeled chip layouts to obtain the initially trained second photolithography mask generation model; wherein, the labeled chip layout refers to the chip layout that has already generated corresponding standard mask images; The second photolithography mask generation model, after initial training, is used to predict the mask for the multiple chip layouts, resulting in predicted mask images corresponding to the multiple chip layouts.

7. The method according to claim 1, characterized in that, The method further includes: For each of the chip layouts, the average predicted mask of the multiple predicted mask images generated by the multiple second lithography mask generation models for the chip layout is determined. The uncertainty corresponding to the chip layout is determined based on the difference between the multiple predicted mask images and the average predicted mask image; The prediction difficulty corresponding to the chip layout is determined based on the uncertainty corresponding to the chip layout.

8. The method according to claim 7, characterized in that, The step of obtaining the prediction mask images corresponding to the multiple chip layouts includes: For each chip layout, multiple predicted mask images corresponding to the chip layout are generated using multiple second lithography mask generation models.

9. The method according to claim 7, characterized in that, The method further includes: Multiple initialized second photolithography mask generation models are generated; wherein, different initialized second photolithography mask generation models have different model parameters; Multiple labeled chip layouts are used to perform preliminary training on each of the initialized second photolithography mask generation models to obtain multiple pre-trained second photolithography mask generation models; wherein, the labeled chip layout refers to a chip layout that has already generated a corresponding standard mask image; The multiple pre-trained second lithography mask generation models are used to generate multiple predicted mask images corresponding to the chip layout.

10. The method according to claim 6 or 9, characterized in that, The first photolithography mask generation model is the second photolithography mask generation model after the initial training.

11. The method according to any one of claims 1 to 9, characterized in that, The step of training the first photolithography mask generation model using the difficult chip layout to obtain the trained first photolithography mask generation model includes: Obtain the standard mask image corresponding to the difficult chip layout, and add the difficult chip layout to the existing labeled dataset to obtain the updated labeled dataset; wherein, the existing labeled dataset includes multiple labeled chip layouts, and the labeled chip layouts refer to chip layouts that have generated corresponding standard mask images; The first lithographic mask generation model is trained using the updated labeled dataset to obtain the trained first lithographic mask generation model.

12. The method according to any one of claims 1 to 9, characterized in that, After training the first photolithography mask generation model using the difficult chip layout to obtain the trained first photolithography mask generation model, the process further includes: The trained first lithography mask generation model is used to perform mask prediction on the labeled chip layout to obtain the predicted mask map corresponding to the labeled chip layout. The labeled chip layout refers to the chip layout that has generated a corresponding standard mask map. A first loss is determined based on the predicted mask and the standard mask corresponding to the labeled chip layout. The first loss is used to measure the difference between the predicted mask and the standard mask corresponding to the labeled chip layout. Multiple wafer patterns corresponding to the labeled chip layout are obtained by acquiring prediction mask images based on various process parameters and the labeled chip layout. A second loss is determined based on the multiple wafer patterns corresponding to the labeled chip layout. The second loss is used to measure the consistency among the multiple wafer patterns corresponding to the labeled chip layout. Based on the first loss and the second loss, the trained first lithography mask generation model is updated to obtain the updated first lithography mask generation model.

13. A training device for a photolithographic mask generation model, characterized in that, The device includes: The mask acquisition module is used to acquire the predicted mask images corresponding to multiple chip layouts; The pattern acquisition module is used to acquire, for each chip layout, multiple wafer patterns corresponding to the chip layout based on various process parameters and the predicted mask map corresponding to the chip layout. An error determination module is used to determine a second error corresponding to the chip layout based on the differences between the multiple wafer patterns, wherein the second error indicates the complexity of the predicted mask pattern; The difficulty determination module is used to determine the prediction difficulty corresponding to the chip layout based on the second error; The layout selection module is used to select a chip layout that meets the predicted difficulty criteria from the plurality of chip layouts, and use it as the difficult chip layout. The model update module is used to train the first photolithography mask generation model using the difficult chip layout to obtain the trained first photolithography mask generation model.

14. The apparatus according to claim 13, characterized in that, The difficulty determination module includes a pattern acquisition submodule, an error determination submodule, and a difficulty determination submodule; The pattern acquisition submodule is used to acquire, for each chip layout, the target wafer pattern corresponding to the chip layout based on standard process parameters and the predicted mask map corresponding to the chip layout. The error determination submodule is used to determine the first error corresponding to the chip layout based on the difference between the target wafer pattern corresponding to the chip layout and the chip layout; The difficulty determination submodule is used to determine the prediction difficulty corresponding to the chip layout based on the first error corresponding to the chip layout.

15. The apparatus according to claim 14, characterized in that, The difficulty determination submodule is used to determine the prediction difficulty corresponding to the chip layout based on the first error and the second error corresponding to the chip layout.

16. The apparatus according to claim 15, characterized in that, The pattern acquisition module is used for: The first wafer pattern and the second wafer pattern are obtained by obtaining the predicted mask pattern corresponding to the chip layout through the first process parameters and the second process parameters; wherein, the exposure of the first process parameter is less than the exposure of the second process parameter, and the defocus of the first process parameter is less than the defocus of the second process parameter. The error determination module is used for: The second error corresponding to the chip layout is determined based on the difference between the first wafer pattern and the second wafer pattern.

17. The apparatus according to claim 14, characterized in that, The mask acquisition module is used for: The target wafer pattern corresponding to the chip layout is generated by using a photolithography physical model based on the standard process parameters and the predicted mask pattern corresponding to the chip layout. The photolithography physical model is a mathematical and physical simulation model based on optical principles. or, A deep learning model is used to generate a target wafer pattern corresponding to the chip layout based on the standard process parameters and the predicted mask map corresponding to the chip layout. The deep learning model is a machine learning model built on a neural network.

18. The apparatus according to claim 14, characterized in that, The mask acquisition module is used for: The second photolithography mask generation model is initially trained using multiple labeled chip layouts to obtain the initially trained second photolithography mask generation model; wherein, the labeled chip layout refers to the chip layout that has already generated corresponding standard mask images; The second photolithography mask generation model, after initial training, is used to predict the mask for the multiple chip layouts, resulting in predicted mask images corresponding to the multiple chip layouts.

19. The apparatus according to claim 13, characterized in that, The difficulty determination module is used for: For each of the chip layouts, the average predicted mask of the multiple predicted mask images generated by the multiple second lithography mask generation models for the chip layout is determined. The uncertainty corresponding to the chip layout is determined based on the difference between the multiple predicted mask images and the average predicted mask image; The prediction difficulty corresponding to the chip layout is determined based on the uncertainty corresponding to the chip layout.

20. The apparatus according to claim 19, characterized in that, The mask acquisition module is used for: For each chip layout, multiple predicted mask images corresponding to the chip layout are generated using multiple second lithography mask generation models.

21. The apparatus according to claim 19, characterized in that, The device also includes a model generation module and a model training module; The model training module is used to generate multiple initialized second lithography mask generation models; wherein, different initialized second lithography mask generation models have different model parameters; The model training module is used to perform preliminary training on each of the initialized second lithography mask generation models using multiple labeled chip layouts to obtain multiple pre-trained second lithography mask generation models; wherein, the labeled chip layout refers to a chip layout that has already generated a corresponding standard mask image; The multiple pre-trained second lithography mask generation models are used to generate multiple predicted mask images corresponding to the chip layout.

22. The apparatus according to claim 18 or 21, characterized in that, The first photolithography mask generation model is the second photolithography mask generation model after the initial training.

23. The apparatus according to any one of claims 13 to 21, characterized in that, The model update module is used for: Obtain the standard mask image corresponding to the difficult chip layout, and add the difficult chip layout to the existing labeled dataset to obtain the updated labeled dataset; wherein, the existing labeled dataset includes multiple labeled chip layouts, and the labeled chip layouts refer to chip layouts that have generated corresponding standard mask images; The first lithographic mask generation model is trained using the updated labeled dataset to obtain the trained first lithographic mask generation model.

24. The apparatus according to any one of claims 13 to 21, characterized in that, The device further includes: a mask prediction module and a loss determination module; The mask prediction module is used to perform mask prediction on the labeled chip layout using the trained first lithography mask generation model to obtain the predicted mask map corresponding to the labeled chip layout. The labeled chip layout refers to the chip layout that has already generated a corresponding standard mask map. The loss determination module is used to determine a first loss based on the predicted mask and the standard mask corresponding to the labeled chip layout. The first loss is used to measure the difference between the predicted mask and the standard mask corresponding to the labeled chip layout. The pattern acquisition module is used to acquire multiple wafer patterns corresponding to the labeled chip layout based on various different process parameters and the predicted mask image corresponding to the labeled chip layout. The loss determination module is further configured to determine a second loss based on the multiple wafer patterns corresponding to the labeled chip layout, wherein the second loss is used to measure the consistency among the multiple wafer patterns corresponding to the labeled chip layout. The model update module is further configured to update the trained first lithography mask generation model based on the first loss and the second loss, so as to obtain the updated first lithography mask generation model.

25. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program, which is loaded and executed by the processor to implement the training method for the photolithographic mask generation model as described in any one of claims 1 to 12.

26. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the training method for the photolithographic mask generation model as described in any one of claims 1 to 12.

27. A computer program product, characterized in that, The computer program product includes a computer program stored in a computer-readable storage medium, and a processor reads from and executes the computer program to implement the training method for the photolithography mask generation model as described in any one of claims 1 to 12.

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