A delay-locked loop, clock synchronization circuit, and memory

Abstract

This disclosure provides a delay-locked loop (DLL), a clock synchronization circuit, and a memory. The DLL includes: a clock generation module configured to generate a first clock signal and a second clock signal; a first delay line configured to perform duty cycle adjustment, delay processing, and phase adjustment processing on the first clock signal to obtain a first synchronous clock signal; a second delay line configured to perform duty cycle adjustment, delay processing, and phase adjustment processing on the second clock signal to obtain a second synchronous clock signal; and a phase splitting module configured to receive the first and second synchronous clock signals and perform phase splitting processing on the first and second synchronous clock signals to obtain a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal. Thus, this embodiment of the DLL has a smaller number of delay lines, which not only reduces circuit area but also improves signal phase error.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more particularly to a delay phase-locked loop, a clock synchronization circuit, and a memory. Background Technology

[0002] In Dynamic Random Access Memory (DRAM), a delay-locked loop (DLL) needs to synchronize four-phase clock signals (i.e., four clock signals with phases 90 degrees out of phase) for subsequent data sampling. Specifically, a DLL requires at least four delay lines to calibrate the four-phase clock signals separately. This not only increases the manufacturing cost of the circuit but also makes it prone to phase errors due to delay line mismatch, thus reducing memory performance. Summary of the Invention

[0003] This disclosure provides a delay phase-locked loop, a clock synchronization circuit, and a memory. The delay phase-locked loop reduces the number of delay lines, thereby reducing circuit area and improving signal phase error.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a delayed phase-locked loop, the delayed phase-locked loop comprising:

[0006] The clock generation module is configured to generate a first clock signal and a second clock signal;

[0007] The first delay line is configured to receive the first clock signal, and perform duty cycle adjustment, delay processing and phase adjustment processing on the first clock signal to obtain the first synchronous clock signal.

[0008] The second delay line is configured to receive the second clock signal, perform duty cycle adjustment, delay processing, and phase adjustment processing on the second clock signal to obtain a second synchronous clock signal; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 90 degrees.

[0009] The phase splitting module is configured to receive the first synchronous clock signal and the second synchronous clock signal; perform phase splitting processing on the first synchronous clock signal and the second synchronous clock signal to obtain a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal, wherein the phases of the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal are sequentially 90 degrees apart.

[0010] In some embodiments, the clock generation module includes:

[0011] A clock conversion module is configured to output a clock signal to be processed based on a pair of differential clock signals; wherein the frequency of the clock signal to be processed is the same as the frequency of the differential clock signals; a clock preprocessing module is configured to receive the clock signal to be processed, perform frequency division and phase shifting processing on the clock signal to be processed, and output a first clock signal and a second clock signal; wherein the frequency of the first clock signal is the same as the frequency of the second clock signal, and the frequency of the first clock signal is half the frequency of the clock signal to be processed.

[0012] In some embodiments, the first delay line includes:

[0013] A first duty cycle adjustment module is configured to receive a first duty cycle control signal and a first clock signal, adjust the duty cycle of the first clock signal based on the first duty cycle control signal, and output a first intermediate clock signal; a first coarse adjustment delay module is configured to receive a coarse adjustment control signal and the first intermediate clock signal, delay the first intermediate clock signal based on the coarse adjustment control signal, and output a second intermediate clock signal; a first fine adjustment delay module is configured to receive a fine adjustment control signal and the second intermediate clock signal, delay the second intermediate clock signal based on the fine adjustment control signal, and output a third intermediate clock signal; a second duty cycle adjustment module is configured to receive a second duty cycle control signal and the third intermediate clock signal, adjust the duty cycle of the third intermediate clock signal based on the second duty cycle control signal, and output a fourth intermediate clock signal; a first phase adjustment module is configured to receive a quadrature phase adjustment signal and the fourth intermediate clock signal, adjust the phase of the fourth intermediate clock signal based on the quadrature phase adjustment signal, and output a first synchronization clock signal.

[0014] In some embodiments, the second delay line includes:

[0015] A third duty cycle adjustment module is configured to receive a first duty cycle control signal and a second clock signal, adjust the duty cycle of the second clock signal based on the first duty cycle control signal, and output a fifth intermediate clock signal; a second coarse adjustment delay module is configured to receive a coarse adjustment control signal and the fifth intermediate clock signal, delay the fifth intermediate clock signal based on the coarse adjustment control signal, and output a sixth intermediate clock signal; a second fine adjustment delay module is configured to receive a fine adjustment control signal and the sixth intermediate clock signal, delay the sixth intermediate clock signal based on the fine adjustment control signal, and output a seventh intermediate clock signal; a fourth duty cycle adjustment module is configured to receive a second duty cycle control signal and the seventh intermediate clock signal, adjust the duty cycle of the seventh intermediate clock signal based on the second duty cycle control signal, and output an eighth intermediate clock signal; a second phase adjustment module is configured to receive a quadrature phase adjustment signal and the eighth intermediate clock signal, adjust the phase of the eighth intermediate clock signal based on the quadrature phase adjustment signal, and output a second synchronization clock signal.

[0016] In some embodiments, the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are used for data sampling processing after passing through a corresponding clock distribution network; the delay phase-locked loop further includes a third delay line and a replication delay module, the third delay line having the same structure as the first delay line, and the replication delay module being at least based on the clock distribution network; the third delay line is configured to receive the first clock signal, perform duty cycle adjustment processing, delay processing, and phase adjustment processing on the first clock signal, and output a replication clock signal; wherein the replication clock signal has the same waveform as the first synchronization clock signal; the replication delay module is configured to receive the replication clock signal, perform delay processing on the replication clock signal, and output a feedback clock signal; wherein the feedback clock signal has the same waveform as the first target clock signal after passing through the clock distribution network.

[0017] In some embodiments, the delay phase-locked loop further includes:

[0018] The delay control module is configured to receive the first clock signal and the feedback clock signal, and output the coarse adjustment control signal and the fine adjustment control signal; the duty cycle control module is configured to receive the replicated clock signal, and output the first duty cycle control signal and the second duty cycle control signal; the quadrature phase control module is configured to receive the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal, and output the quadrature phase adjustment signal.

[0019] In some embodiments, the delay control module includes:

[0020] A time-to-digital conversion module is configured to receive the first clock signal and the feedback clock signal, and output the initial value of the coarse adjustment control signal based on the first clock signal and the feedback clock signal; a phase difference detection module is configured to receive the first clock signal and the feedback clock signal, detect the phase difference between the first clock signal and the feedback clock signal, and output a phase detection signal; a coarse adjustment logic module is configured to receive the phase detection signal and the initial value of the coarse adjustment control signal, and update the initial value of the coarse adjustment control signal based on the phase detection signal; a fine adjustment logic module is configured to receive the phase detection signal and output the fine adjustment control signal based on the phase detection signal.

[0021] In some embodiments, the duty cycle control module includes:

[0022] A duty cycle detection module is configured to receive the replicated clock signal, perform duty cycle detection on the replicated clock signal, and output a duty cycle detection signal; a first duty cycle logic module is configured to receive the duty cycle detection signal and output a first duty cycle control signal based on the duty cycle detection signal; a second duty cycle logic module is configured to receive the duty cycle detection signal and output a second duty cycle control signal based on the duty cycle detection signal.

[0023] In some embodiments, the quadrature phase control module includes:

[0024] The quadrature phase detection module is configured to perform phase detection on the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal to obtain a quadrature detection signal; the quadrature phase logic module is configured to receive the quadrature detection signal and output a second duty cycle control signal based on the quadrature detection signal.

[0025] In some embodiments, the clock preprocessing module includes a first controllable NOT gate unit, a second controllable NOT gate unit, a third controllable NOT gate unit, and a fourth controllable NOT gate unit connected sequentially. A first data holding unit is provided between the output terminals of the first and third controllable NOT gate units, and a second data holding unit is provided between the output terminals of the second and fourth controllable NOT gate units. In the first controllable NOT gate unit, both a first control terminal and a second control terminal receive the clock signal to be processed. In the second controllable NOT gate unit, the first control terminal receives the inverted signal of the clock signal to be processed, and the second control terminal receives the clock signal to be processed. In the third controllable NOT gate unit, the first control terminal receives the clock signal to be processed, and the second control terminal receives the inverted signal of the clock signal to be processed. In the fourth controllable NOT gate unit, the first control terminal receives the inverted signal of the clock signal to be processed, and the second control terminal receives the clock signal to be processed. The output terminal of the third controllable NOT gate unit is used to output the second clock signal, and the output terminal of the fourth controllable NOT gate unit is used to output the first clock signal.

[0026] In some embodiments, the duty cycle detection module includes:

[0027] An inversion processing module is configured to receive the replicated clock signal and output a first signal and a second signal based on the replicated clock signal; wherein the phase difference between the first signal and the second signal is 180 degrees; a conversion module is configured to receive the first signal and the second signal, convert the first signal into a first voltage, and convert the second signal into a second voltage; a filtering module is configured to receive the first voltage and the second voltage, perform filtering processing on the first voltage and the second voltage, and output a first target voltage and a second target voltage; a comparison module is configured to receive the first target voltage and the second target voltage, compare the first target voltage and the second target voltage, and output the duty cycle detection signal.

[0028] In some embodiments, any one of the first duty cycle adjustment module, the second duty cycle adjustment module, the third duty cycle adjustment module, and the fourth duty cycle adjustment module is referred to as a duty cycle adjustment module; wherein, the duty cycle adjustment module includes multiple adjustment modules, and the multiple adjustment modules are connected in series; each adjustment module includes a range selection unit and multiple fifth adjustable NOT gate units, and the range selection unit and the multiple fifth adjustable NOT gate units are connected in parallel; the first duty cycle control signal includes a first range signal and a first control signal, and the second duty cycle control signal includes a second range signal and multiple second control signals; if the adjustment module belongs to the first duty cycle adjustment module or the third duty cycle adjustment module, the range selection unit is controlled by the first range signal, and the fifth adjustable NOT gate unit is controlled by the first control signal; if the adjustment module belongs to the second duty cycle adjustment module or the fourth duty cycle adjustment module, the range selection unit is controlled by the second range signal, and the fifth adjustable NOT gate unit is controlled by the second control signal.

[0029] In some embodiments, the phase-splitting module includes:

[0030] The first phase-splitting module is configured to receive the first synchronous clock signal, perform phase-splitting processing on the first synchronous clock signal, and output the first target clock signal and the third target clock signal; the second phase-splitting module is configured to receive the second synchronous clock signal, perform phase-splitting processing on the second synchronous clock signal, and output the second target clock signal and the fourth target clock signal.

[0031] In some embodiments, the first phase-splitting module includes a first phase-splitting link and a second phase-splitting link, with a third data holding unit disposed between the first phase-splitting link and the second phase-splitting link; the input terminals of both the first and second phase-splitting links are used to receive the first synchronization clock signal; the output terminal of the first phase-splitting link is used to output the first target clock signal, and the output terminal of the second phase-splitting link is used to output the third target clock signal; the second phase-splitting module includes a third phase-splitting link and a fourth phase-splitting link, with a fourth data holding unit disposed between the third and fourth phase-splitting links; the input terminals of both the third and fourth phase-splitting links are connected to receive the second synchronization clock signal; the output terminal of the third phase-splitting link is used to output the second target clock signal, and the output terminal of the fourth phase-splitting link is used to output the fourth target clock signal; wherein the first phase-splitting link and the third phase-splitting link have the same structure, and the second and fourth phase-splitting links have the same structure.

[0032] Secondly, embodiments of this disclosure provide a clock synchronization circuit, which includes a delay-locked loop (PLL) and a data module as described in the first aspect, wherein a first clock distribution network, a second clock distribution network, a third clock distribution network, and a fourth clock distribution network are provided between the PLL and the data module; wherein...

[0033] The delay phase-locked loop is configured to generate a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal, wherein the phases of the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are sequentially 90 degrees apart;

[0034] The data module is configured to receive the first target clock signal through the first clock distribution network, receive the second target clock signal through the second clock distribution network, receive the third target clock signal through the third clock distribution network, receive the fourth target clock signal through the fourth clock distribution network, and perform data sampling processing using the received signals.

[0035] Thirdly, embodiments of this disclosure provide a memory that includes at least the clock synchronization circuit described in the second aspect.

[0036] This disclosure provides a delay-locked loop (DLL), a clock synchronization circuit, and a memory. The DLL includes: a clock generation module configured to generate a first clock signal and a second clock signal; a first delay line configured to receive the first clock signal and perform duty cycle adjustment, delay processing, and phase adjustment processing on the first clock signal to obtain a first synchronous clock signal; a second delay line configured to receive the second clock signal and perform duty cycle adjustment, delay processing, and phase adjustment processing on the second clock signal to obtain a second synchronous clock signal; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 90 degrees; and a phase splitting module configured to receive the first synchronous clock signal and the second synchronous clock signal, and perform phase splitting processing on the first synchronous clock signal and the second synchronous clock signal to obtain a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal, wherein the phases of the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal differ by 90 degrees sequentially. Thus, the DLL provided by this disclosure reduces the number of delay lines, which not only reduces circuit area and manufacturing costs but also improves the phase error caused by delay line mismatch. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a delay phase-locked loop provided in an embodiment of the present disclosure;

[0038] Figure 2 This is a schematic diagram of a specific structure of a delay phase-locked loop provided in an embodiment of the present disclosure;

[0039] Figure 3 This is a schematic diagram of the structure of the clock preprocessing module provided in an embodiment of this disclosure;

[0040] Figure 4 A partial structural diagram of the clock preprocessing module provided in an embodiment of this disclosure;

[0041] Figure 5 This is a schematic diagram of the duty cycle detection module provided in an embodiment of the present disclosure;

[0042] Figure 6 This is a schematic diagram of the duty cycle adjustment module provided in an embodiment of the present disclosure;

[0043] Figure 7 This is a schematic diagram of the structure of the range selection unit provided in an embodiment of the present disclosure;

[0044] Figure 8 A schematic diagram of the structure of the fifth adjustable NOT gate unit provided in the embodiments of this disclosure;

[0045] Figure 9 This is a schematic diagram of the structure of the phase-splitting unit provided in an embodiment of the present disclosure;

[0046] Figure 10 This is a schematic diagram of a clock synchronization circuit provided in an embodiment of the present disclosure;

[0047] Figure 11 A schematic diagram of a delay phase-locked loop provided for related technologies;

[0048] Figure 12 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0049] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0050] Dynamic Random Access Memory (DRAM)

[0051] Synchronous Dynamic Random Access Memory (SDRAM)

[0052] Double Data Rate SDRAM (DDR)

[0053] 5th generation DDR standard (DDR5 Specification, DDR5 SPEC)

[0054] A Delay Locked Loop (DLL) is developed from a Phase Locked Loop (PLL), primarily replacing the PLL's oscillator circuit with an adjustable delay line of a first-order system. Compared to a PLL, a DLL offers advantages such as stability and faster locking speed. DLLs are commonly used in the clock synchronization circuit of DDR5, which synchronizes the read clock from the system with the internal data synchronization signal (DQS). The clock synchronization circuit first divides and phase-shifts the differential clock from the system to generate a four-phase clock signal. This four-phase clock signal is then synchronized by the DLL circuit, calibrating the adjacent phase difference between the four phases to 90 degrees. In this way, the DDR5 data receiver uses the calibrated four-phase clock signal to alternately sample the data, which helps reduce inter-symbol interference (ISI) and improve signal integrity.

[0055] DLLs can be divided into analog DLLs and digital DLLs. Because analog DLL circuits have a slower locking speed, digital DLL circuits are commonly used for phase-locked loops (PLLs) in DDR5. The adjustable delay lines of digital DLLs use cascaded coarse and fine delay lines. Coarse delay lines often use NAND gates as delay units, while fine delay lines often use phase interpolation techniques to achieve signal delay. It should be understood that to meet the resolution requirements of phase interpolation, the delay of the coarse delay unit cannot be set too large. Therefore, to achieve a wider frequency adjustment range, the number of coarse delay units inevitably increases, resulting in the adjustable delay lines occupying a relatively large circuit area.

[0056] In related technologies, delay-locked loops are equipped with an adjustable delay line for each of the four-phase clocks, resulting in a larger circuit area, increased manufacturing costs, and increased phase errors caused by delay line mismatch.

[0057] Based on this, the delay-locked loop includes: a clock generation module configured to generate a first clock signal and a second clock signal; a first delay line configured to receive the first clock signal and perform duty cycle adjustment, delay processing, and phase adjustment processing on the first clock signal to obtain a first synchronous clock signal; a second delay line configured to receive the second clock signal and perform duty cycle adjustment, delay processing, and phase adjustment processing on the second clock signal to obtain a second synchronous clock signal; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 90 degrees; and a phase splitting module configured to receive the first synchronous clock signal and the second synchronous clock signal; perform phase splitting processing on the first synchronous clock signal and the second synchronous clock signal to obtain a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal, wherein the phases of the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal differ by 90 degrees sequentially. Thus, the delay-locked loop provided in this embodiment reduces the number of delay lines, which not only reduces circuit area and manufacturing costs but also improves the phase error caused by delay line mismatch.

[0058] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0059] In one embodiment of this disclosure, see Figure 1 This illustrates a schematic diagram of the structure of a delay phase-locked loop 10 provided in an embodiment of this disclosure. Figure 1 As shown, the delay phase-locked loop 10 includes:

[0060] Clock generation module 11 is configured to generate a first clock signal and a second clock signal;

[0061] The first delay line 12 is configured to receive the first clock signal, perform duty cycle adjustment, delay processing and phase adjustment processing on the first clock signal to obtain the first synchronous clock signal;

[0062] The second delay line 13 is configured to receive the second clock signal, perform duty cycle adjustment, delay processing and phase adjustment processing on the second clock signal to obtain the second synchronous clock signal; wherein, the phase difference between the first synchronous clock signal and the second synchronous clock signal is 90 degrees.

[0063] The phase-splitting module is configured to receive a first synchronous clock signal and a second synchronous clock signal; perform phase-splitting processing on the first synchronous clock signal and the second synchronous clock signal to obtain a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal, and the phases of the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal are successively 90 degrees apart.

[0064] It should be noted that the delay phase-locked loop 10 of this embodiment can be applied to memory, such as DRAM, SDRAM, etc.

[0065] The delay-locked loop 10 includes at least two delay lines and a phase-splitting module. The two delay lines synchronize two clock signals respectively, and then phase-splitting processing is performed to generate four-phase clock signals: a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal. In this way, the delay-locked loop 10 reduces the number of delay lines from four to two, which not only reduces the circuit area and manufacturing cost but also improves the phase error caused by delay line mismatch.

[0066] It should be noted that the phase difference limits in this disclosure are all subject to a certain margin of error. Specifically, the phase difference between the first and second synchronous clock signals is 90 degrees within the allowable error range; the phases of the first, second, third, and fourth target clock signals differ by 90 degrees sequentially within the allowable error range. Subsequent limitations regarding phase values, signal alignment, or identical signal waveforms all refer to limits within the allowable error range.

[0067] In some embodiments, such as Figure 2 As shown, the clock generation module 11 includes:

[0068] The clock conversion module 111 is configured to output a clock signal to be processed based on a pair of differential clock signals; wherein the frequency of the clock signal to be processed is the same as the frequency of the differential clock signals.

[0069] The clock preprocessing module 112 is configured to receive a clock signal to be processed, perform frequency division and phase shifting processing on the clock signal to be processed, and output a first clock signal and a second clock signal; wherein the frequency of the first clock signal is the same as the frequency of the second clock signal, and the frequency of the first clock signal is half the frequency of the clock signal to be processed.

[0070] It should be noted that the differential clock signal received by the clock conversion module 111 is sent by the system to the memory. The differential clock signal is divided and phase-shifted to form the first clock signal clk0 and the second clock signal clk90. At this time, the first clock signal clk0 and the second clock signal clk90 are essentially a pair of differential clock signals, but the frequency is reduced by half. Moreover, they have better stability than the differential clock signal sent directly by the system, which can improve the harmonic lock-in problem in the subsequent processing.

[0071] In some embodiments, such as Figure 2 As shown, the first delay line 12 includes:

[0072] The first duty cycle adjustment module 121 is configured to receive a first duty cycle control signal and a first clock signal clk0, perform duty cycle adjustment processing on the first clock signal clk0 based on the first duty cycle control signal, and output a first intermediate clock signal.

[0073] The first coarse adjustment delay module 122 is configured to receive a coarse adjustment control signal and a first intermediate clock signal, perform delay processing on the first intermediate clock signal based on the coarse adjustment control signal, and output a second intermediate clock signal.

[0074] The first fine-tuning delay module 123 is configured to receive a fine-tuning control signal and a second intermediate clock signal, perform delay processing on the second intermediate clock signal based on the fine-tuning control signal, and output a third intermediate clock signal.

[0075] The second duty cycle adjustment module 124 is configured to receive a second duty cycle control signal and a third intermediate clock signal, perform duty cycle adjustment processing on the third intermediate clock signal based on the second duty cycle control signal, and output a fourth intermediate clock signal.

[0076] The first phase adjustment module 125 is configured to receive the quadrature phase adjustment signal and the fourth intermediate clock signal, perform phase adjustment processing on the fourth intermediate clock signal based on the quadrature phase adjustment signal, and output the first synchronization clock signal Clk0.

[0077] It should be noted that the second delay line has a similar structure to the first delay line. Specifically, as shown below... Figure 2 As shown, the second delay line 13 includes:

[0078] The third duty cycle adjustment module 131 is configured to receive the first duty cycle control signal and the second clock signal clk90, perform duty cycle adjustment processing on the second clock signal clk90 based on the first duty cycle control signal, and output the fifth intermediate clock signal.

[0079] The second coarse adjustment delay module 132 is configured to receive a coarse adjustment control signal and a fifth intermediate clock signal, perform delay processing on the fifth intermediate clock signal based on the coarse adjustment control signal, and output a sixth intermediate clock signal.

[0080] The second fine-tuning delay module 133 is configured to receive a fine-tuning control signal and a sixth intermediate clock signal, perform delay processing on the sixth intermediate clock signal based on the fine-tuning control signal, and output a seventh intermediate clock signal.

[0081] The fourth duty cycle adjustment module 134 is configured to receive the second duty cycle control signal and the seventh intermediate clock signal, perform duty cycle adjustment processing on the seventh intermediate clock signal based on the second duty cycle control signal, and output the eighth intermediate clock signal.

[0082] The second phase adjustment module 135 is configured to receive the quadrature phase adjustment signal and the eighth intermediate clock signal, perform phase adjustment processing on the eighth intermediate clock signal based on the quadrature phase adjustment signal, and output the second synchronization clock signal Clk90.

[0083] It should be noted that the first coarse adjustment delay module 122 / the second coarse adjustment delay module 132 can be composed of multiple cascaded delay units, and the first fine adjustment delay module 123 / the second fine adjustment delay module 133 can be implemented by phase interpolation technology.

[0084] It should be noted that the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are ultimately used for data sampling after subsequent transmission. In some embodiments, such as... Figure 2 As shown, the memory also includes a data module, and four clock distribution networks are set between the delay phase-locked loop and the data module. The first target clock signal CLK0, the second target clock signal CLK90, the third target clock signal CLK180 and the fourth target clock signal CLK270 reach the data module after passing through the corresponding clock distribution networks to realize data sampling processing.

[0085] For the delay phase-locked loop 10, the delay processing is used to ensure that the waveforms of the first synchronous clock signal Clk0 (and the second synchronous clock signal Clk90) and the corresponding clock signals used for data sampling are consistent. The duty cycle adjustment processing is used to ensure that the duty cycle of the clock signals used for data sampling is within a preset range. The phase adjustment processing is used to ensure that the first synchronous clock signal Clk0 and the second synchronous clock signal Clk90 are in an orthogonal state, thereby ensuring that the deviation between the four phase clock signals used for data sampling is 90 degrees in sequence.

[0086] Therefore, the first duty cycle adjustment module 121 and the third duty cycle adjustment module 131 can receive the same first duty cycle control signal, the first coarse adjustment delay module 122 and the second coarse adjustment delay module 132 can receive the same coarse adjustment control signal, the first fine adjustment delay module 123 and the second fine adjustment delay module 133 can receive the same fine adjustment control signal, and the second duty cycle adjustment module 124 and the fourth duty cycle adjustment module 134 can receive the same second duty cycle control signal. Specifically, since the first phase adjustment module 125 and the second phase adjustment module 135 essentially need to calibrate the phase deviation between the first clock signal clk0 and the second clock signal clk90, the quadrature phase adjustment signal received by the first phase adjustment module 125 and the quadrature phase adjustment signal received by the second phase adjustment module 135 may be different, thereby ensuring that the phase difference between the first synchronous clock signal Clk0 and the second synchronous clock signal Clk90 is 90 degrees.

[0087] In some embodiments, the delay phase-locked loop 10 further includes a third delay line 15 and a replication delay module 16. The third delay line 15 has the same structure as the first delay line 13, as shown below. Figure 2 As shown, the third delay line 15 includes a fifth duty cycle adjustment module, a third coarse delay adjustment module, a third fine delay adjustment module, a sixth duty cycle adjustment module, and a third phase adjustment module. The replication delay module 16 is at least based on the clock distribution network. That is, the replication delay module 16 is used to simulate the delay between the first synchronization clock signal Clk0 and the corresponding clock signal received by the data module (including but not limited to the delay caused by the clock distribution network).

[0088] The third delay line 15 is configured to receive the first clock signal clk0, perform duty cycle adjustment, delay processing and phase adjustment processing on the first clock signal clk0, and output a copy clock signal Clk_D; wherein the waveform of the copy clock signal Clk_D is the same as that of the first synchronization clock signal Clk0.

[0089] The replication delay module 16 is configured to receive the replication clock signal Clk_D, delay the replication clock signal Clk_D, and output a feedback clock signal FBCLK; wherein, the waveform of the feedback clock signal FBCLK is the same as that of the first target clock signal CLK0 after passing through the clock distribution network.

[0090] As mentioned earlier, since the rising edges of the first synchronization clock signal Clk0 and the first clock signal clk0 need to be consistent, a feedback adjustment strategy is required. Therefore, by introducing a third delay line 15, a feedback clock signal FBCLK (with the same waveform as the clock signal ultimately used for data sampling) is formed. The feedback clock signal FBCLK and the first clock signal clk0 are used to determine the coarse adjustment control signal and the fine adjustment control signal, forming an overall delay adjustment loop. Similarly, a replication delay module 16 is introduced to form a replication clock signal Clk_D (with the same waveform as the first synchronization clock signal Clk0). The duty cycle adjustment signal is determined based on the duty cycle of the replication clock signal Clk_D, forming a duty cycle adjustment loop. In particular, the introduction of the third delay line 15 and the replication delay module 16 can bring the following advantages: after the memory enters a stable operating state, the replication clock signal Clk_D can be frequency divided, thereby reducing the update frequency of the coarse adjustment control signal / fine adjustment control signal / first duty cycle signal / second duty cycle signal, avoiding signal jitter caused by signal glitches, and reducing power consumption.

[0091] In addition, in the phase adjustment process, the first target clock signal CLK0, the second target clock signal CLK90, the third target clock signal CLK180 and the fourth target clock signal CLK270 are used as feedback signals to determine the quadrature adjustment signal without the need to introduce additional modules.

[0092] Specifically, in some embodiments, such as Figure 2 As shown, the delay phase-locked loop 10 also includes:

[0093] The delay control module 17 is configured to receive the first clock signal clk0 and the feedback clock signal FBCLK, and output coarse adjustment control signal and fine adjustment control signal;

[0094] Duty cycle control module 18 is configured to receive the copy clock signal Clk_D and output a first duty cycle control signal and a second duty cycle control signal;

[0095] The quadrature phase control module 19 is configured to receive the first target clock signal CLK0, the second target clock signal CLK90, the third target clock signal CLK180 and the fourth target clock signal CLK270, and output the quadrature phase adjustment signal.

[0096] In some embodiments, such as Figure 2 As shown, the delay control module 17 includes:

[0097] The time-to-digital conversion module 171 is configured to receive a first clock signal clk0 and a feedback clock signal FBCLK, and output the initial value of the coarse adjustment control signal based on the first clock signal clk0 and the feedback clock signal FBCLK.

[0098] The phase difference detection module 172 is configured to receive a first clock signal clk0 and a feedback clock signal FBCLK, detect the phase difference between the first clock signal clk0 and the feedback clock signal FBCLK, and output a phase detection signal; here, the phase detection signal indicates that the first clock signal clk0 leads the feedback clock signal FBCLK, or the first clock signal clk0 lags the feedback clock signal FBCLK.

[0099] The coarse adjustment logic module 173 is configured to receive the initial values ​​of the phase detection signal and the coarse adjustment control signal, and update the initial value of the coarse adjustment control signal based on the phase detection signal.

[0100] The fine-tuning logic module 174 is configured to receive the phase detection signal and output the fine-tuning control signal based on the phase detection signal.

[0101] Thus, the time-to-digital conversion module 171 first generates an initial value for the coarse adjustment control signal and presets this initial value in the coarse adjustment logic module 173, thereby generating an initial delay. The phase difference detection module 172 detects the phase difference between the first clock signal clk0 and the feedback clock signal FBCLK in real time, forming a phase detection signal. The coarse adjustment logic module 173 updates the coarse adjustment control signal based on the phase detection signal until the phase difference between the first clock signal clk0 and the second clock signal clk90 is less than a first preset range, locking the coarse adjustment control signal to complete the coarse adjustment stage. After the coarse adjustment stage is completed, the fine adjustment logic module 174 starts working, generating a corresponding fine adjustment control signal based on the real-time phase detection signal until the phase difference between the first clock signal clk0 and the second clock signal clk90 is less than a second preset range, locking the fine adjustment control signal to complete the fine adjustment stage. After the fine adjustment stage is completed, the duty cycle control module 18 and the quadrature phase control module 19 start working to complete the duty cycle adjustment process and the phase adjustment process.

[0102] In some embodiments, such as Figure 2 As shown, the duty cycle control module 18 includes:

[0103] The duty cycle detection module 181 is configured to receive the copy clock signal Clk_D, perform duty cycle detection on the copy clock signal Clk_D, and obtain a duty cycle detection signal; wherein, the duty cycle detection signal indicates that the duty cycle of the first clock signal clk0 is greater than 50%, or the duty cycle of the first clock signal clk0 is less than 50%.

[0104] The first duty cycle logic module 182 is configured to receive a duty cycle detection signal and output a first duty cycle control signal based on the duty cycle detection signal.

[0105] The second duty cycle logic module 183 is configured to receive a duty cycle detection signal and output a second duty cycle control signal based on the duty cycle detection signal.

[0106] In this way, by adjusting the duty cycle, the duty cycle of the clock signal used for data sampling is ensured to meet the requirements.

[0107] In some embodiments, such as Figure 2 As shown, the quadrature phase control module 19 includes:

[0108] The quadrature phase detection module 191 is configured to perform phase detection on the first target clock signal CLK0, the second target clock signal CLK90, the third target clock signal CLK180, and the fourth target clock signal CLK270 to obtain a quadrature detection signal. Here, the quadrature detection signal indicates that the phase difference between the first target clock signal CLK0 and the second target clock signal CLK90 is less than 90 degrees, or the phase difference between the first target clock signal CLK0 and the second target clock signal CLK90 is greater than 90 degrees.

[0109] The quadrature phase logic module 192 is configured to receive a quadrature detection signal and output a second duty cycle control signal based on the quadrature detection signal.

[0110] In this way, through phase adjustment processing, the phase difference between the first target clock signal CLK0, the second target clock signal CLK90, the third target clock signal CLK180 and the fourth target clock signal CLK270 is guaranteed to be 90 degrees in sequence within the allowable error range.

[0111] The specific components of each of the aforementioned modules can be designed according to the circuit functions to be implemented. They are not limited to a fixed implementation scheme, and there are a variety of mature circuit modules to choose from.

[0112] The following provides only illustrative examples of the specific configuration of some circuit modules.

[0113] like Figure 3 As shown, the clock preprocessing module 112 includes a first controllable NOT gate unit 201, a second controllable NOT gate unit 202, a third controllable NOT gate unit 203, and a fourth controllable NOT gate unit 204 connected sequentially. A first data holding unit 205 is provided between the output terminals of the first controllable NOT gate unit 201 and the third controllable NOT gate unit 203, and a second data holding unit 206 is provided between the output terminals of the second controllable NOT gate unit 202 and the fourth controllable NOT gate unit 204.

[0114] In the first controllable NOT gate unit 201, both the first control terminal and the second control terminal receive the clock signal PClk to be processed; in the second controllable NOT gate unit 202, the first control terminal receives the inverted signal PClkB of the clock signal to be processed, and the second control terminal receives the clock signal PClk to be processed; in the third controllable NOT gate unit 203, the first control terminal receives the clock signal PClk to be processed, and the second control terminal receives the inverted signal PClkB of the clock signal to be processed; in the fourth controllable NOT gate unit 204, the first control terminal receives the inverted signal PClkB of the clock signal to be processed, and the second control terminal receives the clock signal PClk to be processed.

[0115] The output of the third controllable NOT gate unit 203 is used to output the second clock signal clk90, and the output of the fourth controllable NOT gate unit 204 is used to output the first clock signal clk0.

[0116] It should be noted that, as Figure 3 As shown, the first data holding unit 205 and the second data holding unit 206 have the same structure, both consisting of two NOT gates connected end to end, which serve to hold the data.

[0117] The first controllable NOT gate unit 201, the second controllable NOT gate unit 202, the third controllable NOT gate unit 203, and the fourth controllable NOT gate unit 204 have the same structure. For example... Figure 4 As shown, each controllable NOT gate unit includes two P-type field-effect transistors (PMOS) and two N-type field-effect transistors (NMOS). Please refer to the specific connection structure. Figure 4 .exist Figure 4 In this context, VDD refers to the power signal, and GND refers to the ground signal.

[0118] In some embodiments, such as Figure 5 As shown, the duty cycle detection module 181 includes:

[0119] The inverting processing module 301 is configured to receive the copy clock signal Clk_D, and output a first signal Clk_D and a second signal Clk_DN based on the copy clock signal Clk_D; wherein the phase difference between the first signal Clk_D and the second signal Clk_DN is 180 degrees.

[0120] The conversion module 302 is configured to receive a first signal Clk_D and a second signal Clk_DN, convert the first signal Clk_D into a first voltage V1, and convert the second signal Clk_DN into a second voltage V2;

[0121] The filtering module 303 is configured to receive a first voltage V1 and a second voltage V2, perform filtering processing on the first voltage V1 and the second voltage V2, and output a first target voltage Va and a second target voltage Vb.

[0122] The comparison module 304 is configured to receive a first target voltage Va and a second target voltage Vb, compare the first target voltage Va and the second target voltage Vb, and output a duty cycle detection signal.

[0123] Thus, the inverting processing module 301 converts the copied clock signal Clk_D into a pair of inverted signals. In this embodiment, the waveforms of the first signal and the copied clock signal are the same; therefore, both the first signal and the copied clock signal are represented by Clk_D. The conversion module 302 converts the digital signal into an analog signal to obtain a first voltage V1 and a second voltage V2. The filtering module 303 removes voltage glitches to obtain a first target voltage Va and a second target voltage Vb, which are then compared to obtain the duty cycle detection signal. The conversion module 302 can be a digital loop filter module.

[0124] In some embodiments, the first duty cycle adjustment module 121, the second duty cycle adjustment module 124, the third duty cycle adjustment module 131, the fourth duty cycle adjustment module 134, the fifth duty cycle adjustment module, and the sixth duty cycle adjustment module have the same structure. Any one of the first duty cycle adjustment module 121, the second duty cycle adjustment module 124, the third duty cycle adjustment module 131, the fourth duty cycle adjustment module 134, the fifth duty cycle adjustment module, and the sixth duty cycle adjustment module is referred to as a duty cycle adjustment module. The specific structure of the duty cycle adjustment module is provided below.

[0125] like Figure 6 As shown, the duty cycle adjustment module includes multiple adjustment modules 41 ( Figure 6 Taking two adjustment modules as an example (only one adjustment module is used as an example for labeling), and multiple adjustment modules 41 are connected in series; each adjustment module 41 includes a range selection unit 411 and multiple fifth adjustable NOT gate units 412 ( Figure 6 The example is illustrated using four fifth adjustable NOT gate units (with only one fifth adjustable NOT gate unit being labeled), and the range selection unit 411 and multiple fifth adjustable NOT gate units 412 are connected in parallel.

[0126] The first duty cycle control signal includes a first range signal and a first control signal; the second duty cycle control signal includes a second range signal and multiple second control signals.

[0127] If the adjustment module 41 belongs to the first duty cycle adjustment module or the third duty cycle adjustment module, the range selection unit 411 is controlled by the first range signal, and the fifth adjustable NOT gate unit 412 is controlled by the first control signal; if the adjustment module 41 belongs to the second duty cycle adjustment module or the fourth duty cycle adjustment module, the range selection unit 411 is controlled by the second range signal, and the fifth adjustable NOT gate unit 412 is controlled by the second control signal.

[0128] Here, as Figure 6As shown, the input terminal of the first adjustment module constitutes the input terminal of the duty cycle adjustment module, receiving the signal Clk_Int (the specific location depends on the actual circuit position). The input terminal of the last adjustment module constitutes the output terminal of the duty cycle adjustment module, outputting the signal Clk_Out (the specific location depends on the actual circuit position). The signal at the output terminal of the first adjustment module is denoted as ClkM.

[0129] It should be noted that, in Figure 6 In this context, the first control signal (or the second control signal) is represented as CtrlA3~CtrlB3 and CtrlA3N~CtrlB3N, and CtrlA3 and CtrlA3N are a pair of inverted signals. The rest can be understood by referring to this example.

[0130] by Figure 6 Taking the second adjustment module 41 as an example, the specific structure of the range selection unit and the adjustable NOT gate unit is provided below.

[0131] Please see Figure 7 The diagram illustrates the specific structure of the range selection unit 411. The range selection unit 411 includes three delay units 401 (…). Figure 7 (Taking only one delay unit as an example for labeling), each delay unit 401 consists of 2 PMOS and 2 NMOS, and the specific connection relationship is as follows: Figure 7 As shown.

[0132] For the range selection unit 411, in the first delay unit, the gate of the first PMOS receives the ground signal CND and is fixedly turned on, and the gate of the second NMOS receives the power supply signal VDD and is fixedly turned on; in the second delay unit, the gate of the second NMOS receives one bit of the first range signal En[0], and the gate of the first PMOS receives the signal EnN[0] (i.e., the inverted signal of En[0]); in the third delay unit, the gate of the second NMOS receives one bit of the first range signal En[1], and the gate of the first PMOS receives the signal EnN[1] (i.e., the inverted signal of En[1]). In all delay units 401, the gates of the second PMOS and the first NMOS are connected to the input terminal of the range selection unit 411 and receive the signal ClkM; the drains of the second PMOS and the first NMOS are connected to the output terminal of the range selection unit 411 and form the signal Clk_Out.

[0133] In other words, EnN[0] and EnN[1] in the first range signal can control the working state of different delay units, thereby regulating the duty cycle difference between signal ClM and signal Clk_Out.

[0134] like Figure 8As shown, in the fifth adjustable NOT gate module 412, there are four delay units 402, and the structures of delay units 402 and delay units 401 are basically the same. For the fifth adjustable NOT gate module 412, in all delay units, the gate of the first PMOS receives one bit of the first control signal (or the second control signal), CtrlA3, and the gate of the second NMOS receives one bit of the first control signal (or the second control signal), CtrlB3. The gates of the second PMOS and the first NMOS are both connected to the input terminal of the fifth adjustable NOT gate module 412, receiving the signal ClkM; the drains of the second PMOS and the first NMOS are both connected to the output terminal of the fifth adjustable NOT gate module 412, forming the signal Clk_Out.

[0135] In other words, CtrlA3 to CtrlB3 in the first control signal (or the second control signal) can control the working state of different fifth adjustable NOT gate modules, thereby regulating the duty cycle difference between signal ClM and signal Clk_Out.

[0136] It should be understood that the number of delay units in the range selection unit 411 and the number of delay units in the fifth adjustable NOT gate unit 412 can be selected according to the actual application scenario.

[0137] In some embodiments, such as Figure 2 As shown, the phase-splitting module 14 includes:

[0138] The first phase-splitting module 141 is configured to receive the first synchronous clock signal Clk0, perform phase-splitting processing on the first synchronous clock signal Clk0, and output the first target clock signal CLK0 and the third target clock signal CLK180.

[0139] The second phase-splitting module 142 is configured to receive the second synchronous clock signal Clk90, perform phase-splitting processing on the second synchronous clock signal Clk90, and output the second target clock signal CLK90 and the fourth target clock signal CLK270.

[0140] In some embodiments, such as Figure 9 As shown, the first phase-splitting module 141 includes a first phase-splitting link 501 and a second phase-splitting link 502, and a third data holding unit 503 is provided between the first phase-splitting link 501 and the second phase-splitting link 502; the input terminals of the first phase-splitting link 501 and the second phase-splitting link 502 are both used to receive the first synchronization clock signal Clk0; the output terminal of the first phase-splitting link 501 is used to output the first target clock signal CLK0, and the output terminal of the second phase-splitting link 502 is used to output the third target clock signal CLK180.

[0141] The second phase-splitting module 142 includes a third phase-splitting link 504 and a fourth phase-splitting link 505. A fourth data holding unit 506 is provided between the third phase-splitting link 504 and the fourth phase-splitting link 505. The input terminals of the third phase-splitting link 504 and the fourth phase-splitting link 505 are both used to receive the second synchronization clock signal Clk90. The output terminal of the third phase-splitting link 504 is used to output the second target clock signal CLK9, and the output terminal of the fourth phase-splitting link 505 is used to output the fourth target clock signal CLK270.

[0142] It should be noted that the first phase-splitting link 501 and the third phase-splitting link 504 have the same structure, both consisting of multiple NOT gates. For details, please refer to [link to specific structure]. Figure 9 The second phase link 502 and the fourth phase link 505 have the same structure, both consisting of multiple NOT gates. For details, please refer to [link to specific structure]. Figure 9 .

[0143] In this way, the first synchronous clock signal Clk0 and the second synchronous clock signal Clk90 are processed by phase interpolation to form a four-phase clock signal, which can minimize phase jitter and improve signal stability.

[0144] This disclosure provides a novel delay phase-locked loop structure that reduces the number of delay lines, thereby reducing circuit area and manufacturing costs, and improving phase errors caused by delay line mismatch.

[0145] In another embodiment of this disclosure, see Figure 10 This illustrates a schematic diagram of a clock synchronization circuit 60 provided in an embodiment of the present disclosure. Figure 10 As shown, the clock synchronization circuit 60 includes the aforementioned delay phase-locked loop 10 and data module 601. A first clock distribution network, a second clock distribution network, a third clock distribution network, and a fourth clock distribution network are provided between the delay phase-locked loop 10 and the data module 601; wherein,

[0146] The delay phase-locked loop 10 is configured to generate a first target clock signal CLK0, a second target clock signal CLK90, a third target clock signal CLK180, and a fourth target clock signal CLK270, wherein the phases of the first target clock signal CLK0, the second target clock signal CLK90, the third target clock signal CLK180, and the fourth target clock signal CLK270 are sequentially 90 degrees apart;

[0147] The data module 601 is configured to receive a first target clock signal CLK0 through a first clock distribution network, a second target clock signal CLK90 through a second clock distribution network, a third target clock signal CLK180 through a third clock distribution network, and a fourth target clock signal CLK270 through a fourth clock distribution network, and to perform data sampling processing using the received signals.

[0148] Here, please refer to the description for the structure of the delay phase-locked loop 10. It can output a four-phase clock signal through two delay lines and a phase splitting module, which can not only reduce the circuit area and reduce the manufacturing cost of the circuit, but also improve the phase error caused by delay line mismatch.

[0149] See Figure 11 It shows a schematic diagram of a delay phase-locked loop provided by related technologies. Figure 11 In this diagram, PD stands for Phase Difference Detection Module, TDC for Time-to-Digital Conversion Module, DCC0 and DCC1 are both duty cycle adjustment modules, DCC_Ctrl is the duty cycle logic module, CDL is the coarse-tuning delay module, FDL is the fine-tuning delay module, CDL_Ctrl is the coarse-tuning logic module, FDL_Ctrl is the fine-tuning logic module, QEC is the phase adjustment module, and QEC_Ctrl is the quadrature phase logic module. Those skilled in the art can further understand this concept by combining it with... Figure 2 10 pairs of delay phase-locked loops Figure 11 The circuitry will be understood adaptively, and will not be elaborated upon here. For example... Figure 11 As shown, the clock synchronization circuit in the related art requires at least 4 delay lines (including 1 delay line for feedback), but the delay phase-locked loop 10 in this embodiment only requires 2 delay lines (including 1 delay line for feedback), which not only reduces the circuit area and the manufacturing cost of the circuit, but also improves the phase error caused by delay line mismatch.

[0150] This disclosure provides a clock synchronization circuit. Because the delay phase-locked loop has a small number of delay lines, it can reduce the circuit area and phase error, thereby improving the clock synchronization effect.

[0151] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 12 This illustrates a schematic diagram of the composition structure of a memory 70 provided in an embodiment of this disclosure. For example... Figure 12 As shown, the memory 70 includes at least the aforementioned clock synchronization circuit 60. Because the clock synchronization circuit 60 has a smaller number of delay lines, it reduces circuit area and phase error, thereby improving memory performance.

[0152] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A delay-locked loop, characterized in that, The delay phase-locked loop includes: The clock generation module is configured to generate a first clock signal and a second clock signal; The first delay line is configured to receive the first clock signal, and perform duty cycle adjustment, delay processing and phase adjustment processing on the first clock signal to obtain the first synchronous clock signal. The second delay line is configured to receive the second clock signal, perform duty cycle adjustment, delay processing, and phase adjustment processing on the second clock signal to obtain a second synchronous clock signal; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 90 degrees. The phase-splitting module is configured to receive the first synchronous clock signal and the second synchronous clock signal; perform phase-splitting processing on the first synchronous clock signal and the second synchronous clock signal to obtain a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal, wherein the phases of the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal are sequentially 90 degrees apart; The clock generation module includes: The clock conversion module is configured to output a clock signal to be processed based on a pair of differential clock signals; wherein the frequency of the clock signal to be processed is the same as the frequency of the differential clock signals; A clock preprocessing module is configured to receive the clock signal to be processed, perform frequency division and phase shifting processing on the clock signal to be processed, and output a first clock signal and a second clock signal; wherein the frequency of the first clock signal is the same as the frequency of the second clock signal, and the frequency of the first clock signal is half the frequency of the clock signal to be processed; The first delay line includes: a first duty cycle adjustment module, a first coarse delay adjustment module, a first fine delay adjustment module, a second duty cycle adjustment module, and a first phase adjustment module; and / or, the second delay line includes: a third duty cycle adjustment module, a second coarse delay adjustment module, a second fine delay adjustment module, a fourth duty cycle adjustment module, and a second phase adjustment module.

2. The delay phase-locked loop according to claim 1, characterized in that, The first duty cycle adjustment module is configured to receive a first duty cycle control signal and a first clock signal, perform duty cycle adjustment processing on the first clock signal based on the first duty cycle control signal, and output a first intermediate clock signal; The first coarse adjustment delay module is configured to receive a coarse adjustment control signal and a first intermediate clock signal, perform delay processing on the first intermediate clock signal based on the coarse adjustment control signal, and output a second intermediate clock signal. The first fine-tuning delay module is configured to receive a fine-tuning control signal and a second intermediate clock signal, perform delay processing on the second intermediate clock signal based on the fine-tuning control signal, and output a third intermediate clock signal; The second duty cycle adjustment module is configured to receive a second duty cycle control signal and the third intermediate clock signal, perform duty cycle adjustment processing on the third intermediate clock signal based on the second duty cycle control signal, and output a fourth intermediate clock signal; The first phase adjustment module is configured to receive the quadrature phase adjustment signal and the fourth intermediate clock signal, perform phase adjustment processing on the fourth intermediate clock signal based on the quadrature phase adjustment signal, and output the first synchronization clock signal.

3. The delay phase-locked loop according to claim 1, characterized in that, The third duty cycle adjustment module is configured to receive a first duty cycle control signal and a second clock signal, perform duty cycle adjustment processing on the second clock signal based on the first duty cycle control signal, and output a fifth intermediate clock signal; The second coarse adjustment delay module is configured to receive a coarse adjustment control signal and the fifth intermediate clock signal, perform delay processing on the fifth intermediate clock signal based on the coarse adjustment control signal, and output a sixth intermediate clock signal; The second fine-tuning delay module is configured to receive a fine-tuning control signal and the sixth intermediate clock signal, perform delay processing on the sixth intermediate clock signal based on the fine-tuning control signal, and output a seventh intermediate clock signal; The fourth duty cycle adjustment module is configured to receive the second duty cycle control signal and the seventh intermediate clock signal, perform duty cycle adjustment processing on the seventh intermediate clock signal based on the second duty cycle control signal, and output the eighth intermediate clock signal. The second phase adjustment module is configured to receive the quadrature phase adjustment signal and the eighth intermediate clock signal, perform phase adjustment processing on the eighth intermediate clock signal based on the quadrature phase adjustment signal, and output the second synchronization clock signal.

4. The delay phase-locked loop according to claim 2 or 3, characterized in that, The first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are used for data sampling processing after passing through the corresponding clock distribution network; The delay phase-locked loop further includes a third delay line and a replication delay module. The third delay line has the same structure as the first delay line, and the replication delay module is at least based on the clock distribution network. The third delay line is configured to receive the first clock signal, perform duty cycle adjustment, delay processing, and phase adjustment processing on the first clock signal, and output a copied clock signal; wherein the waveform of the copied clock signal is the same as that of the first synchronization clock signal. The replication delay module is configured to receive the replication clock signal, delay the replication clock signal, and output a feedback clock signal; wherein the feedback clock signal has the same waveform as the first target clock signal after passing through the clock distribution network.

5. The delay phase-locked loop according to claim 4, characterized in that, The delay phase-locked loop also includes: The delay control module is configured to receive the first clock signal and the feedback clock signal, and output the coarse adjustment control signal and the fine adjustment control signal; The duty cycle control module is configured to receive the replicated clock signal and output the first duty cycle control signal and the second duty cycle control signal; The quadrature phase control module is configured to receive the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal, and output the quadrature phase adjustment signal.

6. The delay phase-locked loop according to claim 5, characterized in that, The delay control module includes: The time-to-digital conversion module is configured to receive the first clock signal and the feedback clock signal, and output the initial value of the coarse adjustment control signal based on the first clock signal and the feedback clock signal. The phase difference detection module is configured to receive the first clock signal and the feedback clock signal, detect the phase difference between the first clock signal and the feedback clock signal, and output a phase detection signal. The coarse adjustment logic module is configured to receive the initial values ​​of the phase detection signal and the coarse adjustment control signal, and update the initial value of the coarse adjustment control signal based on the phase detection signal. The fine-tuning logic module is configured to receive the phase detection signal and output the fine-tuning control signal based on the phase detection signal.

7. The delay phase-locked loop according to claim 5, characterized in that, The duty cycle control module includes: The duty cycle detection module is configured to receive the copy clock signal, perform duty cycle detection on the copy clock signal, and output a duty cycle detection signal. The first duty cycle logic module is configured to receive the duty cycle detection signal and output the first duty cycle control signal based on the duty cycle detection signal. The second duty cycle logic module is configured to receive the duty cycle detection signal and output the second duty cycle control signal based on the duty cycle detection signal.

8. The delay phase-locked loop according to claim 5, characterized in that, The orthogonal phase control module includes: The quadrature phase detection module is configured to perform phase detection on the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal to obtain a quadrature detection signal; The quadrature phase logic module is configured to receive the quadrature detection signal and, based on the quadrature detection signal, output the second duty cycle control signal.

9. The delay phase-locked loop according to claim 1, characterized in that, The clock preprocessing module includes a first controllable NOT gate unit, a second controllable NOT gate unit, a third controllable NOT gate unit, and a fourth controllable NOT gate unit connected sequentially. A first data holding unit is provided between the output terminals of the first and third controllable NOT gate units, and a second data holding unit is provided between the output terminals of the second and fourth controllable NOT gate units. In the first controllable NOT gate unit, both the first control terminal and the second control terminal receive the clock signal to be processed; in the second controllable NOT gate unit, the first control terminal receives the inverted signal of the clock signal to be processed, and the second control terminal receives the clock signal to be processed; in the third controllable NOT gate unit, the first control terminal receives the clock signal to be processed, and the second control terminal receives the inverted signal of the clock signal to be processed; in the fourth controllable NOT gate unit, the first control terminal receives the inverted signal of the clock signal to be processed, and the second control terminal receives the clock signal to be processed. The output terminal of the third controllable NOT gate unit is used to output the second clock signal, and the output terminal of the fourth controllable NOT gate unit is used to output the first clock signal.

10. The delay phase-locked loop according to claim 7, characterized in that, The duty cycle detection module includes: The phase inversion processing module is configured to receive the copied clock signal and, based on the copied clock signal, output a first signal and a second signal; wherein the phase difference between the first signal and the second signal is 180 degrees. The conversion module is configured to receive the first signal and the second signal, convert the first signal into a first voltage, and convert the second signal into a second voltage; The filtering module is configured to receive the first voltage and the second voltage, perform filtering processing on the first voltage and the second voltage, and output a first target voltage and a second target voltage. The comparison module is configured to receive the first target voltage and the second target voltage, compare the first target voltage and the second target voltage, and output the duty cycle detection signal.

11. The delay phase-locked loop according to claim 2 or 3, characterized in that, Any one of the first duty cycle adjustment module, the second duty cycle adjustment module, the third duty cycle adjustment module, and the fourth duty cycle adjustment module is referred to as the duty cycle adjustment module; wherein... The duty cycle adjustment module includes multiple adjustment modules, which are connected in series; each adjustment module includes a range selection unit and multiple fifth adjustable NOT gate units, which are connected in parallel. The first duty cycle control signal includes a first range signal and a first control signal, and the second duty cycle control signal includes a second range signal and a plurality of second control signals; If the adjustment module belongs to the first duty cycle adjustment module or the third duty cycle adjustment module, the range selection unit is controlled by the first range signal, and the fifth adjustable NOT gate unit is controlled by the first control signal; If the adjustment module belongs to the second duty cycle adjustment module or the fourth duty cycle adjustment module, the range selection unit is controlled by the second range signal, and the fifth adjustable NOT gate unit is controlled by the second control signal.

12. The delay phase-locked loop according to claim 1, characterized in that, The phase separation module includes: The first phase-splitting module is configured to receive the first synchronous clock signal, perform phase-splitting processing on the first synchronous clock signal, and output the first target clock signal and the third target clock signal. The second phase-splitting module is configured to receive the second synchronous clock signal, perform phase-splitting processing on the second synchronous clock signal, and output the second target clock signal and the fourth target clock signal.

13. The delay phase-locked loop according to claim 12, characterized in that, The first phase-splitting module includes a first phase-splitting link and a second phase-splitting link, and a third data holding unit is provided between the first phase-splitting link and the second phase-splitting link; the input terminals of the first phase-splitting link and the second phase-splitting link are both used to receive the first synchronization clock signal; the output terminal of the first phase-splitting link is used to output the first target clock signal, and the output terminal of the second phase-splitting link is used to output the third target clock signal. The second phase-splitting module includes a third phase-splitting link and a fourth phase-splitting link, and a fourth data holding unit is provided between the third phase-splitting link and the fourth phase-splitting link; the input terminals of the third phase-splitting link and the fourth phase-splitting link are both connected to receive the second synchronization clock signal; the output terminal of the third phase-splitting link is used to output the second target clock signal, and the output terminal of the fourth phase-splitting link is used to output the fourth target clock signal. The first phase link and the third phase link have the same structure, and the second phase link and the fourth phase link have the same structure.

14. A clock synchronization circuit, characterized in that, The clock synchronization circuit includes a delay phase-locked loop (PLL) and a data module as described in any one of claims 1-13, wherein a first clock distribution network, a second clock distribution network, a third clock distribution network, and a fourth clock distribution network are provided between the delay PLL and the data module; wherein... The delay phase-locked loop is configured to generate a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal, wherein the phases of the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are sequentially 90 degrees apart; The data module is configured to receive the first target clock signal through the first clock distribution network, receive the second target clock signal through the second clock distribution network, receive the third target clock signal through the third clock distribution network, receive the fourth target clock signal through the fourth clock distribution network, and perform data sampling processing using the received signals.

15. A memory, characterized in that, The memory includes the clock synchronization circuit as described in claim 14.

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