Data receiving circuit, data receiving system and storage device

Abstract

This disclosure provides a data receiving circuit, a data receiving system, and a storage device. The data receiving circuit includes: a receiving module configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal; and a decision feedback equalization module connected to the feedback node of the receiving module, configured to perform decision feedback equalization on the receiving module based on the feedback signal to adjust the first output signal and the second output signal, wherein the feedback signal is obtained based on previously received data, and the adjustment capability of the decision feedback equalization module for the first and second output signals is adjustable. This disclosure provides at least the advantage of flexibly controlling the adjustment capability of the decision feedback equalization module for the first and second output signals, thereby reducing the impact of inter-symbol interference of received data on the data receiving circuit and improving the receiving performance of the data receiving circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a data receiving circuit, a data receiving system, and a storage device. Background Technology

[0002] In memory applications, as signal transmission rates increase, channel loss has a greater impact on signal quality, easily leading to inter-symbol interference. Currently, equalization circuits are commonly used to compensate for channel loss. These circuits can be either CTLE (Continuous Time Linear Equalizer) or DFE (Decision Feedback Equalizer).

[0003] However, the current equalization circuits have limited ability to adjust signals, and the accuracy of signal adjustment by equalization circuits needs to be improved. Summary of the Invention

[0004] This disclosure provides a data receiving circuit, a data receiving system, and a storage device, which at least facilitates flexible control of the decision feedback equalization module's ability to adjust the first and second output signals, thereby reducing the impact of inter-symbol interference of the data received by the data receiving circuit on the data receiving circuit and improving the receiving performance of the data receiving circuit.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a data receiving circuit, including: a receiving module configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal; and a decision feedback equalization module connected to a feedback node of the receiving module, configured to perform decision feedback equalization on the receiving module based on the feedback signal to adjust the first output signal and the second output signal, wherein the feedback signal is obtained based on previously received data, and the adjustment capability of the decision feedback equalization module for the first output signal and the second output signal is adjustable.

[0006] In some embodiments, the receiving module includes: a first amplification module configured to receive the data signal and the reference signal, compare the data signal and the reference signal in response to the sampling clock signal, and output a first voltage signal through a first node and a second voltage signal through a second node; a second amplification module connected to the first node and the second node, configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output the first output signal through a third node and the second output signal through a fourth node; wherein the feedback node includes a first feedback node and a second feedback node, the first node serving as the first feedback node and the second node serving as the second feedback node, and the decision feedback equalization module configured to perform decision feedback equalization on the first node and the second node based on the feedback signal to adjust the first voltage signal and the second voltage signal.

[0007] In some embodiments, the data receiving circuit further includes an offset compensation module connected to the second amplification module and configured to compensate for the offset voltage of the second amplification module.

[0008] In some embodiments, the receiving module includes: a first amplification module configured to receive the data signal and the reference signal, compare the data signal and the reference signal in response to the sampling clock signal, and output a first voltage signal through a first node and a second voltage signal through a second node; a second amplification module connected to the first node and the second node, configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output the first output signal through a third node and the second output signal through a fourth node, wherein the second amplification module has a first internal node and a second internal node, and the first output signal and the second output signal are obtained based on the signals of the first internal node and the second internal node; wherein the feedback node includes a first feedback node and a second feedback node, the first internal node serves as the first feedback node, the second internal node serves as the second feedback node, and the decision feedback equalization module is configured to perform decision feedback equalization on the first internal node and the second internal node based on the feedback signal.

[0009] In some embodiments, the data receiving circuit further includes: an offset compensation module connected to the first amplification module and configured to compensate for the offset voltage of the first amplification module.

[0010] In some embodiments, the first amplification module includes: a current source configured to be connected between a power supply node and a fifth node, providing current to the fifth node in response to the sampling clock signal; and a comparison unit connected to the fifth node, the first node, and the second node, configured to receive the data signal and the reference signal, compare the data signal and the reference signal when the current source provides current to the fifth node in response to the sampling clock signal, and output the first voltage signal through the first node and the second voltage signal through the second node.

[0011] In some embodiments, the current source includes a first PMOS transistor connected between the power supply node and the fifth node, wherein the gate of the first PMOS transistor receives the sampling clock signal.

[0012] In some embodiments, the current source further includes a second PMOS transistor connected between the power supply node and the first PMOS transistor, wherein the gate of the second PMOS transistor receives an enable signal.

[0013] In some embodiments, the comparison unit includes: a third PMOS transistor connected between the fifth node and the first node, the gate of the third PMOS transistor receiving the data signal; and a fourth PMOS transistor connected between the fifth node and the second node, the gate of the fourth PMOS transistor receiving the reference signal.

[0014] In some embodiments, the first amplification module further includes: a first reset unit, connected to the first node and the second node, configured to reset the first node and the second node.

[0015] In some embodiments, the first reset unit includes: a first NMOS transistor connected between the first node and ground, the gate of the first NMOS transistor receiving the sampling clock signal; and a second NMOS transistor connected between the second node and ground, the gate of the second NMOS transistor receiving the sampling clock signal.

[0016] In some embodiments, the first node serves as the first feedback node, the second node serves as the second feedback node, and the feedback signal includes a first feedback signal and a second feedback signal; the decision feedback equalization module includes: a first decision feedback unit connected to the first node and the fifth node, configured to perform decision feedback equalization on the first node based on the first feedback signal to adjust the first voltage signal; and a second decision feedback unit connected to the second node and the fifth node, configured to perform decision feedback equalization on the second node based on the second feedback signal to adjust the second voltage signal.

[0017] In some embodiments, each of the first decision feedback unit and the second decision feedback unit includes: a switching unit configured to turn on the fifth node and the sixth node in response to the feedback signal; and an adjustment unit connected between the sixth node and the output node, wherein the output node is one of the first node and the second node, configured to adjust the equivalent resistance value between the sixth node and the output node in response to a control signal; wherein, in the first decision feedback unit, the feedback signal is the first feedback signal, the output node is the first node, and the switching unit responds to the first feedback signal; and in the second decision feedback unit, the feedback signal is the second feedback signal, the output node is the second node, and the switching unit responds to the second feedback signal.

[0018] In some embodiments, the switching unit includes a fifth PMOS transistor connected between the fifth node and the sixth node, wherein the gate of the fifth PMOS transistor receives the feedback signal.

[0019] In some embodiments, the adjustment unit includes: a plurality of transistor groups connected in parallel between the sixth node and the output node, wherein the control terminals of different transistor groups receive different control signals and the equivalent resistance values ​​of different transistor groups are different.

[0020] In some embodiments, different transistor groups include: at least one transistor group consisting of a single MOS transistor; at least one transistor group comprising at least two MOS transistors connected in series.

[0021] In some embodiments, the different transistor groups include: a first transistor group, a second transistor group, and a third transistor group connected in parallel, wherein the channel equivalent width-to-length ratio of the first transistor group is twice that of the channel equivalent width-to-length ratio of the second transistor group, and the channel equivalent width-to-length ratio of the second transistor group is twice that of the channel equivalent width-to-length ratio of the third transistor group.

[0022] In some embodiments, the second amplification module includes: an input unit connected to the first node and the second node, configured to compare the first voltage signal and the second voltage signal, and provide a third voltage signal to a seventh node and a fourth voltage signal to an eighth node, wherein the second amplification module has a first internal node and a second internal node, and the seventh node is the first internal node and the eighth node is the second internal node; and a latching unit configured to amplify and latch the third voltage signal and the fourth voltage signal, and output the first output signal to the third node and the second output signal to the fourth node.

[0023] In some embodiments, the input unit includes: a third NMOS transistor connected between the seventh node and ground, the gate of the third NMOS transistor receiving the first voltage signal; and a fourth NMOS transistor connected between the eighth node and ground, the gate of the fourth NMOS transistor receiving the second voltage signal.

[0024] In some embodiments, the latching unit includes: a fifth NMOS transistor connected between the seventh node and the third node, the gate of the fifth NMOS transistor receiving the second output signal; a sixth NMOS transistor connected between the eighth node and the fourth node, the gate of the sixth NMOS transistor receiving the first output signal; a sixth PMOS transistor connected between the power supply node and the third node, the gate of the sixth PMOS transistor receiving the second output signal; and a seventh PMOS transistor connected between the power supply node and the fourth node, the gate of the seventh PMOS transistor receiving the first output signal.

[0025] In some embodiments, the first node serves as the first feedback node and the second node serves as the second feedback node; the data receiving circuit further includes: an offset compensation module connected to the seventh node and the eighth node, configured to compensate for the offset voltage of the input unit.

[0026] In some embodiments, the misalignment compensation module includes: a first misalignment compensation unit connected between the seventh node and the ground terminal; and a second misalignment compensation unit connected between the eighth node and the ground terminal.

[0027] In some embodiments, the first offset compensation unit includes: at least two sets of transistor groups connected in parallel, each set of transistors including: a seventh NMOS transistor, the first terminal of which is connected to the seventh node and the gate of which is connected to the first node; and a seventh MOS transistor, which is configured in a one-to-one correspondence with the seventh NMOS transistor, the seventh MOS transistor being connected between the second terminal of the seventh NMOS transistor and the ground terminal, the gate of which receives a first mismatch adjustment signal.

[0028] In some embodiments, the second offset compensation unit includes: at least two sets of transistor groups connected in parallel, each set of transistors including: an eighth NMOS transistor, the first terminal of which is connected to the eighth node and the gate of which is connected to the second node; and an eighth MOS transistor, which is configured in a one-to-one correspondence with the eighth NMOS transistor, the eighth MOS transistor being connected between the second terminal of the eighth NMOS transistor and the ground terminal, and the gate of which receives a second mismatch adjustment signal.

[0029] In some embodiments, the second amplification module further includes: a second reset unit connected to the latch unit and configured to reset the latch unit.

[0030] In some embodiments, the second reset unit includes: an eighth PMOS transistor connected between a power supply node and the third node; and a ninth PMOS transistor connected between the power supply node and the fourth node, wherein the gates of the eighth PMOS transistor and the ninth PMOS transistor are both responsive to the inverted signal of the sampling clock signal.

[0031] In some embodiments, the second reset unit further includes: a tenth PMOS transistor connected between the power supply node and the seventh node; and an eleventh PMOS transistor connected between the power supply node and the eighth node, wherein the gates of the tenth PMOS transistor and the eleventh PMOS transistor are both responsive to the inverted signal of the sampling clock signal.

[0032] In some embodiments, the first internal node serves as the first feedback node, and the second internal node serves as the second feedback node. The feedback signal includes a first feedback signal and a second feedback signal. The decision feedback equalization module includes: a first decision feedback unit connected to the first internal node and a ground terminal, configured to perform decision feedback equalization on the first internal node based on the first feedback signal; and a second decision feedback unit connected to the second internal node and a ground terminal, configured to perform decision feedback equalization on the second internal node based on the second feedback signal.

[0033] According to some embodiments of this disclosure, another aspect of this disclosure provides a data receiving system, including: a plurality of cascaded data transmission circuits, each data transmission circuit including a data receiving circuit as described in any of the foregoing claims and a latching circuit connected to the data receiving circuit, each data receiving circuit being connected to the data port to receive the data signal; a decision feedback equalization module of a higher-level data transmission circuit being connected to a lower-level data transmission circuit, the output of the higher-level data transmission circuit serving as the feedback signal of the decision feedback equalization module of the lower-level data transmission circuit; and a final-level data transmission circuit being connected to the decision feedback equalization module of a first-level data transmission circuit, the output of the final-level data transmission circuit serving as the feedback signal of the decision feedback equalization module of the first-level data transmission circuit.

[0034] In some embodiments, the data receiving system includes four cascaded data receiving circuits, with a 90° phase difference between the sampling clock signals of adjacent data receiving circuits.

[0035] According to some embodiments of the present disclosure, another aspect of the present disclosure also provides a storage device, including: a plurality of data ports; a plurality of data receiving systems as described in any of the preceding claims, each of the data receiving systems corresponding to one of the data ports.

[0036] The technical solutions provided in this disclosure have at least the following advantages: By integrating the decision feedback equalization module into the data receiving circuit, and adjusting the first and second output signals through the decision feedback equalization module to reduce the impact of inter-symbol interference (ISI) on data reception, this embodiment of the present disclosure is advantageous in using a smaller circuit layout area and lower power consumption to adjust the output signal of the data receiving circuit. Furthermore, by flexibly controlling the adjustment capability of the first and second output signals by the decision feedback equalization module, the impact of ISI on the data receiving circuit is reduced, thereby improving the reception performance of the data receiving circuit and minimizing the impact of ISI on the accuracy of the output signal of the data receiving circuit. Attached Figure Description

[0037] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A functional block diagram of a data receiving circuit provided in an embodiment of this disclosure; Figure 2 A functional block diagram of a data receiving system provided in another embodiment of this disclosure; Figures 3 to 4 Two other functional block diagrams of a data receiving circuit provided in one embodiment of this disclosure; Figure 5 A schematic diagram of a data receiving circuit provided in an embodiment of this disclosure; Figures 6 to 7 Schematic diagrams of two circuit structures of the first decision feedback unit in a data receiving circuit provided in an embodiment of this disclosure; Figures 8 to 9 The following are schematic diagrams of two other circuit structures of a data receiving circuit provided in one embodiment of this disclosure. Detailed Implementation

[0039] As can be seen from the background technology, the signal adjustment capability of equalization circuits needs to be improved.

[0040] This disclosure provides a data receiving circuit, a data receiving system, and a storage device. In the data receiving circuit, a decision feedback equalization module is integrated. The decision feedback equalization module adjusts a first output signal and a second output signal to reduce inter-symbol interference (ISI) between the signals output by the data receiving circuit. Furthermore, this disclosure allows for the adjustment of the output signals of the data receiving circuit using a smaller circuit layout area and lower power consumption. The ability of the decision feedback equalization module to flexibly control the adjustment of the first and second output signals reduces the impact of ISI on the data receiving circuit, thereby improving the receiving performance of the data receiving circuit and minimizing the impact of ISI on the accuracy of the output signals.

[0041] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0042] This disclosure provides a data receiving circuit according to an embodiment. The data receiving circuit provided by this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 A functional block diagram of a data receiving circuit provided in an embodiment of this disclosure; Figures 3 to 4 Two other functional block diagrams of a data receiving circuit provided in one embodiment of this disclosure; Figure 5 A schematic diagram of a data receiving circuit provided in an embodiment of this disclosure; Figures 6 to 7 Schematic diagrams of two circuit structures of the first decision feedback unit in a data receiving circuit provided in an embodiment of this disclosure; Figures 8 to 9 The following are schematic diagrams of two other circuit structures of a data receiving circuit provided in one embodiment of this disclosure.

[0043] refer to Figure 1 The data receiving circuit 110 includes: a receiving module 100 configured to receive a data signal DQ and a reference signal Vref, compare the data signal DQ and the reference signal Vref in response to a sampling clock signal CLK1, and output a first output signal Vout and a second output signal VoutN; and a decision feedback equalization module 103 connected to the feedback node of the receiving module 100, configured to perform decision feedback equalization on the receiving module 100 based on the feedback signal to adjust the first output signal Vout and the second output signal VoutN, wherein the feedback signal is obtained based on previously received data, and the adjustment capability of the decision feedback equalization module 103 for the first output signal Vout and the second output signal VoutN is adjustable.

[0044] Integrating the decision feedback equalization module 103 into the data receiving circuit allows for adjustments to the output signal of the data receiving circuit using a smaller circuit layout area and lower power consumption. Furthermore, the decision feedback equalization module 103 provided in this embodiment has adjustable capabilities for adjusting the first output signal Vout and the second output signal VoutN. This means that when the data signal DQ and / or reference signal Vref received by the receiving module 100 change, the adjustment capabilities of the decision feedback equalization module 103 for the first output signal Vout and the second output signal VoutN can be flexibly controlled. This reduces the impact of inter-symbol interference (ISI) on the data receiving circuit, thereby improving the receiving performance of the data receiving circuit and minimizing the impact of ISI on the accuracy of the output signal.

[0045] It should be noted that the connection between the decision feedback equalization module 103 and the feedback node of the receiving module 100 includes at least the following two examples.

[0046] In some embodiments, reference Figure 3 Receiver module 100 (reference) Figure 1 The system may include: a first amplification module 101, configured to receive a data signal DQ and a reference signal Vref, compare the data signal DQ and the reference signal Vref in response to a sampling clock signal CLK1, and output a first voltage signal through a first node n_stg1 and a second voltage signal through a second node p_stg1; a second amplification module 102, connected to the first node n_stg1 and the second node p_stg1, configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output a second voltage signal through a third node net3 (reference...). Figure 5 The first output signal Vout is output through the fourth node net4 (reference). Figure 5 The second output signal VoutN is output; wherein the feedback nodes include a first feedback node and a second feedback node, the first node n_stg1 is the first feedback node, the second node p_stg1 is the second feedback node, and the decision feedback equalization module 103 is configured to perform decision feedback equalization on the first node n_stg1 and the second node p_stg1 based on the feedback signal to adjust the first voltage signal and the second voltage signal.

[0047] It should be noted that the second amplification module 102 receives the first voltage signal and the second voltage signal, and amplifies the voltage difference between the first voltage signal and the second voltage signal to output a first output signal Vout and a second output signal VoutN. That is, the first output signal Vout and the second output signal VoutN are affected by the first voltage signal and the second voltage signal. The decision feedback equalization module 103 adjusts the first voltage signal and the second voltage signal based on the feedback signal, and can also further adjust the first output signal Vout and the second output signal VoutN. Moreover, the adjustment of the first voltage signal and the second voltage signal by the decision feedback equalization module 103 will be explained in detail later with reference to the specific circuit diagram.

[0048] In some embodiments, continue to refer to Figure 3 The data receiving circuit may further include an offset compensation module 104, connected to the second amplification module 102, configured to compensate for the offset voltage of the second amplification module 102. It should be noted that the specific connection relationship between the offset compensation module 104 and the second amplification module 102 will be explained in detail later with reference to specific circuit diagrams.

[0049] In other embodiments, reference is made to Figure 9 Receiver module 100 (reference) Figure 1 The amplification module 102 may include: a first amplification module 101, configured to receive a data signal DQ and a reference signal Vref, compare the data signal DQ and the reference signal Vref in response to a sampling clock signal CLK1, and output a first voltage signal through a first node n_stg1 and a second voltage signal through a second node p_stg1; and a second amplification module 102, connected to the first node n_stg1 and the second node p_stg1, configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output a first output signal Vout through a third node net3 and a second output signal Vout through a fourth node net4. outN, the second amplification module 102 has a first internal node n_stg2 and a second internal node p_stg2, and the first output signal Vout and the second output signal VoutN are obtained based on the signals of the first internal node n_stg2 and the second internal node p_stg2; wherein, the feedback node includes a first feedback node and a second feedback node, the first internal node n_stg2 is used as the first feedback node, the second internal node p_stg2 is used as the second feedback node, and the decision feedback equalization module 103 is configured to perform decision feedback equalization on the first internal node n_stg2 and the second internal node p_stg2 based on the feedback signal.

[0050] It should be noted that the voltage signal at the first internal node n_stg2 is the third voltage signal, and the voltage signal at the second internal node p_stg2 is the fourth voltage signal. The decision feedback equalization module 103 performs decision feedback equalization on the first internal node n_stg2 and the second internal node p_stg2 based on the feedback signal, that is, the decision feedback equalization module 103 adjusts the third and fourth voltage signals. The first output signal Vout and the second output signal VoutN are based on the third and fourth voltage signals, so the decision feedback equalization module 103 can further adjust the first output signal Vout and the second output signal VoutN by adjusting the third and fourth voltage signals based on the feedback signal. Moreover, the adjustment of the third and fourth voltage signals by the decision feedback equalization module 103 will be explained in detail later with reference to the specific circuit diagram.

[0051] In some embodiments, the data receiving circuit may further include: an offset compensation module connected to the first amplification module, configured to compensate for the offset voltage of the first amplification module. It should be noted that the specific connection relationship between the offset compensation module and the first amplification module will be described in detail later.

[0052] In the two examples above, the data receiving circuit employs a two-stage amplification module, namely the first amplification module 101 and the second amplification module 102, to process the data signal DQ and the reference signal Vref. This enhances the amplification capability of the data receiving circuit and increases the voltage amplitude of the first output signal Vout and the second output signal VoutN, facilitating processing by subsequent circuits. Furthermore, the decision feedback equalization module 103 is used to reduce inter-symbol interference by equivalently adjusting the data signal DQ.

[0053] The following will combine Figures 4 to 9 The specific structure of a data receiving circuit provided in one embodiment of this disclosure will be described in detail below. It should be noted that the following detailed descriptions of each module apply to both of the aforementioned examples.

[0054] In some embodiments, reference Figure 4 The first amplification module 101 may include: a current source 111, configured to be connected to the power supply node Vcc (reference). Figure 5Between the current source 111 and the fifth node net5, current is supplied to the fifth node net5 in response to the sampling clock signal CLK1; the comparison unit 121, connected to the fifth node net5, the first node n_stg1 and the second node p_stg1, is configured to receive the data signal DQ and the reference signal Vref, and when the current source 111 supplies current to the fifth node net5 in response to the sampling clock signal CLK1, compares the data signal DQ and the reference signal Vref, and outputs a first voltage signal through the first node n_stg1 and a second voltage signal through the second node p_stg1.

[0055] It is understood that the comparison unit 121 can control the difference between the current supplied to the first node n_stg1 and the current supplied to the second node p_stg1 based on the difference between the data signal DQ and the reference signal Vref, so as to output a first voltage signal and a second voltage signal.

[0056] The following combination Figure 5 , Figure 8 and Figure 9 The first amplification module 101 is described in detail.

[0057] In some embodiments, reference Figure 5 , Figure 8 and Figure 9 The current source 111 may include a first PMOS transistor MP1 connected between the power supply node Vcc and the fifth node net5. The gate of the first PMOS transistor MP1 receives the sampling clock signal CLK1. When the sampling clock signal CLK1 is low, the gate of the first PMOS transistor MP1 is turned on, providing current to the fifth node net5, so that the comparison unit 121 is in working state, comparing the received data signal DQ and the reference signal Vref.

[0058] In some embodiments, continue to refer to Figure 8 In addition to including the first PMOS transistor MP1, the current source 111 may further include a second PMOS transistor MP2, connected between the power supply node Vcc and the first PMOS transistor MP1. The gate of the second PMOS transistor MP2 receives the enable signal SampEnN. When the sampling clock signal CLK1 is low and the enable signal SampEnN is also low, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, providing current to the fifth node net5, thereby putting the comparison unit 121 into operation and comparing the received data signal DQ with the reference signal Vref.

[0059] Furthermore, by setting a second PMOS transistor MP2 based on the on or off state of the enable signal SampEnN, it is beneficial to control the second PMOS transistor MP2 to turn off based on the enable signal SampEnN when the device containing the data receiving circuit is in a low-power mode, thereby shutting down the data receiving circuit corresponding to the second PMOS transistor MP2 and reducing the overall power consumption of the device containing the data receiving circuit.

[0060] In some embodiments, reference Figure 5 , Figure 8 and Figure 9 The comparison unit 121 may include: a third PMOS transistor MP3, connected between the fifth node net5 and the first node n_stg1, the gate of the third PMOS transistor MP3 receiving the data signal DQ; and a fourth PMOS transistor MP4, connected between the fifth node net5 and the second node p_stg1, the gate of the fourth PMOS transistor MP4 receiving the reference signal Vref.

[0061] It should be noted that the level changes of the data signal DQ and the reference signal Vref are asynchronous. This causes the turn-on time of the third PMOS transistor MP3, which receives the data signal DQ, to differ from the turn-on time of the fourth PMOS transistor MP4, which receives the reference signal Vref. Furthermore, at the same time, the conduction degree of the third PMOS transistor MP3 differs from that of the fourth PMOS transistor MP4. Understandably, because the conduction degree of the third PMOS transistor MP3 differs from that of the fourth PMOS transistor MP4, their current shunting capabilities at the fifth node net5 also differ, resulting in a difference between the voltage at the first node n_stg1 and the voltage at the second node p_stg1.

[0062] In one example, when the level of the data signal DQ is lower than the level of the reference signal Vref, the conduction level of the third PMOS transistor MP3 is greater than that of the fourth PMOS transistor MP4. This causes more current to flow into the path of the third PMOS transistor MP3 at the fifth node net5, making the current at the first node n_stg1 greater than the current at the second node p_stg1. Consequently, the level of the first voltage signal output by the first node n_stg1 is higher, and the level of the second voltage signal output by the second node p_stg1 is lower.

[0063] In some embodiments, reference Figure 4The first amplification module 101 may further include a first reset unit 131, connected to the first node n_stg1 and the second node p_stg1, configured to reset the first node n_stg1 and the second node p_stg1. Thus, after the data receiving circuit completes the reception of a data signal DQ and a reference signal Vref, and the output of the first output signal Vout and the second output signal VoutN, the first reset unit 131 can restore the level values ​​at the first node n_stg1 and the second node p_stg1 to their initial values, facilitating subsequent data reception and processing by the data receiving circuit.

[0064] In some embodiments, continue to refer to Figure 5 , Figure 8 and Figure 9 The first reset unit 131 may include: a first NMOS transistor MN1, connected between the first node n_stg1 and the ground terminal, the gate of the first NMOS transistor MN1 receiving the sampling clock signal CLK1; and a second NMOS transistor MN2, connected between the second node p_stg1 and the ground terminal, the gate of the second NMOS transistor MN2 receiving the sampling clock signal CLK1.

[0065] In one example, when both the sampling clock signal CLK1 and the enable signal SampEnN are low, the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned on, while the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned off to ensure the normal operation of the data receiving circuit. At the same time, the first NMOS transistor MN1 and the second NMOS transistor MN2 can serve as the load of the first amplification module 101 to increase the amplification gain of the first amplification module 101. When the sampling clock signal CLK1 is high, the first PMOS transistor MP1 is turned off, while the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned on. This pulls down the voltage at the first node n_stg1 and the voltage at the second node p_stg1 to reset the first node n_stg1 and the second node p_stg1.

[0066] The decision feedback equalization module 103 is described in detail below through two examples. In one example, the decision feedback equalization module 103 is connected to the first node n_stg1 and the second node p_stg1 in the first amplification module 101 to adjust the first voltage signal and the second voltage signal output by the first amplification module 101. In another example, the decision feedback equalization module 103 is connected to the first internal node n_stg2 and the second internal node p_stg2 in the second amplification module 102 to adjust the voltage at the first internal node n_stg2 and the voltage at the second internal node p_stg2.

[0067] In some embodiments, reference Figure 5 and Figure 8 The first node n_stg1 can serve as the first feedback node, and the second node p_stg1 can serve as the second feedback node. The feedback signals include the first feedback signal fbn and the second feedback signal fbp. The decision feedback equalization module 103 can include: a first decision feedback unit 113, connected to the first node n_stg1 and the fifth node net5, configured to perform decision feedback equalization on the first node n_stg1 based on the first feedback signal fbn to adjust the first voltage signal; and a second decision feedback unit 123, connected to the second node p_stg1 and the fifth node net5, configured to perform decision feedback equalization on the second node p_stg1 based on the second feedback signal fbp to adjust the second voltage signal.

[0068] The first decision feedback unit 113 is used to adjust the current in the third PMOS transistor MP3 to adjust the voltage at the first node n_stg1, which is equivalent to adjusting the data signal DQ. The second decision feedback unit 123 is used to adjust the current in the fourth PMOS transistor MP4 to adjust the voltage at the second node p_stg1, which is equivalent to adjusting the reference signal Vref.

[0069] In some embodiments, reference Figure 6 and Figure 7 Each of the first decision feedback unit 113 and the second decision feedback unit 123 includes: a switching unit 1131 configured to conduct the fifth node net5 and the sixth node net6 in response to a feedback signal; and an adjustment unit 1132 connected between the sixth node net6 and the output node, wherein the output node is one of the first node n_stg1 and the second node p_stg1, configured to adjust the equivalent resistance value between the sixth node net6 and the output node in response to a control signal; wherein, in the first decision feedback unit 113, the feedback signal is the first feedback signal fbn, the output node is the first node n_stg1, and the switching unit 1131 responds to the first feedback signal fbn; and in the second decision feedback unit 123, the feedback signal is the second feedback signal fbp, the output node is the second node p_stg1, and the switching unit 1131 responds to the second feedback signal fbp.

[0070] In this system, the switching unit 1131 in the first decision feedback unit 113 is either on or off based on the first feedback signal fbn, and the switching unit 1131 in the second decision feedback unit 123 is either on or off based on the second feedback signal fbp. Whether it's the first decision feedback unit 113 or the second decision feedback unit 123, the regulating unit 1132 will only be operational when the switching unit 1131 is on, in order to regulate the voltage at the first node n_stg1 or the second node p_stg1.

[0071] In some embodiments, continue to refer to Figure 6 and Figure 7 The switching unit 1131 may include: a fifth PMOS transistor MP5, connected between the fifth node net5 and the sixth node net6, and the gate of the fifth PMOS transistor MP5 receives the feedback signal.

[0072] It should be noted that, Figure 6 and Figure 7 In this example, the gate of the fifth PMOS transistor MP5 receives the first feedback signal fbn, and the output node is the first node n_stg1. Figure 6 and Figure 7 The diagram shows the specific structure of the first decision feedback unit 113. In practical applications, the specific structure of the second decision feedback unit 123 is similar to that of the first decision feedback unit 113. The difference is that the gate of the fifth PMOS transistor MP5 in the second decision feedback unit 123 receives the second feedback signal fbp, and the output node is the second node p_stg1. Everything else is the same.

[0073] In one example, the first feedback signal fbn received by the switching unit 1131 in the first decision feedback unit 113 is low, and the fifth PMOS transistor MP5 is turned on. At this time, the adjustment unit 1132 adjusts the voltage at the first node n_stg1 based on the control signal. In another example, the second feedback signal fbp received by the switching unit 1131 in the second decision feedback unit 123 is low, and the fifth PMOS transistor MP5 is turned on. At this time, the adjustment unit 1132 adjusts the voltage at the second node p_stg1 based on the control signal.

[0074] In some embodiments, continue to refer to Figure 6 and Figure 7The adjustment unit 1132 may include multiple transistor groups connected in parallel between the sixth node net6 and the output node. Different transistor groups receive different control signals at their control terminals, and their equivalent resistance values ​​are also different. It is understood that the different equivalent resistance values ​​of the different transistor groups make the overall equivalent resistance of the adjustment unit 1132 flexibly controllable. Since the control signals received by the control terminals of the different transistor groups are different, the number of transistor groups in the conducting state can be selected by the control signals to adjust the overall equivalent resistance of the adjustment unit 1132, thereby achieving flexible control of the voltage at the first node n_stg1.

[0075] In one example, refer to Figure 6 The adjustment unit 1132 may include three single MOS transistors connected in parallel between the sixth node net6 and the first node n_stg1, namely the first MOS transistor M01, the second MOS transistor M02, and the third MOS transistor M03, wherein the gate of the first MOS transistor M01 receives the first control signal DfeTrim. <2> The gate of the second MOSFET M02 receives the second control signal DfeTrim. <1> The gate of the third MOSFET M03 receives the third control signal DfeTrim. <0> .

[0076] In some embodiments, reference Figure 7 Different transistor groups may include: at least one transistor group consisting of a single MOSFET; or at least one transistor group comprising at least two MOSFETs connected in series. Thus, a transistor group can be formed by using several single MOSFETs connected in series with the same channel width-to-length ratio to adjust the equivalent channel width-to-length ratio of the transistor group, thereby achieving diverse designs for the adjustment unit 1132. It is understood that different equivalent channel width-to-length ratios of transistor groups can result in different equivalent resistances for the transistor groups.

[0077] In one example, the adjustment unit may include three transistor groups connected in parallel between the sixth node and the first node: a first transistor group, a second transistor group, and a third transistor group. The first transistor group includes a first MOSFET, the gate of which receives a first control signal. The second transistor group includes a second MOSFET, the gate of which receives a second control signal. The third transistor group includes a third MOSFET and a fourth MOSFET connected in series. The first terminal of the fourth MOSFET is connected to the sixth node, the second terminal of the fourth MOSFET is connected to the first terminal of the third MOSFET, the second terminal of the third MOSFET is connected to the first node, and the gates of both the third and fourth MOSFETs receive a third control signal.

[0078] In another example, refer to Figure 7In addition to the first transistor group 13, the second transistor group 23, and the third transistor group 33 mentioned above, the adjustment unit 1132 may also include a fourth transistor group 43 and a fifth transistor group 53 connected in parallel between the sixth node net6 and the first node n_stg1. The first transistor group 13 includes a first MOS transistor MOSFET MO1, whose gate receives the first control signal DfeTrim. <2> The second transistor group 23 includes a second MOSFET MOS transistor ... <1> The third transistor group 33 includes a third MOSFET M03 and a fourth MOSFET M04 connected in series. The first terminal of the fourth MOSFET M04 is connected to the sixth node net6, and the second terminal of the fourth MOSFET M04 is connected to the first terminal of the third MOSFET M03. The second terminal of the third MOSFET M03 is connected to the first node n_stg1. The gates of both the third MOSFET M03 and the fourth MOSFET M04 receive the third control signal DfeTrim. <0> The fourth transistor group 43 includes a fifth MOSFET M05, whose gate receives the fourth control signal DfePerPin. <1> The fifth transistor group 53 includes a sixth MOSFET M06 and a seventh MOSFET M07 connected in series. The first terminal of the seventh MOSFET M07 is connected to the sixth node net6, and the second terminal of the seventh MOSFET M07 is connected to the first terminal of the sixth MOSFET M06. The second terminal of the sixth MOSFET M06 is connected to the first node n_stg1. The gates of both the sixth MOSFET M06 and the seventh MOSFET M07 receive the fifth control signal DfePerPin. <0> .

[0079] It should be noted that in the three examples above, the first control signal DfeTrim <2> Second control signal DfeTrim <1> And the third control signal DfeTrim <0> It can be universal for all data receiving circuits, that is, for different data receiving circuits connected to different DQ ports, the first control signal DfeTrim is provided to different data receiving circuits. <2> Second control signal DfeTrim <1> And the third control signal DfeTrim <0> Same. Furthermore, Figure 7In the example shown, the fourth control signal DfePerPin <1> and the fifth control signal DfePerPin <0> It is designed individually for each DQ port. This means that for different data receiving circuits on each DQ port, such as the first data receiving circuit connected to port DQ1 and the second data receiving circuit connected to port DQ2, the fourth control signal DfePerPin in the first data receiving circuit... <1> and the fifth control signal DfePerPin <0> It is designed based on port DQ1, and the fourth control signal DfePerPin in the second data receiving circuit is... <1> and the fifth control signal DfePerPin <0> It is designed based on port DQ2. Since the inter-symbol interference (ISI) received by data from different DQ ports varies, and the interference experienced by each data signal DQ in the transmission path is also different, a different fourth control signal DfePerPin is designed for each data signal DQ received by each DQ port. <1> and the fifth control signal DfePerPin <0> This allows for targeted adjustment of each DQ port via the adjustment unit 1132, thereby further improving the receiving performance of the data receiving circuit. The DQ port is the port used by the data receiving circuit to receive the data signal DQ.

[0080] In the above embodiments, reference is made to Figure 6 and Figure 7 Different transistor groups may include a first transistor group 13, a second transistor group 23, and a third transistor group 33 connected in parallel. The channel equivalent width-to-length ratio of the first transistor group 13 is twice that of the second transistor group 23, and the channel equivalent width-to-length ratio of the second transistor group 23 is twice that of the third transistor group 33. Thus, the ratio of the equivalent resistance of the first transistor group 13, the second transistor group 23, and the third transistor group 33 is 1:2:4, allowing the total equivalent resistance of the adjustment unit 1132 to be linearly adjustable, thereby achieving linear adjustment of the voltage at the first node n_stg1 and the voltage at the second node p_stg1.

[0081] It should be noted that the above is only an example of the ratio of the channel equivalent width-to-length ratio of the first transistor group 13 to the channel equivalent width-to-length ratio of the second transistor group 23 being 2, and the ratio of the channel equivalent width-to-length ratio of the second transistor group 23 to the channel equivalent width-to-length ratio of the third transistor group 33 being 2. In practical applications, the ratio of the channel equivalent width-to-length ratio of the first transistor group 13 to the channel equivalent width-to-length ratio of the second transistor group 23, or the ratio of the channel equivalent width-to-length ratio of the second transistor group 23 to the channel equivalent width-to-length ratio of the third transistor group 33, can also be other values, such as 3 or 4.

[0082] It should be noted that, Figure 6 In this process, the channel width-to-length ratio of the first MOS transistor M01 can be controlled to be twice the channel width-to-length ratio of the second MOS transistor M02, so that the channel equivalent width-to-length ratio of the first transistor group 13 is twice the channel equivalent width-to-length ratio of the second transistor group 23. Similarly, the channel width-to-length ratio of the second MOS transistor M02 can be controlled to be twice the channel width-to-length ratio of the third MOS transistor M03, so that the channel equivalent width-to-length ratio of the second transistor group 23 is twice the channel equivalent width-to-length ratio of the third transistor group 33. Figure 7 The channel width-to-length ratio of the first MOSFET M01 can be controlled to be twice that of the second MOSFET M02, so that the channel equivalent width-to-length ratio of the first transistor group 13 is twice that of the second transistor group 23. By controlling the channel width-to-length ratios of the second MOSFET M02, the third MOSFET M03, and the fourth MOSFET M04 to be equal, the channel width-to-length ratio of the second MOSFET M02 is twice that of the third transistor group 33, that is, the channel equivalent width-to-length ratio of the second transistor group 23 is twice that of the third transistor group 33.

[0083] also, Figure 7 Furthermore, by controlling the channel width-to-length ratios of the fifth MOSFET M05, the sixth MOSFET M06, and the seventh MOSFET M07 to be equal, the channel width-to-length ratio of the fifth MOSFET M05 can be made twice the equivalent channel width-to-length ratio of the fifth transistor group 53, thus achieving twice the equivalent channel width-to-length ratio of the fourth transistor group 43. In some embodiments, the channel width-to-length ratio of the fifth MOSFET M05 can also be equal to the channel width-to-length ratio of the second MOSFET M02.

[0084] In one example, refer to Figure 5The lengths of the channels of the first MOSFET M01, the second MOSFET M02, and the third MOSFET M03 can be equal. The width of the channel of the first MOSFET M01 can be twice the width of the channel of the second MOSFET M02, and the width of the channel of the second MOSFET M02 can be twice the width of the channel of the third MOSFET M03. It should be noted that in practical applications, while keeping the channel widths of the first MOSFET M01, the second MOSFET M02, and the third MOSFET M03 the same, the ratio of the channel lengths of the first MOSFET M01, the second MOSFET M02, and the third MOSFET M03 can be adjusted, or both the ratio of the channel widths and the ratio of the channel lengths of the first MOSFET M01, the second MOSFET M02, and the third MOSFET M03 can be adjusted, to achieve the ratio between the equivalent width-to-length ratios of the channels of the first transistor group 13, the second transistor group 23, and the third transistor group 33.

[0085] It should be noted that the first MOSFET M01, the second MOSFET M02, the third MOSFET M03, the fourth MOSFET M04, the fifth MOSFET M05, the sixth MOSFET M06, and the seventh MOSFET M07 can all be PMOS transistors or NMOS transistors. When any one of the first MOSFETs M01, the second MOSFET M02, the third MOSFET M03, the fourth MOSFET M04, the fifth MOSFET M05, the sixth MOSFET M06, and the seventh MOSFET M07 is a PMOS transistor, the phase of the control signal controlling the PMOS transistor to be in the on state is the first phase, and when the MOSFET is an NMOS transistor, the phase of the control signal controlling the NMOS transistor to be in the on state is the second phase. The first phase and the second phase are opposite.

[0086] In other embodiments, reference is made to Figure 9 The first internal node n_stg2 serves as the first feedback node, and the second internal node p_stg2 serves as the second feedback node. The feedback signals include the first feedback signal fbn and the second feedback signal fbp. The decision feedback equalization module 103 may include: a first decision feedback unit 113, connected to the first internal node n_stg2 and ground, configured to perform decision feedback equalization on the first internal node n_stg2 based on the first feedback signal fbn; and a second decision feedback unit 123, connected to the second internal node p_stg2 and ground, configured to perform decision feedback equalization on the second internal node p_stg2 based on the second feedback signal fbp.

[0087] The first decision feedback unit 113 is used to adjust the current in the third NMOS transistor MN3 to adjust the voltage at the first internal node n_stg2, and the second decision feedback unit 123 is used to adjust the current in the fourth NMOS transistor MN4 to adjust the voltage at the second internal node p_stg2.

[0088] It should be noted that when the decision feedback equalization module 103 is connected to the first internal node n_stg2 and the second internal node p_stg2 in the second amplification module 102, the specific structure of the first decision feedback unit 113 and the second decision feedback unit 123 and Figure 6 and Figure 7 Similar to the example shown, the only difference is the type of MOS transistor in the switching unit 1131. For instance, when the decision feedback equalization module 103 is connected to the first node n_stg1 and the second node p_stg1 in the first amplification module 101, the MOS transistor in the switching unit 1131 is a PMOS transistor. When the decision feedback equalization module 103 is connected to the first internal node n_stg2 and the second internal node p_stg2 in the second amplification module 102, the MOS transistor in the switching unit 1131 is an NMOS transistor. Details identical or corresponding to those described above will not be repeated here. The following provides a detailed explanation of the differences between the decision feedback equalization module 103 connected to the second amplification module 102 and the decision feedback equalization module 103 connected to the first amplification module 101.

[0089] refer to Figure 9 Each of the first decision feedback unit 113 and the second decision feedback unit 123 includes: a switching unit 1131 configured to conduct the first internal node n_stg2 and the sixth node net6, or the second internal node p_stg2 and the sixth node net6, in response to a feedback signal; and an adjustment unit 1132 connected between the sixth node net6 and ground, configured to adjust the equivalent resistance value between the sixth node net6 and ground in response to a control signal. In the first decision feedback unit 113, the feedback signal is a first feedback signal fbn, and the switching unit 1131 conducts the first internal node n_stg2 and the sixth node net6 in response to the first feedback signal fbn. In the second decision feedback unit 123, the feedback signal is a second feedback signal fbp, and the switching unit 1131 conducts the second internal node p_stg2 and the sixth node net6 in response to the second feedback signal fbp.

[0090] Continue to refer to Figure 9The switching unit 1131 may include: an eleventh NMOS transistor MN11, connected between the first internal node n_stg2 and the sixth node net6, with its gate receiving a first feedback signal fbn; or connected between the second internal node p_stg2 and the sixth node net6, with its gate receiving a second feedback signal fbp. It can be understood that the eleventh NMOS transistor MN11 is equivalent to... Figure 6 and Figure 7 The fifth PMOS transistor, MP5.

[0091] In one example, the first feedback signal fbn received by the switching unit 1131 in the first decision feedback unit 113 is low, and the eleventh NMOS transistor MN11 is turned on. At this time, the adjustment unit 1132 adjusts the voltage at the first internal node n_stg2 based on the control signal. The second feedback signal fbp received by the switching unit 1131 in the second decision feedback unit 123 is low, and the eleventh NMOS transistor MN11 is turned on. At this time, the adjustment unit 1132 adjusts the voltage at the second internal node p_stg2 based on the control signal.

[0092] It should be noted that, Figure 9 Taking the NMOS transistor included in the adjustment unit 1132 as an example, in actual applications, the specific structure of the adjustment unit 1132 is similar to that in the aforementioned embodiment, and will not be described again here.

[0093] In some embodiments, reference Figures 4 to 9 The second amplification module 102 may include: an input unit 112, connected to the first node n_stg1 and the second node p_stg1, configured to compare the first voltage signal and the second voltage signal, and provide a third voltage signal to the seventh node n_stg2 and a fourth voltage signal to the eighth node p_stg2, wherein the second amplification module 102 has a first internal node n_stg2 and a second internal node p_stg2, and the seventh node n_stg2 is the first internal node n_stg2, and the eighth node p_stg2 is the second internal node p_stg2; and a latching unit 122, configured to amplify and latch the third voltage signal and the fourth voltage signal, and output a first output signal Vout to the third node net3 and a second output signal VoutN to the fourth node net4.

[0094] The input unit 112 is used to compare the first voltage signal and the second voltage signal to output the third voltage signal and the fourth voltage signal; the latch unit 122 is used to output a high-level signal to the third node net3 and a low-level signal to the fourth node net4 according to the third voltage signal and the fourth voltage signal, or output a low-level signal to the third node net3 and a high-level signal to the fourth node net4.

[0095] In some embodiments, reference Figure 5 , Figure 8 and Figure 9 The input unit 112 may include: a third NMOS transistor MN3, connected between the seventh node n_stg2 and ground, the gate of the third NMOS transistor MN3 receiving a first voltage signal; and a fourth NMOS transistor MN4, connected between the eighth node p_stg2 and ground, the gate of the fourth NMOS transistor MN4 receiving a second voltage signal.

[0096] In one example, when the first voltage signal level output by the first node n_stg1 is higher than the second voltage signal level output by the second node p_stg1, the conduction level of the third NMOS transistor MN3 is greater than that of the fourth NMOS transistor MN4. This causes the voltage at the seventh node n_stg2 to be less than the voltage at the eighth node p_stg2, which in turn causes the conduction level of the fifth NMOS transistor MN5 to be greater than that of the sixth NMOS transistor MN6. The voltage at the third node net3 is less than the voltage at the fourth node net4. Therefore, the conduction level of the seventh PMOS transistor MP7 is greater than that of the sixth PMOS transistor MP6. The latch unit 122 forms positive feedback amplification, which further causes the first output signal Vout output by the third node net3 to be low and the second output signal VoutN output by the fourth node net4 to be high.

[0097] In some embodiments, continue to refer to Figure 5 , Figure 8 and Figure 9 The latch unit 122 may include: a fifth NMOS transistor MN5, connected between the seventh node n_stg2 and the third node net3, the gate of the fifth NMOS transistor MN5 receiving the second output signal VoutN; a sixth NMOS transistor MN6, connected between the eighth node p_stg2 and the fourth node net4, the gate of the sixth NMOS transistor MN6 receiving the first output signal Vout; a sixth PMOS transistor MP6, connected between the power supply node Vcc and the third node net3, the gate of the sixth PMOS transistor MP6 receiving the second output signal VoutN; and a seventh PMOS transistor MP7, connected between the power supply node Vcc and the fourth node net4, the gate of the seventh PMOS transistor MP7 receiving the first output signal Vout.

[0098] In some embodiments, reference Figure 4 The second amplification module 102 may further include a second reset unit 142, connected to the latch unit 122, configured to reset the latch unit 122. Thus, after the data receiving circuit completes the reception of a data signal DQ and a reference signal Vref, and the output of the first output signal Vout and the second output signal VoutN, the second reset unit 142 can restore the level values ​​at the third node net3 and the fourth node net4 to their initial values, facilitating the subsequent data receiving circuit to perform the next data reception and processing.

[0099] In some embodiments, continue to refer to Figure 5 , Figure 8 and Figure 9 The second reset unit 142 may include: an eighth PMOS transistor MP8 connected between the power supply node Vcc and the third node net3; and a ninth PMOS transistor MP9 connected between the power supply node Vcc and the fourth node net4. The gates of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both responsive to the inverted signal CLK2 of the sampling clock signal CLK1.

[0100] In one example, when the sampling clock signal CLK1 and the enable signal SampEnN are low, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, while the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off. The inverted signal CLK2 of the sampling clock signal CLK1 is high, and both the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are turned off to ensure the normal operation of the data receiving circuit. When the sampling clock signal CLK1 is high, the first PMOS transistor MP1 is turned off, while both the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on. The inverted signal CLK2 of the sampling clock signal CLK1 is low, and both the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are turned on. This pulls up the voltage at the third node net3 and the fourth node net4 to reset the third node net3 and the fourth node net4.

[0101] In some embodiments, reference Figure 8Based on the inclusion of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 in the second reset unit 142, the second reset unit 142 may further include: a tenth PMOS transistor MP10 connected between the power supply node Vcc and the seventh node n_stg2; and an eleventh PMOS transistor MP11 connected between the power supply node Vcc and the eighth node p_stg2. The gates of both the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11 respond to the inverted signal CLK2 of the sampling clock signal CLK1. Thus, when the data receiving circuit does not need to receive the received data signal DQ and the reference signal Vref, it is beneficial to further ensure that the voltage at the third node net3 and the voltage at the fourth node net4 are pulled up, thereby achieving the reset of the third node net3 and the fourth node net4.

[0102] The following provides a detailed explanation of the specific connection relationship between the offset compensation module 104 and the second amplification module 102.

[0103] In some embodiments, reference Figure 5 The first node n_stg1 serves as the first feedback node, and the second node p_stg1 serves as the second feedback node. The data receiving circuit may also include an offset compensation module 104, which is connected to the seventh node n_stg2 and the eighth node p_stg2 and is configured to compensate for the offset voltage of the input unit 112.

[0104] In some embodiments, reference Figure 5 The offset compensation module 104 may include: a first offset compensation unit 114 connected between the seventh node n_stg2 and ground; and a second offset compensation unit 124 connected between the eighth node p_stg2 and ground. The first offset compensation unit 114 is used to compensate for the parameters of the third NMOS transistor MN3; the second offset compensation unit 124 is used to compensate for the parameters of the fourth NMOS transistor MN4. The first offset compensation unit 114 and the second offset compensation unit 124 can adjust the offset voltage of the data receiving circuit by compensating for the parameters of the third NMOS transistor MN3 and the fourth NMOS transistor MN4.

[0105] In some embodiments, reference Figure 5The first offset compensation unit 114 may include: at least two sets of transistor groups connected in parallel, each transistor group including: a seventh NMOS transistor MN7, the first terminal of the seventh NMOS transistor MN7 being connected to the seventh node n_stg2, and the gate of the seventh NMOS transistor MN7 being connected to the first node n_stg1; and a seventh MOS transistor M7, which is configured one-to-one with the seventh NMOS transistor MN7, and is connected between the second terminal of the seventh NMOS transistor MN7 and the ground terminal, with the gate of the seventh MOS transistor M7 receiving the first mismatch adjustment signal Offset_1. It should be noted that, for the sake of simplicity in the illustration, Figure 5 Only one group of transistors in the first offset compensation unit 114 is shown in the diagram.

[0106] Thus, the conduction level of the seventh NMOS transistor MN7 can be controlled by the first mismatch adjustment signal Offset_1 to adjust the overall equivalent resistance of the first mismatch compensation unit 114, thereby further adjusting the voltage at the seventh node n_stg2.

[0107] In some embodiments, the first offset compensation unit 114 includes two sets of transistors connected in parallel. One set of transistors consists of a 7th NMOS transistor (not shown) and a 7th MOS transistor (not shown), and the other set of transistors consists of a 7th NMOS transistor (not shown) and a 7th MOS transistor (not shown). The first mismatch adjustment signal Offset_1 includes a third mismatch adjustment signal (not shown) and a fourth mismatch adjustment signal (not shown). The gates of the 7th NMOS transistor and the 7th MOS transistor are connected to the first node n_stg1. The gate of the 7th MOS transistor receives the third mismatch adjustment signal, and the gate of the 7th MOS transistor receives the fourth mismatch adjustment signal.

[0108] The third mismatch adjustment signal and the fourth mismatch adjustment signal can be different. In this way, the conduction degree of the seventh NMOS transistor and / or the seventh MOS transistor can be controlled based on the third mismatch adjustment signal and the fourth mismatch adjustment signal, so as to flexibly adjust the overall equivalent resistance of the first mismatch compensation unit 114, and further improve the adjustment effect of the voltage at the seventh node n_stg2.

[0109] In some embodiments, reference Figure 5The second offset compensation unit 124 may include: at least two sets of transistor groups connected in parallel, each transistor group including: an eighth NMOS transistor MN8, the first terminal of the eighth NMOS transistor MN8 is connected to the eighth node p_stg2, and the gate of the eighth NMOS transistor MN8 is connected to the second node p_stg1; an eighth MOS transistor M8, the eighth MOS transistor M8 is configured one-to-one with the eighth NMOS transistor MN8, the eighth MOS transistor M8 is connected between the second terminal of the eighth NMOS transistor MN8 and the ground terminal, and the gate of the eighth MOS transistor M8 receives the second mismatch adjustment signal Offset_2. It should be noted that, for the sake of simplicity of the illustration, Figure 5 Only one group of transistors in the second offset compensation unit 124 is shown in the diagram.

[0110] Thus, the conduction level of the eighth NMOS transistor MN8 can be controlled by the second mismatch adjustment signal Offset_2 to adjust the overall equivalent resistance of the second offset compensation unit 124, thereby further adjusting the voltage at the eighth node p_stg2.

[0111] In some embodiments, the second offset compensation unit 124 includes two sets of transistors connected in parallel. One set of transistors consists of an eighth-order NMOS transistor (not shown) and an eighth-order MOS transistor (not shown), and the other set of transistors consists of an eighth-order NMOS transistor (not shown) and an eighth-order MOS transistor (not shown). The second mismatch adjustment signal Offset_2 includes a fifth mismatch adjustment signal (not shown) and a sixth mismatch adjustment signal (not shown). The gates of the eighth-order NMOS transistor and the eighth-order NMOS transistor are connected to the first node n_stg1. The gate of the eighth-order MOS transistor receives the fifth mismatch adjustment signal, and the gate of the eighth-order MOS transistor receives the sixth mismatch adjustment signal.

[0112] The fifth mismatch adjustment signal and the sixth mismatch adjustment signal can be different. In this way, the conduction degree of the eighth NMOS transistor and / or the eighth MOS transistor can be controlled based on the fifth mismatch adjustment signal and the sixth mismatch adjustment signal, so as to flexibly adjust the overall equivalent resistance of the second mismatch compensation unit 124, and further improve the adjustment effect of the voltage at the eighth node p_stg2.

[0113] It should be noted that the seventh MOSFET M7, the seventh-first MOSFET, the seventh-second MOSFET, the eighth MOSFET M8, the eighth-first MOSFET, and the eighth-second MOSFET can all be PMOS or NMOS transistors. When any of the above MOSFETs is a PMOS transistor, the phase of the first mismatch adjustment signal Offset_1 when controlling the PMOS transistor to conduct is the third phase; when the MOSFET is an NMOS transistor, the phase of the second mismatch adjustment signal Offset_2 when controlling the NMOS transistor to conduct is the fourth phase, and the third phase and the fourth phase are opposite.

[0114] The following provides a detailed explanation of the specific connection relationship between the offset compensation module 104 and the first amplification module 101.

[0115] In some embodiments, the seventh node n_stg2 serves as the first feedback node and the eighth node p_stg2 serves as the second feedback node; the data receiving circuit may further include: an offset compensation module 104, connected to the first node n_stg1 and the second node p_stg1, configured to compensate the offset voltage of the comparison unit 121.

[0116] The offset compensation module 104 may include: a first offset compensation unit 114 connected between the fifth node net5 and the first node n_stg1; and a second offset compensation unit 124 connected between the fifth node net5 and the second node p_stg1. The first offset compensation unit 114 is used to compensate for the parameters of the third PMOS transistor MP3; the second offset compensation unit 124 is used to compensate for the parameters of the fourth PMOS transistor MP4. The first offset compensation unit 114 and the second offset compensation unit 124 can adjust the offset voltage of the data receiving circuit by compensating for the parameters of the third PMOS transistor MP3 and the fourth PMOS transistor MP4.

[0117] In some embodiments, reference Figure 8 The data receiving circuit may also include: a thirteenth MOSFET M1, the gate of the thirteenth MOSFET M1 receiving the sampling clock signal CLK1, the drain of the thirteenth MOSFET M1 connected to the fifth node net5, and the source of the thirteenth MOSFET M1 connected to ground.

[0118] In summary, integrating the decision feedback equalization module 103 into the data receiving circuit allows for the adjustment of the signal output by the data receiving circuit using a smaller circuit layout area and lower power consumption. Furthermore, the decision feedback equalization module 103 provided in this embodiment has adjustable adjustment capabilities for the first output signal Vout and the second output signal VoutN. It is understood that when the data signal DQ and / or the reference signal Vref received by the receiving module 100 change, the adjustment capabilities of the decision feedback equalization module 103 for the first output signal Vout and the second output signal VoutN can be flexibly controlled to reduce inter-symbol interference in the data receiving circuit, thereby improving the receiving performance of the data receiving circuit.

[0119] Another embodiment of this disclosure also provides a data receiving system, which will be described in detail below with reference to the accompanying drawings. Figure 1 A functional block diagram of a data receiving system provided in another embodiment of this disclosure.

[0120] refer to Figure 2The data receiving system includes: multiple cascaded data transmission circuits 130, each data transmission circuit 130 including a data receiving circuit 110 as described in an embodiment of the present disclosure and a latching circuit 120 connected to the data receiving circuit 110, each data receiving circuit 110 being connected to a data port to receive a data signal DQ; the upper-level data transmission circuit 130 is connected to the decision feedback equalization module DFE of the lower-level data transmission circuit 130, and the output of the upper-level data transmission circuit 130 serves as the feedback signal of the decision feedback equalization module DFE of the lower-level data transmission circuit 130; the last-level data transmission circuit 130 is connected to the decision feedback equalization module DFE of the first-level data transmission circuit 130, and the output of the last-level data transmission circuit 130 serves as the feedback signal of the decision feedback equalization module DFE of the first-level data transmission circuit 130.

[0121] The latch circuit 120 is configured in a one-to-one correspondence with the data receiving circuit 110. The latch circuit 120 is used to latch and output the signal output by the data receiving circuit 110 corresponding to the latch circuit 120.

[0122] It should be noted that the output of any data transmission circuit 130 can include the following two scenarios: In some embodiments, the output of the data transmission circuit 130 refers to the output of the data receiving circuit 110. This means that the output of the previous-level data receiving circuit 110 serves as the feedback signal for the decision feedback equalization module DFE of the next-level data receiving system, and the output of the last-level data receiving circuit 110 serves as the feedback signal for the decision feedback equalization module DFE of the first-level data receiving system. Thus, the output of the data receiving circuit 110 is directly transmitted to the decision feedback equalization module DFE without passing through the latching circuit 120, which is beneficial for reducing... Low data transmission latency; in other embodiments, the output of the data transmission circuit 130 refers to the output of the latch circuit 120. It can be understood that after the output of the previous level data receiving circuit 110 is latched by the latch circuit 120 corresponding to the data receiving circuit 110, it is connected to the decision feedback equalization module DFE of the next level data receiving system via the output terminal of the latch circuit 120. That is, the output of the previous level latch circuit 120 serves as the feedback signal of the decision feedback equalization module DFE of the next level data receiving system, and the output of the last level latch circuit 120 serves as the feedback signal of the decision feedback equalization module DFE of the first level data receiving system.

[0123] It should be noted that, Figure 1The Sino-Israeli data receiving system includes four cascaded data receiving circuits 110. Taking the phase difference of the sampling clock signals of adjacent data receiving circuits 110 as an example, the number of cascaded data receiving circuits 110 included in the data receiving system is not limited in practical applications. The phase difference of the sampling clock signals of adjacent data receiving circuits 110 can be reasonably set based on the number of cascaded data receiving circuits 110.

[0124] In some embodiments, the phase difference between the sampling clock signals of adjacent data receiving circuits 110 is 90°, and the period of the sampling clock signal is twice the period of the data signal DQ received by the data port. This is beneficial for clock routing and saves power consumption.

[0125] In summary, the data receiving system provided in another embodiment of this disclosure can flexibly control the adjustment capability of the first output signal Vout and the second output signal VoutN, so as to reduce the impact of inter-symbol interference of the data received by the data receiving circuit 110 on the data receiving circuit 110, thereby improving the receiving performance of the data receiving circuit 110 and reducing the impact of inter-symbol interference of the data on the accuracy of the signal output by the data receiving circuit 110, thereby improving the receiving performance of the data receiving system.

[0126] Another embodiment of this disclosure also provides a storage device, including: a plurality of data ports; and a plurality of data receiving systems as provided in another embodiment of this disclosure, each data receiving system corresponding to a data port. Thus, each data port in the storage device can flexibly control the received data signal DQ through the data receiving system, and improve the adjustment capability of the first output signal Vout and the second output signal VoutN, thereby improving the receiving performance of the storage device.

[0127] In some embodiments, the storage device may be a DDR memory, such as a DDR4 memory, DDR5 memory, DDR6 memory, LPDDR4 memory, LPDDR5 memory, or LPDDR6 memory.

[0128] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A data receiving circuit, characterized in that, include: The receiving module is configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal. A decision feedback equalization module, connected to the feedback node of the receiving module, is configured to perform decision feedback equalization on the receiving module based on a feedback signal to adjust the first output signal and the second output signal, wherein the feedback signal is obtained based on previously received data, and the decision feedback equalization module's ability to adjust the first output signal and the second output signal is adjustable. The receiving module includes: The first amplification module is configured to receive the data signal and the reference signal, compare the data signal and the reference signal in response to the sampling clock signal, and output a first voltage signal through a first node and a second voltage signal through a second node. The second amplification module, connected to the first node and the second node, is configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output the first output signal through the third node and the second output signal through the fourth node. The feedback node includes a first feedback node and a second feedback node, with the first node serving as the first feedback node and the second node serving as the second feedback node. The decision feedback equalization module is configured to perform decision feedback equalization on the first node and the second node based on the feedback signal to adjust the first voltage signal and the second voltage signal. The first amplification module includes: A current source is configured to be connected between the power supply node and the fifth node, and to provide current to the fifth node in response to the sampling clock signal; The comparison unit, connected to the fifth node, the first node, and the second node, is configured to receive the data signal and the reference signal, compare the data signal and the reference signal when the current source provides current to the fifth node in response to the sampling clock signal, and output the first voltage signal through the first node and the second voltage signal through the second node. The first node serves as the first feedback node, the second node serves as the second feedback node, and the feedback signal includes a first feedback signal and a second feedback signal; the decision feedback equalization module includes: The first decision feedback unit, connected to the first node and the fifth node, is configured to perform decision feedback equalization on the first node based on the first feedback signal to adjust the first voltage signal. The second decision feedback unit, connected to the second node and the fifth node, is configured to perform decision feedback equalization on the second node based on the second feedback signal to adjust the second voltage signal.

2. The data receiving circuit as described in claim 1, characterized in that, The data receiving circuit further includes an offset compensation module, connected to the second amplification module, configured to compensate for the offset voltage of the second amplification module.

3. The data receiving circuit as described in claim 1, characterized in that, The current source includes: A first PMOS transistor is connected between the power supply node and the fifth node, and the gate of the first PMOS transistor receives the sampling clock signal.

4. The data receiving circuit as described in claim 3, characterized in that, The current source also includes: A second PMOS transistor is connected between the power supply node and the first PMOS transistor, and the gate of the second PMOS transistor receives an enable signal.

5. The data receiving circuit as described in claim 3, characterized in that, The comparison unit includes: A third PMOS transistor is connected between the fifth node and the first node, and the gate of the third PMOS transistor receives the data signal. A fourth PMOS transistor is connected between the fifth node and the second node, and the gate of the fourth PMOS transistor receives the reference signal.

6. The data receiving circuit as described in claim 3, characterized in that, The first amplification module also includes: A first reset unit, connected to the first node and the second node, is configured to reset the first node and the second node.

7. The data receiving circuit as described in claim 6, characterized in that, The first reset unit includes: A first NMOS transistor is connected between the first node and ground, and the gate of the first NMOS transistor receives the sampling clock signal. A second NMOS transistor is connected between the second node and the ground terminal, and the gate of the second NMOS transistor receives the sampling clock signal.

8. The data receiving circuit as described in claim 1, characterized in that, Each of the first decision feedback unit and the second decision feedback unit includes: A switching unit is configured to turn on the fifth node and the sixth node in response to the feedback signal; An adjustment unit, connected between the sixth node and the output node, the output node being one of the first node and the second node, is configured to adjust the equivalent resistance value between the sixth node and the output node in response to a control signal. In the first decision feedback unit, the feedback signal is the first feedback signal, the output node is the first node, and the switching unit responds to the first feedback signal; in the second decision feedback unit, the feedback signal is the second feedback signal, the output node is the second node, and the switching unit responds to the second feedback signal.

9. The data receiving circuit as described in claim 8, characterized in that, The switching unit includes: A fifth PMOS transistor is connected between the fifth node and the sixth node, and the gate of the fifth PMOS transistor receives the feedback signal.

10. The data receiving circuit as described in claim 9, characterized in that, The adjustment unit includes: Multiple transistor groups are connected in parallel between the sixth node and the output node. The control terminals of different transistor groups receive different control signals, and the equivalent resistance values ​​of different transistor groups are different.

11. The data receiving circuit as described in claim 10, characterized in that, The different transistor groups include: At least one of the transistor groups is composed of a single MOS transistor; At least one of the transistor groups comprises at least two MOS transistors connected in series.

12. The data receiving circuit as described in claim 11, characterized in that, The different transistor groups include: A first transistor group, a second transistor group, and a third transistor group are connected in parallel. The channel equivalent width-to-length ratio of the first transistor group is twice that of the channel equivalent width-to-length ratio of the second transistor group, and the channel equivalent width-to-length ratio of the second transistor group is twice that of the channel equivalent width-to-length ratio of the third transistor group.

13. The data receiving circuit as described in claim 1, characterized in that, The second amplification module includes: An input unit, connected to the first node and the second node, is configured to compare the first voltage signal and the second voltage signal, and provide a third voltage signal to a seventh node and a fourth voltage signal to an eighth node, wherein the second amplification module has a first internal node and a second internal node, and the seventh node is the first internal node and the eighth node is the second internal node; The latching unit is configured to amplify and latch the third voltage signal and the fourth voltage signal, and output the first output signal to the third node and the second output signal to the fourth node.

14. The data receiving circuit as described in claim 13, characterized in that, The input unit includes: A third NMOS transistor is connected between the seventh node and ground, and the gate of the third NMOS transistor receives the first voltage signal. A fourth NMOS transistor is connected between the eighth node and the ground terminal, and the gate of the fourth NMOS transistor receives the second voltage signal.

15. The data receiving circuit as described in claim 13, characterized in that, The latch unit includes: A fifth NMOS transistor is connected between the seventh node and the third node, and the gate of the fifth NMOS transistor receives the second output signal; A sixth NMOS transistor is connected between the eighth node and the fourth node, and the gate of the sixth NMOS transistor receives the first output signal; A sixth PMOS transistor is connected between the power supply node and the third node, and the gate of the sixth PMOS transistor receives the second output signal; A seventh PMOS transistor is connected between the power supply node and the fourth node, and the gate of the seventh PMOS transistor receives the first output signal.

16. The data receiving circuit as described in claim 13, characterized in that, The first node serves as the first feedback node, and the second node serves as the second feedback node; The data receiving circuit further includes: An offset compensation module, connected to the seventh node and the eighth node, is configured to compensate for the offset voltage of the input unit.

17. The data receiving circuit as described in claim 16, characterized in that, The misalignment compensation module includes: The first misalignment compensation unit is connected between the seventh node and the ground terminal; The second misalignment compensation unit is connected between the eighth node and the ground terminal.

18. The data receiving circuit as described in claim 17, characterized in that, The first misalignment compensation unit includes: At least two sets of transistors connected in parallel, each set of transistors comprising: A seventh NMOS transistor, wherein the first terminal of the seventh NMOS transistor is connected to the seventh node, and the gate of the seventh NMOS transistor is connected to the first node; The seventh MOS transistor is configured in a one-to-one correspondence with the seventh NMOS transistor. The seventh MOS transistor is connected between the second terminal of the seventh NMOS transistor and the ground terminal. The gate of the seventh MOS transistor receives the first mismatch adjustment signal.

19. The data receiving circuit as claimed in claim 17, wherein the second offset compensation unit comprises: At least two sets of transistors connected in parallel, each set of transistors comprising: The eighth NMOS transistor, the first terminal of which is connected to the eighth node, and the gate of which is connected to the second node; The eighth MOS transistor is configured in a one-to-one correspondence with the eighth NMOS transistor. The eighth MOS transistor is connected between the second terminal of the eighth NMOS transistor and the ground terminal. The gate of the eighth MOS transistor receives the second mismatch adjustment signal.

20. The data receiving circuit as described in claim 13, characterized in that, The second amplification module also includes: The second reset unit, connected to the latch unit, is configured to reset the latch unit.

21. The data receiving circuit as described in claim 20, characterized in that, The second reset unit includes: The eighth PMOS transistor is connected between the power supply node and the third node; The ninth PMOS transistor is connected between the power supply node and the fourth node, and the gates of both the eighth PMOS transistor and the ninth PMOS transistor respond to the inverted signal of the sampling clock signal.

22. The data receiving circuit as described in claim 21, characterized in that, The second reset unit further includes: The tenth PMOS transistor is connected between the power supply node and the seventh node; The eleventh PMOS transistor is connected between the power supply node and the eighth node. The gates of both the tenth and eleventh PMOS transistors respond to the inverted signal of the sampling clock signal.

23. A data receiving system, characterized in that, include: Multiple cascaded data transmission circuits, each of which includes a data receiving circuit as described in any one of claims 1-22 and a latching circuit connected to the data receiving circuit, each of which is connected to a data port to receive the data signal; the decision feedback equalization module of the next-level data transmission circuit is connected to the previous-level data transmission circuit, and the output of the previous-level data transmission circuit serves as the feedback signal of the decision feedback equalization module of the next-level data transmission circuit; The final stage of the data transmission circuit is connected to the decision feedback equalization module of the first stage of the data transmission circuit, and the output of the final stage of the data transmission circuit serves as the feedback signal of the decision feedback equalization module of the first stage of the data transmission circuit.

24. The data receiving system as described in claim 23, characterized in that, The system includes four cascaded data receiving circuits, with a 90° phase difference between the sampling clock signals of adjacent stages.

25. A storage device, characterized in that, include: Multiple data ports; Multiple data receiving systems as described in claim 23 or 24, each of the data receiving systems corresponding to one of the data ports.

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