Word line drive circuit and word line driver, storage device

Abstract

This disclosure relates to a word line driving circuit, a word line driver, and a memory device. The word line driving circuit includes: at least two sub-word line drivers connected to a main word line and a sub-word line, the main word line providing an enable signal; each sub-word line driver includes a holding transistor, with a first terminal and a second terminal of the holding transistor connected to different sub-word lines, and the holding transistor receiving a second driving signal; the sub-word line drivers are configured to provide a first driving signal to a selected sub-word line in response to the first driving signal and the enable signal; and to turn on the holding transistor in response to the first driving signal, the enable signal, and the second driving signal; the holding transistor includes a first transistor and a second transistor, the sub-word line connected to the first terminal and the second terminal of the first transistor corresponding to the same main word line, and the main word line connected to the first terminal and the second terminal of the second transistor corresponding to a different main word line. This disclosure helps to reduce the layout area of ​​the word line driving circuit.

Description

1.1.1 Technical Field This disclosure relates to the field of semiconductor technology, and in particular to a word line driving circuit, a word line driver, and a storage device. 1.1.2 Background Technology Memory is a common semiconductor structure. As the size of semiconductor structures continues to shrink, more memory can be integrated onto a chip, thus contributing to increased product capacity. In dynamic random access memory (DRAM), data needs to be written to / read from memory cells using word lines and bit lines, and operation is based on the voltage applied to the word lines.

[0003] As DRAM capacity increases, the number of memory cells connected to a word line increases, and the distance between word lines decreases, potentially leading to speed latency issues. To improve word line voltage latency, a word line can be divided into multiple sub-word lines, and each sub-word line can be driven using a sub-word-line driver (SWD). The sub-word-line driver can be integrated into the word line driving circuit.

[0004] However, the current word line driver circuits have a large layout area, resulting in low memory integration density. 1.1.3 Summary of the Invention This disclosure provides a word line driving circuit, a word line driver, and a storage device, which at least helps to reduce the layout area of ​​the word line driving circuit.

[0006] This disclosure provides a word line driving circuit, including: at least two sub-word line drivers, each sub-word line driver being connected to a main word line and a sub-word line, the main word line being used to provide an enable signal; each sub-word line driver includes a holding transistor, a first terminal and a second terminal of the holding transistor being respectively connected to different sub-word lines, and the gate of the holding transistor receiving a second driving signal; the sub-word line drivers are configured to provide a first driving signal to a selected sub-word line in response to a first driving signal and an enable signal; and to turn on the first terminal and the second terminal of the holding transistor in response to the first driving signal, the enable signal, and the second driving signal; wherein the holding transistor includes a first transistor and a second transistor, two sub-word lines connected to the first terminal and the second terminal of the first transistor respectively correspond to the same main word line, and two sub-word lines connected to the first terminal and the second terminal of the second transistor respectively correspond to different main word lines.

[0007] In some embodiments, the selected sub-word line is a sub-word line connected to the first or second terminal of the holding transistor. In some embodiments, the holding transistor includes an NMOS transistor.

[0008] In some embodiments, the sub-word line driver includes: a pull-up transistor with its gate connected to the main word line, its source receiving a first drive signal, and its drain connected to the sub-word line and a first or second terminal of a holding transistor; and a pull-down transistor with its gate connected to the main word line, its drain connected to the drain of the pull-up transistor, and its source receiving a third drive signal.

[0009] In some embodiments, the pull-up transistor includes a PMOS transistor; the pull-down transistor includes an NMOS transistor.

[0010] Accordingly, this disclosure also provides a word line driver, comprising: a PMOS region including a plurality of first active regions extending along a first direction, the first active regions including a first channel region and a first source region and a first drain region respectively located on opposite sides of the first channel region; an NMOS region arranged along a second direction with the PMOS region, including a plurality of second active regions extending along the first direction, the second active regions including a second channel region and a second source region and a second drain region respectively located on opposite sides of the second channel region, the second active regions further including a third channel region and a third source region and a third drain region respectively located on opposite sides of the third channel region; and a first gate, each first gate extending along the second direction and covering the plurality of first channel regions and the plurality of second channel regions, the first gate being electrically connected to the main word line. The transistor is configured such that a first gate, a first source region, and a first drain region constitute a pull-up transistor, and a first gate, a second source region, and a second drain region constitute a pull-down transistor, the pull-down transistor including a first transistor and a second transistor; a plurality of second gates, each second gate covering a corresponding third channel region, the second gate, the third source region, and the third drain region constitute a holding transistor; wherein, the first drain region of a pull-up transistor is electrically connected to the first drain region of a pull-down transistor and is electrically connected to a corresponding sub-word line; the third drain region and the third source region of the same first transistor are respectively electrically connected to the second drain regions of two pull-down transistors sharing the same first gate; the third drain region and the third source region of the same second transistor are respectively electrically connected to the second drain regions of two pull-down transistors corresponding to different first gates.

[0011] In some embodiments, the NMOS region includes: a first NMOS region and a second NMOS region, located on opposite sides of the PMOS region; wherein, a first transistor is located in the first NMOS region; a second transistor is located in the second NMOS region; a portion of the pull-down transistors are located in the first NMOS region, and the remaining portion of the pull-down transistors are located in the second NMOS region.

[0012] In some embodiments, each first gate includes: at least two extensions spaced apart along a first direction, extending along a second direction and covering a plurality of first channel regions and a plurality of second channel regions; and a connecting portion connecting the extensions arranged adjacent to each other along the first direction.

[0013] In some embodiments, the connecting portion covers the area between adjacent first active regions, and also covers the area between the first active region and the second active region.

[0014] In some embodiments, along the first direction, the distance between adjacent extensions of the first NMOS region is greater than the distance between adjacent extensions of a portion of the PMOS region, and the second gate corresponding to the first transistor is located between adjacent extensions.

[0015] In some embodiments, the third drain region of the first transistor is shared with the second drain region of a pull-down transistor located in the first NMOS region; the third source region of the first transistor is shared with the second drain region of another pull-down transistor located in the first NMOS region.

[0016] In some embodiments, along the first direction, the distance between adjacent extensions of the second NMOS region is less than the distance between adjacent extensions of a portion of the PMOS region, and the second gate corresponding to the second transistor is located outside the region enclosed by the two extensions.

[0017] In some embodiments, the third drain region of the second transistor is shared with the second drain region of a pull-down transistor located in the second NMOS region; the third source region of the second transistor is shared with the second drain region of another pull-down transistor located in the second NMOS region.

[0018] In some embodiments, the PMOS region includes: a first PMOS region and a second PMOS region arranged along a second direction, the second PMOS region being located between the first PMOS region and the first NMOS region; two extensions of the same first gate cover the same first active region of the first PMOS region, and the two extensions also respectively cover two first active regions of the second PMOS region arranged along a first direction; wherein, along the first direction, the distance between adjacent extensions of the first PMOS region is smaller than the distance between adjacent extensions of the second PMOS region.

[0019] In some embodiments, the pull-up transistors corresponding to the first PMOS region share a first source region, and the shared first source region receives the first drive signal.

[0020] In some embodiments, each first gate covers 4×N first channel regions and 4×N second channel regions, and each first gate forms a pull-up transistor and a pull-down transistor that are electrically connected to 2×N holding transistors; wherein N is a positive integer greater than or equal to 1.

[0021] In some embodiments, the plurality of first active regions include: at least two first active regions disposed near the NMOS region, the two first active regions being spaced apart along a first direction and having a spacer region, wherein the second gate and the spacer region are disposed opposite each other along a second direction.

[0022] Accordingly, embodiments of this disclosure also provide a storage device, including: a storage cell array including a plurality of storage cells connected to a plurality of sub-word lines and a plurality of bit lines; a word line driving circuit provided in any of the above; or a word line driver provided in any of the above.

[0023] In some embodiments, the system further includes a signal generation circuit configured to output a first driving signal and a second driving signal, wherein the rising edge of the second driving signal has a preset duration delay compared to the falling edge of the first driving signal.

[0024] In some embodiments, the signal generation circuit includes: a decoder configured to output a first drive signal; a PMOS switch whose gate receives the first drive signal, one end receives the original drive signal, and the other end is connected to an inverter, the inverter outputs a second drive signal, wherein the change edge of the original drive signal is consistent with the change edge of the first drive signal.

[0025] The technical solution provided in this disclosure has the following advantages: The word line driving circuit provided in this disclosure includes at least two sub-word line drivers. Each sub-word line driver is connected to a main word line and a sub-word line, enabling the sub-word line driver to drive the sub-word line based on an enable signal received from the main word line. Each sub-word line driver includes a holding transistor, with its first and second ends connected to different sub-word lines. This means two sub-word lines share the same holding transistor, allowing one sub-word line connected to one end of the holding transistor to be driven while the other sub-word line connected to the other end of the holding transistor is in an unselected state. Furthermore, a first transistor controls two sub-word lines corresponding to the same main word line, and a second transistor controls two sub-word lines corresponding to two different main word lines. This allows for flexible configuration of the holding transistor's connection to different sub-word lines, reducing the area occupied by the word line driving circuit while maintaining its performance, thereby reducing the layout area of ​​the word line driving circuit. 1.1.4 Attached Figure Description One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a circuit diagram of a word line driving circuit; Figure 2 This is a diagram of a sub-word line system architecture; Figure 3 A circuit diagram of a word line driving circuit provided for an embodiment of this disclosure; Figure 4 A timing diagram of each signal in a word line driving circuit provided in an embodiment of this disclosure; Figure 5 A schematic diagram of the layout structure of a word line driver provided in an embodiment of this disclosure; Figure 6 A schematic diagram of another word line driver layout provided in an embodiment of this disclosure; Figure 7 A schematic diagram of the layout structure of another word line driver provided in an embodiment of this disclosure; Figure 8 A schematic diagram of the layout structure of another word line driver provided in an embodiment of this disclosure; Figure 9 This is a circuit diagram of a signal generation device provided in an embodiment of the present disclosure. 1.1.5 Detailed Implementation As is known from the background technology, current word line driver circuits suffer from a large layout area. Analysis reveals that one reason for this large layout area is the reference... Figure 1 as well as Figure 2 Currently, word line driving circuits include at least one sub-word line driver, which is connected to an MWLb and a sub-word line WL. The sub-word line driver also includes a holding transistor, with one end of the holding transistor 1 connected to the sub-word line WL and the other end coupled to a low level VKK. The sub-word line driver receives an enable signal and a drive signal PXID, and provides the drive signal PXID to the sub-word line WL, thereby driving the sub-word line WL. When sub-word line WL is not needed, the first and second ends of the holding transistor can be turned on in response to the enable signal, drive signal PXID, and drive signal PXIB, causing the first end of the holding transistor 1 to be coupled to a low level VKK, thereby pulling the sub-word line WL connected to the first end of the holding transistor 1 low to a low level VKK, thus turning off the sub-word line WL. In other words, one holding transistor is used to control only one sub-word line, keeping the sub-word line in an unselected state. (Reference) Figure 2As can be seen, when there are two main word lines in the word line driver circuit, denoted as MWLb1 and MWLb2 respectively, and each main word line corresponds to two sub-word line drivers SWD respectively, and each holding transistor is electrically connected to a sub-word line (multiple sub-word lines are denoted as WL0 to WL15 in the figure), the sub-word line drivers respond to the corresponding drive signal PXIB and the corresponding drive signal PXID respectively, thereby controlling the shutdown of the sub-word line. This will occupy a lot of space in the word line driver circuit layout.

[0029] This disclosure provides a word line driving circuit, a word line driver, and a storage device. The word line driving circuit includes at least two word line drivers, each connected to a main word line and a sub-word line. The first and second terminals of a holding transistor in the sub-word line driver are respectively connected to two sub-word lines, meaning the two sub-word lines share the same holding transistor. When a sub-word line connected to one end of the holding transistor is driven, the holding transistor can keep the sub-word line connected to the other end of the holding transistor in an unselected state. Furthermore, a first transistor controls two sub-word lines corresponding to the same main word line, and a second transistor controls two sub-word lines corresponding to two different main word lines, thereby reducing the area occupied by the word line driving circuit and its layout area while maintaining its performance.

[0030] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0031] Figure 3 This is a circuit diagram of a word line driving circuit provided in an embodiment of the present disclosure.

[0032] refer to Figure 3At least two sub-word line drivers 100 are provided, each sub-word line driver 100 being connected to a main word line and a sub-word line, the main word line being used to provide an enable signal; each sub-word line driver 100 includes a holding transistor, the first and second terminals of which are respectively connected to different sub-word lines, and the gate of the holding transistor receiving a second drive signal PXIB; the sub-word line driver 100 is configured to provide the first drive signal PXID to the selected sub-word line in response to the first drive signal PXID and the enable signal; and to turn on the first and second terminals of the holding transistor in response to the first drive signal PXID, the enable signal, and the second drive signal PXIB; wherein the holding transistor includes a first transistor 103 and a second transistor 104, two sub-word lines connected to the first and second terminals of the first transistor 103 respectively correspond to the same main word line, and two sub-word lines connected to the first and second terminals of the second transistor 104 respectively correspond to different main word lines.

[0033] The first and second terminals of the holding transistor are connected to two different sub-word lines, meaning the two sub-word lines share the same holding transistor. When the word line driver responds to the first drive signal PXID and the enable signal, it provides the first drive signal PXID to the selected sub-word line. In some embodiments, the selected sub-word line is the sub-word line connected to either the first or second terminal of the holding transistor, thus selecting the sub-word line connected to either the first or second terminal of the holding transistor, while the other sub-word line connected to the holding transistor is not selected. When the word line driver responds to the first drive signal PXID, the enable signal, and the second drive signal PXIB, it turns on the first and second terminals of the holding transistor, thereby pulling the level of the selected sub-word line to match the level of the unselected sub-word line, thus turning off the selected sub-word line. That is, when the sub-word line connected to one end of the holding transistor is driven, the holding transistor can keep the sub-word line connected to the other end of the holding transistor in an unselected state, thereby reducing the area occupied by the word line driving circuit and reducing the layout area of ​​the word line driving circuit while maintaining the performance of the word line driving circuit.

[0034] refer to Figure 3 Each main word line is connected to at least two sub-word line drivers 100, and each main word line corresponds to at least two sub-word lines. Two sub-word lines connected to the first and second terminals of the first transistor 103 each correspond to the same main word line. Two sub-word lines connected to the first and second terminals of the second transistor 104 each correspond to different main word lines. In other words, the enable signal provided by the same main word line can be used to drive multiple corresponding sub-word lines.

[0035] In some embodiments, there are two main word lines. One main word line can be connected to eight sub-word line drivers 100, and one main word line corresponds to eight sub-word lines. That is, two main word lines can be used to control 16 sub-word lines. Since the two sub-word lines share the same holding transistor, the number of holding transistors is only eight. There are four first transistors 103 and four second transistors 104. Specifically, the word line driving circuit can be divided into a first region 11 and a second region 12. In the first region 11, there are four first transistors 103. The first and second ends of each first transistor 103 are respectively connected to two sub-word lines corresponding to the same main word line. In the second region 12, the first and second ends of each second transistor 104 are respectively connected to two sub-word lines corresponding to different main word lines. Specifically, main word line MWL1 corresponds to sub-word line WL1, and main word line MWL2 corresponds to sub-word line WL2. That is, in the first region 11, each main word line corresponds to a different first transistor 103, and in the second region 12, two main word lines can share the same second transistor 104. When there are two main word lines, a total of 16 sub-word lines can be driven, while only 8 holding transistors are required. Compared to one main word line corresponding to 8 holding transistors, the area occupied by the sub-word line driver 100 is greatly reduced, thereby significantly reducing the layout area of ​​the word line driving circuit.

[0036] It is understood that in some other embodiments, the number of first transistors 103 in the first region 11 may also be two, and the number of second transistors 104 in the second region 12 may be six. This disclosure does not limit the number of first transistors 103 in the first region 11 or the number of second transistors 104 in the second region 12; it only requires that the first and second ends of each holding transistor are connected to different sub-word lines.

[0037] It is understandable that, regardless of how many sub-word line drivers 100 are connected to a main word line, and whether a main word line shares 4 holding transistors or two main word lines share 8 holding transistors, only one sub-word line can be driven at any given time in a word line driving circuit, and the remaining sub-word lines are in an unselected state.

[0038] The sub-word line driver 100 can activate or precharge a selected sub-word line in response to an enable signal provided by the main word line and a first drive signal PXID and a second drive signal PXIB input to the sub-word line driver 100. The enable signal, the first drive signal PXID, and the second drive signal PXIB can be provided by external circuitry. In some embodiments, the first drive signal PXID can be a high voltage level, and the sub-word line driver 100 can drive the sub-word line with a high voltage. Correspondingly, when a high voltage level is used to drive the sub-word line, a low voltage level can be used to turn off the sub-word line.

[0039] refer to Figure 3 Since a sub-word line driver 100 is connected to a sub-word line, and a holding transistor is connected to two different sub-word lines respectively, in the word line driving circuit, the number of sub-word line drivers 100 is twice the number of holding transistors, that is, the two sub-word lines connected to a holding transistor are also connected to two sub-word line drivers 100 respectively.

[0040] It is worth noting that in the word line driving circuit, when one word line driver drives its connected sub-word line, the sub-word lines connected to the remaining sub-word line drivers 100 are all in an unselected state. That is, only one sub-word line can be selected at a time in the word line driving circuit. Therefore, when a sub-word line connected to either the first or second terminal of the holding transistor is selected, the sub-word line connected to the other terminal is unselected. Thus, when the first and second terminals of the holding transistor are turned on, the voltage level of the sub-word line connected to the first terminal of the holding transistor will be pulled down to match the voltage level of the sub-word line connected to the second terminal of the holding transistor. This allows the voltage level of the selected sub-word line to be pulled down to match the voltage level of the unselected sub-word line, thus turning the selected sub-word line off.

[0041] In some embodiments, the holding transistor includes an NMOS transistor. The second drive signal PXIB can be a high-level signal. The holding transistor turns on in response to the high-level signal, thereby turning on both the first and second terminals of the holding transistor. When the first and second terminals are turned on, the voltage levels of the two sub-word lines connected to the first and second terminals are the same. Specifically, when the sub-word line connected to the first terminal of the holding transistor is selected, the sub-word line connected to the second terminal of the holding transistor is in an unselected state. If the sub-word line is driven in response to a high voltage level, the node at the first terminal of the holding transistor is at a high voltage level, and the node at the second terminal is at a low voltage level. When the first and second terminals of the holding transistor are turned on, the voltage level of the node at the first terminal of the holding transistor is pulled down to match the voltage level of the node at the second terminal, that is, the node at the first terminal of the holding transistor has a negative voltage level, which is equivalent to pre-charging the sub-word line connected to the first terminal of the holding transistor with a negative voltage, ensuring that the sub-word line connected to the first terminal of the transistor is turned off.

[0042] It is not difficult to see that in this embodiment of the present disclosure, since the first and second ends of the holding transistor are respectively connected to two sub-word lines, when the first and second ends of the holding transistor are turned on, the level of the node at the first end is consistent with the level of the node at the second end, that is, the voltage of the selected word line is consistent with the voltage of the unselected word line, thereby ensuring that the selected word line can be turned off.

[0043] In some embodiments, the sub-word line driver 100 includes: a pull-up transistor 101, with its gate connected to the main word line, its source receiving a first drive signal PXID, and its drain connected to the sub-word line and a first or second terminal of a holding transistor; and a pull-down transistor 102, with its gate connected to the main word line, its drain connected to the drain of the pull-up transistor 101, and its source receiving a third drive signal VKK. The pull-up transistor 101, in response to an enable signal and the first drive signal PXID, pulls the sub-word line up to the level of the first drive signal PXID, and the sub-word line is driven in response to the first drive signal PXID. The pull-down transistor 102, in response to an enable signal, pulls the sub-word line down to the level of the third drive signal VKK, and the sub-word line is turned off in response to the third drive signal VKK. In some embodiments, the first drive signal PXID can be high, and the third drive signal VKK can be low; for example, the voltage of the third drive signal VKK can be 0 or less than 0.

[0044] Specifically, when the sub-word line driver 100 drives the sub-word line, the gate of the pull-up transistor 101 is turned on in response to the enable signal, and the first drive signal PXID is transmitted from the source to the drain of the pull-up transistor 101. Since the drain of the pull-up transistor 101 is connected to the sub-word line, the first drive signal PXID is transmitted from the drain of the pull-up transistor 101 to the sub-word line, thereby pulling up the level of the sub-word line to the level of the first drive signal PXID.

[0045] When the sub-word line driver 100 turns off the sub-word line, the gate of the pull-down transistor 102 turns on in response to the enable signal. The third drive signal VKK is transmitted from the source of the pull-down transistor 102 to the drain. The drain of the pull-down transistor 102 is connected to the drain of the pull-up transistor 101, and the drain of the pull-up transistor 101 is connected to the sub-word line. This causes the third drive signal VKK to be transmitted from the drain of the pull-down transistor 102 to the sub-word line, thereby pulling down the level of the sub-word line to the third drive signal VKK.

[0046] It is worth noting that, due to potential instability of the enable signal or the third drive signal VKK, or interference from external noise affecting the word line drive circuit, the sub-word line voltage may not be less than 0. Therefore, relying solely on the third drive signal VKK may not be sufficient to completely turn off the sub-word line. However, in this embodiment, since the first and second terminals of the holding transistor are connected to two different sub-word lines, when the first and second terminals of the holding transistor are turned on, the voltage of the selected word line will be pulled down to match the voltage of the unselected word line. That is, the holding transistor can couple the voltage of the selected word line to a negative voltage level, thereby turning it off. Therefore, regardless of changes in the level of the enable signal or the third drive signal VKK, the unselected word line can maintain a stable voltage value.

[0047] In some embodiments, pull-up transistor 101 includes a PMOS transistor; pull-down transistor 102 includes an NMOS transistor. That is, pull-up transistor 101 turns on in response to a low-level signal, and pull-down transistor 102 turns on in response to a high-level signal, so that pull-up transistor 101 and pull-down transistor 102 can operate independently and control the driving and turning off of the sub-word line respectively.

[0048] Specifically, when pull-up transistor 101 is a PMOS transistor and pull-down transistor 102 is an NMOS transistor, the word line drive circuit operates as follows: The two sub-word line drivers 100 are respectively designated as: First Sub-Word Line Driver and Second Sub-Word Line Driver. The sub-word line connected to the first terminal of the holding transistor is designated as First Sub-Word Line WL1, and the sub-word line connected to the second terminal of the holding transistor is designated as Second Sub-Word Line WL2. First Sub-Word Line WL1 is connected to First Sub-Word Line Driver, and Second Sub-Word Line WL2 is connected to First Sub-Word Line Driver.

[0049] The first sub-word line driver drives the first sub-word line WL1, at which time the second sub-word line WL2 is in an unselected state.

[0050] The first sub-word line driver drives the first sub-word line WL1 in response to a low-level enable signal, a high-level first drive signal PXID, and a low-level second drive signal PXIB. Specifically, the pull-up transistor 101 is turned on in response to the low-level enable signal, and the high-level first drive signal PXID is transmitted from the source of the pull-up transistor 101 to the drain of the pull-up transistor 101. At the same time, the holding transistor is turned off in response to the low-level second drive signal PXIB, so that the level of the first sub-word line WL1 is pulled up to the first drive signal PXID, has a high level, and is thus driven.

[0051] The first sub-word line driver shuts down the first sub-word line WL1 in response to a high-level enable signal, a low-level first drive signal PXID, and a high-level second drive signal PXIB. The pull-down transistor 102 turns on in response to a high-level enable signal, and the pull-up transistor 101 turns off in response to a low-level enable signal. The third drive signal VKK is transmitted from the source to the drain of the pull-down transistor 102, pulling the level of the first sub-word line WL1 down to the third drive signal VKK, resulting in a low level. Simultaneously, the holding transistor turns on in response to a high-level second drive signal PXIB, ensuring that the level of the first sub-word line WL1 matches the level of the second sub-word line WL2. Since the second sub-word line WL2 is in an unselected state, the first sub-word line WL1 is ensured to be turned off, thus becoming unselected.

[0052] The principle of the first sub-word line driver driving the second sub-word line WL2 and turning off the sub-word line is the same as that of the first sub-word line driver, and will not be repeated below. It is worth noting that since the first sub-word line driver and the second sub-word line driver correspond to the same holding transistor, when it is necessary to turn off the selected second sub-word line WL2, the level of the second sub-word line WL2 can be pulled low to the level of the first sub-word line WL1 by turning on both ends of the holding transistor, thereby turning off the second sub-word line WL2. In other words, a holding transistor can be connected to two different sub-word lines to control the turning off of both sub-word lines.

[0053] In the first region 11, the first sub-word line driver and the first sub-word line driver are connected to the same main word line. When an enable signal is input to the main word line, the gates of the pull-up transistors of the first sub-word line driver and the pull-up transistor 101 of the first sub-word line driver will simultaneously receive the enable signal from the main word line. Considering that only one sub-word line can be driven, the level of the first driving signal PXID received by the source of the pull-up transistor 101 of the first sub-word line driver can be set to be different from the level of the first driving signal PXID received by the source of the pull-up transistor 101 of the first sub-word line driver, preventing two sub-word lines from being turned on simultaneously.

[0054] In the second region 12, in some embodiments, the first sub-word line driver and the second sub-word line driver are respectively connected to different main word lines. For example, the first word line driver is connected to the first main word line, and the second word line driver is connected to the second main word line, so that the first word line driver and the second word line driver can respectively drive the connected sub-word line in response to the enable signal from the first main word line and the enable signal from the second main word line.

[0055] refer to Figure 4 , Figure 4 This is a timing diagram of each signal in a word line driving circuit provided in an embodiment of the present disclosure.

[0056] When the sub-word line WL is driven, in response to the enable signal provided by the main word line MWL, the level of the first drive signal PXID is first pulled high. At the same time as the level of the first drive signal PXID is pulled high, the level of the second drive signal PXIB is pulled low. Then the level of the enable signal is pulled low, thereby driving the sub-word line.

[0057] When the sub-word line is turned off, the level of the first drive signal PXID is first pulled low. After the level of the first drive signal PXID has been pulled low for a period of time, the level of the second drive signal PXIB is pulled high. That is, the level of the second drive signal PXIB is pulled high later than the level of the first drive signal PXID. When the second drive signal PXIB is high, the holding transistor is kept in the off state. In this way, the holding transistor can be kept off for a longer period of time, which can slow down the aging rate of the holding transistor.

[0058] In the word line driving circuit technical solution provided in the above-disclosed embodiments, the first and second ends of the holding transistor in the sub-word line driver 100 are respectively connected to two sub-word lines, that is, the two sub-word lines share the same holding transistor. When the sub-word line connected to one end of the holding transistor is driven, the holding transistor can keep the sub-word line connected to the other end of the holding transistor in an unselected state. Furthermore, the first transistor 103 controls the two sub-word lines corresponding to the same main word line, and the second transistor 104 controls the two sub-word lines corresponding to two different main word lines. This allows for flexible configuration of the connection between the holding transistor and different sub-word lines, thereby reducing the area occupied by the word line driving circuit and the layout area of ​​the word line driving circuit while maintaining the performance of the word line driving circuit.

[0059] Accordingly, this disclosure also provides a word line driver, which can be used to form the word line driving circuit provided in the previous embodiment. The word line driver provided in this disclosure will be described in detail below.

[0060] refer to Figure 5The word line driver includes: a PMOS region 20, comprising a plurality of first active regions 110 extending along a first direction X, each first active region 110 including a first channel region and a first source region 13 and a first drain region 14 located on opposite sides of the first channel region; an NMOS region, arranged along a second direction Y with the PMOS region 20, comprising a plurality of second active regions 120 extending along the first direction X, each second active region 120 including a second channel region 15 and a second source region 16 and a second drain region 17 located on opposite sides of the second channel region 15, the second active region 120 further including a third channel region and a third source region 18 and a third drain region located on opposite sides of the third channel region; and a first gate 130, each first gate 130 extending along the second direction Y and covering the plurality of first channel regions and the plurality of second channel regions 15, the first gate 130 being connected to the main word line driver. The transistor is electrically connected to a first gate 130, a first source region 13, and a first drain region 14, which together form a pull-up transistor. The first gate 130, a second source region 16, and a second drain region 17 form a pull-down transistor. The holding transistor includes a first transistor and a second transistor. Multiple second gates 140 are included, each covering a corresponding third channel region. The second gate 140, a third source region 18, and a third drain region form a holding transistor. The first drain region 14 of a pull-up transistor is electrically connected to the first drain region 14 of a pull-down transistor and is electrically connected to the corresponding sub-word line. The third drain region and third source region of the same first transistor are electrically connected to the second drain regions of two pull-down transistors sharing the same first gate. The third drain region and third source region of the same second transistor are electrically connected to the second drain regions of two pull-down transistors with different first gates.

[0061] Specifically, the third drain region of the same first transistor is electrically connected to the second drain region 17 of a pull-down transistor, the third source region 18 is electrically connected to the second drain region 17 of another pull-down transistor, and the two pull-down transistors electrically connected to the same first transistor share the first gate 130; the third drain region of the same second transistor is electrically connected to the second drain region 17 of a pull-down transistor, the third source region 18 is electrically connected to the second drain region 17 of another pull-down transistor, and the two pull-down transistors electrically connected to the same second transistor correspond to two first gates 130.

[0062] PMOS region 20 is used to form PMOS transistors, with pull-up transistors located within it, making the pull-up transistors PMOS transistors. NMOS region is used to form NMOS transistors, with pull-down transistors located within it, making the pull-down transistors NMOS transistors. First drain region 14 forms the drain of the pull-up transistor, and second drain region 17 forms the drain of the pull-down transistor. The first drain region 14 of the pull-up transistor and the second drain region 17 of the pull-down transistor are electrically connected, and both are also electrically connected to a sub-word line. Thus, the drive signal for driving the sub-word line can be transmitted from the source of the pull-up transistor to its drain and input to the sub-word line to control its drive; the drive signal for turning off the sub-word line can be transmitted from the source of the pull-down transistor to its drain and input to the sub-word line to control its turn-off. Furthermore, since pull-up transistors and pull-down transistors are different types of transistors, when a pull-up transistor is on, the pull-down transistor is off, allowing the pull-up transistor to be used to drive the sub-word line; conversely, when a pull-down transistor is on, the pull-up transistor is off, allowing the pull-down transistor to be used to drive the sub-word line. In other words, pull-up transistors and pull-down transistors can be used to drive and turn off the sub-word line, respectively.

[0063] It is understood that a pull-up transistor and a pull-down transistor can be used to form a sub-word driver 100 for driving and turning off a sub-word line. Since the pull-up transistor and the pull-down transistor are different types of transistors, with the pull-up transistor located in the PMOS region 20 and the pull-down transistor located in the NMOS region, in some embodiments, a metal layer may also be included for electrically connecting the first drain region 14 of the pull-up transistor and the second drain region 17 of the pull-down transistor.

[0064] refer to Figure 5In some embodiments, when there are two first gates 130, 16 first drain regions 14, and 16 second drain regions 17, the first drain regions 14 located in the PMOS region 20 are marked as (1), (2), (3), (4), (5), (6), (7), (8), (9), (10), (11), (12), (13), (14), (15), and (16); the second drain regions 17 located in the NMOS region are marked as (1), (2), (3), (4), (5), (6), (7), (8), (9), (10), (11), (12), (13), (14), (15), and (16). When using a metal layer to electrically connect the first drain region 14 and the second drain region 17, the metal layer can be configured to connect the first drain region 14 and the second drain region 17 with the same marking. For example, the metal layer can electrically connect the first drain region 14 marked (1) in the PMOS region 20 and the second drain region 17 marked (1) in the NMOS region. In this way, when multiple metal layers connect the first drain region 14 and the second drain region 17, the extension direction of the multiple metal layers is consistent, that is, they extend along the second direction Y, which helps to simplify the complexity of the layout. In other embodiments, the metal layer can also be configured to connect the first drain region 14 and the second drain region 17 with different markings. For example, the metal layer can electrically connect the first drain region 14 marked (1) in the PMOS region 20 and the second drain region 17 marked (2) in the NMOS region, as long as the metal layer connects one first drain region 14 and one second drain region 17 respectively.

[0065] Specifically, in some embodiments, the metal layer can be electrically connected to the first drain region 14 and the second drain region 17 via conductive plugs.

[0066] The first gate 130 can serve as a main word line and also as the gate of multiple pull-up transistors and pull-down transistors, thereby enabling multiple pull-up transistors and pull-down transistors to drive multiple sub-word lines in response to the enable signal provided by the first gate 130.

[0067] The third drain region is used as the drain of the holding transistor, and the third source region 18 is used as the source of the holding transistor. The third source region 18 and the third drain region of the same holding transistor are electrically connected to the second drain regions 17 of two different pull-down transistors, respectively. That is, the source and drain of the same holding transistor are connected to the drains of two different pull-down transistors. Since the drains of the two different pull-down transistors are also connected to two different sub-word lines, the source and drain of the same holding transistor are also electrically connected to two different sub-word lines. In this way, a holding transistor can maintain the voltage stability of two different sub-word lines. This is because, at any given time, the word line driver can only drive one sub-word line. For example, if the number of sub-word lines is two, when one of the sub-word lines connected to the holding transistor is selected, the other sub-word line is in an unselected state. When it is necessary to turn off the selected sub-word line, the source and drain of the holding transistor are turned on, so that the level of the selected sub-word line is pulled to the same level as the unselected sub-word line, thereby ensuring that the selected sub-word line can be completely turned off.

[0068] Compared to using a holding transistor to control one sub-word line, in this embodiment of the disclosure, the source and drain of a holding transistor are electrically connected to two sub-word lines respectively, thereby controlling two sub-word lines. This greatly reduces the number of holding transistors in the word line driver, and thus reduces the layout area of ​​the word line driver.

[0069] The holding transistor includes a first transistor 103 and a second transistor 104, wherein two pull-down transistors electrically connected to the first transistor 103 share a first gate 130. That is, the two pull-down transistors electrically connected to the first transistor 103 correspond to the same main word line, allowing the first transistor 103 to control two sub-word lines corresponding to the same main word line. The two pull-down transistors electrically connected to the same second transistor 104 each correspond to two different first gates 130, meaning the two pull-down transistors electrically connected to the second transistor 104 correspond to two different main word lines, allowing the second transistor 104 to control two different main word lines.

[0070] In some embodiments, the NMOS region includes a first NMOS region 21 and a second NMOS region 22, located on opposite sides of the PMOS region 20, respectively. A first transistor 103 is located in the first NMOS region 21; a second transistor 104 is located in the second NMOS region 22; a portion of the pull-down transistors are located in the first NMOS region 21, and the remaining portion are located in the second NMOS region 22. Since the two pull-down transistors electrically connected to the first transistor share a first gate 130, and the two pull-down transistors electrically connected to the same second transistor 104 correspond to two different first gates 130, the connection methods between the first transistor and the first gate 130 are different from those between the second transistor and the first gate 130. Therefore, placing the first transistor in the first NMOS region 21 and the second transistor in the second NMOS region 22 facilitates the separate formation of the first and second transistors, simplifying the complexity of the layout design. Furthermore, the pull-down transistor electrically connected to the first transistor is disposed in the first NMOS region 21, and the pull-down transistor electrically connected to the second transistor is disposed in the second NMOS region 22. In this way, when the pull-down transistor is electrically connected to the first transistor and the second transistor respectively, it is beneficial to shorten the trace length of the metal layer, thereby reducing the signal delay in the metal layer.

[0071] In some embodiments, each first gate 130 includes: at least two extensions spaced apart along a first direction X, extending along a second direction Y and covering a plurality of first channel regions and a plurality of second channel regions 15; and a connecting portion 131 connected to the adjacent extensions along the first direction X. The two extensions cover the plurality of first channel regions and second channel regions 15, such that one first gate 130 is electrically connected to the plurality of first channel regions and the plurality of second channel regions 15 for controlling the conduction of a plurality of pull-up transistors, thereby allowing the pull-up transistors to be used to drive and turn off sub-word lines, respectively. The connecting portion 131 connects the adjacent extensions along the first direction X, such that two spaced-apart extensions are electrically connected to form a main word line for controlling the conduction of the plurality of pull-up transistors and second pull-down transistors.

[0072] In some embodiments, the material of the first gate 130 may include at least one of polysilicon or metal.

[0073] In some embodiments, the connection portion 131 covers the area between adjacent first active regions 110, and also covers the area between the first active region 110 and the second active region 120. Compared to the connection portion 131 only covering the area between the first active region 110 and the second active region 120, the connection portion 131 covers the area between both the first active region 110 and the second active region 120, thereby increasing the volume of the connection portion 131 and reducing its resistance. This helps to reduce signal delay and improve the performance of the word line driver.

[0074] Specifically, in some embodiments, when there are multiple first active regions 110, the connecting portion 131 can cover the area between each adjacent first active region 110, or it can only cover the area between one of the adjacent first active regions 110.

[0075] In other embodiments, the connecting portion 131 may only cover the area between the first active region 110 and the second active region 120, thereby reducing process complexity and saving material for forming the connecting portion 131.

[0076] refer to Figure 5 In some embodiments, along the first direction X, the distance between adjacent extensions of the first NMOS region 21 is greater than the distance between adjacent extensions of a portion of the PMOS region 20, and the second gate 140 corresponding to the first transistor 103 is located between adjacent extensions. That is, the distance between adjacent extensions of a portion of the PMOS region 20 is smaller, reducing the area occupied by the second gate 140, thereby helping to reduce the layout area of ​​the word line driver. The extensions located on both sides of the second gate 140 can serve as the gates of two different pull-up transistors, while the third drain region and the third source region 18 of the first transistor are electrically connected to the second drain regions 17 of two different pull-down transistors, respectively. Therefore, when the second gate 140 is located between two extensions, it is beneficial to form an electrical connection between the first transistor 103 and the second drain regions 17 of the different pull-down transistors on both sides, and the extensions located on both sides of the second gate 140 belong to the first gate 130, allowing the first transistor to form an electrical connection with the two pull-down transistors corresponding to the same first gate 130, improving the rationality of the layout.

[0077] The extensions located on both sides of the second gate 140 belong to the same first gate 130. This means that the same main word line is connected to two sub-word line drivers 100, and the two sub-word line drivers 100 share the same holding transistor; that is, one main word line corresponds to only one holding transistor. For details, please refer to the corresponding circuit diagram. Figure 3 as well as Figure 4In the first region 11, a main word line is connected to at least two sub-word line drivers 100, and a main word line corresponds to at least two sub-word lines. The two sub-word lines connected to the first and second terminals of the first transistor 103 in the first region 11 each correspond to the same main word line. When the number of sub-word line drivers 100 in the first region 11 is 8, one main word line can be connected to 4 sub-word line drivers 100, one main word line corresponds to 4 sub-word lines, and two sub-word lines share one sub-word line driver 100, meaning one main word line corresponds to only 2 holding transistors. When there are two main word lines, each main word line corresponds to a different first transistor, which can drive a total of 8 sub-word lines in the first region 11, while only 8 first transistors are needed, thus greatly reducing the layout area of ​​the word line drivers.

[0078] Specifically, when the second gate 140 is located between two adjacent extensions, the principle of the word line driver driving the sub-word line and turning off the sub-word line can be as follows: taking the first gate 130 as the gate of two pull-up transistors and the gate of two pull-down transistors as an example, wherein the two pull-up transistors are respectively referred to as the first pull-up transistor and the second pull-up transistor, and the pull-down transistors are respectively referred to as the first pull-down transistor and the second pull-down transistor, wherein the first pull-down transistor is electrically connected to the source of the holding transistor, and the second pull-down transistor is electrically connected to the drain of the holding transistor.

[0079] The principle of driving the sub-word line connected to the first pull-up transistor is as follows: an enable signal is input to the first gate 130, the gates of the first pull-up transistor and the second pull-up transistor are turned on in response to the enable signal, the first transistor is turned off in response to the low level of the second drive signal PXIB, the source of the first pull-up transistor is input to the high level of the first drive signal PXID, and the source of the second pull-up transistor is input to the low level of the first drive signal PXID, thereby making the sub-word line connected to the first pull-up transistor have a high level and be driven, and the sub-word line connected to the second pull-up transistor have a low level and be turned off.

[0080] The principle for shutting down the sub-word line connected to the first pull-up transistor is as follows: An enable signal is input to the first gate 130, and the gates of the first pull-down transistor and the second pull-down transistor are turned on in response to the enable signal. The first transistor is turned on in response to the high-level second drive signal PXIB. A low-level third drive signal VKK is input to the source of the first pull-down transistor, thereby making the sub-word line connected to the drain of the first pull-down transistor have a low level. Since the source and drain of the first transistor are connected to different pull-down transistors, the level of the sub-word line connected to the first pull-down transistor is pulled down to the level of the sub-word line connected to the second pull-down transistor, thereby turning off the sub-word line connected to the first pull-down transistor.

[0081] The process of driving the sub-word line connected to the second pull-down transistor and turning off the sub-word line connected to the second pull-down transistor is the same as the process described above, and will not be repeated here.

[0082] In some embodiments, the third drain region of the first transistor is shared with the second drain region 17 of a pull-down transistor located in the first NMOS region 21; the third source region 18 of the first transistor is shared with the second drain region of another pull-down transistor located in the first NMOS region 21.

[0083] In the first NMOS region 21, the second gate 140 covers the surface of the third channel region, so that the formed second gate 140 is electrically connected to the third channel region. The second gate 140 serves as the gate of a holding transistor. The third drain region and the third source region 18 on both sides of the third channel region serve as the drain and source of the first transistor, respectively. The two extended portions located on both sides of the second gate 140 serve as the gates of two different pull-down transistors to provide a third drive signal VKK. The third drain region can serve as the drain of one of the pull-down transistors, and the third source region 18 can serve as the drain of the other pull-down transistor. The second source region 16 of the two pull-down transistors is located on the side of the extended portion away from the third gate and serves as the source of the pull-down transistor. In some embodiments, the second source region 16 can also serve as the source of the pull-down transistor corresponding to another first gate 130. In other words, the second drain region 17 of the same pull-down transistor is shared with the third drain region of the holding transistor, and the second source region 16 is shared with the second source region 16 of the pull-down transistor corresponding to the other first gate 130. In this way, the occupied area of ​​the second active region 120 can be greatly reduced, thereby improving the integration density of the word line driver.

[0084] In some embodiments, along the first direction X, the distance between adjacent extensions of the second NMOS region 22 is smaller than the distance between adjacent extensions of a portion of the PMOS region 20, and the second gate 140 corresponding to the second transistor 104 is located outside the region enclosed by the two extensions. Thus, when multiple spaced first gates 130 are present, the distance between the extensions of different first gates 130 in the second NMOS region 22 is larger, providing more space for forming the second gate 140.

[0085] In the second NMOS region 22, the extensions on both sides of the second gate 140 are used as gates for two different pull-up transistors, and the extensions on both sides of the second gate 140 belong to different first gates 130, so that the formed second transistors correspond to different main word lines.

[0086] The corresponding circuit diagram can be referenced. Figure 3In the second region 12, two sub-word line drivers 100 connected to different main word lines share the same second transistor 104. When four different sub-word line drivers 100 are connected to the same main word line, one main word line corresponds to four second transistors 104. Since two main word lines share the same second transistor 104, they share four second transistors 104. That is, two main word lines can drive a total of eight sub-word lines in the second region 12, while only four transistors are needed to maintain the connection. This reduces the number of transistors in the sub-word line drivers 100, thus reducing the layout area of ​​the word line driving circuit. When a sub-word line driver 100 connected to two different main word lines drives its connected sub-word line, it can drive the connected sub-word line in response to the enable signal from each of the different main word lines.

[0087] There are a total of 16 sub-word line drivers 100 in Zone 11 and Zone 12. Each main word line corresponds to 8 sub-word line drivers 100, and each sub-word line driver 100 corresponds to one sub-word line. The total number of holding transistors in Zone 11 and Zone 12 is 8, meaning the number of holding transistors is only half the number of sub-word line drivers 100. It can be understood that regardless of the specific number of holding transistors in Zone 11 and Zone 12, it is sufficient that one holding transistor corresponds to two sub-word lines, such that the number of holding transistors is only half the number of sub-word line drivers 100.

[0088] In some embodiments, the third drain region of the second transistor is shared with the second drain region of a pull-down transistor located in the second NMOS region 22; the third source region of the second transistor is shared with the second drain region of another pull-down transistor located in the second NMOS region 22.

[0089] The two extensions located on either side of the second gate 140 belong to different first gates 130 and are used to form different pull-down transistors. That is, the second transistor is electrically connected to the pull-down transistors corresponding to the two different first gates 130. The third drain region located on one side of the third channel region can be the drain of one pull-down transistor corresponding to a first gate 130, and the third source region located on the other side of the third channel region can be the drain of another pull-down transistor corresponding to a first gate 130. The second source regions of the two pull-down transistors corresponding to the two different first gates 130 are located on the side of the extension away from the second gate 140. In some embodiments, two adjacent pull-down transistors corresponding to the same first gate 130 can also share the second source region, thereby reducing the occupied area of ​​the second active region 120 and thus reducing the layout area of ​​the word line driver.

[0090] In some embodiments, each first gate 130 covers 4×N first channel regions and 4×N second channel regions 15. Each first gate 130 forms a pull-up transistor and a pull-down transistor, which are electrically connected to 2×N holding transistors; where N is a positive integer greater than or equal to 1. That is, the number of first channel regions and the number of second channel regions 15 are kept equal, such that the number of pull-up transistors is the same as the number of pull-down transistors. Each pull-up transistor and pull-down transistor constitutes a sub-word line driver. The number of holding transistors is half the number of pull-up transistors or pull-down transistors, allowing two sub-word line drivers to share a single holding transistor. This helps reduce the number of holding transistors in the word line driver, thereby reducing the layout area of ​​the word line driver.

[0091] Specifically, refer to Figure 5 as well as Figure 3 In some embodiments, N is 2, and there are 2 extensions, wherein one extension covers 4 first channel regions, and one extension also covers 4 second channel regions 15. Based on this, there are 8 pull-up transistors 101 and 8 pull-down transistors 102, forming 8 sub-word line drivers 100. Each sub-word line driver 100 corresponds to one sub-word line. There are 4 holding transistors, that is, one holding transistor is used to control 2 sub-word lines, thereby making one main word line formed by the first gate 130 used to control 8 sub-word lines. When there are 2 first gates 130, two main word lines are used to control 8 sub-word lines.

[0092] In other embodiments, reference is made to Figure 6 N can be 4, and there are 4 extensions, where one extension covers 4 first channel regions and one extension also covers 4 second channel regions 15. Based on this, there are 16 pull-up transistors and 16 pull-down transistors, forming 16 sub-word line drivers. Each sub-word line driver corresponds to one sub-word line. There are 8 holding transistors, that is, one holding transistor is used to control 2 sub-word lines, so that one main word line formed by the first gate 130 is used to control 16 sub-word lines. When the number of first gates 130 is 2, two main word lines are used to control 32 sub-word lines.

[0093] In some other embodiments, N can be 3, there are 3 extensions, 12 pull-up transistors, and 12 pull-down transistors, forming 12 sub-word line drivers. Each sub-word line driver corresponds to one sub-word line, and there are 6 holding transistors, that is, one holding transistor is used to control 2 sub-word lines, so that one main word line formed by the first gate 130 is used to control 12 sub-word lines. When the number of first gates 130 is 2, two main word lines are used to control 24 sub-word lines.

[0094] In some embodiments, the PMOS region 20 includes: a first PMOS region 23 and a second PMOS region 24 arranged along a second direction Y, the second PMOS region 24 being located between the first PMOS region 23 and the first NMOS region 21; two extensions of the same first gate 130 cover the same first active region 110 of the first PMOS region 23, and the two extensions also respectively cover two first active regions 110 of the second PMOS region 24 arranged along a first direction X; wherein, along the first direction X, the distance between adjacent extensions of the first PMOS region 23 is smaller than the distance between adjacent extensions of the second PMOS region 24.

[0095] Two extensions of the same first gate 130 cover the same first active region 110 of the first PMOS region 23, such that the two extensions of the formed first gate 130 are electrically connected to the same first active region 110 of the first PMOS region 23, thereby forming two pull-up transistors. The two extensions also cover two first active regions 110 of the second PMOS region 24 arranged along the first direction X, such that the two extensions are electrically connected to the two first active regions 110 respectively, forming two pull-up transistors. Because the two extensions of the first gate 130 are located on the same active region, the distance between adjacent extensions of the first PMOS region 23 is small, thereby reducing the area occupied by the first gate 130 and thus reducing the layout area.

[0096] In some embodiments, the pull-up transistors corresponding to the first PMOS region 23 share the first source region 13, and the shared first source region 13 receives the first drive signal PXID.

[0097] In the first active region 110 of the first PMOS region 23, each extension covers a first channel region. A first source region 13 is located between two first extensions and is used to input a first drive signal PXID. A first drain region 14 is located on the side of the channel region away from the first extension and is used to form a pull-up transistor. The number of first source regions 13 located between two first extensions can be one, and the number of first drain regions 14 can be two, meaning that two pull-up transistors share the same first source region 13. This improves the integration density of the formed word line driver and further reduces the layout area.

[0098] In the first active region 110 of the second PMOS region 24, each extension covers a first channel region, and the first source region 13 and the first drain region 14 are located on both sides of the first channel region. The first drain region 14 can be located between two extensions, and the first source region 13 is located on the side of the extension away from the first channel region. Thus, in the second PMOS region 24, the two pull-up transistors do not share the first source region 13, preventing excessive loss of the first drive signal PXID input to the source of the pull-up transistor due to an excessive number of common-source pull-up transistors, which could lead to the inability to drive the corresponding sub-word line. In some embodiments, the first source region 13 in the second PMOS region 24 can serve as the source of the pull-up transistor corresponding to another first gate 130. Therefore, when there are multiple first gates 130, the overall size of the active region can be smaller, resulting in a smaller layout area.

[0099] refer to Figure 6 In some embodiments, a connection portion 131 is provided between two extensions of the same first gate 130. The connection portion is used to electrically connect the two extensions, and the connection portion is located between the first PMOS region 23 and the second PMOS region 24 and between the first NMOS region 21 and the first PMOS region 23. The length of the connection portion is equal to the distance between the two extensions.

[0100] refer to Figure 7 In other embodiments, the length of the connection between the first NMOS region 21 and the first PMOS region 23 can be greater than the length between two adjacent extensions. This makes the connection longer, thereby increasing the volume of the first gate 130 and reducing the resistance of the first gate 130, thereby improving the transmission rate of the electrical signal.

[0101] Furthermore, the first gate 130 also includes an extension portion 132, which extends in a first direction X and is connected to the extension portion. (Reference) Figure 7 The number of extension portions 132 can be two. The two extension portions 132 are located between two adjacent first active regions 110 in the second PMOS region 24, and also between two adjacent extension portions. The two extension portions 132 are arranged opposite to each other and are not connected. The provision of extension portions 132 can further increase the volume of the first gate 130, which is beneficial to further reduce the resistance of the first gate 130. When the enable signal is transmitted through the first gate 130, the delay can be reduced.

[0102] refer to Figure 8In some other embodiments, an extension portion 132 may be provided between two adjacent first active regions 110 in the first PMOS region 23, and between the second PMOS region 24 and the second NMOS region 22. This allows for full utilization of space, resulting in a larger volume for the first gate 130 and a reduced resistance. Considering that the distance between two adjacent extension portions 132 in the first PMOS region 23 is smaller than the distance between two adjacent extension portions 132 in the second PMOS region 24, the two extension portions 132 in the first PMOS region 23 may be positioned outside the region enclosed by the two adjacent extension portions, thus separating the two extension portions 132.

[0103] Additionally, refer to Figure 6 , Figure 7 as well as Figure 8 The regions between the first PMOS region 23 and the first NMOS region 21, the region between the first PMOS region 23 and the second PMOS region 24, the region between adjacent first active regions 110 in the first PMOS region 23, and the region between adjacent first active regions 110 in the second PMOS region 24 can be used to form isolation structures. The presence of the isolation structure may lead to a punch-through effect (Hot-Electron-Induced Punchthrough, HEIP), resulting in a punch-through current between the two active regions. Therefore, referring to... Figure 6 A connection portion is provided in the region between the first PMOS region 23 and the first NMOS region 21, and a connection portion 131 is provided between the first PMOS region 23 and the second PMOS region 24. This not only allows the two extensions to be electrically connected, but also prevents punch-through effects caused by the isolation structure. Similarly, refer to... Figure 7 An extension portion 132 is provided between adjacent first active regions 110 in the second PMOS region 24 to prevent punch-through effect between adjacent PMOS transistors formed in the second PMOS region 24. (Reference) Figure 8 Furthermore, an extension portion 132 is provided between adjacent first active regions 110 in the first PMOS region 23, and an extension portion 132 is provided between the second NMOS region 22 in the second PMOS region 24, which can further prevent punch-through effect between adjacent PMOS transistors formed in the first PMOS region 23.

[0104] It is understandable that when two active regions with different doping types are adjacent, a punch-through effect will occur. Specifically, when the circuit formed by the two active regions with different doping types is an analog circuit, their potentials may be different. When the potential difference between the two active regions is large enough, the depletion region of the active region will expand outward, thereby forming a punch-through current between the two active regions and generating electrical interference. Based on this, in some embodiments, the plurality of first active regions 110 include: at least two first active regions 110 disposed near the NMOS region, the two first active regions 110 being spaced apart along a first direction X and having a spacer region, wherein the second gate 140 is disposed opposite to the spacer region along a second direction Y. That is, the extension direction of the second gate 140 is the same as the extension direction of the spacer region, and the second gate 140 is located on the extension line of the spacer region. The second gate 140 is used to cover the third channel region, that is, the third channel region is opposite to the spacer region. The spacer region is used to form an isolation structure between the two spaced first active regions 110. Therefore, by setting the second gate 140 to face the isolation structure, the third channel region of the second source region 16 is not adjacent to the first channel region of the first source region 13, which is beneficial to improving the punch-through effect.

[0105] In the word line driver provided in the above embodiments, the third source region 18 and the third drain region of the same holding transistor are electrically connected to the second drain regions 17 of two different pull-down transistors, respectively. That is, the source and drain of the same holding transistor are connected to the drains of two different pull-down transistors, respectively. Furthermore, a first transistor 103 controls two sub-word lines corresponding to the same main word line, and a second transistor 104 controls two sub-word lines corresponding to two different main word lines. Compared to using one holding transistor to control one sub-word line, the number of holding transistors in the word line driver can be greatly reduced, thereby reducing the layout area of ​​the word line driver.

[0106] Accordingly, embodiments of this disclosure also provide a storage device, including: a storage cell array including a plurality of storage cells connected to a plurality of sub-word lines and a plurality of bit lines; a word line driving circuit provided in any of the above embodiments; or a word line driver provided in any of the above embodiments. In some embodiments, the storage cells may be DRAM storage cells.

[0107] In some embodiments, the system further includes a signal generation circuit configured to output a first driving signal PXID and a second driving signal PXIB, wherein the rising edge of the second driving signal PXIB is delayed by a preset duration compared to the falling edge of the first driving signal PXID. For details, please refer to... Figure 4When the sub-word line is turned off, the level of the first drive signal PXID is first pulled low. After the level of the first drive signal PXID has been pulled low for a period of time, the level of the second drive signal PXIB is pulled high. That is, the level of the second drive signal PXIB is pulled high later than the level of the first drive signal PXID. When the second drive signal PXIB is high, the holding transistor is kept in the off state. In this way, the holding transistor can be kept off for a longer period of time, which can slow down the aging rate of the holding transistor.

[0108] refer to Figure 9 In some embodiments, the signal generation circuit includes: a decoder 150 configured to output a first drive signal PXID; a PMOS switch 151, whose gate receives the first drive signal PXID, one end receives the original drive signal, and the other end is connected to an inverter 152, which outputs a second drive signal PXIB, wherein the change edge of the original drive signal coincides with the change edge of the first drive signal PXID. That is, the level of the original drive signal is the same as that of the first drive signal PXID, and the source of the PMOS switch 151 receives the original drive signal, while its drain is connected to the inverter 152. Thus, when the PMOS switch 151 is turned on, the original drive signal is transmitted from the source of the PMOS switch 151 to its drain, and after passing through the inverter 152, the output second drive signal PXIB is opposite in level to the original drive signal, i.e., opposite in level to the first drive signal PXID.

[0109] Specifically, in some embodiments, taking the shutdown of the sub-word line when the first drive signal PXID is low as an example, the principle of the signal generation circuit generating the first drive signal PXID and the second drive signal PXIB when it is necessary to shut down the sub-word line is as follows: The decoder 150 outputs a low-level first drive signal PXID, and the gate of the PMOS switch 151 turns on in response to the low-level first drive signal PXID. The source of PMOS switch 151 receives a low-level initial drive signal. This initial drive signal is transmitted from the source to the drain of PMOS switch 151, and then through inverter 152 to output a high-level second drive signal PXIB. Holding transistor 103 is turned on based on the high-level second drive signal PXIB, thereby turning off the sub-word line. Since the initial drive signal needs to be inverted by inverter 152 to form the second drive signal PXIB before being transmitted to the gate of holding transistor 103, inverter 152 acts as a buffer. Therefore, the rising edge of the second drive signal PXIB has a preset time delay compared to the falling edge of the first drive signal PXID.

[0110] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A word line driving circuit, characterized in that, include: At least two sub-word line drivers, each of the sub-word line drivers being connected to a main word line and a sub-word line, the main word line being used to provide an enable signal; The sub-word line driver includes a holding transistor, the first and second ends of which are respectively connected to different sub-word lines, and the gate of the holding transistor receives a second driving signal; The sub-word line driver is configured to provide the first drive signal to the selected sub-word line in response to the first drive signal and the enable signal; and to turn on the first and second terminals of the holding transistor in response to the first drive signal, the enable signal, and the second drive signal. The holding transistor includes a first transistor or a second transistor. The two sub-word lines connected to the first terminal and the second terminal of the first transistor correspond to the same main word line, and the two sub-word lines connected to the first terminal and the second terminal of the second transistor correspond to different main word lines. Each of the main word lines is connected to 4×N sub-word line drivers, and each sub-word line driver connected to each of the main word lines is electrically connected to 2×N holding transistors; where N is a positive integer greater than or equal to 1.

2. The word line driving circuit as described in claim 1, characterized in that, The selected sub-word line is the sub-word line connected to the first or second terminal of the holding transistor.

3. The word line driving circuit as described in claim 1, characterized in that, The holding transistor includes an NMOS transistor.

4. The word line driving circuit as described in claim 1, characterized in that, The sub-word line driver includes: A pull-up transistor has its gate connected to the main word line, its source receiving the first drive signal, and its drain connected to the sub-word line and either the first or second terminal of the holding transistor. The pull-down transistor has its gate connected to the main word line, its drain connected to the drain of the pull-up transistor, and its source receiving the third drive signal.

5. The word line driving circuit as described in claim 4, characterized in that, The pull-up transistor includes a PMOS transistor; the pull-down transistor includes an NMOS transistor.

6. A word line driver, characterized in that, include: The PMOS region includes a plurality of first active regions extending along a first direction, wherein the first active region includes a first channel region and a first source region and a first drain region located on opposite sides of the first channel region. The NMOS region, arranged along the second direction with the PMOS region, includes a plurality of second active regions extending along the first direction. The second active region includes a second channel region and a second source region and a second drain region located on opposite sides of the second channel region. The second active region also includes a third channel region and a third source region and a third drain region located on opposite sides of the third channel region. A first gate, each of the first gates extending along the second direction and covering a plurality of first channel regions and a plurality of second channel regions, the first gate being electrically connected to the main word line, the first gate, the first source region and the first drain region constituting a pull-up transistor, and the first gate, the second source region and the second drain region constituting a pull-down transistor. A plurality of second gates, each second gate covering a corresponding third channel region, the second gate, the third source region and the third drain region constituting a holding transistor, the holding transistor including a first transistor or a second transistor; The first drain region of one of the pull-up transistors is electrically connected to the first drain region of one of the pull-down transistors, and is also electrically connected to the corresponding sub-word line. The third drain region and the third source region of the same first transistor are respectively electrically connected to the second drain regions of two pull-down transistors that share the same first gate; the third drain region and the third source region of the same second transistor are respectively electrically connected to the second drain regions of two pull-down transistors that correspond to different first gates. Each of the first gates covers 4×N first channel regions and 4×N second channel regions, and the pull-up transistors and pull-down transistors formed by each of the first gates are electrically connected to 2×N holding transistors; where N is a positive integer greater than or equal to 1.

7. The word line driver as claimed in claim 6, characterized in that, The NMOS region includes: The first NMOS region and the second NMOS region are located on opposite sides of the PMOS region, respectively. Wherein, the first transistor is located in the first NMOS region; the second transistor is located in the second NMOS region; a portion of the pull-down transistors are located in the first NMOS region, and the remaining portion of the pull-down transistors are located in the second NMOS region.

8. The word line driver as claimed in claim 7, characterized in that, Each of the first gates includes: At least two extensions spaced apart along the first direction extend along the second direction and cover a plurality of first channel regions and a plurality of second channel regions; A connecting portion, which connects to the extensions arranged adjacent to each other along the first direction.

9. The word line driver as claimed in claim 8, characterized in that, The connecting portion covers the area between adjacent first active regions, and also covers the area between the first active region and the second active region.

10. The word line driver as claimed in claim 8, characterized in that, Along the first direction, the distance between adjacent extensions of the first NMOS region is greater than the distance between adjacent extensions of a portion of the PMOS region, and the second gate corresponding to the first transistor is located between adjacent extensions.

11. The word line driver as claimed in claim 10, characterized in that, The third drain region of the first transistor is shared with the second drain region of a pull-down transistor located in the first NMOS region; the third source region of the first transistor is shared with the second drain region of another pull-down transistor located in the first NMOS region.

12. The word line driver as claimed in claim 8, characterized in that, Along the first direction, the distance between adjacent extensions of the second NMOS region is less than the distance between adjacent extensions of a portion of the PMOS region, and the second gate corresponding to the second transistor is located outside the region enclosed by the two extensions.

13. The word line driver as claimed in claim 12, characterized in that, The third drain region of the second transistor is shared with the second drain region of a pull-down transistor located in the second NMOS region; the third source region of the second transistor is shared with the second drain region of another pull-down transistor located in the second NMOS region.

14. The word line driver as claimed in claim 10 or 12, characterized in that, The PMOS region includes: A first PMOS region and a second PMOS region are arranged along the second direction, wherein the second PMOS region is located between the first PMOS region and the first NMOS region; The two extensions of the same first gate cover the same first active region of the first PMOS region, and the two extensions also respectively cover the two first active regions of the second PMOS region arranged along the first direction; Wherein, along the first direction, the distance between adjacent extensions of the first PMOS region is less than the distance between adjacent extensions of the second PMOS region.

15. The word line driver as claimed in claim 14, characterized in that, The pull-up transistors corresponding to the first PMOS region share the first source region, and the shared first source region receives the first drive signal.

16. The word line driver as claimed in claim 6, characterized in that, The plurality of first active regions include: at least two first active regions disposed near the NMOS region, the two first active regions being spaced apart along the first direction and having a spacer region, wherein the second gate and the spacer region are disposed opposite each other along the second direction.

17. A storage device, characterized in that, include: A memory cell array comprising multiple memory cells connected to multiple subword lines and multiple bit lines. ； The word line driving circuit as described in any one of claims 1-5, or the word line driver as described in any one of claims 6-16.

18. The storage device as claimed in claim 17, characterized in that, Also includes: The signal generation circuit is configured to output a first driving signal and a second driving signal, wherein the rising edge of the second driving signal has a preset time delay compared to the falling edge of the first driving signal.

19. The storage device as claimed in claim 18, characterized in that, The signal generation circuit includes: The decoder is configured to output the first drive signal; The PMOS switch receives the first drive signal at its gate, receives the original drive signal at one end, and is connected to an inverter at the other end. The inverter outputs the second drive signal, wherein the change edge of the original drive signal is consistent with the change edge of the first drive signal.

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