Non-volatile memory device and method of controlling the same

Abstract

A control method of a non-volatile memory device includes a set of memory cells, a cycle transistor, a reference transistor, and a control circuit coupled to the set of memory cells, the cycle transistor, and the reference transistor. The control method includes, during a program operation or an erase operation of the set of memory cells, the control circuit reading the cycle transistor, and after reading that the cycle transistor is in an erase state (or a program state), the control circuit sequentially setting the reference transistor from a reference state to the erase state (or the program state), and reverting the reference transistor from the erase state (or the program state) to the reference state, the reference state being between the erase state and the program state.

Description

Technical Field

[0001] This invention relates to memory devices, and more particularly to non-volatile memory devices and their control methods. Background Technology

[0002] Non-volatile memories (NVMe) are widely used in personal computers, telecommunications, consumer electronics, and various other fields. Multi-time programmable (MTP) memory, electrically erasable programmable read-only memory (EEPROM), and flash memory are among the most widely used NVMs. Due to defects in the gate oxide layer of NVMs, electrons can become trapped in the gate oxide layer after multiple program-erase cycles, a phenomenon known as the cycling trapped effect. If electrons escape from the gate oxide layer, the data current generated by the NVM will drift. Using a fixed reference current to read the NVM at this point will result in data read errors. Related technologies use trimming techniques to manually adjust the reference current; however, this method is time-consuming and inaccurate. Summary of the Invention

[0003] This invention provides a control method for a non-volatile memory device. The non-volatile memory device includes a set of memory cells, a periodic transistor, a reference transistor, and a control circuit. The control circuit is coupled to the set of memory cells, the periodic transistor, and the reference transistor. The control method includes, during a programming or erasing operation of the set of memory cells, the control circuit reads the periodic transistor; and after reading that the periodic transistor is in an erasing state, the control circuit sequentially sets the reference transistor from a reference state to an erasing state, and restores the reference transistor from the erasing state to the reference state, wherein the reference state is between the erasing state and the programming state.

[0004] This invention also provides a control method for a non-volatile memory device. The non-volatile memory device includes a set of memory cells, a periodic transistor, a reference transistor, and a control circuit. The control circuit is coupled to the set of memory cells, the periodic transistor, and the reference transistor. The control method includes, during a programming or erasing operation of the set of memory cells, the control circuit reads the periodic transistor; and after reading that the periodic transistor is in a programming state, the control circuit sequentially sets the reference transistor from a reference state to a programming state, and then restores the reference transistor from the programming state to the reference state, wherein the reference state is between an erasing state and a programming state.

[0005] This invention also provides a non-volatile memory device, comprising a set of memory cells, a periodic transistor, a reference transistor, a comparator circuit, and a control circuit. The comparator circuit includes a comparator coupled to the periodic transistor and the reference transistor, used to compare the periodic current generated by the periodic transistor and the reference current generated by the reference transistor during programming or erasing operations of the memory cells to generate a comparison result. The control circuit is coupled to the memory cells, the periodic transistor, the reference transistor, and the comparator, used to control the operation of the periodic transistor and the reference transistor based on the comparison result. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a non-volatile memory cell in an embodiment of the present invention. Figure 2 This is a schematic diagram of the cyclic trap effect. Figure 3 This is a distribution map of the cyclic trap effect. Figure 4A This is a schematic diagram of a non-volatile memory device according to an embodiment of the present invention. Figure 4B yes Figure 4A A circuit diagram of a portion of the circuitry of a non-volatile memory device. Figure 5 show Figure 4A A schematic diagram of a control method for a non-volatile memory device. Figure 6 yes Figure 4A A flowchart of a control method for a non-volatile memory device. Figure 7 yes Figure 4A Timing diagram of programming / erasing operations for non-volatile memory devices. Figure 8 yes Figure 4A Timing diagram of read operations for non-volatile memory devices in the diagram.

[0007] Explanation of icon numbers: 1. M0(0,0) to M0(P,Q), M1(0,0) to M1(P,Q): Non-volatile memory cells 10: Base 12: Jiji 13: Passage Area 14: Source 16: Gate oxide layer 18: Floating gate 20a, 20b, 22a, 22b, 30, 31, 50 to 52: Distribution 4: Non-volatile memory devices 40: Control Circuit 401, 402: Comparators 41 to 4R: Group 411: First group of sub-memory units 412: Reference Current Update Circuit 413: Second group of sub-memory units 414, 415: Input / output circuits 416, 417: Comparator circuits 4140, 4142, 4150, 4152, 4162, 4172: Multiplexers 4144, 4154, 4164, 4174: Comparators 53: Erasure cycle 54: Programming Cycle 55 to 58: Cycle 600: Control Method S602 to S610: Steps ADR: Address BL0(0) to BL0(Q), BL1(0) to BL1(Q), BLc, BLr: bit lines C: Capacitor CLKwt, CLKrd: Clock signals cmpd0, cmpd1, cmpc, cmpr: Comparison results E: Erasure status Ev,Rve: Lower limit current ic: periodic current i00 to i0q, i10 to i1q, id0, id1: Data current ir: Reference current ir0,ir1,irc,irr: Selected reference current Icell: Current N: Quantity M0, M1: Read margin MA: Memory Array P: Programming Status Pv,Rvp: Upper limit current R: Read status Rf: Fixed reference current Rv: Reference state S0, Sd0, S1, Sd1, Sc, Sr: Selection signals SL: Source Line t1 to t10: Time Tc(0) to Tc(P), Tc: periodic transistor Tr(0) to Tr(P), Tr: reference transistor Vg: Gate voltage signal Vd: Drain voltage signal Vs: Source voltage signal WL(0) to WL(P): Character lines Detailed Implementation

[0008] Figure 1 This is a schematic diagram of a non-volatile memory (NVM) cell 1 according to an embodiment of the present invention. The NVM cell 1 can be a single-level, multi-time programmable (MTP) memory cell, and can be represented by a transistor, such as an N-type transistor. The NVM cell 1 includes a substrate 10, a source 14, a channel region 13, a drain 12, a gate oxide layer 16, a floating gate 18, and a capacitor C. The substrate 10 can be formed of a semiconductor, and the source 14 and drain 12 can be formed of doped regions, such as N-type doped regions. The channel region 13 can be formed between the source 14 and drain 12 and below the floating gate 18. The gate oxide layer 16 can contain silicon dioxide or other dielectric materials, and the floating gate 18 can contain doped polysilicon.

[0009] The drain 12 can receive the drain voltage signal Vd, the source 14 can receive the source voltage signal Vs, the floating gate 18 can receive the gate voltage signal Vg via capacitor C, and the substrate 10 can be grounded. The control circuit can control the drain voltage signal Vd, the source voltage signal Vs, and the gate voltage signal Vg to perform programming, erasing, and reading operations on the NVM unit 1.

[0010] During programming, the control circuit can set the gate voltage signal Vg as a continuous pulse wave, with each pulse wave having the same pulse value, for example, 9V, and connect the drain voltage signal Vd to a high voltage, for example, 9V, and maintain the source voltage signal Vs at ground voltage, for example, 0V, thereby introducing negative charges into the floating gate 18. When the negative charges stored in the floating gate 18 reach a predetermined number, for example, 9 negative charges, the NVM unit 1 is set to the programming state (or logic 0).

[0011] During erasure, the control circuit can set the drain voltage signal Vd to a high voltage level, such as 9V, maintain the source voltage signal Vs at ground voltage, and set the gate voltage signal Vg to a low voltage level, such as 0V, so as to remove the negative charge from the floating gate 18. The floating gate 18 may not store negative charge, and the NVM unit 1 is set to the erase state (or logic 1).

[0012] During reading, the control circuit can set the gate voltage signal Vg to the reading voltage level, such as 2V, set the drain voltage signal Vd to a low voltage level, and maintain the source voltage signal Vs at ground voltage. This allows the control circuit to determine the data stored in the NVM cell 1 based on the magnitude of the data current at drain 12, thereby completing the data reading operation. For example, if the NVM cell 1 is in the programming state, the negative charge in the floating gate 18 makes it difficult to form the channel region 13. Therefore, no or only a small amount of data current flows from drain 12, and the control circuit can determine that the data in the NVM cell 1 is in the programming state based on the data current at drain 12. If the NVM cell 1 is in the erasure state, since there is no negative charge in the floating gate 18, the channel region 13 can be formed, resulting in a larger current flowing from drain 12. The control circuit can determine that the data in the NVM cell 1 is in the erasure state based on the data current at drain 12.

[0013] The control circuit can repeatedly program and erase NVM cell 1. One programming and one erasing operation can be called a program-erase (PE) cycle. As the number of PE cycles increases, some negative charges may become trapped in the gate oxide layer 16. Therefore, the floating gate 18 only needs to store a smaller amount of negative charge than a predetermined amount to put NVM cell 1 into the programming state. For example, in Figure 1 Two negative charges are trapped in the gate oxide layer 16, so the floating gate 18 only needs to store 7 negative charges to achieve the programming state (9 negative charges). However, the negative charge retention capability of the gate oxide layer 16 is poor. After a period of time, the negative charges will escape from the gate oxide layer 16, causing an increase in the data current in both the programming and erasing states. This phenomenon is called the cycling trapped effect. The cycling trapped effect may cause the control circuit to misinterpret the data in NVM cell 1.

[0014] An NVM device may contain a plurality of NVM cells 1, arranged in an array. Since the characteristics of individual NVM cells 1 may vary slightly due to process, voltage, and temperature (PVT), a plurality of NVM cells 1 can be distributed in a group, such as... Figure 2 As shown. Figure 2This is a schematic diagram of the cycle trap effect, where the horizontal axis represents the current Icell and the vertical axis represents the quantity N. Distribution 20a represents the current distribution of a plurality of NVM cells 1 in the programming state P without the cycle trap effect, distribution 22a represents the current distribution of a plurality of NVM cells 1 in the erasure state E without the cycle trap effect, distribution 20b represents the current distribution of a plurality of NVM cells 1 in the programming state P with the cycle trap effect, and distribution 22b represents the current distribution of a plurality of NVM cells 1 in the erasure state E with the cycle trap effect.

[0015] Related technologies employ a fixed reference current Rf to read data, for example, generated by a bandgap reference circuit. The fixed reference current Rf is approximately located between the maximum data current of distribution 20a and the minimum data current of distribution 22a, thereby optimizing the read margin of the programming state P and the read margin of the erase state E. If the data current of NVM cell 1 exceeds the fixed reference current Rf, the control circuit determines that the data of NVM cell 1 is in the erase state E; if the data current of NVM cell 1 is less than the fixed reference current Rf, the control circuit determines that the data of NVM cell 1 is in the programming state P. After the cycle trap effect occurs, due to the reduction of negative charge in NVM cell 1, distributions 20a and 22a will drift to the right, forming distributions 20b and 22b respectively. However, the fixed reference current Rf remains unchanged, causing an increase in the read margin M1 of the erase state E and a decrease in the read margin M0 of the programming state P. If the negative charge in NVM cell 1 decreases too much, the data current of some NVM cells 1 in distribution 20b may exceed the fixed reference current Rf, and the read margin M0 of programming state P may be less than 0, causing the control circuit to misjudge the data of some NVM cells 1 in distribution 20b as erase state E.

[0016] The cyclic trap effect is related to the location of NVM unit 1. Figure 3 This is a distribution diagram of the cyclic trap effect, where the horizontal axis represents the address ADR and the vertical axis represents the current Icell in microamperes. Distribution 31 shows the current distribution of NVM cell 1 in the erase state E, and distribution 30 shows the current distribution of NVM cell 1 in the programming state P.

[0017] Distributions 30 and 31 both show that compared to NVM cells 1 with smaller addresses (e.g., less than address 2048) and larger addresses (e.g., greater than address 8192), NVM cells 1 with intermediate addresses (e.g., between address 2048 and address 8192) have larger data currents. This indicates that the cycle trap effect has regional characteristics; the cycle trap effect is more severe in NVM cells 1 with intermediate addresses, and less severe in NVM cells 1 with smaller and larger addresses. In this embodiment of the invention, the non-volatile memory device can dynamically adjust the reference current ir according to the address, so that the reference current ir is approximately located in the middle of distributions 30 and 31 for all addresses, thereby simultaneously optimizing the read margin of the programming state P and the read margin of the erase state E. In contrast, if a fixed reference current Rf (e.g., Rf = 13.5 microamps) is used to read data, the data current of the NVM cell 1 at the intermediate address will exceed the reference current Rf, causing the non-volatile memory device in the related technology to misjudge the NVM cell 1 in the programming state P as the erase state E.

[0018] Figure 4A This is a schematic diagram of a non-volatile memory device 4 according to an embodiment of the present invention. The non-volatile memory device 4 can dynamically adjust the reference current ir according to the location of the NVM cell, optimize the read margin of the programming state P and the read margin of the erase state E of the NVM cell, and at the same time make the NVM cell unaffected by the cycle trap effect.

[0019] The non-volatile memory device 4 may include character lines WL(0) to WL(P), bit lines BL0(0) to BL0(Q), bit lines BLc, BLr, BL1(0) to BL1(Q), source line SL, memory array MA, input / output (IO) circuitry 414, input / output circuitry 415, comparator circuitry 416, comparator circuitry 417, and control circuitry 40, where P and Q are positive integers, for example, P equals 1023 and Q equals 15. Bit lines BL0(0) to BL0(Q), BLc, BLr, and BL1(0) to BL1(Q) may be regional bit lines, global bit lines, or combinations thereof. The memory array MA includes groups 41 to 4R, where R is a positive integer greater than 1, for example, R equals 16. Each group is configured and operates similarly, and each has corresponding input / output circuitry and comparator circuitry. Group 41 will be explained below. Group 41 corresponds to input / output circuits 414, 415, comparator circuit 416, and 417, and includes a first group of sub-memory cells 411, a reference current update circuit 412, and a second group of sub-memory cells 413. The first group of sub-memory cells 411 may include NVM cells M0(0,0) to M0(P,Q), arranged as an array of (P+1) x (Q+1), and the second group of sub-memory cells 413 may include NVM cells M1(0,0) to M1(P,Q), arranged as an array of (P+1) x (Q+1). The reference current update circuit 412 may include periodic transistors Tc(0) to Tc(P), arranged as one row and (P+1) columns, and reference transistors Tr(0) to Tr(P), arranged as one row and (P+1) columns.

[0020] The reference current update circuit 412 can be disposed between the first group of sub-memory cells 411 and the second group of sub-memory cells 413 to provide the reference current ir required to read the first group of sub-memory cells 411 and / or the second group of sub-memory cells 413. For example, in a 0.15-micrometer (µm) process, the width-to-length dimension of each NVM cell can be 2.0µm x 3.93µm, and the total width of 16 NVM cells can be 32µm. Therefore, the left and right sides of each reference transistor Tr(0) to Tr(P) (hereinafter referred to as Tr) can each cover the width (32µm) of 16 NVM cells, and the circuit area overhead generated by the reference current update circuit 412 is 6.25% (=2 / (16+16)). Since each reference transistor Tr and the 16 NVM cells covered by its left and right sides are located close to each other, the PVT environment is similar, resulting in similar component characteristics. However, the present invention is not limited thereto. In some embodiments, the reference current update circuit 412 may also be located to the left or right of the first group of sub-memory cells 411 and the second group of sub-memory cells 413, with each reference transistor Tr and the 32 NVM cells it covers located close to each other and having similar device characteristics. In other embodiments, the reference current update circuit 412 may also be located between, to the left or right of other numbers of sub-memory cells to provide the reference current ir required to read other numbers of sub-memory cells. The more sub-memory cells the reference current update circuit 412 covers, the smaller the circuit area burden it generates. For example, when the PVT variation is small, the reference current update circuit 412 may be located between the two sub-memory cells on the left and the two sub-memory cells on the right to provide the reference current ir required to read four sub-memory cells, generating a circuit area burden of approximately 3.13% (=2 / (32+32)). And so on.

[0021] The structure and operation of each of the NVM cells M0(0,0) to M0(P,Q), NVM cells M1(0,0) to M1(P,Q), periodic transistors Tc(0) to Tc(P), and reference transistors Tr(0) to Tr(P) are similar to those of NVM cell 1, as explained in the preceding paragraphs and will not be repeated here. The character line WL(0) can be coupled to the floating gate of the 0th column NVM cells (M0(0,0) to M0(0,Q)) of the first group of sub-memory cells 411, the floating gate of the periodic transistor Tc(0), the floating gate of the reference transistor Tr(0), and the floating gate of the 0th column NVM cells (M1(0,0) to M1(0,Q)) of the second group of sub-memory cells 413. Following a coupling method similar to that of character line WL(0), character lines WL(1) to WL(P) can be coupled to the floating gates of the first to P columns of NVM cells in the first group of sub-memory cells 411, the floating gates of periodic transistors Tc(1) to Tc(P), the floating gates of reference transistors Tr(1) to Tr(P), and the floating gates of the first to P columns of NVM cells in the second group of sub-memory cells 413, respectively. Character line BL0(0) can be coupled to the drain of the NVM cell (M0(0,0) to M0(P,0)) in the 0th row of the first group of sub-memory cells 411. In a similar coupling manner to character line BL0(0), bit lines BL0(1) to BL0(Q) can be coupled to the drain of the NVM cell in the 1st to Qth rows of the first group of sub-memory cells 411, bit line BLc can be coupled to the drain of the periodic transistor Tc(0) to Tc(P), bit line BLr can be coupled to the drain of the reference transistor Tr(0) to Tr(P), and bit lines BL1(0) to BL1(Q) can be coupled to the drain of the NVM cell in the 0th to Qth rows of the second group of sub-memory cells 413. The source line SL can be coupled to the ground terminal, the source of NVM cells M0(0,0) to M0(P,Q), the source of periodic transistors Tc(0) to Tc(P), the source of reference transistors Tr(0) to Tr(P), and the source of NVM cells M1(0,0) to M1(P,Q). The ground terminal can provide a ground voltage.

[0022] The input / output circuit 414 can be coupled to the first set of sub-memory cells 411, the reference current update circuit 412, and the control circuit 40, so that the control circuit 40 reads or writes NVM cells M0(0,0) to M0(P,Q) via the input / output circuit 414. When reading a selected NVM cell from NVM cells M0(0,0) to M0(P,Q), the input / output circuit 414 can receive the respective data currents i00 to i0q via bit lines BL0(0) to BL0(Q) and the reference current ir via bit line BLr to generate a comparison result cmpd0, and output the comparison result cmpd0 to the control circuit 40. The comparison result cmpd0 indicates the state of the selected NVM cell, such as the erase state E or the programming state P.

[0023] Input / output circuit 415 can be coupled to the second set of sub-memory cells 413, reference current update circuit 412, and control circuit 40, so that control circuit 40 reads or writes NVM cells M1(0,0) to M1(P,Q) via input / output circuit 415. Input / output circuit 414 can be adjacent to input / output circuit 415. When reading a selected NVM cell from NVM cells M1(0,0) to M1(P,Q), input / output circuit 415 can receive respective data currents i10 to i1q via bit lines BL1(0) to BL1(Q) and receive reference current ir via bit line BLr to generate comparison result cmpd1, and output comparison result cmpd1 to control circuit 40. Comparison result cmpd1 indicates the state of the selected NVM cell, such as erase state E or programming state P.

[0024] Comparator circuit 416 can be coupled to reference current update circuit 412 and control circuit 40 so that control circuit 40 reads or writes periodic transistors Tc(1) to Tc(P) via comparator circuit 416. When reading a selected periodic transistor among periodic transistors Tc(1) to Tc(P), comparator circuit 416 can receive periodic current ic via bit line Blc and reference current ir via bit line BLR to generate comparison result cmpc, and output comparison result cmpc to control circuit 40. Comparison result cmpc indicates the state of the selected periodic transistor, such as erase state E or programming state P.

[0025] Comparator circuit 417 can be coupled to reference current update circuit 412 and control circuit 40, so that control circuit 40 reads or writes reference transistors Tr(0) to Tr(P) via comparator circuit 417. When reading a selected periodic transistor among periodic transistors Tc(0) to Tc(P), comparator circuit 417 can receive reference current ir via bit line BLr to generate comparison result cmpr, and output comparison result cmpr to control circuit 40. Comparison result cmpr indicates the state of the selected reference transistor, such as erase state E, programming state P, or a reference state between erase state E and programming state P.

[0026] The control circuit 40 can receive comparison results cmpd0, cmpd1, cmpc and cmpr, and is coupled to group 41 via character lines WL(0) to WL(P), bit lines BL0(0) to BL0(Q), bit lines BLc, bit lines BLr and BL1(0) to BL1(Q) to control the operation of NVM units M0(0,0) to M0(P,Q), NVM units M1(0,0) to M1(P,Q), periodic transistors Tc(0) to Tc(P) and reference transistors Tr(0) to Tr(P), and transmit selection signals to input / output circuits 414, 415, comparator circuit 416 and 417 to control their operation.

[0027] The first group of sub-memory cells 411 and the second group of sub-memory cells 413 can form a group of memory cells. Periodic transistors Tc(0) to Tc(P) can be set to either a programming state P or an erase state E. Each periodic transistor Tc(0) to Tc(P) (hereinafter referred to as Tc) can toggle between programming state P and erase state E, that is, switching from programming state P to erase state E (performing an erase operation), or switching from erase state E to programming state P (performing a programming operation). The time required for each periodic transistor Tc to perform erase and programming operations is the same as that of the NVM cells in the group of memory cells; therefore, the erase and programming operations of the periodic transistor Tc can be performed simultaneously with the NVM cells without requiring additional time. Reference transistors Tr(0) to Tr(P) can be set to their respective small cycles and returned to the reference state according to the states of the periodic transistors Tc(0) to Tc(P), respectively, to generate the reference current ir of the NVM cells in columns 0 to P of the group of memory cells. For example, the reference transistor Tr(0) can generate the reference current ir for the NVM cell in column 0 of the memory cell set. The reference states of the reference transistors Tr(0) to Tr(P) are between the erase state E and the programming state P.

[0028] Figure 4BThis is a circuit diagram of the input / output circuits 414, 415, 416, 417, and control circuit 40 of the non-volatile memory device 4. The input / output circuit 414 may include multiplexers 4140 and 4142, and comparator 4144. The multiplexer 4140 may include (Q+1) input terminals for receiving data currents i00 to i0q; a selection terminal for receiving a selection signal S0; and an output terminal for outputting the selected data current id0. The selection signal S0 may be generated by the control circuit 40. The multiplexer 4140 can select one of the data currents i00 to i0q as the selected data current id0 for the selected NVM cell based on the selection signal S0. Multiplexer 4142 may include three input terminals for receiving a reference current ir, a lower limit current Ev, and an upper limit current Pv, respectively; a selection terminal for receiving a selection signal Sd0; and an output terminal for outputting the selected reference current ir0. The selection signal Sd0 may be generated by control circuit 40. Multiplexer 4142 may select one of the reference current ir, the lower limit current Ev, and the upper limit current Pv as the selected reference current ir0 based on the selection signal Sd0. Comparator 4144 may include a first input terminal for receiving the selected data current id0; a second input terminal for receiving the selected reference current ir0; and an output terminal for outputting the comparison result cmpd0.

[0029] Figure 5 The current distribution of NVM cells M0(0,0) to M0(P,Q), M1(0,0) to M1(P,Q), periodic transistors Tc(1) to Tc(P) and reference transistors Tr(0) to Tr(P) is shown, where the horizontal axis represents the current Icell and the vertical axis represents the quantity N. Distribution 50 represents the current distribution of NVM cells M0(0,0) to M0(P,Q), M1(0,0) to M1(P,Q), periodic transistors Tc(0) to Tc(P), and reference transistors Tr(0) to Tr(P) in programming state P. Distribution 51 represents the current distribution of NVM cells M0(0,0) to M0(P,Q), M1(0,0) to M1(P,Q), periodic transistors Tc(0) to Tc(P), and reference transistors Tr(0) to Tr(P) in erase state E. Distribution 52 represents the current distribution of reference transistors Tr(0) to Tr(P) in reference state Rv, where reference state Rv is between erase state E and programming state P. Distribution 50 may have an upper limit current Pv, distribution 51 may have a lower limit current Ev, and distribution 52 may have a lower limit current Rve and an upper limit current Rvp. The difference between the lower limit current Rve and the upper limit current Pv can be considered the read margin for the programming state P, and the difference between the lower limit current Ev and the upper limit current Rvp can be considered the read margin for the erase state E. The following combinations... Figure 5Explain the operation of input / output circuit 414. When reading a selected memory cell, multiplexer 4142 can select a reference current ir as the selected reference current ir0 based on selection signal Sd0, and comparator 4144 can compare the selected data current id0 and the selected reference current ir0 to generate a comparison result cmpd0. For example, if the selected data current id0 exceeds the selected reference current ir0, the comparison result cmpd0 indicates that the selected memory cell is in erase state E; if the selected data current id0 is less than the selected reference current ir0, the comparison result cmpd0 indicates that the selected memory cell is in programming state P. In the verification procedure after writing programming state P to the selected memory cell, multiplexer 4142 can select an upper limit current Pv as the selected reference current ir0 based on selection signal Sd0, and comparator 4144 can compare the selected data current id0 and the selected reference current ir0 to generate a comparison result cmpd0. For example, if the selected data current id0 exceeds the selected reference current ir0, the comparison result cmpd0 indicates that the selected memory cell has not yet been written to the programming state P, thus the verification fails; if the selected data current id0 is less than the selected reference current ir0, the comparison result cmpd0 indicates that the selected memory cell has been written to the programming state P, thus the verification succeeds. In the erase verification procedure after erasing the selected memory cell, the multiplexer 4142 can select the lower limit current Ev as the selected reference current ir0 based on the selection signal Sd0, and the comparator 4144 can compare the selected data current id0 and the selected reference current ir0 to generate a comparison result cmpd0. For example, if the selected data current id0 is less than the selected reference current ir0, the comparison result cmpd0 indicates that the selected memory cell has not yet been set to the erase state E, thus the erase verification fails; if the selected data current id0 exceeds the selected reference current ir0, the comparison result cmpd0 indicates that the selected memory cell has been set to the erase state E, thus the erase verification succeeds.

[0030] Similar to input / output circuit 414, input / output circuit 415 may include multiplexer 4150, multiplexer 4152, and comparator 4154. Multiplexer 4150 may include (Q+1) input terminals for receiving data currents i10 to i1q; a selection terminal for receiving a selection signal S1; and an output terminal for outputting the selected data current id1. The selection signal S1 may be generated by control circuit 40. Multiplexer 4150 can select one of the data currents i10 to i1q as the selected data current id1 for selecting the NVM cell based on the selection signal S1. Multiplexer 4152 may include three input terminals for receiving a reference current ir, a lower limit current Ev, and an upper limit current Pv; a selection terminal for receiving a selection signal Sd1; and an output terminal for outputting the selected reference current ir1. The selection signal Sd1 may be generated by control circuit 40. Multiplexer 4152 can select one of the reference current ir, lower limit current Ev, and upper limit current Pv as the selected reference current ir1 based on the selection signal Sd1. Comparator 4154 may include a first input terminal for receiving the selected data current id1; a second input terminal for receiving the selected reference current ir1; and an output terminal for outputting the comparison result cmpd1. The operation of multiplexers 4150, 4152, and 4154 is similar to that of multiplexers 4140, 4142, and 4144, respectively. Their explanations can be found in the preceding paragraphs and will not be repeated here.

[0031] The comparator circuit 416 may include a multiplexer 4162 and a comparator 4164. The multiplexer 4162 may include three input terminals for receiving a reference current ir, a lower limit current Ev, and an upper limit current Pv; a selection terminal for receiving a selection signal Sc; and an output terminal for outputting the selected reference current irc. The selection signal Sc may be generated by the control circuit 40. The multiplexer 4162 can select one of the reference current ir, the lower limit current Ev, and the upper limit current Pv as the selected reference current irc based on the selection signal Sc. The comparator 4164 may include a first input terminal for receiving a periodic current ic; a second input terminal for receiving the selected reference current irc; and an output terminal for outputting the comparison result cmpc. The operation of the multiplexer 4162 and the comparator 4164 is similar to that of the multiplexer 4142 and the comparator 4144, respectively. Their explanations can be found in the preceding paragraphs and will not be repeated here.

[0032] The comparator circuit 417 may include a multiplexer 4172 and a comparator 4174. The multiplexer 4172 may include four input terminals for receiving the lower limit current Rve, the upper limit current Rvp, the lower limit current Ev, and the upper limit current Pv, respectively; a selection terminal for receiving a selection signal Sr; and an output terminal for outputting the selected reference current irr. The selection signal Sr may be generated by the control circuit 40. The multiplexer 4172 can select one of the lower limit current Rve, the upper limit current Rvp, the lower limit current Ev, and the upper limit current Pv as the selected reference current irr based on the selection signal Sr. The comparator 4174 may include a first input terminal for receiving the reference current ir; a second input terminal for receiving the selected reference current irr; and an output terminal for outputting the comparison result cmpr.

[0033] The following combinations Figure 5 Explain the operation of comparator circuit 417. In the verification process after the selected reference transistor is programmed from reference state Rv to programming state P, multiplexer 4172 selects the upper limit current Pv as the selected reference current irr based on the selection signal Sr, and comparator 4174 compares the reference current ir and the selected reference current irr to generate a comparison result cmpr. For example, if the reference current ir exceeds the selected reference current irr, the comparison result cmpr indicates that the selected reference transistor has not yet been programmed to programming state P, and therefore the verification fails; if the reference current ir is less than the selected reference current irr, the comparison result cmpr indicates that the selected reference transistor has been programmed to programming state P, and therefore the verification succeeds. In the verification process after the selected reference transistor is programmed from programming state P to reference state Rv, multiplexer 4172 selects the lower limit current Rve as the selected reference current irr based on the selection signal Sr, and comparator 4174 compares the reference current ir and the selected reference current irr to generate a comparison result cmpr. For example, if the reference current ir is less than the selected reference current irr, the comparison result cmpr indicates that the selected reference transistor has not yet been programmed to the reference state Rv, and therefore the verification fails; if the reference current ir exceeds the selected reference current irr, the comparison result cmpr indicates that the selected reference transistor has been programmed to the reference state Rv, and therefore the verification succeeds.

[0034] In the verification procedure after the selected reference transistor is programmed from the reference state Rv to the erase state E, the multiplexer 4172 can select a lower limit current Ev as the selected reference current irr based on the selection signal Sr, and the comparator 4174 can compare the reference current ir and the selected reference current irr to generate a comparison result cmpr. For example, if the reference current ir is less than the selected reference current irr, the comparison result cmpr indicates that the selected reference transistor has not yet been programmed to the erase state E, and therefore the verification fails; if the reference current ir exceeds the selected reference current irr, the comparison result cmpr indicates that the selected reference transistor has been programmed to the erase state E, and therefore the verification succeeds. In the verification procedure after the selected reference transistor is programmed from the erase state E to the reference state Rv, the multiplexer 4172 can select an upper limit current Rvp as the selected reference current irr based on the selection signal Sr, and the comparator 4174 can compare the reference current ir and the selected reference current irr to generate a comparison result cmpr. For example, if the reference current ir exceeds the selected reference current irr, the comparison result cmpr indicates that the selected reference transistor has not yet been programmed to the reference state Rv, and therefore the verification fails; if the reference current ir is less than the selected reference current irr, the comparison result cmpr indicates that the selected reference transistor has been programmed to the reference state Rv, and therefore the verification succeeds.

[0035] Figure 5 This diagram illustrates the control method of the NVM device 4. In some embodiments, at the factory, the control circuit 40 can set the NVM cells M0(0,0) to M0(P,Q), the NVM cells M1(0,0) to M1(P,Q), and the periodic transistors Tc(0) to Tc(P) to a preset state of erase state E, and set the reference transistors Tr(0) to Tr(P) to a preset state of reference state Rv, which is between erase state E and programming state P. For example, the preset state of reference state Rv can be substantially located in distribution 52, which is between the upper limit current Pv of distribution 50 and the lower limit current Ev of distribution 51, thereby optimizing the read margin of programming state P and the read margin of erase state E for the plurality of NVM cells. NVM cells M0(0,0) to M0(P,Q), NVM cells M1(0,0) to M1(P,Q), and periodic transistors Tc(0) to Tc(P) can be switched between erase state E and programming state P. During programming, any selected NVM cell in distribution 51 can switch from erase state E to programming state P via programming cycle 54. During erase operation, any selected NVM cell in distribution 50 can switch from programming state P to erase state E via erase cycle 53. The PE cycle includes one erase cycle 53 and one programming cycle 54.

[0036] For example, during the programming or erasing operation of the NVM cell in column 0 of the memory cell group, the control circuit 40 can read the reference transistor Tr(0) to generate a reference current ir, and read the periodic transistor Tc(0) to generate a periodic current ic. The comparator 416 can compare the periodic current ic and the reference current ir to generate a comparison result cmpc, and the control circuit 40 can control the operation of the periodic transistor Tc(0) and the reference transistor Tr(0) according to the comparison result cmpc. If the periodic current ic exceeds the reference current ir, the comparison result cmpc indicates that the periodic transistor Tc(0) is in the erasure state E. If the periodic current ic is less than the reference current ir, the comparison result cmpc indicates that the periodic transistor Tc(0) is in the programming state P. If the comparison result cmpc indicates that the periodic transistor Tc(0) is in the erasure state E, the control circuit 40 can switch the periodic transistor Tc(0) from the erasure state E to the programming state P. Furthermore, the control circuit 40 can sequentially set the reference transistor Tr(0) from the reference state Rv to the erase state E via cycle 57, and restore the reference transistor Tr(0) from the erase state E to the reference state Rv via cycle 58.

[0037] During the programming or erasing operation of the NVM cell in column 0 of this group of memory cells, if the comparison result cmpc indicates that the periodic transistor Tc(0) is in programming state P, the control circuit 40 can switch the periodic transistor Tc(0) from programming state P to erasing state E. The control circuit 40 can sequentially set the reference transistor Tr(0) from reference state Rv to programming state P via cycle 55, and restore the reference transistor Tr(0) from programming state P to reference state Rv via cycle 56. Therefore, in each PE cycle, the reference transistor Tr(0) will go through cycles 55 to 58. Since cycle 55 is equivalent to a portion of programming cycle 54, cycle 56 is equivalent to a portion of erase cycle 53, cycle 57 is equivalent to the remaining portion of erase cycle 53, and cycle 58 is equivalent to the remaining portion of programming cycle 54, the total charge change in cycles 58 and 55 is approximately equal to the charge change in programming cycle 54, and the total charge change in cycles 56 and 57 is approximately equal to the charge change in erase cycle 53. The reference transistor Tr(0) is equivalent to experiencing one PE cycle, resulting in similar degrees of cyclic trap effects for the reference transistor Tr(0) and the 0th column NVM cell of the memory cell group. Furthermore, after a period of time, the current drift direction and drift degree of the reference transistor Tr(0) and the 0th column NVM cell of the memory cell group are also similar, thereby optimizing the read margin of the programming state P and the read margin of the erase state E of the 0th column NVM cell of the memory cell group. For example, in Figure 5If the programming state P and erase state E of the NVM cell in column 0 of the memory cell group are within distribution 50 and distribution 51 respectively, and the reference transistor Tr(0) is within distribution 52, then after a period of time, distributions 50, 51, and 52 will all drift to the right by a similar distance. Therefore, the read margin of programming state P and the read margin of erase state E will remain unchanged, so as to correctly read the data of the NVM cell. In addition, since the reference transistor Tr(0) and the NVM cell in column 0 of the memory cell group are close to each other, if the PVT environment changes, distributions 50, 51, and 52 will all drift to the left or to the right by a similar distance. Therefore, the read margin of programming state P and the read margin of erase state E will remain unchanged, so as to correctly read the data of the NVM cell.

[0038] During a read operation of NVM cell M1(0,0) in this group of memory cells, the control circuit 40 can read the reference transistor Tr(0) to generate a reference current ir, and read the NVM cell M1(0,0) to generate a data current id. The comparator 415 can compare the reference current ir and the data current id to generate a comparison result cmpd1, and the control circuit 40 can determine the data of NVM cell M1(0,0) based on the comparison result cmpd1. If the data current id exceeds the reference current ir, the comparison result cmpd1 indicates that the data of NVM cell M1(0,0) is in the erase state E; if the data current id is less than the reference current ir, the comparison result cmpd1 indicates that the data of NVM cell M1(0,0) is in the programming state P.

[0039] Although the NVM cells in the non-volatile memory device 4 are MTP memory cells, those skilled in the art can use other types of NVM cells in the non-volatile memory device 4 according to actual needs, such as electrically erasable programmable read-only memory (EEPROM), NOR flash memory, and NAND flash memory. Furthermore, although the NVM cells in the non-volatile memory device 4 are single-level memory cells, those skilled in the art can change the reference transistor settings of the reference current update circuit 412 according to actual needs to apply the present invention to multi-level memory cells. For example, for a double-level memory cell, each NVM cell can store 2 bits of metadata and can be set to one of four states. The reference current update circuit 412 can include three reference transistors, which respectively generate the three reference currents required to read the three programming states according to the embodiments of the present invention.

[0040] Figure 6This is a flowchart of a control method 600 for a non-volatile memory device 4. The control method 600 includes steps S602 to S610, wherein steps S604 and S606 are used to control the operation of the periodic transistor and the reference transistor after the periodic transistor is read into an erase state, and steps S608 and S610 are used to control the operation of the periodic transistor and the reference transistor after the periodic transistor is read into a programming state. Any reasonable changes, orders, or adjustments to the steps fall within the scope of this disclosure. Steps S602 to S610 are explained as follows:

[0041] Step S602: During a programming or erasing operation of a group of memory cells, the control circuit 40 reads the periodic transistor; if the periodic transistor is in the erasing state, continue with steps S604 and S606; if the periodic transistor is in the programming state, continue with steps S608 and S610.

[0042] Step S604: Control circuit 40 switches the periodic transistor from the erase state to the programming state;

[0043] Step S606: The control circuit 40 sequentially sets the reference transistor from the reference state to the erase state and restores the reference transistor from the erase state to the reference state.

[0044] Step S608: Control circuit 40 switches the periodic transistor from the programming state to the erase state;

[0045] Step S610: The control circuit 40 sequentially sets the reference transistor from the reference state to the programming state and restores the reference transistor from the programming state to the reference state.

[0046] At the time of manufacture, all periodic transistors and NVM cells in the non-volatile memory device 4 are set to the erase state E, and all reference transistors are set to a preset state, which is the initial reference state Rv. In step S602, after receiving a programming or erasing instruction for a group of memory cells (i.e., the first group of sub-memory cells 411 and the second group of sub-memory cells 413), the control circuit 40 determines that the group of memory cells needs to be programmed or erased, and reads the periodic transistors. The group of NVM cells can be a column of NVM cells, multiple columns of NVM cells, or a subset of NVM cells. For example, the group of NVM cells can be the 0th column of the first group of sub-memory cells 411 or the 0th column of the second group of sub-memory cells 413.

[0047] If the periodic transistor is found to be in erase state E in step S602, then in step S604, the control circuit 40 switches the periodic transistor from erase state E to programming state P. In step S606, the control circuit 40 sequentially sets the reference transistor from reference state Rv to erase state E and then returns the reference transistor from erase state E to reference state Rv, thereby causing the reference transistor to experience cycles 57 and 58. Steps S604 and S606 can be performed simultaneously.

[0048] If the periodic transistor is read as being in programming state P in step S602, then in step S608, the control circuit 40 switches the periodic transistor from programming state P to erase state E. In step S610, the control circuit 40 sequentially sets the reference transistor from reference state Rv to programming state P and then returns it from programming state P to reference state Rv, thereby allowing the reference transistor to experience cycles 55 and 56. Steps S608 and S610 can be performed simultaneously. After the group of NVM cells completes one PE cycle, the reference transistor also equivalently completes one PE cycle. Therefore, the degree of the cycle trap effect of the reference transistor and the group of NVM cells is similar, and thus the read margin of programming state P and the read margin of erase state E remain unchanged and do not deteriorate.

[0049] Figure 7This is a timing diagram of the PE cycle of NVM device 4, including clock signal CLKwt, NVM cell M1(0,0), periodic transistor Tc(0), and reference transistor Tr(0). Clock signal CLKwt is used for the erase / programming operation of NVM cell M1(0,0). Between times t1 and t2, NVM cell M1(0,0) and periodic transistor Tc(0) are initialized to the erase state E, and reference transistor Tr(0) is initialized to the reference state Rv. At time t2, control circuit 40 receives the erase / programming command from NVM cell M1(0,0), and clock signal CLKwt begins to rise. Between times t2 and t3, control circuit 40 performs a read operation (R) on NVM cell M1(0,0) and periodic transistor Tc(0) to read the original state (E) of NVM cell M1(0,0) and the original state (E) of periodic transistor Tc(0), while reference transistor Tr(0) remains in the reference state Rv. Between times t3 and t4, an erasure operation is performed. Therefore, the periodic transistor Tc(0) remains in the erasure state E, and the NVM cell M1(0,0) is set to the target state (E). Since the original state of the periodic transistor Tc(0) is erasure state E, the reference transistor Tr(0) is set from the reference state Rv to the erasure state E. The NVM cell M1(0,0) is only switched when there is a difference between the original state and the target state of the NVM cell M1(0,0), for example, the original state is erasure state E and the target state is programming state P, or the original state is programming state P and the target state is erasure state E. Between times t4 and t5, a programming operation is performed. Therefore, the periodic transistor Tc(0) switches from the erasure state E to the programming state P, and the reference transistor Tr(0) switches from the erasure state E to the reference state Rv. The NVM cell M1(0,0) is set to the target state (P). In some embodiments, the lengths between times t3 and t4 and between times t4 and t5 may be similar, with the time period between times t3 and t4 used to set the erase state E, and the time period between times t4 and t5 used to set the programming state P.

[0050] At time t6, the clock signal CLKwt begins to rise, and the control circuit 40 receives the erase / program command from the NVM cell M1(0,0). Between times t6 and t7, the control circuit 40 performs a read operation (R) on the NVM cell M1(0,0) and the periodic transistor Tc(0) to read the original state (E or P) of the NVM cell M1(0,0) and the original state (P) of the periodic transistor Tc(0).

[0051] Between times t7 and t8, an erasure operation is performed, so the NVM cell M1(0,0) is set to the target state (E), the periodic transistor Tc(0) switches from the programming state P to the erasure state E, and the reference transistor Tr(0) remains in the reference state Rv. Between times t8 and t9, a programming operation is performed, so the NVM cell M1(0,0) is set to the target state (P), and since the original state of the periodic transistor Tc(0) is the programming state P, the reference transistor Tr(0) is set from the reference state Rv to the programming state P, while the periodic transistor Tc(0) remains unchanged. In some embodiments, the lengths between times t7 and t8 and between times t8 and t9 may be similar, with the period between times t7 and t8 used to set the erasure state E, and the period between times t8 and t9 used to set the programming state P. Between time t9 and t10, an erasure operation is performed during this phase. The reference transistor Tr(0) returns from the programming state P to the reference state Rv, the periodic transistor Tc(0) remains in the erasure state E, and the NVM cell M1(0,0) remains in the target state (E or P).

[0052] The time interval from t2 to t10 can be considered as a PE cycle. The NVM device 4 can repeat the operation between time t2 and t10 to make the degree of the cyclic trap effect of the reference transistor Tr(0) and the NVM cell M1(0,0) similar, so that the read margin of the programming state P and the read margin of the erase state E remain unchanged, so as to correctly read the data of the NVM cell.

[0053] Figure 8 This is a timing diagram of the read operation of NVM device 4, including clock signal CLKrd, memory array MA, periodic transistor Tc, and reference transistor Tr. Clock signal CLKrd is used for the read operation of memory array MA. At time t1, control circuit 40 receives a read command for the first group of selected NVM cells in memory array MA, and clock signal CLKrd begins to rise. Between times t1 and t2, control circuit 40 performs a read operation (R) on the first group of selected NVM cells. The corresponding reference transistor Tr for the first group of selected NVM cells remains in the reference state Rv, and periodic transistor Tc remains in its original state (E or P). At time t2, control circuit 40 receives a read command for the second group of selected NVM cells in memory array MA, and clock signal CLKrd begins to rise. Between times t1 and t2, control circuit 40 performs a read operation (R) on the second group of selected NVM cells. The corresponding reference transistor Tr for the second group of selected NVM cells remains in the reference state Rv, and periodic transistor Tc remains in its original state (E or P). NVM device 4 can repeat the actions between time t1 and t2 to read multiple selected NVM cells.

[0054] Figure 4Aand Figure 6 The non-volatile memory device 4 and its control method 600 of the embodiment use periodic transistors and reference transistors to adjust the reference current at the corresponding positions so that the read margin of the programming state P and the read margin of the erase state E remain unchanged and do not deteriorate, thereby correctly reading the data of the non-volatile memory cell. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the protection scope of the present invention.

Claims

1. A control method for a non-volatile memory device, characterized in that, The non-volatile memory device includes a set of memory cells, a periodic transistor, a reference transistor, and a control circuit. The control circuit is configured to perform a programming operation or an erasure operation on the set of memory cells according to an instruction. The control circuit is coupled to the set of memory cells, the periodic transistor, and the reference transistor. The method includes: Before performing the programming or erasing operation on the group of memory cells, the control circuit reads the state of one of the periodic transistors; and After reading that the cycle transistor is in an erase state, the control circuit sequentially sets the reference transistor from a reference state to the erase state and restores the reference transistor from the erase state to the reference state, which is between the erase state and a programming state.

2. The method as described in claim 1, characterized in that, It also includes: after reading that the cycle transistor is in the erase state, the control circuit switches the cycle transistor from the erase state to the programming state.

3. A control method for a non-volatile memory device, characterized in that, The non-volatile memory device includes a set of memory cells, a periodic transistor, a reference transistor, and a control circuit. The control circuit is configured to perform a programming operation or an erasure operation on the set of memory cells according to an instruction. The control circuit is coupled to the set of memory cells, the periodic transistor, and the reference transistor. The method includes: Before performing the programming or erasing operation on the group of memory cells, the control circuit reads the state of one of the periodic transistors; and After reading that the periodic transistor is in a programming state, the control circuit sequentially sets the reference transistor from a reference state to the programming state and restores the reference transistor from the programming state to the reference state, which is between an erase state and the programming state.

4. The method as described in claim 3, characterized in that, It also includes: after reading that the periodic transistor is in the programming state, the control circuit switches the periodic transistor from the programming state to the erase state.

5. The method according to any one of claims 3 to 4, characterized in that, Also includes: During a read operation of the group of memory cells, the control circuit reads the reference transistor to generate a reference current, reads a memory cell in the group of memory cells to generate a data current, and compares the reference current and the data current to determine a data in the memory cell.

6. The method according to any one of claims 3 to 4, characterized in that, Also includes: The reference transistor is set to a preset state, which is between the erase state and the programmable state.

7. The method according to any one of claims 3 to 4, characterized in that, Also includes: The cycle current generated by the cycle transistor is compared with the reference current generated by the reference transistor to determine whether the cycle transistor is in the erase state or the programmable state.

8. A non-volatile memory device, characterized in that, Include: A set of memory units; One-cycle transistor; A reference transistor; A comparator circuit includes: A first comparator, coupled to the periodic transistor and the reference transistor, is used to compare a periodic current generated by the periodic transistor and a reference current generated by the reference transistor to generate a first comparison result before performing a programming operation or an erasure operation of the group of memory cells. and A control circuit, coupled to the group of memory cells, the periodic transistor, the reference transistor, and the first comparator, is configured to sequentially set the reference transistor from a reference state to the erase state and restore the reference transistor from the erase state to the reference state after the first comparison result indicates that the periodic transistor is in an erase state, the reference state being between the erase state and a programming state.

9. The non-volatile memory device as claimed in claim 8, characterized in that, The first comparison result indicates that after the periodic transistor is in the erase state, the control circuit is also used to switch the periodic transistor from the erase state to the programming state.

10. The non-volatile memory device as claimed in claim 8, characterized in that, After the first comparison result indicates that the periodic transistor is in the programming state, the control circuit sequentially sets the reference transistor from the reference state to the programming state and restores the reference transistor from the programming state to the reference state.

11. The non-volatile memory device as claimed in claim 10, characterized in that, After the first comparison result indicates that the periodic transistor is in the programming state, the control circuit is also used to switch the periodic transistor from the programming state to the erase state.

12. The non-volatile memory device as claimed in claim 8, characterized in that, Also includes: An input / output circuit includes a second comparator coupled to the reference transistor and the group of memory cells, for comparing a reference current generated by the reference transistor and a data current generated by a memory cell in the group of memory cells to generate a second comparison result. and The control circuit is used to determine a data in the memory cell based on the second comparison result.

13. The non-volatile memory device as claimed in claim 12, characterized in that, This group of memory cells contains: A first set of sub-memory cells, coupled to the input / output circuit; and A second set of sub-memory cells is coupled to another input / output circuit.

14. The non-volatile memory device as claimed in claim 13, characterized in that, The input / output circuit is adjacent to the other input / output circuit.

15. The non-volatile memory device as claimed in claim 8, characterized in that: The control circuit is used to set the reference transistor to a preset state, which is between the erase state and the programming state.

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