Biasing circuit and method for reducing flash read cross talk

Abstract

The application discloses a bias circuit for reducing read string interference of flash memory. The array structure of the flash memory is formed by a plurality of memory cells, and each memory cell adopts a split-gate floating-gate device. The bias circuit provides a first voltage. When reading a selected memory cell of the flash memory, the following voltage settings are adopted: the control gate line corresponding to the selected memory bit of the selected memory cell is grounded, the control gate line corresponding to the non-selected memory bit is connected to a control gate read voltage, and the word line is connected to a word line read voltage. The first voltage is connected to each bit line connected to the non-selected memory cell, and the difference between the first voltage and the control gate read voltage is used to reduce the read string interference of the control gate read voltage on each non-selected memory cell located in the same row as the selected memory cell. The application also discloses a bias method for reducing read string interference of flash memory. The application can reduce the read string interference of the higher control gate read voltage on each non-selected memory cell located in the same row as the selected memory cell during the read operation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and in particular to a bias circuit for reducing flash memory read crosstalk. This invention also relates to a bias method for reducing flash memory read crosstalk. Background Technology

[0002] like Figure 1 The diagram shown is a schematic of the circuit structure of a conventional flash memory storage cell; as shown... Figure 2 The diagram shown is a cross-sectional view of a conventional flash memory cell; each of the memory cells 101 employs a discrete-gate floating-gate device.

[0003] like Figure 2 As shown, the split-gate floating gate device includes: a first source-drain region 205 and a second source-drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source-drain region 205 and the second source-drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0004] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0005] The separated gate floating gate device is an N-type device, and both the first source / drain region 205 and the second source / drain region 206 are composed of N+ regions.

[0006] The P-type doped channel region is located between the first source / drain region 205 and the second source / drain region 206 and is covered by each of the first gate structure and the second gate structure 103. The first source / drain region 205 and the second source / drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205 and the second source / drain region 206 or by further doping on the P-type semiconductor substrate 201.

[0007] The second source / drain region 206 of the storage cell 101 is connected to the bit line BL1.

[0008] The first source-drain region 205 of the storage unit 101 is connected to bit line BL0.

[0009] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0010] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0011] Figure 2 In this configuration, the two control gates 105 can be controlled separately and are connected to control gate lines CG0 and CG1 respectively, and the word line gate 106 is connected to the word line WL.

[0012] When reading from the storage unit 101, taking the reading operation on the storage bit 'a' corresponding to the first source-drain region 205 as an example:

[0013] The control gate line CG0 is connected to 0V, i.e., grounded GND;

[0014] The word line WL is connected to the word line read voltage VWLR, which is, for example, 3.8V;

[0015] The control gate line CG1 is connected to the control gate read voltage VCGR, which is, for example, 5.4V;

[0016] The bit line BL0 is connected to 0V.

[0017] The bit line BL1 is connected to the read current Isense, which corresponds to a low voltage of approximately 0.8V.

[0018] A high VCGR (Vibration Capacity Growing Rate) can easily lead to read crosstalk, such as... Figure 2 As shown, if electrons are stored in the floating gate 104 corresponding to storage bit 'b', under the long-term action of VCGR, the stored electrons will leak from the floating gate 104 to the control gate 105 at the top. Under the cumulative effect, the state of storage bit 'b' may change, which generates read crosstalk.

[0019] like Figure 3 The diagram shown illustrates read crosstalk that occurs during read operations in existing flash memory. Figure 3 The image shows a row of memory cells 101, with dashed lines like 301 indicating that the selected memory cell 101 is the one from which the read of memory bit 'a' described above will be performed. The control gate read voltage VCGR is also connected to the control gate 105 corresponding to other non-selected memory cells in the same row as the selected memory cell 101, thus... Figure 2 Just like the storage bit 'b' of the selected memory cell, non-selected memory cells will also generate read crosstalk caused by VCGR. Summary of the Invention

[0020] The technical problem to be solved by this invention is to provide a bias circuit for reducing flash memory read crosstalk, thereby reducing the crosstalk between the high control gate read voltage during read operations and non-selected memory cells in the same row as the selected memory cell. To this end, this invention also provides a bias method for reducing flash memory read crosstalk.

[0021] Therefore, in the bias circuit for reducing flash memory read crosstalk provided by the present invention, the array structure of the flash memory is formed by arranging multiple memory cells, and each memory cell adopts a discrete gate floating gate device.

[0022] The split-gate floating gate device includes: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0023] The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a segment of the channel region.

[0024] Each of the floating gates of the first gate structure serves as a storage bit.

[0025] The control gate of each of the first gate structures is connected to the corresponding control gate line.

[0026] Each of the second gate structures is connected to the corresponding word line.

[0027] In the array structure, the word line gates of each memory cell in the same row are all connected to the word lines of the same row.

[0028] The control gates of each memory cell in the same row are connected to the control gate lines in the same row.

[0029] The first source-drain region of the memory cell in the same column is connected to the corresponding bit line in the same column.

[0030] The second source-drain region of the memory cell in the same column is connected to the corresponding bit line in the same column.

[0031] The bias circuit provides the first voltage.

[0032] When reading a selected memory cell from the flash memory, the following voltage settings are used:

[0033] The control gate line corresponding to the selected memory bit of the selected memory cell is grounded, and the control gate line corresponding to the non-selected memory bit is connected to the control gate read voltage, and the word line is connected to the word line read voltage.

[0034] The first voltage is connected to each of the bit lines to which the non-selected memory cells are connected, and the difference between the first voltage and the control gate read voltage is used to reduce the read crosstalk of the control gate read voltage to each of the non-selected memory cells located in the same row as the selected memory cell.

[0035] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0036] A further improvement is that the separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions.

[0037] The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

[0038] A further improvement is that each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate.

[0039] The second gate structure is formed by stacking a word line gate dielectric layer and a word line gate.

[0040] A further improvement is that, of the two bit lines connected to the selected memory cell, one is grounded and the other outputs the read current, with the grounded bit line being closer to the selected memory bit than the bit line that outputs the read current.

[0041] A further improvement is that the bias circuit includes a plurality of first switches connected to the bit line. The control terminal of the first switch is connected to a control signal, the input terminal of the first switch is connected to a power supply voltage, and the output terminal of the first switch is connected to the bit line. The high level of the control signal is the power supply voltage, and the low level is 0V.

[0042] During reading, the first switch corresponding to each bit line connected to all the non-selected memory cells is turned on, and the output terminal of the first switch outputs the first voltage obtained from the power supply voltage to the connected bit line; the first switch corresponding to the two bit lines connected to the selected memory cell is turned off.

[0043] A further improvement is that the first switch is a PMOS transistor, and the first voltage is equal to the power supply voltage; or, the first switch is an NMOS transistor, and the first voltage is equal to the power supply voltage minus a first threshold voltage, wherein the first threshold voltage is the threshold voltage of the NMOS transistor of the first switch.

[0044] A further improvement is that the control gate read voltage is above 5.4V.

[0045] To solve the above-mentioned technical problems, the bias method for reducing flash memory read crosstalk provided by the present invention is that the array structure of the flash memory is formed by arranging multiple memory cells, and each memory cell adopts a split-gate floating-gate device.

[0046] The split-gate floating gate device includes: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0047] The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a segment of the channel region.

[0048] Each of the floating gates of the first gate structure serves as a storage bit.

[0049] The control gate of each of the first gate structures is connected to the corresponding control gate line.

[0050] Each of the second gate structures is connected to the corresponding word line.

[0051] In the array structure, the word line gates of each memory cell in the same row are all connected to the word lines of the same row.

[0052] The control gates of each memory cell in the same row are connected to the control gate lines in the same row.

[0053] The first source-drain region of the memory cell in the same column is connected to the corresponding bit line in the same column.

[0054] The second source-drain region of the memory cell in the same column is connected to the corresponding bit line in the same column.

[0055] When reading a selected memory cell from the flash memory, the following voltage settings are used:

[0056] The control gate line corresponding to the selected memory bit of the selected memory cell is grounded, and the control gate line corresponding to the non-selected memory bit is connected to the control gate read voltage, and the word line is connected to the word line read voltage.

[0057] Bias methods include:

[0058] During reading, a first voltage is provided to each of the bit lines to which the non-selected memory cell is connected, and the difference between the first voltage and the control gate read voltage is used to reduce read crosstalk of the control gate read voltage to each of the non-selected memory cells located in the same row as the selected memory cell.

[0059] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0060] A further improvement is that the separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions.

[0061] The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

[0062] A further improvement is that each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate.

[0063] The second gate structure is formed by stacking a word line gate dielectric layer and a word line gate.

[0064] A further improvement is that, of the two bit lines connected to the selected memory cell, one is grounded and the other outputs the read current, with the grounded bit line being closer to the selected memory bit than the bit line that outputs the read current.

[0065] A further improvement is that the first voltage is provided by a bias circuit, which includes a plurality of first switches connected to the bit line. The control terminal of the first switch is connected to a control signal, the input terminal of the first switch is connected to a power supply voltage, and the output terminal of the first switch is connected to the bit line. The high level of the control signal is the power supply voltage, and the low level is 0V.

[0066] During reading, the first switch corresponding to each bit line connected to all the non-selected memory cells is turned on, and the output terminal of the first switch outputs the first voltage obtained from the power supply voltage to the connected bit line; the first switch corresponding to the two bit lines connected to the selected memory cell is turned off.

[0067] A further improvement is that the first switch is a PMOS transistor, and the first voltage is equal to the power supply voltage; or, the first switch is an NMOS transistor, and the first voltage is equal to the power supply voltage minus a first threshold voltage, wherein the first threshold voltage is the threshold voltage of the NMOS transistor of the first switch.

[0068] A further improvement is that the control gate read voltage is above 5.4V.

[0069] This invention applies a first voltage to all bit lines connected to non-selected memory cells during reading using a bias circuit. The difference between the first voltage and the control gate read voltage during reading is set to ensure that read crosstalk between the control gate read voltage and non-selected memory cells located in the same row as the selected memory cell is reduced or eliminated. Therefore, this invention can reduce the crosstalk between the higher control gate read voltage during read operations and non-selected memory cells in the same row as the selected memory cell. Attached Figure Description

[0070] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0071] Figure 1 This is a schematic diagram of the circuit structure of an existing flash memory storage cell;

[0072] Figure 2 This is a cross-sectional structural diagram of an existing flash memory storage cell;

[0073] Figure 3 This is a schematic diagram illustrating read crosstalk that occurs during read operations in existing flash memory;

[0074] Figure 4 This is a block diagram of the bias circuit for reducing flash memory read crosstalk according to an embodiment of the present invention;

[0075] Figure 5 This is a circuit diagram of one structure of the bias circuit for reducing flash memory read crosstalk in an embodiment of the present invention;

[0076] Figure 6 This is a circuit diagram of another structure of the bias circuit for reducing flash memory read crosstalk in an embodiment of the present invention. Detailed Implementation

[0077] like Figure 4 The diagram shown is a block diagram of the bias circuit 403 for reducing flash memory read crosstalk according to an embodiment of the present invention; please also refer to the structure of the flash memory storage cell 101. Figure 1 and Figure 2 As shown, in the bias circuit 403 for reducing flash memory read crosstalk in this embodiment of the invention, the array structure of the flash memory is formed by arranging multiple memory cells 101, and each memory cell 101 adopts a discrete gate floating gate device.

[0078] The separated gate floating gate device includes: a first source / drain region 205 and a second source / drain region 206, a plurality of separated first gate structures with floating gates 104 located between the first source / drain region 205 and the second source / drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0079] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0080] The separated gate floating gate device is an N-type device, and both the first source / drain region 205 and the second source / drain region 206 are composed of N+ regions.

[0081] The P-type doped channel region is located between the first source / drain region 205 and the second source / drain region 206 and is covered by each of the first gate structure and the second gate structure 103. The first source / drain region 205 and the second source / drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205 and the second source / drain region 206 or by further doping on the P-type semiconductor substrate 201.

[0082] The second source / drain region 206 of the storage cell 101 is connected to the bit line BL1.

[0083] The first source-drain region 205 of the storage unit 101 is connected to bit line BL0.

[0084] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0085] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0086] Figure 2 In this configuration, the two control gates 105 can be controlled separately and are connected to control gate lines CG0 and CG1 respectively, and the word line gate 106 is connected to the word line WL.

[0087] In the array structure, the word line gates of each of the memory cells 101 in the same row are connected to the word line WL in the same row.

[0088] The control gates of each of the memory cells 101 in the same row are all connected to the control gate lines in the same row.

[0089] The first source-drain region of the memory cell 101 in the same column is connected to the corresponding bit line in the same column.

[0090] The second source-drain region of the memory cell 101 in the same column is connected to the corresponding bit line in the same column.

[0091] The bias circuit 403 provides the first voltage Vinh.

[0092] When reading a selected memory cell 101 of the flash memory, the following voltage setting is used:

[0093] The control gate line corresponding to the selected memory bit of the selected memory cell 101 is grounded, and the control gate line corresponding to the non-selected memory bit is connected to the control gate read voltage VCGR. The word line WL is connected to the word line read voltage VWLR.

[0094] In some embodiments, the control gate readout voltage VCGR is 5.4V or higher.

[0095] The first voltage Vinh is connected to each of the bit lines to which the non-selected memory cell 101 is connected. The difference between the first voltage Vinh and the control gate read voltage VCGR is used to reduce the read crosstalk of the control gate read voltage VCGR to each of the non-selected memory cells 101 located in the same row as the selected memory cell 101.

[0096] Figure 4 In the diagram, the dashed coil 402 corresponds to one of the selected memory cells 101, and all bit lines outside the range of the dashed coil 402 are connected to Vinh. Figure 4 The median line is represented by BL, which is a column line; the word line and the control gate line are both row lines.

[0097] Of the two bit lines connected to the selected memory cell 101, namely the two bit lines within the range of the dashed coil 402, one is grounded (0V); the other outputs the read current, corresponding to a voltage of approximately 0.8V; the grounded bit line is closer to the selected memory bit than the bit line that outputs the read current.

[0098] The bias circuit 403 includes a plurality of first switches connected to the bit line. The control terminal of the first switch is connected to a control signal, the input terminal of the first switch is connected to the power supply voltage Vdd, and the output terminal of the first switch is connected to the bit line. The high level of the control signal is the power supply voltage Vdd, and the low level is 0V.

[0099] During reading, the first switch corresponding to each bit line connected to all the non-selected memory cells 101 is turned on, and the output terminal of the first switch outputs the first voltage Vinh obtained from the power supply voltage Vdd to the connected bit line; the first switch corresponding to the two bit lines connected to the selected memory cell 101 is turned off.

[0100] like Figure 5The diagram shown is a circuit diagram of a bias circuit for reducing flash memory read crosstalk according to an embodiment of the present invention. The bias circuit is marked separately as 403a. In the bias circuit 403a, the first switch is a PMOS transistor 404a, and the first voltage Vinh is equal to the power supply voltage Vdd. The gate of the PMOS transistor 404a is connected to the control signal YC.

[0101] like Figure 6 The diagram shown is a circuit diagram of another structure of the bias circuit for reducing flash memory read crosstalk according to an embodiment of the present invention. The bias circuit is marked separately by 403b. In the bias circuit 403b, the first switch is an NMOS transistor 404b, and the first voltage Vinh is equal to the power supply voltage Vdd minus the first threshold voltage. The first threshold voltage is the threshold voltage of the NMOS transistor of the first switch.

[0102] Figure 5 and Figure 6 The two bias circuits shown are relatively simple and can be implemented directly using the power supply voltage Vdd and the first switch. In other embodiments, the first voltage Vinh can also be other values, as long as it can prevent read crosstalk caused by VCGR.

[0103] In this embodiment of the invention, the bias circuit 403 applies a first voltage Vinh to all bit lines connected to the non-selected memory cell 101 during reading. The difference between the first voltage Vinh and the control gate read voltage VCGR during reading is set to ensure that the read crosstalk between the control gate read voltage VCGR and the non-selected memory cells 101 located in the same row as the selected memory cell 101 is reduced or eliminated. Therefore, this embodiment of the invention can reduce the crosstalk between the higher control gate read voltage VCGR during read operations and the non-selected memory cells 101 in the same row as the selected memory cell 101.

[0104] The bias method for reducing flash memory read crosstalk in this invention embodiment:

[0105] In the method of this embodiment of the invention, please also refer to the structure of the flash memory storage cell 101. Figure 1 and Figure 2 As shown, in the bias circuit 403 for reducing flash memory read crosstalk in this embodiment of the invention, the array structure of the flash memory is formed by arranging multiple memory cells 101, and each memory cell 101 adopts a discrete gate floating gate device.

[0106] The separated gate floating gate device includes: a first source / drain region 205 and a second source / drain region 206, a plurality of separated first gate structures with floating gates 104 located between the first source / drain region 205 and the second source / drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0107] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0108] The separated gate floating gate device is an N-type device, and both the first source / drain region 205 and the second source / drain region 206 are composed of N+ regions.

[0109] The P-type doped channel region is located between the first source / drain region 205 and the second source / drain region 206 and is covered by each of the first gate structure and the second gate structure 103. The first source / drain region 205 and the second source / drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205 and the second source / drain region 206 or by further doping on the P-type semiconductor substrate 201.

[0110] The second source / drain region 206 of the storage cell 101 is connected to the bit line BL1.

[0111] The first source-drain region 205 of the storage unit 101 is connected to bit line BL0.

[0112] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0113] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0114] Figure 2 In this configuration, the two control gates 105 can be controlled separately and are connected to control gate lines CG0 and CG1 respectively, and the word line gate 106 is connected to the word line WL.

[0115] In the array structure, the word line gates of each of the memory cells 101 in the same row are connected to the word line WL in the same row.

[0116] The control gates of each of the memory cells 101 in the same row are all connected to the control gate lines in the same row.

[0117] The first source-drain region of the memory cell 101 in the same column is connected to the corresponding bit line in the same column.

[0118] The second source-drain region of the memory cell 101 in the same column is connected to the corresponding bit line in the same column.

[0119] When reading a selected memory cell 101 of the flash memory, the following voltage setting is used:

[0120] The control gate line corresponding to the selected memory bit of the selected memory cell 101 is grounded, and the control gate line corresponding to the non-selected memory bit is connected to the control gate read voltage VCGR. The word line WL is connected to the word line read voltage VWLR.

[0121] In some embodiments, the control gate readout voltage VCGR is 5.4V or higher.

[0122] Bias methods include:

[0123] During reading, a first voltage Vinh is provided to each of the bit lines to which the non-selected memory cell 101 is connected, and the difference between the first voltage Vinh and the control gate read voltage VCGR is used to reduce read crosstalk of the control gate read voltage VCGR to each of the non-selected memory cells 101 located in the same row as the selected memory cell 101.

[0124] Figure 4 In the diagram, the dashed coil 402 corresponds to one of the selected memory cells 101, and all bit lines outside the range of the dashed coil 402 are connected to Vinh. Figure 4 The median line is represented by BL, which is a column line; the word line and the control gate line are both row lines.

[0125] Of the two bit lines connected to the selected memory cell 101, namely the two bit lines within the range of the dashed coil 402, one is grounded (0V); the other outputs the read current, corresponding to a voltage of approximately 0.8V; the grounded bit line is closer to the selected memory bit than the bit line that outputs the read current.

[0126] The first voltage is provided by a bias circuit 403, which includes a plurality of first switches connected to the bit line. The control terminal of the first switch is connected to a control signal, the input terminal of the first switch is connected to the power supply voltage Vdd, and the output terminal of the first switch is connected to the bit line. The high level of the control signal is the power supply voltage Vdd, and the low level is 0V.

[0127] During reading, the first switch corresponding to each bit line connected to all the non-selected memory cells 101 is turned on, and the output terminal of the first switch outputs the first voltage Vinh obtained from the power supply voltage Vdd to the connected bit line; the first switch corresponding to the two bit lines connected to the selected memory cell 101 is turned off.

[0128] like Figure 5 The diagram shown is a circuit diagram of a bias circuit for reducing flash memory read crosstalk according to an embodiment of the present invention. The bias circuit is marked separately as 403a. In the bias circuit 403a, the first switch is a PMOS transistor 404a, and the first voltage Vinh is equal to the power supply voltage Vdd. The gate of the PMOS transistor 404a is connected to the control signal YC.

[0129] like Figure 6 The diagram shown is a circuit diagram of another structure of the bias circuit for reducing flash memory read crosstalk according to an embodiment of the present invention. The bias circuit is marked separately by 403b. In the bias circuit 403b, the first switch is an NMOS transistor 404b, and the first voltage Vinh is equal to the power supply voltage Vdd minus the first threshold voltage. The first threshold voltage is the threshold voltage of the NMOS transistor of the first switch.

[0130] Figure 5 and Figure 6 The two bias circuits shown are relatively simple and can be implemented directly using the power supply voltage Vdd and the first switch. In other embodiments, the first voltage Vinh can also be other values, as long as it can prevent read crosstalk caused by VCGR.

[0131] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A bias circuit for reducing flash memory read crosstalk, characterized in that, The array structure of flash memory is formed by arranging multiple memory cells, and each memory cell adopts a discrete gate floating gate device; The split-gate floating gate device includes: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a segment of the channel region; Each of the floating gates of the first gate structure serves as a storage bit; The control gate of each of the first gate structures is connected to the corresponding control gate line; Each of the second gate structures is connected to the corresponding word line; In the array structure, the word line gates of each memory cell in the same row are all connected to the word lines of the same row; The control gates of each memory cell in the same row are all connected to the control gate lines in the same row; The first source-drain regions of the memory cells in the same column are connected to the corresponding bit lines in the same column; The second source-drain regions of the memory cells in the same column are connected to the corresponding bit lines in the same column; The bias circuit provides the first voltage; When reading a selected memory cell from the flash memory, the following voltage settings are used: The control gate line corresponding to the selected memory bit of the selected memory cell is grounded, and the control gate line corresponding to the non-selected memory bit is connected to the control gate read voltage, and the word line is connected to the word line read voltage. The first voltage is connected to each of the bit lines to which the non-selected memory cells are connected, and the difference between the first voltage and the control gate read voltage is used to reduce the read crosstalk of the control gate read voltage to each of the non-selected memory cells located in the same row as the selected memory cell.

2. The bias circuit for reducing flash memory read crosstalk as described in claim 1, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

3. The bias circuit for reducing flash memory read crosstalk as described in claim 2, characterized in that: The separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions; The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

4. The bias circuit for reducing flash memory read crosstalk as described in claim 3, characterized in that: Each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate; The second gate structure is formed by stacking a word line gate dielectric layer and a word line gate.

5. The bias circuit for reducing flash memory read crosstalk as described in claim 3, characterized in that: Of the two bit lines connected to the selected memory cell, one is grounded and the other outputs the read current. The grounded bit line is closer to the selected memory bit than the bit line that outputs the read current.

6. The bias circuit for reducing flash memory read crosstalk as described in claim 1, characterized in that: The bias circuit includes a plurality of first switches connected to the bit line. The control terminal of the first switch is connected to a control signal, the input terminal of the first switch is connected to a power supply voltage, and the output terminal of the first switch is connected to the bit line. The high level of the control signal is the power supply voltage, and the low level is 0V. During reading, the first switch corresponding to each bit line connected to all the non-selected memory cells is turned on, and the output terminal of the first switch outputs the first voltage obtained from the power supply voltage to the connected bit line; The first switch corresponding to the two bit lines connected to the selected memory cell is turned off.

7. The bias circuit for reducing flash memory read crosstalk as described in claim 6, characterized in that: The first switch is a PMOS transistor, and the first voltage is equal to the power supply voltage; or, the first switch is an NMOS transistor, and the first voltage is equal to the power supply voltage minus a first threshold voltage, wherein the first threshold voltage is the threshold voltage of the NMOS transistor of the first switch.

8. The bias circuit for reducing flash memory read crosstalk as described in claim 7, characterized in that: The control gate read voltage is above 5.4V.

9. A biasing method for reducing flash memory read crosstalk, characterized in that, The array structure of flash memory is formed by arranging multiple memory cells, and each memory cell adopts a discrete gate floating gate device; The split-gate floating gate device includes: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a segment of the channel region; Each of the floating gates of the first gate structure serves as a storage bit; The control gate of each of the first gate structures is connected to the corresponding control gate line; Each of the second gate structures is connected to the corresponding word line; In the array structure, the word line gates of each memory cell in the same row are all connected to the word lines of the same row; The control gates of each memory cell in the same row are all connected to the control gate lines in the same row; The first source-drain regions of the memory cells in the same column are connected to the corresponding bit lines in the same column; The second source-drain regions of the memory cells in the same column are connected to the corresponding bit lines in the same column; When reading a selected memory cell from the flash memory, the following voltage settings are used: The control gate line corresponding to the selected memory bit of the selected memory cell is grounded, and the control gate line corresponding to the non-selected memory bit is connected to the control gate read voltage, and the word line is connected to the word line read voltage. Bias methods include: During reading, a first voltage is provided to each of the bit lines to which the non-selected memory cell is connected, and the difference between the first voltage and the control gate read voltage is used to reduce read crosstalk of the control gate read voltage to each of the non-selected memory cells located in the same row as the selected memory cell.

10. The biasing method for reducing flash memory read crosstalk as described in claim 9, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

11. The biasing method for reducing flash memory read crosstalk as described in claim 10, characterized in that: The separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions; The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

12. The biasing method for reducing flash memory read crosstalk as described in claim 11, characterized in that: Each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate; The second gate structure is formed by stacking a word line gate dielectric layer and a word line gate.

13. The biasing method for reducing flash memory read crosstalk as described in claim 11, characterized in that: Of the two bit lines connected to the selected memory cell, one is grounded and the other outputs the read current. The grounded bit line is closer to the selected memory bit than the bit line that outputs the read current.

14. The biasing method for reducing flash memory read crosstalk as described in claim 9, characterized in that: The first voltage is provided by a bias circuit, which includes a plurality of first switches connected to the bit line. The control terminal of the first switch is connected to a control signal, the input terminal of the first switch is connected to a power supply voltage, and the output terminal of the first switch is connected to the bit line. The high level of the control signal is the power supply voltage, and the low level is 0V. During reading, the first switch corresponding to each bit line connected to all the non-selected memory cells is turned on, and the output terminal of the first switch outputs the first voltage obtained from the power supply voltage to the connected bit line; The first switch corresponding to the two bit lines connected to the selected memory cell is turned off.

15. The biasing method for reducing flash memory read crosstalk as described in claim 14, characterized in that: The first switch is a PMOS transistor, and the first voltage is equal to the power supply voltage; or, the first switch is an NMOS transistor, and the first voltage is equal to the power supply voltage minus a first threshold voltage, wherein the first threshold voltage is the threshold voltage of the NMOS transistor of the first switch.

16. The biasing method for reducing flash memory read crosstalk as described in claim 15, characterized in that: The control gate read voltage is above 5.4V.

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