Method for manufacturing top layer metal double damascene structure

Abstract

The application provides a manufacturing method of a top-layer metal double damascene structure, which comprises the following steps: providing a semiconductor structure with discrete metal structures embedded on the surface, and sequentially forming an etching stop layer, a first dielectric layer, a barrier layer and a second dielectric layer on the semiconductor structure; etching the second dielectric layer and the barrier layer by using a first etching process to form first grooves in the second dielectric layer and the barrier layer, and each first groove at least partially overlaps with a vertical projection of a metal structure on a vertical projection of the semiconductor structure; etching away the first dielectric layer and a partial thickness of the etching stop layer in the first grooves by using a second etching process to form second grooves; and etching the etching stop layer in the second grooves by using a third etching process until the metal structures are exposed. The manufacturing method reduces and optimizes the manufacturing process of semiconductor components by using two partial first through holes and a top-layer metal sandwich layer, thereby reducing the manufacturing cost of the semiconductor components.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices and manufacturing, and more specifically, to a method for fabricating a top-layer metal double damask structure. Background Technology

[0002] As transistor sizes continue to shrink, the number of transistors in integrated circuits continues to rise. The signal integration of a large number of transistors requires increasingly dense metal interconnect layers for connection. The resulting resistance and parasitic capacitance of these metal interconnects have severely hampered the rapid development of integrated circuits. Traditional metal interconnects are made of aluminum. To overcome the resistance and parasitic capacitance of metal interconnects, i.e., to reduce the RC delay of back-end of line (BEOL) interconnects, the semiconductor industry has evolved from aluminum interconnect technology to copper interconnect technology. Since copper wires cannot be formed using the subtractive etching process of traditional aluminum wires, the copper double damask process was developed.

[0003] Currently, copper double damascene etching is widely used in 90nm and below processes. The double damascene process typically involves first etching vias, then etching open holes, filling the vias and open holes with copper, and finally planarizing the copper to form a double damascene structure between every two dielectric layers. For the top metal, the aspect ratio (AR) of the full via-first (FVF) process is generally around 4.5. The BARC ET-Back process in the double damascene process increases the overall fabrication difficulty and cost. For RF devices that require inductors, the thickness of the top metal layer increases from 9,000 angstroms to 30,000 angstroms, and the aspect ratio increases from 4.5 to about 10. This increases the difficulty of using a full via-first etching process, and the increase in depth carries the risk of etching stop. Using a partial via-first (PVF) process can reduce the process difficulty, but the dielectric layer does not have an etching stop layer. Partial via-first is not easy to control and will produce holes of different depths due to load effects.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To address the problems in the prior art, the present invention aims to provide a method for fabricating a top-layer metal double damask structure. This method reduces and optimizes the manufacturing process of semiconductor devices by combining two partial through-holes with a top-layer metal sandwich layer, thereby lowering the manufacturing cost of semiconductor devices.

[0006] Some examples of the present invention provide a method for fabricating a top-layer metal double damask structure, comprising the following steps:

[0007] S10: Provide a semiconductor structure with discrete metal structures embedded on its surface, wherein an etch stop layer, a first dielectric layer, a barrier layer and a second dielectric layer are sequentially formed on the semiconductor structure;

[0008] S20: The second dielectric layer and the barrier layer are etched using a first etching process, and a first trench is formed in the second dielectric layer and the barrier layer, wherein the vertical projection of each first trench in the semiconductor structure at least partially coincides with the vertical projection of the metal structure in the semiconductor structure;

[0009] S30: The first dielectric layer and part of the etch stop layer in the first trench are etched away using a second etching process to form a second trench;

[0010] S40: The third etching process is used to etch the etch stop layer in the second trench until the metal structure is exposed to form a through hole.

[0011] According to some examples of the present invention, the thickness of the first dielectric layer is between 400 nm and 1000 nm; and / or

[0012] The thickness of the second dielectric layer is between 400 nm and 1000 nm.

[0013] According to some examples of the present invention, when the total thickness of the first dielectric layer, the barrier layer, and the second dielectric layer is less than or equal to 900 nm, the thickness of the barrier layer is between 50 nm and 80 nm.

[0014] When the total thickness of the first dielectric layer, the barrier layer and the second dielectric layer is greater than or equal to 3300 nm, the thickness of the barrier layer is greater than or equal to 200 nm.

[0015] According to some examples of the present invention, both the first dielectric layer and the second dielectric layer are low dielectric constant material layers.

[0016] According to some examples of the present invention, the barrier layer is a SiN layer; and / or

[0017] The etch stop layer is one or more of SiON, SiCN and SiN layers.

[0018] According to some examples of the invention, the metal structure is copper.

[0019] According to some examples of the present invention, an adhesion layer is provided between the metal structure and the semiconductor structure, the adhesion layer being TaN / Ta.

[0020] According to some examples of the present invention, the first etching process, the second etching process and the third etching process are physical etching processes.

[0021] According to some examples of the present invention, after step S30, the width of the first trench is greater than the width of the second trench.

[0022] According to some examples of the present invention, the manufacturing method further includes:

[0023] S50: Fill the through hole with metal material to form an intermediate metal wire connected to the metal structure.

[0024] The method for fabricating the top metal double damask structure of the present invention reduces and optimizes the manufacturing process of semiconductor devices by combining two partial through-holes with the top metal sandwich layer. At the same time, the method eliminates the need for the Barc ET-Back process, thereby reducing the manufacturing cost of semiconductor devices. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without inventive effort. Furthermore, the drawings are merely illustrative diagrams of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0026] Figure 1 A flowchart illustrating a method for fabricating a top-layer metal double damask structure according to an embodiment of the present invention; and

[0027] Figures 2 to 8 This is a schematic diagram of the semiconductor structure corresponding to each step of the fabrication method of the top-layer metal double damask structure according to an embodiment of the present invention.

[0028] Figure Labels

[0029] 10 Semiconductor Structure

[0030] 101 Metal Structure

[0031] 102 Adhesion Layer

[0032] 20 Etching Stop Layer

[0033] 30 First dielectric layer

[0034] 40 barrier layers

[0035] 50 Second dielectric layer

[0036] 6a First photoresist layer

[0037] 6b Second photoresist layer

[0038] A First Trench

[0039] B Second trench

[0040] C Through Hole Detailed Implementation

[0041] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0042] In this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this specification. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples represented in this specification, as well as the features of different embodiments or examples.

[0043] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Terms indicating relative space, such as "front," "back," "up," and "down," are used to more easily explain the relationship of one device relative to another illustrated in the figures. These terms refer not only to their meaning in the figures but also to other meanings or operations of the device in use. For example, if the device in the figures is flipped, a device previously described as "below" another device may now be described as "above" another device. Therefore, the exemplary term "down" includes both "up" and "below." The device may be rotated 90° or other angles, and the terms representing relative space are interpreted accordingly.

[0044] Although the terms first, second, etc., are used herein to refer to various elements in some instances, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first dielectric layer and second dielectric layer, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, component, item, type, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups. The terms “or” and “and / or” as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0045] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this specification pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with relevant technical literature and the content of this present instruction, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0046] This invention provides a method for fabricating a top-layer metal double damask structure, comprising the following steps: S10: providing a semiconductor structure with discrete metal structures embedded on its surface, wherein an etch stop layer, a first dielectric layer, a barrier layer, and a second dielectric layer are sequentially formed on the semiconductor structure; S20: etching the second dielectric layer and the barrier layer using a first etching process, and forming a first trench in the second dielectric layer and the barrier layer, wherein the vertical projection of each first trench in the semiconductor structure at least partially overlaps with the vertical projection of the metal structure in the semiconductor structure; S30: etching away the first dielectric layer and a portion of the etch stop layer within the first trench using a second etching process, and forming a second trench; S40: etching the etch stop layer within the second trench using a third etching process until the metal structure is exposed, forming a via. The method for fabricating a top-layer metal double damask structure of this invention reduces and optimizes the manufacturing process of semiconductor devices by combining two partial vias with a top-layer metal sandwich layer. Simultaneously, this method eliminates the need for a Barc ET-Back process, reducing the manufacturing cost of semiconductor devices.

[0047] The following describes the various steps of the method for manufacturing the top-layer metal double damask structure of the present invention in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the scope of protection of the present invention.

[0048] Figure 1 This is a flowchart illustrating a method for fabricating a top-layer metal double damask structure according to an embodiment of the present invention. Specifically, the fabrication method includes the following steps:

[0049] S10: Provide a semiconductor structure 10 with discrete metal structures 101 embedded on its surface, wherein an etch stop layer 20, a first dielectric layer 30, a barrier layer 40 and a second dielectric layer 50 are sequentially stacked on the semiconductor structure 10.

[0050] The structure obtained in step S10 is as follows: Figure 2 As shown, the semiconductor structure 10 can be any suitable semiconductor substrate, such as a silicon substrate, a germanium silicon substrate, or a silicon carbide substrate. The etch stop layer 20 is a nitrogen-doped silicide layer, such as one or more layers of SiON, SiCN (Nitride Doped Silicon Carbide, NDC), and SiN. The barrier layer 40 can be a SiN layer, and the first dielectric layer 30 and the second dielectric layer 50 on the upper and lower surfaces of the barrier layer 40 can be made of the same material, such as a low-dielectric-constant doped silicon dioxide layer, such as a fluorine-doped silicon dioxide layer (SiOF) or a carbon-doped silicon dioxide layer (SiOC). That is, an OX / SiN / OX sandwich structure is formed above the semiconductor structure 10. It can be seen that the first dielectric layer 30 and the second dielectric layer 50 preferably use low-k dielectric material layers (low-κ material layers). Here, low-κ refers to a dielectric constant below 3.8. Compared to a silicon dioxide layer, using low-κ material layers of the same thickness for the first dielectric layer 30 and the second dielectric layer 50 can reduce parasitic capacitance between conductive layers, thereby achieving lower heat dissipation and improving the power of the semiconductor device. The low-k dielectric first dielectric layer 30 and the second dielectric layer 50 can be prepared using chemical vapor deposition.

[0051] In obtaining Figure 2 After the structure is formed, step S20 is performed: the second dielectric layer 50 and the barrier layer 40 are etched using a first etching process, and a first trench A is formed in the second dielectric layer 50 and the barrier layer 40. The vertical projection of each first trench A onto the plane where the semiconductor structure 10 is located at least partially coincides with the vertical projection of the metal structure 101 onto the plane where the semiconductor structure 10 is located.

[0052] More specifically, a first trench A is obtained at a corresponding position above the metal structure 101. This can be achieved using photolithography. A first photoresist layer 6a of a certain thickness is spin-coated onto the semiconductor structure obtained in step S10. A photomask is designed, and after development and exposure, a patterned first photoresist layer 6a is obtained, such as... Figure 3 As shown, the linewidth of the second dielectric layer exposed by the first photoresist layer 6a is the width of the first trench A obtained subsequently. Then, the structure of the patterned first photoresist layer is etched using a first etching process. To improve the accuracy of the first trench A obtained after the first etching process, i.e., to keep the linewidth of the first trench A as small as possible, the first etching process can be a physical etching process, or an anisotropic etching process. The etching of the second dielectric layer 50 (silicon oxide) and the barrier layer 40 (silicon nitride) can both be performed using reactive plasma etching (RIE). Physical etching involves plasma with high energy and low gas density, using the physical bombardment of charged ions on the etched surface to promote etching of the thin film. In other words, etching mainly occurs in the direction perpendicular to the surface of the etched thin film, also known as anisotropic plasma etching. The sidewalls of the etched holes are nearly vertical or have a slope of less than 90°.

[0053] During the etching process in step S20, a structure with a patterned first photoresist layer 6a is placed into the plasma reaction chamber. Reactive gases are then introduced, and simultaneously, radio frequency power generated by an RF power supply is fed between the upper and lower electrodes of the plasma reaction chamber to ionize the reactive gases and generate plasma. Commonly used reactive gases include mixtures of SF6, CF4, O2, and / or Ar.

[0054] Since in step S20 of the fabrication method of the present invention, the first etching process requires sequential etching of the second dielectric layer 50 (silicon oxide) and the barrier layer 40 (silicon nitride), the reaction gas used when etching the second dielectric layer 50 can be C. x F y A mixture of O2 and Ar gas; the reaction gas used when etching the barrier layer 40 can be C. x H y F zA mixture of N2 and Ar gas is used, where the values ​​of x, y, and z are determined based on the actual thicknesses of the second dielectric layer 50 and the barrier layer 40 to be etched, as well as the linewidth of the first trench A. During the etching process, fluoride ions in the reaction gas and silicon atoms in the second dielectric layer 50 / barrier layer 40 form SiF4 gas, which is then extracted from the reaction chamber by a vacuum pump. It should be noted that the carbon-containing polymer components generated during the etching process deposit on the sidewalls of the first trench A to form a protective layer, preventing it from being etched horizontally. The polymer layer at the bottom of the first trench A is removed by bombardment with vertically incident charged ions, especially Ar. The etching continues downwards, ultimately forming a vertically oriented first trench A, as shown in [reference needed]. Figure 4 As shown. After removing and washing away the first photoresist layer 6a from the reaction chamber, the desired result can be obtained. Figure 5 The structure.

[0055] The etching process in step S20 can be considered a first partial via etching process. Unlike existing dual damascene etching processes, where the trenches obtained in the first etching process typically remain at the barrier layer, the first partial via etching process of this invention remains at the first dielectric layer, i.e., the barrier layer is completely etched. The thickness of both the first dielectric layer 30 and the second dielectric layer 50 can be between 400 nm and 1000 nm. The total thickness of the first dielectric layer 30, the barrier layer 40, and the second dielectric layer 50 can be determined according to the desired thickness of the top layer metal. Preferably, when the total thickness of the first dielectric layer, the barrier layer, and the second dielectric layer is less than or equal to 900 nm, the thickness of the barrier layer 40 is between 50 nm and 80 nm; when the total thickness of the first dielectric layer, the barrier layer, and the second dielectric layer is greater than or equal to 3300 nm, the thickness of the barrier layer 40 is greater than or equal to 200 nm. The risk of over-etching of vias can be reduced or the process window can be expanded by adjusting the thickness of the barrier layer.

[0056] In obtaining Figure 5 After structuring, step S30 is performed: the first dielectric layer 30 and a portion of the etch stop layer 20 within the first trench A are etched using a second etching process to form the second trench B; similar to step S20, a second photoresist layer 6b of a certain thickness is spin-coated onto the semiconductor structure obtained in step S20, a photomask is designed, and after development and exposure, a patterned second photoresist layer 6b is obtained, see... Figure 6In this process, the linewidth of the second dielectric layer exposed by the second photoresist layer 6b is greater than the width of the first trench A. The second etching process can also be a physical etching process, such as plasma etching, but the reaction gas used can be determined based on the thickness of the first dielectric layer 30 and the thickness of the etch stop layer to be etched. After step S30, the width of the first trench A at the second dielectric layer 50 and the barrier layer 40 increases, forming a second trench B at the first dielectric layer 30 and the etch stop layer 20. The structure obtained after removing the second photoresist layer 6b from the reaction chamber and washing it off is shown in [Figure 1]. Figure 7 .

[0057] After step S30, step S40 is performed: the etch stop layer 20 is etched in the second trench B using a third etching process until the metal structure 101 is exposed. Step S40 can be performed by linear removal (LRM) to open the connection between the second trench B and the lower metal structure 101, forming a via C penetrating the second dielectric layer to the metal structure 101. The third etching process should only etch away the etch stop layer 20, i.e., etch the nitrogen-doped silicide layer. The second etching process uses a physical etching process, selecting a reactive gas to make the etching rate of the nitrogen-doped silicide layer greater than the etching rate of the first dielectric layer 30, the barrier layer 40, and the second dielectric layer 50. In some embodiments, the metal structure 101 can be copper. An adhesion layer 102 is provided between the metal structure 101 and the semiconductor structure 10. The adhesion layer 102 can be a TaN / Ta material. The adhesion layer 102 can prevent the diffusion of copper in the semiconductor structure 10. The structure obtained after step S40 is as follows. Figure 8 As shown.

[0058] In some other embodiments, the fabrication method further includes step S50: filling the through-hole C with metal material to form an intermediate metal wire connected to the metal structure 101. The fabrication method of the top-layer metal double damask structure of the present invention reduces and optimizes the manufacturing process of semiconductor devices by combining two partial through-holes with a top-layer metal sandwich layer.

[0059] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention and should not be construed as limiting the specific implementation of the invention to these descriptions. It will be apparent to those skilled in the art that this application is not limited to the details of the above exemplary embodiments, and that the application can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for manufacturing a top-layer metal double damask structure, characterized in that, Includes the following steps: S10: A semiconductor structure with discrete metal structures embedded on its surface is provided. An etch stop layer, a first dielectric layer, a barrier layer, and a second dielectric layer are sequentially formed on the semiconductor structure. The etch stop layer is a multilayer of SiON, SiCN, and SiN layers. When the total thickness of the first dielectric layer, the barrier layer, and the second dielectric layer is less than or equal to 900 nm, the thickness of the barrier layer is between 50 nm and 80 nm. When the total thickness of the first dielectric layer, the barrier layer, and the second dielectric layer is greater than or equal to 3300 nm, the thickness of the barrier layer is greater than or equal to 200 nm. S20: The second dielectric layer and the barrier layer are etched using a first etching process, and a first trench is formed in the second dielectric layer and the barrier layer, wherein the vertical projection of each first trench in the semiconductor structure at least partially coincides with the vertical projection of the metal structure in the semiconductor structure; S30: The first dielectric layer and part of the etch stop layer in the first trench are etched away using a second etching process. The linewidth of the second dielectric layer exposed by the photoresist layer in the second etching process is greater than the width of the first trench. The width of the first trench at the second dielectric layer and the barrier layer increases to form a second trench. After step S30, the width of the first trench is greater than the width of the second trench. S40: The third etching process is used to etch the etch stop layer in the second trench until the metal structure is exposed to form a through hole; The first etching process, the second etching process, and the third etching process are physical etching processes.

2. The method for manufacturing the top-layer metal double damask structure according to claim 1, characterized in that, The thickness of the first dielectric layer is between 400 nm and 1000 nm; and / or The thickness of the second dielectric layer is between 400 nm and 1000 nm.

3. The method for manufacturing the top-layer metal double damask structure according to claim 1, characterized in that, Both the first dielectric layer and the second dielectric layer are low dielectric constant material layers.

4. The method for manufacturing the double damask structure according to claim 1, characterized in that, The barrier layer is a SiN layer.

5. The method for manufacturing the double damask structure according to claim 1, characterized in that, The metal structure is made of copper.

6. The method for manufacturing a double damask structure according to claim 5, characterized in that, An adhesion layer, which is TaN / Ta, is disposed between the metal structure and the semiconductor structure.

7. The method for manufacturing the top-layer metal double damask structure according to claim 1, characterized in that, The manufacturing method further includes: S50: Fill the through hole with metal material to form an intermediate metal wire connected to the metal structure.

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