Method for manufacturing a chip assembly

Abstract

The application discloses a manufacturing method of a chip assembly, comprising the following steps: providing a semiconductor wafer, the semiconductor wafer comprising a plurality of semiconductor device units; etching the semiconductor wafer in a cutting path region between two adjacent semiconductor device units to form a first groove; temporarily bonding the semiconductor wafer with a carrier substrate; thinning the semiconductor wafer; making a photoresist layer on one side of the semiconductor wafer to expose the semiconductor wafer; making a metal layer to cover the remaining photoresist layer and the surface of the semiconductor wafer; stripping the remaining photoresist layer to obtain a metal structure corresponding to each semiconductor device unit; etching the semiconductor wafer to form a second groove in communication with the first groove; and debonding the carrier substrate to obtain a plurality of separated chip assemblies. The method realizes reduction of the width of the cutting path region, increase of the number of chip assemblies on a single wafer, and metallization of the back surface of the thinned wafer.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing technology, and in particular to a method for manufacturing chip components. Background Technology

[0002] Narrowing the width of the chip dicing channel is one of the effective ways to reduce chip size, especially for small chips. For example, narrowing the dicing channel of a small chip with a dicing channel width of 50um and a size of 0.25*0.25mm to 10um will increase the number of chips on a single wafer by 25%, which can effectively reduce the wafer manufacturing process cost of a single chip.

[0003] The dicing channel is the physical space reserved for separating individual chips from a wafer. Dividing wafers using a cutting tool is currently the process used for large-scale mass production in the semiconductor industry. Because the cutting tool has a certain thickness and the cutting process causes some physical damage to the surrounding area, the dicing channel width generally cannot be too small. A 50µm dicing channel width is currently the narrowest width that can be used in the industry while ensuring the cutting quality. However, the dicing channel area occupies the surface area of ​​the wafer, reducing the number of chip components that can be cut from the wafer. Summary of the Invention

[0004] The embodiments of the present invention provide a method for manufacturing chip components, which can achieve metallization on the back side of a semiconductor wafer while using an etching process to separate the chip components, reduce the area occupied by the dicing channels on the semiconductor wafer, and increase the number of chip components that can be removed from a unit semiconductor wafer.

[0005] To address the aforementioned technical problems, embodiments of the present invention disclose the following technical solutions:

[0006] On the one hand, a method for manufacturing a chip component is provided, including:

[0007] A semiconductor wafer is provided, the semiconductor wafer comprising a plurality of semiconductor device units, wherein the semiconductor wafer is etched in a cleavage region between two adjacent semiconductor device units to form a first groove;

[0008] The side of the semiconductor wafer with the first groove is temporarily bonded to the carrier substrate;

[0009] The semiconductor wafer body is thinned on the side of the semiconductor wafer away from the carrier substrate;

[0010] A photoresist layer is formed on the side of the semiconductor wafer away from the substrate, and the photoresist layer is opened to expose the surface of the semiconductor wafer; wherein, in the thickness direction of the semiconductor wafer, the remaining photoresist layer overlaps with the projection of the first groove on the semiconductor wafer.

[0011] A metal layer is fabricated, which covers the remaining photoresist layer and the surface of the semiconductor wafer;

[0012] The remaining photoresist layer is removed to retain the metal layer covering the surface of the semiconductor wafer, thereby obtaining the metal structure corresponding to each semiconductor device unit;

[0013] The semiconductor wafer is etched on one side of the semiconductor wafer having the metal structure to form a second groove, and the second groove is connected to the first groove;

[0014] The carrier substrate is debonded to obtain multiple separate chip components.

[0015] In addition to one or more of the features disclosed above, or as an alternative, the first groove has a first width w1 and the second groove has a second width w2, satisfying: 2μm≤w1≤20μm, 6μm≤w2≤50μm, and w2≥w1.

[0016] In addition to one or more of the features disclosed above, or as an alternative, the first depth d1 of the first groove satisfies 5μm≤d1≤50μm, 10≤d1 / w1≤30; the second depth d2 of the second groove satisfies 50μm≤d2≤200μm, 10≤d2 / w2≤30.

[0017] In addition to one or more of the features disclosed above, or as an alternative, a portion of the semiconductor device unit extends into the semiconductor wafer, and the third thickness t3 of the portion of the semiconductor device unit satisfies: d1 > t3.

[0018] In addition to one or more of the features disclosed above, or as an alternative, the second thickness t2 of the semiconductor wafer after the step of thinning the body of the semiconductor wafer satisfies: 50μm≤t2≤200μm.

[0019] In addition to one or more of the features disclosed above, or as an alternative, after the metal layer is fabricated, a protective layer is fabricated on the side of the metal layer away from the semiconductor wafer, the protective layer covering the metal layer; the remaining photoresist layer is removed and the protective layer covering the remaining photoresist layer is removed.

[0020] In addition to one or more of the features disclosed above, or as an alternative, the protective layer may be made of at least one of silicon dioxide or silicon nitride.

[0021] In addition to one or more of the features disclosed above, or as an alternative, the method of temporarily bonding the side of the semiconductor wafer having the first groove to the carrier substrate includes: temporarily bonding the side of the semiconductor wafer having the first groove to the carrier substrate through a temporary bonding film.

[0022] Both sides of the temporary bonding film are adhesive. One side of the temporary bonding film is attached to the semiconductor wafer and the semiconductor device unit, and the other side is attached to the carrier substrate.

[0023] In addition to one or more of the features disclosed above, or as an alternative, the temporary bonding film includes a photosensitive material that is removed by light irradiation.

[0024] In addition to one or more of the features disclosed above, or as an alternative, the carrier substrate comprises a glass substrate.

[0025] In addition to one or more of the features disclosed above, or as an alternative, it also includes:

[0026] After the step of debonding the carrier substrate, a support film is attached to the side of the metal layer away from the semiconductor wafer.

[0027] In addition to one or more of the features disclosed above, or as an alternative, the support film is a UV film, and the material of the support film includes at least one of PVC, PET or PP.

[0028] In addition to one or more of the features disclosed above, or as an alternative, the method of etching the semiconductor wafer in the cleavage region between two adjacent semiconductor device units includes: etching the semiconductor wafer in the cleavage region between two adjacent semiconductor device units using deep reactive ion etching.

[0029] The method for etching the semiconductor wafer on the side of the semiconductor wafer having the metal structure includes: etching the semiconductor wafer on the side of the semiconductor wafer having the metal structure using deep reactive ion etching.

[0030] In addition to one or more of the features disclosed above, or as an alternative, the material of the metal layer includes at least one of Ti, Cr, TiW, Ni, Ag, Al, Cu or Au;

[0031] When the metal layer is made of multiple materials, the structure of the metal layer is a multi-layered structure of multiple materials.

[0032] In addition to one or more of the features disclosed above, or alternatively, along the thickness direction of the semiconductor wafer, the cross-section of the remaining photoresist layer has a first end and a second end opposite to each other, the first end being located on the side of the second end away from the semiconductor wafer, and the width of the first end being greater than the width of the second end.

[0033] One of the above technical solutions has the following advantages or beneficial effects: On the one hand, this application achieves metallization of the back side of the semiconductor wafer while simultaneously using etching to separate chip components. Compared to traditional tool cutting, this application can simultaneously etch all areas that need etching, reducing process difficulty and production costs. It avoids the problems of complex cutting paths and excessively long cutting tracks in traditional tool cutting, which lead to high process difficulty and high production costs. While avoiding the above problems, this application can set more semiconductor device units on a single semiconductor wafer to separate more chip components. On the other hand, this application uses a method of etching a first groove and a second groove on both sides of the semiconductor wafer and connecting the first groove and the second groove to separate chip components. Because the depth and width of the etching trench formed by the etching process are positively correlated, it avoids the limitation that a single etching trench needs a larger area on the side of the semiconductor wafer with semiconductor device units. A first groove with a smaller size than a single etching trench can be set on the side of the semiconductor wafer with semiconductor device units, so as to further arrange more semiconductor device units on a single semiconductor wafer. Attached Figure Description

[0034] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0035] Figure 1 This is a flowchart of a method for manufacturing a chip assembly according to an embodiment of the present invention;

[0036] Figures 2-11 This is a schematic diagram of the manufacturing process of the chip component manufacturing method provided in Embodiment 1 of the present invention;

[0037] Figures 12-23 This is a schematic diagram of the manufacturing process of the chip component manufacturing method provided in Embodiment 2 of the present invention;

[0038] In the figure: 100-semiconductor wafer; 110-semiconductor device unit; 120-dicing area; 130-first groove; 200-carrying substrate; 210-temporary bonding film; 140-metal layer; 150-target area; 160-second groove; 170-protective layer; 300-photoresist layer; 400-support film; 10-chip assembly; 11-device structure; 12-substrate structure; 13-metal structure. Detailed Implementation

[0039] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described in this specification are merely for explaining the invention and are not intended to limit the invention.

[0040] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0042] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0043] See Figure 1 , Figure 1 A method for manufacturing a chip assembly according to an embodiment of the present invention is illustrated. The method for manufacturing a chip assembly according to an embodiment of the present application includes:

[0044] S10, a semiconductor wafer is provided, the semiconductor wafer including a plurality of semiconductor device units, and the semiconductor wafer is etched in a dicing region between two adjacent semiconductor device units to form a first groove;

[0045] S20, temporarily bond the side of the semiconductor wafer with the first groove to the carrier substrate;

[0046] S30, the body of the semiconductor wafer is thinned on the side of the semiconductor wafer away from the carrier substrate;

[0047] S40, a photoresist layer is formed on the side of the semiconductor wafer away from the carrier substrate, and an opening is made in the photoresist layer to expose the surface of the semiconductor wafer; wherein, in the thickness direction of the semiconductor wafer, the remaining photoresist layer overlaps with the projection of the first groove on the semiconductor wafer.

[0048] S50, Fabricate a metal layer that covers the remaining photoresist layer and the surface of the semiconductor wafer;

[0049] S60, the remaining photoresist layer is peeled off to retain the metal layer covering the surface of the semiconductor wafer, thereby obtaining the metal structure corresponding to each semiconductor device unit;

[0050] S70, the semiconductor wafer is etched on one side of the semiconductor wafer having the metal structure to form a second groove, and the second groove is connected to the first groove;

[0051] S80, the carrier substrate is debonded to obtain multiple separate chip components.

[0052] Steps S10 to S80 will be described in detail below.

[0053] In step S10, a semiconductor wafer is provided, the semiconductor wafer being made of silicon. The semiconductor wafer has a first surface and a second surface opposite each other along its thickness direction. A plurality of semiconductor device units are arranged in an array on the first surface of the semiconductor wafer, and the area between adjacent semiconductor device units is a etchable groove. Transistors and circuit structures are disposed inside each semiconductor device unit. In this embodiment, the semiconductor device units are partially embedded in the semiconductor wafer; in other embodiments, the semiconductor device units may also be located on the first surface of the semiconductor wafer.

[0054] The semiconductor wafer is etched in the dicing area to form a first groove. When the semiconductor device unit is partially embedded in the semiconductor wafer, the depth of the first groove is greater than the depth to which the semiconductor device unit is embedded in the semiconductor wafer.

[0055] Methods for etching the first groove on a semiconductor wafer include Deep Reactive Ion Etching (DRIE). DRIE can etch grooves with widths ranging from a few micrometers to hundreds of micrometers in depth onto a first substrate, enabling the "cutting" of the first substrate and the separation of chip components. It is an ideal alternative to traditional tool cutting, especially when processing small-sized chips, offering significant cost advantages. This is due to a significant increase in the number of chip components per unit area on the first substrate and a substantial reduction in cutting production costs. Specifically, the smaller the chip components, the more etchable tracks are required on the first substrate, resulting in longer processing times and higher costs for traditional tool cutting. DRIE, however, simultaneously etches all areas of the entire first substrate regardless of the layout or length of the etchable areas, thus the process cost does not increase with the complexity or length of the etchable areas.

[0056] In step S20, the first surface of the semiconductor wafer is temporarily bonded to a carrier substrate, which is made of glass substrate material. In this embodiment, the carrier substrate is temporarily bonded to the semiconductor wafer via a temporary bonding film, which is a UV film with adhesive on both sides. In other embodiments, the carrier substrate is temporarily bonded to the semiconductor wafer via adhesive. Because the semiconductor wafer needs to be thinned in the subsequent step S30, the thinned semiconductor wafer has low structural strength, making it difficult to directly perform photolithography, lift-off, or etching processes on the semiconductor wafer. Therefore, this application uses a carrier substrate to temporarily bond to the semiconductor wafer to strengthen the overall structure, avoid damage caused by low structural strength in subsequent processes, and improve the yield of this application.

[0057] In step S30, the semiconductor wafer is thinned in its thickness direction from the second surface of the semiconductor wafer. The initial thickness of the semiconductor wafer is usually not the target thickness required for the final product chip assembly. If the initial thickness of the semiconductor wafer is too large, the distance between the metal layer made on the second surface of the semiconductor wafer and the semiconductor device unit on the first surface will be too large, which will lead to difficulties in subsequent processing of the chip assembly. Therefore, it is necessary to thin the semiconductor wafer.

[0058] In step S40, a photoresist layer covering the second surface of the semiconductor wafer is formed, and an opening is made in the photoresist layer to expose a portion of the semiconductor wafer surface. In the thickness direction of the semiconductor wafer, the partial semiconductor wafer surface and the orthographic projection of the semiconductor device unit on the second surface overlap, and the remaining photoresist layer and the orthographic projection of the first groove on the second surface overlap. In this embodiment, the method for opening the photoresist layer includes a photolithography process.

[0059] In step S50, a metal layer is formed on the side of the semiconductor wafer facing the second surface by depositing metal. The metal layer covers the exposed portion of the semiconductor wafer surface and the side of the remaining photoresist layer away from the semiconductor wafer. In this embodiment, the cross-section of the remaining photoresist layer is an inverted trapezoid, preventing the deposition of metal on the sidewalls of the remaining photoresist layer. Furthermore, because the photoresist layer has a certain thickness, the metal layer deposited on the semiconductor wafer surface is not connected to the metal layer deposited on the photoresist surface.

[0060] In step S60, the remaining photoresist layer is peeled off, and the metal layer on the photoresist layer is also peeled off along with the remaining photoresist layer. The metal layer on the surface of the semiconductor wafer is retained, thereby obtaining the metal structure corresponding to each semiconductor device unit. The semiconductor wafer exposed by peeling off the remaining photoresist layer forms the target region, and the width of the target region is greater than the width of the first groove.

[0061] In step S70, the semiconductor wafer is etched through the target area to form a second groove. The etching direction extends along the thickness direction of the semiconductor wafer until the second groove connects with the first groove, thereby separating the semiconductor device units and obtaining a substrate structure corresponding to each semiconductor device unit. The width and cross-sectional depth of the second groove are both greater than those of the first groove. The method for etching the semiconductor wafer to form the second groove includes deep reactive ion etching (DRIE).

[0062] The width and depth of the etching trenches formed by etching processes on semiconductor wafers are positively correlated. Therefore, this application employs etching a first trench with a small width and depth on the first surface of the semiconductor wafer where semiconductor device units are located. This reduces the area occupied by the first trench on the semiconductor wafer while increasing the number of semiconductor device units that can be arranged per unit semiconductor wafer. A second trench is etched on the second surface of the semiconductor wafer. The width and depth of the second trench are both greater than the width and depth of the first trench, and the depth of the first trench is greater than the depth to which the semiconductor device unit is embedded in the semiconductor wafer. This prevents the etching depth of the second trench from reaching the position where the semiconductor device unit is embedded in the semiconductor wafer, thus avoiding damage to the semiconductor device unit caused by the etching of the second trench.

[0063] In step S80, the carrier substrate is debonded to the semiconductor wafer, and the temporary bonding film or adhesive used for temporary bonding is removed to obtain several separate chip components.

[0064] Example 1

[0065] The following will combine Figures 2-11 The first embodiment of the present invention will be described in detail.

[0066] Reference Figure 2 As shown, a semiconductor wafer 100 is provided, the semiconductor wafer 100 being made of silicon. The semiconductor wafer 100 has opposing first and second surfaces, wherein the first surface is on the upper side of the figure, and the second surface is on the lower side of the figure. A plurality of arrayed semiconductor device units 110 are disposed on the first surface of the semiconductor wafer 100, and the area between adjacent semiconductor device units 110 forms a dicing region 120. Transistors and circuits are disposed within the semiconductor device units 110. In this embodiment, the semiconductor device units 110 are at least partially embedded in the semiconductor wafer 100; in other embodiments, the semiconductor device units 110 are located on the first surface of the semiconductor wafer 100.

[0067] In this embodiment, semiconductor device units 110 are arranged in an array on the first surface of semiconductor wafer 100. In other embodiments, semiconductor device units 110 may also be arranged regularly on the first surface of semiconductor wafer 100 so that a single semiconductor wafer 100 can carry more semiconductor device units 110.

[0068] It should be noted that, because this application uses an etching process to separate the chip assembly 10, the etching process simultaneously etches all areas that need to be etched, without considering the size and distribution of the etched areas. In traditional tool cutting methods, the more complex the cutting path, the higher the manufacturing difficulty; the longer the total length of the cutting tool, the higher the process cost. Because the path of the tool during the cutting process and the total length of the cutting path need to be considered to avoid high manufacturing difficulty and high process cost, in traditional tool cutting methods, the semiconductor device units 110 on the surface of the semiconductor wafer 100 are usually arranged in an array. The semiconductor device units 110 arrangement order on the semiconductor wafer 100 provided in this application can be arranged in an interleaved or other regular manner, with the maximum number of semiconductor device units 110 arranged, only requiring that there is a cutting path region 120 for etching between adjacent semiconductor device units 110, without considering the cutting path and cutting path length.

[0069] Reference Figure 3 As shown, the semiconductor wafer 100 is etched in the dicing region 120 to form a first groove 130. The depth direction of the first groove 130 extends along the thickness direction of the semiconductor wafer 100, and the depth of the first groove 130 is greater than the depth at which the semiconductor device unit 110 is embedded in the semiconductor wafer 100. Specifically, the first groove 130 has a first width w1 and a first depth d1, which are positively correlated. The third thickness t3 of the portion of the semiconductor device unit 110 extending into the semiconductor wafer 100 satisfies: 2μm≤w1≤20μm, 5μm≤d1≤50μm, 10≤d1 / w1≤30, and d1>t3. Further, the method of etching the semiconductor wafer 100 in the dicing region 120 to form the first groove 130 includes a deep reactive ion etching process.

[0070] Reference Figure 4 As shown, the first surface of the semiconductor wafer 100 is temporarily bonded to the carrier substrate 200, which is made of glass substrate material. In this embodiment, the carrier substrate 200 is temporarily bonded to the semiconductor wafer 100 via a temporary bonding film 210. The temporary bonding film 210 is a UV film with adhesiveness on both sides. One side of the temporary bonding film 210 is attached to the semiconductor wafer 100 and the semiconductor device unit 110, and the other side of the temporary bonding film 210 is attached to the carrier substrate 200. Figure 4 In this structure, the carrier substrate 200, the temporary bonding film 210, and the semiconductor wafer 100 are stacked sequentially from top to bottom to improve the overall structural strength.

[0071] The temporary bonding film 210 covers the semiconductor device unit 110 so that the semiconductor wafer 100 and the carrier substrate 200 remain horizontal. This makes it easier to place the bonded semiconductor wafer 100 and the carrier substrate 200 on a horizontal platform after the semiconductor wafer 100 is horizontally flipped in a subsequent step. The second surface of the semiconductor wafer 100 facing upward after being flipped is also on the horizontal surface.

[0072] Reference Figure 5 As shown, the horizontally flipped semiconductor device unit 110 flips the semiconductor wafer 100 horizontally to facilitate subsequent processes such as metal deposition and etching on the second surface of the semiconductor wafer 100. Thinning of the semiconductor wafer 100 is performed from its second surface towards its first surface. The thinned semiconductor wafer 100 facilitates the function of the metal layer 140 deposited in subsequent steps as a metal electrode in the chip. Specifically, the semiconductor wafer 100 before thinning has a first thickness t1, satisfying 400μm≤t1≤1200μm. The thinned semiconductor wafer 100 has a second thickness t2, satisfying 50μm≤t2≤200μm.

[0073] Reference Figure 6 As shown, a photoresist layer 300 covering the second surface of the thinned semiconductor wafer 100 is formed, and an opening is made in the photoresist layer 300 to expose a portion of the semiconductor wafer 100 surface. In the thickness direction of the semiconductor wafer 100, the partial semiconductor wafer 100 surface and the orthographic projection of the semiconductor device unit 110 on the second surface overlap, and the remaining photoresist layer 300 and the first groove 130 overlap in their orthographic projections on the second surface. In this embodiment, the method for making the opening in the photoresist layer 300 includes a photolithography process.

[0074] The remaining photoresist layer 300 has a first end and a second end in its cross-section with respect to the thickness direction of the semiconductor wafer 100. The first end is located on the side of the remaining photoresist layer 300 away from the semiconductor wafer 100, and the second end is located on the side of the photoresist layer 300 close to the semiconductor wafer 100 and abuts against the semiconductor wafer 100. The width of the first end is greater than the width of the second end. In this embodiment, the cross-section of the remaining photoresist layer 300 is an inverted trapezoidal structure.

[0075] Reference Figure 7As shown, a metal layer 140 is formed on the side of the semiconductor wafer 100 facing the second surface by depositing metal. The metal layer 140 covers the exposed portion of the semiconductor wafer 100 surface and the first end of the remaining photoresist layer 300. The method for forming the metal layer 140 on the side of the semiconductor wafer 100 facing the second surface by depositing metal includes PVD, CVD, or vapor deposition. The material of the metal layer 140 includes at least one of Ti, Cr, TiW, Ni, Ag, Al, Cu, and Au. When the metal layer 140 is made of multiple materials, the structure of the metal layer 140 is a stacked structure of multiple materials; during the formation of the metal layer 140, multiple materials are sequentially deposited on the second surface of the first carrier substrate 200 to construct a metal layer 140 with a sequentially stacked structure of multiple materials.

[0076] It should be noted that because the width of the first end of the remaining photoresist layer 300 is greater than the width of the second end, during the metal deposition process, the metal layer 140 cannot be deposited on the sidewalls on both sides of the remaining photoresist layer 300, so that the metal layer 140 deposited on the surface of part of the semiconductor wafer 100 and the metal layer 140 deposited on the remaining photoresist layer 300 are separated from each other.

[0077] Reference Figure 8 As shown, after the remaining photoresist layer 300 is peeled off, the metal layer 140 deposited on a portion of the semiconductor wafer 100 surface and the metal layer 140 deposited on the remaining photoresist layer 300 are separated from each other. The metal layer 140 on the photoresist layer 300 is also peeled off along with the remaining photoresist layer 300, while the metal layer 140 on the semiconductor wafer 100 surface is retained, thereby obtaining a metal structure 13 corresponding to each semiconductor device unit 110. This metal structure 13 is constructed in the chip assembly 10 as a necessary metal electrode in the chip. After the remaining photoresist layer 300 is peeled off, a target region 150 is formed on the second surface of the semiconductor wafer 100, and the width of the target region 150 is greater than the width of the first groove 130.

[0078] Reference Figure 9 As shown, the semiconductor wafer 100 is etched through the target area 150 to form a second groove 160. The etching direction extends along the thickness direction of the semiconductor wafer 100 until the second groove 160 connects with the first groove 130, thereby separating the semiconductor device units 110 and obtaining a substrate structure 12 corresponding to each semiconductor device unit 110. The width and cross-sectional depth of the second groove 160 are both greater than the width and cross-sectional depth of the first groove 130.

[0079] Specifically, the second groove 160 has a second width w2 and a second depth d2. The second width w2 and the second depth d2 are positively correlated, satisfying the following conditions: w2 > w1, 6μm ≤ w2 ≤ 50μm, 50μm ≤ d2 ≤ 200μm, and 10 ≤ d2 / w2 ≤ 30. It should be noted that the width and depth of the etching trench formed by the etching process on the semiconductor wafer 100 are positively correlated. Therefore, this application uses a first groove 130 with a smaller width and depth on the first surface of the semiconductor wafer 100 where semiconductor device units 110 are located, in order to reduce the area occupied by the first groove 130 on the semiconductor wafer 100 while increasing the number of semiconductor device units 110 that can be arranged per unit semiconductor wafer 100. A second groove 160 is etched on the second surface of the semiconductor wafer 100. The width and depth of the second groove 160 are both greater than the depth and width of the first groove 130, and the depth of the first groove 130 is greater than the depth at which the semiconductor device unit 110 is embedded in the semiconductor wafer 100. This is to prevent the etching depth of the second groove 160 from reaching the position where the semiconductor device unit 110 is embedded in the semiconductor wafer 100, and to prevent damage to the semiconductor device unit 110 during the etching process of the second groove 160.

[0080] It should be noted that, in this embodiment, because the semiconductor wafer 100 and the metal layer 140 are made of different materials, the etching process for the semiconductor device unit 110 cannot be applied to the metal layer 140. The method for etching the semiconductor wafer 100 to form the second groove 160 includes deep reactive ion etching.

[0081] Reference Figure 10 As shown, a support film 400 is adhered to the side of the metal layer 140 away from the semiconductor wafer 100. The support film 400 facilitates the subsequent overall transfer of all chip components 10. Specifically, the support film 400 is a UV film with an adhesive surface, and the material of the support film 400 includes at least one of PVC, PET, or PP.

[0082] Reference Figure 11 As shown, the support film 400, semiconductor wafer 100, and carrier substrate 200 are horizontally flipped. The carrier substrate 200 and semiconductor wafer 100 are debonded, and the temporary bonding film 210 or adhesive used for temporary bonding is removed to obtain several separate chip assemblies 10. The chip assembly 10 includes a device structure 11 composed of semiconductor device units 110, a substrate structure 12, and a metal structure 13. When the carrier substrate 200 and semiconductor wafer 100 are bonded by the temporary bonding film 210, the temporary bonding film 210 includes a photosensitive material, and the temporary bonding film 210 is removed by light irradiation.

[0083] On the one hand, this application achieves metallization of the back side of the semiconductor wafer 100 while using etching process to separate the chip components 10. Compared with traditional tool cutting, this application can simultaneously etch all areas that need to be etched, reducing process difficulty and production costs. It avoids the problems of high process difficulty and high production costs caused by complex cutting paths and excessively long cutting channels in traditional tool cutting. While avoiding the above problems, this application can set more semiconductor device units 110 on a single semiconductor wafer 100 to separate more chip components 10. On the other hand, this application employs etching a first groove 130 and a second groove 160 on both sides of the semiconductor wafer 100, and connecting the first groove 130 and the second groove 160 to divide the chip assembly 10. The size of the first groove 130 is smaller than the size of the second groove 160. Because the depth and width of the etching trench formed by the etching process are positively correlated, the limitation of requiring a larger area for a single etching trench on the side of the semiconductor wafer 100 with semiconductor device units 110 is avoided. A first groove 130 with a smaller size than a single etching trench can be provided on the side of the semiconductor wafer 100 with semiconductor device units 110, so that a greater number of semiconductor device units 110 can be arranged on a single semiconductor wafer 100.

[0084] Example 2

[0085] The following will combine Figures 12-23 The second embodiment of the present invention will be described in detail.

[0086] Reference Figure 12 As shown, a semiconductor wafer 100 is provided, the semiconductor wafer 100 being made of silicon. The semiconductor wafer 100 has opposing first and second surfaces, wherein the first surface is on the upper side of the figure, and the second surface is on the lower side of the figure. A plurality of arrayed semiconductor device units 110 are disposed on the first surface of the semiconductor wafer 100, and the area between adjacent semiconductor device units 110 forms a dicing region 120. Transistors and circuits are disposed within the semiconductor device units 110. In this embodiment, the semiconductor device units 110 are at least partially embedded in the semiconductor wafer 100; in other embodiments, the semiconductor device units 110 are located on the first surface of the semiconductor wafer 100.

[0087] Reference Figure 13As shown, the semiconductor wafer 100 is etched in the dicing region 120 to form a first groove 130. The depth direction of the first groove 130 extends along the thickness direction of the semiconductor wafer 100, and the depth of the first groove 130 is greater than the depth at which the semiconductor device unit 110 is embedded in the semiconductor wafer 100. Specifically, the first groove 130 has a first width w1 and a first depth d1, and the first width w1 and the first depth d1 are positively correlated, satisfying: 2μm≤w1≤20μm, 5μm≤d1≤50μm, and 10≤d1 / w1≤30. Further, the method of etching the semiconductor wafer 100 in the dicing region 120 to form the first groove 130 includes a deep reactive ion etching process.

[0088] Reference Figure 14 As shown, the first surface of the semiconductor wafer 100 is temporarily bonded to the carrier substrate 200, which is made of glass substrate material. In this embodiment, the carrier substrate 200 is temporarily bonded to the semiconductor wafer 100 via a temporary bonding film 210. The temporary bonding film 210 is a UV film with adhesiveness on both sides. One side of the temporary bonding film 210 is attached to the semiconductor wafer 100 and the semiconductor device unit 110, and the other side of the temporary bonding film 210 is attached to the carrier substrate 200. Figure 4 In this structure, the carrier substrate 200, the temporary bonding film 210, and the semiconductor wafer 100 are stacked sequentially from top to bottom to improve the overall structural strength.

[0089] Reference Figure 15 As shown, the horizontally flipped semiconductor device unit 110 flips the semiconductor wafer 100 horizontally to facilitate subsequent processes such as metal deposition and etching on the second surface of the semiconductor wafer 100. Thinning of the semiconductor wafer 100 is performed from its second surface towards its first surface. The thinned semiconductor wafer 100 facilitates the function of the metal layer 140 deposited in subsequent steps as a metal electrode in the chip. Specifically, the semiconductor wafer 100 before thinning has a first thickness t1, satisfying 400μm≤t1≤1200μm. The thinned semiconductor wafer 100 has a second thickness t2, satisfying 50μm≤t2≤200μm.

[0090] Reference Figure 16As shown, a photoresist layer 300 covering the second surface of the thinned semiconductor wafer 100 is formed, and an opening is made in the photoresist layer 300 to expose a portion of the semiconductor wafer 100 surface. In the thickness direction of the semiconductor wafer 100, the partial semiconductor wafer 100 surface and the orthographic projection of the semiconductor device unit 110 on the second surface overlap, and the remaining photoresist layer 300 and the first groove 130 overlap in their orthographic projections on the second surface. In this embodiment, the method for making the opening in the photoresist layer 300 includes a photolithography process.

[0091] The remaining photoresist layer 300 has a first end and a second end in its cross-section with respect to the thickness direction of the semiconductor wafer 100. The first end is located on the side of the remaining photoresist layer 300 away from the semiconductor wafer 100, and the second end is located on the side of the photoresist layer 300 close to the semiconductor wafer 100 and abuts against the semiconductor wafer 100. The width of the first end is greater than the width of the second end. In this embodiment, the cross-section of the remaining photoresist layer 300 is an inverted trapezoidal structure.

[0092] Reference Figure 17 As shown, a metal layer 140 is formed on the side of the semiconductor wafer 100 facing the second surface by depositing metal. The metal layer 140 covers the exposed portion of the semiconductor wafer 100 surface and the first end of the remaining photoresist layer 300. The method for forming the metal layer 140 on the side of the semiconductor wafer 100 facing the second surface by depositing metal includes PVD, CVD, or vapor deposition. The material of the metal layer 140 includes at least one of Ti, Cr, TiW, Ni, Ag, Al, Cu, and Au. When the metal layer 140 is made of multiple materials, the structure of the metal layer 140 is a stacked structure of multiple materials; during the formation of the metal layer 140, multiple materials are sequentially deposited on the second surface of the first carrier substrate 200 to construct a metal layer 140 with a sequentially stacked structure of multiple materials.

[0093] Reference Figure 18As shown, a protective layer 170 is deposited on the side of the semiconductor wafer 100 facing the second surface, covering all the metal layers 140 on the surface away from the semiconductor wafer 100. Because the width of the first end of the remaining photoresist layer 300 is greater than the width of the second end, the protective layer 170 cannot be deposited on the sidewalls of both sides of the remaining photoresist layer 300, and the protective layer 170 covering the semiconductor wafer 100 and the gold protective layer 170 covering the photoresist layer 300 are separated. In the event that part of the metal layer 140 is etched or damaged during the etching process of the semiconductor wafer 100, the protective layer 170 protects the metal layer 140 in the subsequent step of etching the semiconductor wafer 100 to form the second groove 160.

[0094] Specifically, the material of the protective layer 170 includes at least one of Al, Ti, TiW, Cr, SiO2, or SiN. When the material of the protective layer 170 includes multiple materials, the structure of the protective layer 170 is a stacked structure of multiple materials; during the formation of the protective layer 170, multiple protective layers 170 are sequentially deposited on the side of the semiconductor wafer 100 facing the second surface to construct a protective layer 170 having a stacked structure of multiple materials.

[0095] Reference Figure 19 As shown, the remaining photoresist layer 300 is peeled off, and the metal layer 140 and protective layer 170 on the photoresist layer 300 are also peeled off along with the remaining photoresist layer 300. The metal layer 140 and protective layer 170 on the surface of the semiconductor wafer 100 are retained. The retained metal layer 140 forms a metal structure 13 corresponding to each semiconductor device unit 110. This metal structure 13 is constructed in the chip assembly 10 as a necessary metal electrode in the chip. After the remaining photoresist layer 300 is peeled off, the semiconductor wafer 100 is exposed on the second surface to form a target region 150. The width of the target region 150 is greater than the width of the first groove 130.

[0096] Reference Figure 20 As shown, the semiconductor wafer 100 is etched through the target area 150 to form a second groove 160. The etching direction extends along the thickness direction of the semiconductor wafer 100 until the second groove 160 connects with the first groove 130, thereby separating the semiconductor device units 110 and obtaining a substrate structure 12 corresponding to each semiconductor device unit 110. The width and cross-sectional depth of the second groove 160 are both greater than the width and cross-sectional depth of the first groove 130. In the event that a portion of the metal layer 140 is etched or damaged during the etching process of the semiconductor wafer 100, the protective layer 170 protects the metal layer 140, preventing it from being damaged during the etching process of the semiconductor wafer 100.

[0097] Specifically, the second groove 160 has a second width w2 and a second depth d2, and the second width w2 and the second depth d2 are positively correlated, satisfying that w2 > w1, 6μm ≤ w2 ≤ 50μm, 50μm ≤ d2 ≤ 200μm, and 10 ≤ d2 / w2 ≤ 30.

[0098] Reference Figure 21 As shown, the protective layer 170 on the metal layer 140 is removed by means of etching.

[0099] Reference Figure 22 As shown, a support film 400 is adhered to the side of the metal layer 140 away from the semiconductor wafer 100. The support film 400 facilitates the subsequent overall transfer of all chip components 10. Specifically, the support film 400 is a UV film with an adhesive surface, and the material of the support film 400 includes at least one of PVC, PET, or PP.

[0100] Reference Figure 23 As shown, the support film 400, semiconductor wafer 100, and carrier substrate 200 are horizontally flipped, and the carrier substrate 200 and semiconductor wafer 100 are debonded. At the same time, the temporary bonding film 210 or adhesive used for temporary bonding is removed to obtain several separate chip assemblies 10. The chip assembly 10 includes: a device structure 11 composed of semiconductor device units 110, a substrate structure 12, and a metal structure 13.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a chip component, characterized in that, include: A semiconductor wafer is provided, the semiconductor wafer including a plurality of semiconductor device units, and the semiconductor wafer is etched in a cleavage region between two adjacent semiconductor device units to form a first groove; The side of the semiconductor wafer with the first groove is temporarily bonded to the carrier substrate; The semiconductor wafer body is thinned on the side of the semiconductor wafer away from the carrier substrate; A photoresist layer is formed on the side of the semiconductor wafer away from the substrate, and the photoresist layer is opened to expose the surface of the semiconductor wafer; wherein, in the thickness direction of the semiconductor wafer, the remaining photoresist layer overlaps with the projection of the first groove on the semiconductor wafer. A metal layer is fabricated, which covers the remaining photoresist layer and the surface of the semiconductor wafer; The remaining photoresist layer is removed to retain the metal layer covering the surface of the semiconductor wafer, thereby obtaining the metal structure corresponding to each semiconductor device unit; The semiconductor wafer is etched on one side of the semiconductor wafer having the metal structure to form a second groove, and the second groove is connected to the first groove; The carrier substrate is debonded to obtain multiple separate chip components.

2. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The first groove has a first width w1, and the second groove has a second width w2, satisfying: 2μm≤w1≤20μm, 6μm≤w2≤50μm, and w2≥w1.

3. The method for manufacturing a chip assembly as described in claim 2, characterized in that, The first depth d1 of the first groove satisfies 5μm≤d1≤50μm and 10≤d1 / w1≤30; the second depth d2 of the second groove satisfies 50μm≤d2≤200μm and 10≤d2 / w2≤30.

4. The method for manufacturing a chip assembly as described in claim 3, characterized in that, A portion of the semiconductor device unit extends into the semiconductor wafer, and the third thickness t3 of the portion of the semiconductor device unit satisfies: d1 > t3.

5. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The second thickness t2 of the semiconductor wafer after the step of thinning the body of the semiconductor wafer satisfies: 50μm≤t2≤200μm.

6. The method for manufacturing a chip assembly as described in claim 1, characterized in that, Also includes: After the metal layer is fabricated, a protective layer is fabricated on the side of the metal layer away from the semiconductor wafer, and the protective layer covers the metal layer. Remove the remaining photoresist layer and the protective layer covering the remaining photoresist layer.

7. The method for manufacturing a chip assembly as described in claim 6, characterized in that, The protective layer is made of at least one of silicon dioxide or silicon nitride.

8. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The method for temporarily bonding one side of the semiconductor wafer with the first groove to the carrier substrate includes: temporarily bonding one side of the semiconductor wafer with the first groove to the carrier substrate through a temporary bonding film; Both sides of the temporary bonding film are adhesive. One side of the temporary bonding film is attached to the semiconductor wafer and the semiconductor device unit, and the other side is attached to the carrier substrate.

9. The method for manufacturing a chip assembly as described in claim 8, characterized in that, The temporary bonding film includes a photosensitive material, which is removed by light irradiation.

10. The method for manufacturing a chip assembly as described in claim 8, characterized in that, The supporting substrate includes a glass substrate.

11. The method for manufacturing a chip assembly as described in claim 1, characterized in that, Also includes: After the step of debonding the carrier substrate, a support film is attached to the side of the metal layer away from the semiconductor wafer.

12. The method for manufacturing a chip assembly as described in claim 11, characterized in that, The support film is a UV film, and the material of the support film includes at least one of PVC, PET or PP.

13. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The method for etching the semiconductor wafer in the cleavage region between two adjacent semiconductor device units includes: etching the semiconductor wafer in the cleavage region between two adjacent semiconductor device units using deep reactive ion etching. The method for etching the semiconductor wafer on the side of the semiconductor wafer having the metal structure includes: etching the semiconductor wafer on the side of the semiconductor wafer having the metal structure using deep reactive ion etching.

14. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The metal layer is made of at least one of Ti, Cr, TiW, Ni, Ag, Al, Cu, or Au; When the metal layer is made of multiple materials, the structure of the metal layer is a multi-layered structure of multiple materials.

15. The method for manufacturing a chip assembly as described in claim 1, characterized in that, Along the thickness direction of the semiconductor wafer, the cross-section of the remaining photoresist layer has a first end and a second end opposite to each other, the first end being located on the side of the second end away from the semiconductor wafer, and the width of the first end being greater than the width of the second end.

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