Method for manufacturing a chip assembly

Abstract

Embodiments of the present application disclose a chip assembly manufacturing method, which comprises the following steps: a first supporting substrate has opposite first and second surfaces, the first supporting substrate is thinned from the second surface; a metal layer is formed on the second surface; the metal layer is temporarily bonded with a second supporting substrate; a photoresist layer covering a semiconductor device unit is formed on the first surface, and the photoresist layer is subjected to a patterning process to expose a target cutting path region; the first supporting substrate is etched in the target cutting path region, and the etching stops at the metal layer; the metal layer is etched to obtain a metal structure; the photoresist layer is removed; and the second supporting substrate is unbonded to obtain a plurality of separated chip assemblies. The technical scheme of the present application reduces the width of the cutting path region, improves the number of chip assemblies on a single wafer, and realizes the metallization of the back surface of the thinned wafer.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing technology, and in particular to a method for manufacturing chip components. Background Technology

[0002] Narrowing the width of the chip dicing channel is one of the effective ways to reduce chip size, especially for small chips. For example, narrowing the dicing channel of a small chip with a dicing channel width of 50um and a size of 0.25*0.25mm to 10um will increase the number of chips on a single wafer by 25%, which can effectively reduce the wafer manufacturing process cost of a single chip.

[0003] The dicing channel is the physical space reserved for separating individual chips from a wafer. Dividing wafers using a cutting tool is currently the process used for large-scale mass production in the semiconductor industry. Because the cutting tool has a certain thickness and the cutting process causes some physical damage to the surrounding area, the dicing channel width generally cannot be too small. A 50µm dicing channel width is currently the narrowest width that can be used in the industry while ensuring the cutting quality. However, the dicing channel area occupies the surface area of ​​the wafer, reducing the number of chip components that can be cut from the wafer. Summary of the Invention

[0004] The embodiments of the present invention provide a method for manufacturing a chip assembly, which can achieve metallization on the back side of a first carrier substrate while using an etching process to separate the chip assembly, reduce the area occupied by the cutting track on the first carrier substrate, and increase the number of chip assemblies that can be cut out per unit area of ​​the first carrier substrate.

[0005] To address the aforementioned technical problems, embodiments of the present invention disclose the following technical solutions:

[0006] On the one hand, a method for manufacturing a chip component is provided, including:

[0007] A first carrier substrate is provided, the first carrier substrate having a first surface and a second surface opposite to each other, a plurality of semiconductor device units arranged in an array are formed on the first surface, and the region between two adjacent semiconductor device units is used as the initial dicing region.

[0008] The first carrier substrate is thinned in the thickness direction from the second surface;

[0009] A metal layer is formed on the second surface of the thinned first carrier substrate;

[0010] The metal layer is temporarily bonded to the second carrier substrate;

[0011] A photoresist layer is formed on the first surface covering the semiconductor device unit, and the photoresist layer is patterned to expose a target cleavage region between two adjacent semiconductor device units; wherein the width of the target cleavage region is smaller than the width of the initial cleavage region.

[0012] The first carrier substrate is etched in the target cleavage region between two adjacent semiconductor device units, and the etching remains on the metal layer.

[0013] The metal layer is etched in the target cut area between two adjacent semiconductor device units to obtain the metal structure corresponding to each semiconductor device unit.

[0014] Remove the photoresist layer covering the semiconductor device unit;

[0015] The second carrier substrate is debonded to obtain multiple separate chip components.

[0016] In addition to one or more of the features disclosed above, or alternatively, the thinning process of the first carrier substrate from the second surface in the thickness direction includes:

[0017] The thickness t2 of the first carrier substrate after thinning satisfies: 50μm≤t2≤200μm.

[0018] In addition to one or more of the features disclosed above, or alternatively, the temporary bonding of the metal layer to the second carrier substrate includes:

[0019] The metal layer is temporarily bonded to the second carrier substrate using a temporary bonding film;

[0020] The temporary bonding film has adhesive properties on both opposite sides, and the first carrier substrate and the second carrier substrate are respectively adhered to the opposite opposite sides of the temporary bonding film.

[0021] In addition to one or more of the features disclosed above, or as an alternative, the temporary bonding film includes a photosensitive material that is removed by light irradiation.

[0022] In addition to one or more of the features disclosed above, or as an alternative, the second carrier substrate includes a glass substrate.

[0023] In addition to one or more of the features disclosed above, or as an alternative, it also includes:

[0024] After completing the step of debonding the second carrier substrate, a support film is attached to the side of the metal layer away from the first carrier substrate.

[0025] In addition to one or more of the features disclosed above, or as an alternative, the support film is a UV film, and the material of the support film includes at least one of PVC, PET or PP.

[0026] In addition to one or more of the features disclosed above, or alternatively, the method of etching the first carrier substrate in the target cleavage region between two adjacent semiconductor device units includes:

[0027] The first substrate is etched using a deep reactive ion etching process in the target cut area between two adjacent semiconductor device units to obtain an etched groove.

[0028] In addition to one or more of the features disclosed above, or as an alternative, in the thickness direction of the first carrier substrate, the projection width w of the etching groove on the first surface, the width of the etching groove being perpendicular to the extension direction of the etching groove, and the depth d of the etching groove satisfying: 10≤d / w≤30, 2μm≤w≤20μm; 50μm≤d≤200μm.

[0029] In addition to one or more of the features disclosed above, or alternatively, the method of etching the metal layer in a target cleavage region between two adjacent semiconductor device units includes:

[0030] The metal layer is etched using a wet chemical etching process in the target cut area between two adjacent semiconductor device units.

[0031] In addition to one or more of the features disclosed above, or as an alternative, in the wet chemical etching process, a chemical etching liquid is used to etch the metal layer, the chemical etching liquid including at least one of phosphoric acid, nitric acid or hydrofluoric acid.

[0032] In addition to one or more of the features disclosed above, or as an alternative, the material of the metal layer includes at least one of Ti, Cr, TiW, Ni, Ag, Al, Cu or Au;

[0033] When the metal layer is made of multiple materials, the structure of the metal layer is a multi-layered structure of multiple materials.

[0034] One of the above technical solutions has the following advantages or beneficial effects: On the one hand, this application achieves metallization on the back side of the first carrier substrate while simultaneously using an etching process to separate the chip components. Through the etching process, this application can simultaneously etch all target cleaving areas on the first carrier substrate, reducing process difficulty and production costs, and avoiding the increased process difficulty and production costs caused by the complex cutting paths and long path lengths in traditional tool cutting. On the other hand, this application refines the areas of the first carrier substrate and the metal layer that need to be etched by targeting the cleaving areas, reducing the etching area, improving the etching precision, and increasing the surface utilization of the first carrier substrate. At the same time, it avoids damage to the semiconductor device units caused by lateral propagation etching due to the etching trenches being too close to the semiconductor device units during the etching process, and avoids the problem of insufficient metal structure coverage caused by lateral propagation etching of the metal layer, thereby improving production yield and reducing production costs. Attached Figure Description

[0035] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0036] Figure 1 This is a flowchart of a method for manufacturing a chip assembly according to an embodiment of the present invention;

[0037] Figures 2-10 This is a schematic diagram of the manufacturing process of a chip component manufacturing method according to an embodiment of the present invention;

[0038] In the figure: 100-first carrier substrate; 110-semiconductor device unit; 120-initial dicing region; 121-target dicing region; 130-etching trench; 200-metal layer; 300-second carrier substrate; 310-temporary bonding film; 400-photoresist; 500-support film; 10-chip assembly; 11-device structure; 12-substrate structure; 13-metal structure. Detailed Implementation

[0039] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described in this specification are merely for explaining the invention and are not intended to limit the invention.

[0040] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0042] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0043] See Figure 1 , Figure 1 A method for manufacturing a chip assembly according to an embodiment of the present invention is illustrated. The method for manufacturing a chip assembly according to an embodiment of the present application includes:

[0044] S10, a first carrier substrate is provided, the first carrier substrate has a first surface and a second surface opposite to each other, a plurality of semiconductor device units are formed on the first surface in an array, and the area between two adjacent semiconductor device units is used as the initial dicing area.

[0045] S20, the first carrier substrate is thinned in the thickness direction from the second surface;

[0046] S30, a metal layer is formed on the second surface of the thinned first carrier substrate;

[0047] S40, temporarily bond the metal layer to the second carrier substrate;

[0048] S50, a photoresist layer is formed on the first surface covering the semiconductor device unit, and the photoresist layer is patterned to expose a target cleavage area between two adjacent semiconductor device units; wherein the cross-sectional size of the target cleavage area is smaller than the cross-sectional size of the initial cleavage area;

[0049] S60, the first carrier substrate is etched in the target cleavage region between two adjacent semiconductor device units, and the etching remains on the metal layer;

[0050] S70, the metal layer is etched in the target cleavage region between two adjacent semiconductor device units to obtain the metal structure corresponding to each semiconductor device unit;

[0051] S80, Remove the photoresist layer covering the semiconductor device unit;

[0052] S90, the second carrier substrate is debonded to obtain multiple separate chip components.

[0053] Steps S10 to S90 will be described in detail below.

[0054] In step S10, a first carrier substrate is provided, the first carrier substrate being made of silicon. The first carrier substrate has a first surface and a second surface opposite each other with respect to its thickness direction. A plurality of semiconductor device units arranged in an array are disposed on the first surface of the first carrier substrate, and the area between adjacent semiconductor device units is an initial etch track area for subsequent etching. The semiconductor device units contain transistors and circuit structures. In this embodiment, the semiconductor device units are partially embedded in the first carrier substrate; in other embodiments, the semiconductor device units may also be located on the first surface of the first carrier substrate.

[0055] In step S20, the second carrier substrate is thinned in its thickness direction from the second surface of the first carrier substrate. The initial thickness of the first carrier substrate is usually not the target thickness required for the final product chip assembly. An excessively thick first carrier substrate will cause the distance between the metal layer subsequently deposited on the second surface of the first carrier substrate and the semiconductor device unit on the first surface to be too large, which will lead to difficulties in the subsequent processing of the chip assembly. Therefore, it is necessary to thin the first carrier substrate.

[0056] In step S30, a metal layer is formed on the second surface of the thinned first substrate by depositing metal, and the metal layer covers the second surface of the first substrate. The formed metal layer serves as a necessary metal electrode in the chip constructed from the chip assembly. Methods for forming the metal layer on the second surface of the thinned first substrate include PVD, CVD, or vapor deposition processes.

[0057] In step S40, the metal layer is temporarily bonded to the second carrier substrate on the side of the metal layer away from the first carrier substrate. The second carrier substrate is made of glass substrate material. In this embodiment, the metal layer is temporarily bonded to the second carrier substrate through a temporary bonding film, which is a UV film with adhesive on both sides. In other embodiments, the metal layer is temporarily bonded to the second carrier substrate through adhesive. Because the first carrier substrate is too thin after thinning to be directly subjected to photolithography, lift-off, or etching processes, this application uses a second carrier substrate to strengthen the overall structure of the first carrier substrate, avoiding damage caused by low structural strength in subsequent processes and improving the yield of this application.

[0058] In step S50, a photoresist layer covering the first surface of the first carrier substrate is formed. The photoresist layer covers the semiconductor device unit and the initial dicing region. The photoresist layer is patterned to expose the target dicing region between adjacent semiconductor device units. In this embodiment, the method for patterning the photoresist layer includes a photolithography process. The target dicing region is accommodated within the initial dicing region and has a cross-sectional size smaller than the initial dicing region. The remaining regions (i.e., the semiconductor device unit and part of the initial dicing region are covered by the photoresist layer) are still covered by the photoresist layer.

[0059] In step S60, the first carrier substrate is etched through the target dicing area exposed between adjacent semiconductor device units. The etching direction extends along the thickness direction of the first carrier substrate and stops at the metal layer to form etching trenches separating the semiconductor device units, thus obtaining a substrate structure corresponding to each semiconductor device unit. Because the materials of the first carrier substrate and the metal layer are different, the etching process on the first carrier substrate cannot be applied to the metal layer, so the etching stops at the metal layer. The etching trenches extend along the thickness direction of the first carrier substrate and penetrate the first carrier substrate. The etching method for the first carrier substrate includes deep reactive ion etching (DRIE).

[0060] Deep Reactive Ion Etching (DRIE) can etch grooves with widths ranging from a few micrometers to depths of hundreds of micrometers onto the first substrate. This allows for the "cutting" of the first substrate and the separation of chip components, making it an ideal alternative to traditional tool cutting. It offers significant cost advantages, especially when processing small-sized chips, as it significantly increases the number of chip components per unit of the first substrate while significantly reducing cutting production costs. Specifically, the smaller the chip component, the more etchable grooves are on the first substrate, resulting in longer processing times and higher costs for traditional tool cutting. DRIE, however, simultaneously etches all target etchable areas across the entire first substrate, regardless of the number of target etchable areas, thus maintaining consistent processing costs regardless of the number of target etchable areas. However, DRIE cannot etch metal layers.

[0061] In step S70, the metal layer is etched sequentially through the target dicing area and the etching trench to obtain the metal structure corresponding to each semiconductor device unit. Each metal structure corresponds one-to-one with its corresponding substrate structure and the semiconductor device unit carried by the substrate structure. The individual metal structure, the corresponding substrate structure, and the semiconductor device unit carried by the substrate structure are constructed into a single chip assembly, realizing the separation of the chip assembly.

[0062] In step S80, the photoresist layer covering the semiconductor device unit is removed.

[0063] In step S90, the second carrier substrate is debonded to the metal layer, and the temporary bonding film or adhesive used for temporary bonding is removed to obtain several separate chip components.

[0064] The following will combine Figures 2-10 The embodiments of the present invention will be described in detail below.

[0065] See Figure 2First, a first carrier substrate 100 is provided. The first carrier substrate 100 has opposing first and second surfaces, wherein the first surface is on the upper side and the second surface is on the lower side. A plurality of arrayed semiconductor device units 110 are disposed on the first surface of the first carrier substrate 100, and the area between adjacent semiconductor device units 110 forms an initial dicing region 120. Each semiconductor device unit 110 contains transistors and circuits. In this embodiment, the semiconductor device units 110 are arrayed on the first surface of the first carrier substrate 100. In other embodiments, the semiconductor device units 110 may also be regularly disposed on the first surface of the first carrier substrate 100, so that the first carrier substrate 100 can support more semiconductor device units 110.

[0066] Furthermore, the first carrier substrate 100 is made of silicon. In this embodiment, the semiconductor device unit 110 is at least partially embedded in the first carrier substrate 100; in other embodiments, the semiconductor device unit 110 is located on the first surface of the first carrier substrate 100.

[0067] It should be noted that, because this application uses an etching process to separate the chip assembly 10, the etching process simultaneously etches all areas that need to be etched, without considering the size and distribution of the etched areas. In traditional tool cutting methods, the more complex the cutting path, the higher the manufacturing difficulty; the longer the cutting track, the higher the manufacturing cost. Because the tool path and the length of the cutting track need to be considered during the cutting process to avoid high manufacturing difficulty and high manufacturing cost, in traditional tool cutting methods, the semiconductor device units 110 on the surface of the first carrier substrate 100 are usually arranged in an array. The semiconductor device units 110 arrangement order on the first carrier substrate 100 provided in this application can adopt an interleaved arrangement or other arrangement methods to arrange the maximum number of semiconductor device units 110, only requiring that there is an initial cutting track region 120 for etching between adjacent semiconductor device units 110, without considering the cutting path and cutting track length.

[0068] Continue to refer to Figure 3 As shown, the first carrier substrate 100 is thinned in its thickness direction from its second surface, that is, thinning is performed from the second surface towards the first surface. The thinned first carrier substrate 100 facilitates the function of the metal layer 200 deposited in subsequent steps as a metal electrode in the chip. Specifically, the first thickness t1 of the first carrier substrate 100 before thinning satisfies: 400μm ≤ t1 ≤ 1200μm. The second thickness t2 of the first carrier substrate 100 after thinning satisfies: 50μm ≤ t2 ≤ 200μm.

[0069] Continue to refer to Figure 4 As shown, a metal layer 200 is formed on the second surface of the thinned first substrate 100 by depositing metal, and the metal layer 200 covers the second surface of the first substrate 100. The formed metal layer 200 serves as an essential metal electrode in the chip constructed by the chip assembly 10. The method for forming the metal layer 200 on the second surface of the thinned first substrate 100 includes PVD, CVD, or vapor deposition processes. The material of the metal layer 200 includes at least one material selected from Ti, Cr, TiW, Ni, Ag, Al, Cu, and Au. When the metal layer 200 is made of multiple materials, the structure of the metal layer 200 is a stacked structure of multiple materials; during the formation of the metal layer 200, multiple materials are sequentially deposited on the second surface of the first substrate 100 to construct a metal layer 200 having a stacked structure of multiple materials.

[0070] Continue to refer to Figure 5 As shown, on the side of the metal layer 200 away from the first carrier substrate 100, the metal layer 200 is temporarily bonded to the second carrier substrate 300 via a temporary bonding film 310. The first carrier substrate 100, the metal layer 200, the temporary bonding film 310, and the second carrier substrate 300 are stacked sequentially from top to bottom to improve overall strength. In this embodiment, the metal layer 200 is temporarily bonded to the second carrier substrate 300 via the temporary bonding film 310, which is a UV film with adhesive on both sides. In other embodiments, the metal layer 200 is temporarily bonded to the second carrier substrate 300 via adhesive; no specific limitation is made here. The second carrier substrate 300 is a glass substrate.

[0071] Continue to refer to Figure 6 As shown, a photoresist layer 400 is formed on a first surface of a first substrate 100, covering the first surface. The photoresist layer 400 covers the semiconductor device unit 110 and the initial dicing region 120. The photoresist layer 400 is patterned to expose the target dicing region 121 between adjacent semiconductor device units 110. In this embodiment, the method for patterning the photoresist layer 400 includes a photolithography process. The target dicing region 121 is accommodated within the initial dicing region 120 and has a cross-sectional size smaller than the initial dicing region 120. The remaining areas (i.e., the semiconductor device unit 110 and part of the initial dicing region 120 are covered by the photoresist layer 400) are still covered by the photoresist layer 400.

[0072] It should be noted that the target dicing region 121 is smaller than the initial dicing region 120, so that the photoresist can protect the edge of the semiconductor device unit 110 during the etching process. Furthermore, during the etching process, the etching will spread to a certain extent in the lateral direction shown in the figure. The smaller cross-sectional size of the target dicing region 121 controls the lateral spread during etching within a controllable range. In some embodiments, the semiconductor device unit 110 is partially embedded in the first carrier substrate 100 to avoid damage to the transistors or circuits in the semiconductor device unit 110 caused by the etching process.

[0073] Specifically, the first width (i.e., the width between adjacent semiconductor device units 110) L1 of the initial cleavage region 120 between adjacent semiconductor device units 110 within the first surface satisfies: 20 ≤ L1 ≤ 100 μm. The second width L2 of the target cleavage region 121 between adjacent semiconductor device units 110 within the first surface satisfies: 2 μm ≤ L2 ≤ 20 μm, L2 < L1.

[0074] Continue to refer to Figure 7 As shown, the first carrier substrate 100 is etched through the target dicing region 121 exposed between adjacent semiconductor device units 110. The etching direction extends along the thickness direction of the first carrier substrate 100 and stops at the metal layer 200 to form etching trenches 130 separating the semiconductor device units 110. The metal layer 200 is exposed from the etching trenches 130, and a substrate structure 12 corresponding to each semiconductor device unit 110 is obtained. Along the thickness direction of the first carrier substrate 100, the depth d of the etching trenches 130 satisfies: 50μm≤d≤200μm; the projection width w of the etching trenches 130 on the first surface satisfies: 2μm≤w≤20μm, 10≤d / w≤30. Further, the first carrier substrate 100 is etched by a deep reactive ion etching (DRIE) process to form the etching trenches 130. Along the thickness direction of the first substrate 100, the orthographic projection of the etching trench 130 on the first surface overlaps with the target cutting area 121. It should be noted that, since the etching process on the first substrate 100 cannot be applied to the metal layer 200, the etching stops at the metal layer 200, so that the metal layer 200 is exposed from the etching trench 130, so as to facilitate the etching of the metal plate in subsequent steps.

[0075] Continue to refer to Figure 8As shown, the metal layer 200 at the bottom of the etching trench 130 is etched to obtain a metal structure 13 corresponding to each semiconductor device unit 110. The metal structure 13 serves as a metal electrode in the chip composed of the chip assembly 10. The individual metal structure 13, the corresponding substrate structure 12, and the semiconductor device unit 110 supported by the substrate structure 12 are configured to form a single chip assembly 10. During the etching process of the metal layer 200, the etching direction will have a certain degree of lateral spread, and the metal layer 200 near the edge of the substrate structure 12 will be etched away. The width of the etched metal layer 200 is in the range of 0.5μm-10μm. The target dicing region 121 is smaller than the initial dicing region 120 as a redundancy design to ensure that the orthographic projection of the semiconductor device structure on the first surface is within the orthographic projection range of the metal structure 13 in the thickness direction of the first carrier substrate 100, thereby improving the yield of this application.

[0076] Furthermore, the method for etching the metal layer 200 includes etching the metal layer 200 using a wet chemical etching process. It should be noted that different chemical etching solutions must be selected for different metal materials. When the metal layer 200 is a stacked structure of multiple metal materials, the corresponding chemical etching solutions are sequentially used to etch the metal layer 200 according to the stacking order of the different metal materials. Specifically, during the wet chemical etching process for etching the metal layer 200, the first substrate 100 is immersed in a chemical etching tank containing the chemical etching solution to achieve a top-down view of the metal layer 200. Although the etching tanks 130 on the first substrate 100 are relatively narrow, they are interconnected, allowing the chemical etching solution to easily enter the etching tanks 130 and etch the metal layer 200. In some embodiments, while performing a wet chemical etching process on the metal layer 200, the process is aided by introducing N2 gas into the chemical etching liquid through bubbling or by ultrasonically vibrating the chemical etching liquid to improve the efficiency of the wet chemical etching process. Depending on the material of the metal layer 200, the chemical etching liquid may be an aqueous solution or a mixture of at least one of the conventional chemicals such as phosphoric acid, nitric acid, and hydrofluoric acid.

[0077] Continue to refer to Figure 9 As shown, the photoresist layer 400 covering the semiconductor device unit 110 is removed.

[0078] Continue to refer to Figure 10As shown, the second carrier substrate 300 is debonded from the metal layer 200, and the temporary bonding film 310 or adhesive used for temporary bonding is removed to obtain several separate chip assemblies 10. In this embodiment, the temporary bonding film 310 includes a photosensitive material, and the temporary bonding film 310 is removed by light irradiation. The chip assembly 10 includes a device structure 11 formed by semiconductor device units 110, a substrate structure 12, and a metal structure 13.

[0079] A support film 500 is adhered to the side of the metal layer 200 away from the first carrier substrate 100. This support film 500 facilitates the overall transfer of all chip assemblies 10. Specifically, the support film 500 is a UV film with an adhesive surface, and the material of the support film 500 includes at least one of PVC, PET, or PP.

[0080] On the one hand, this application achieves metallization on the back side of the first carrier substrate while simultaneously using an etching process to separate the chip components. Through the etching process, this application can simultaneously etch all target cleaving areas on the first carrier substrate, reducing process difficulty and production costs. It avoids the increased process difficulty and production costs caused by the complex cutting paths and long path lengths in traditional tool cutting. On the other hand, this application refines the areas of the first carrier substrate and the metal layer that need to be etched by targeting the cleaving areas, reducing the etching area, improving etching precision, and increasing the surface utilization of the first carrier substrate. Simultaneously, it avoids damage to the semiconductor device units caused by lateral creep etching due to excessive proximity of the etching trenches to the semiconductor device units during etching, and avoids insufficient metal structure coverage caused by lateral creep etching of the metal layer. This improves production yield and reduces production costs.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a chip component, characterized in that, The method includes: A first carrier substrate is provided, the first carrier substrate having a first surface and a second surface opposite to each other, a plurality of semiconductor device units arranged in an array are formed on the first surface, and the region between two adjacent semiconductor device units is used as the initial dicing region. The first carrier substrate is thinned in the thickness direction from the second surface; A metal layer is formed on the second surface of the thinned first carrier substrate, and the metal layer is temporarily bonded to the second carrier substrate; A photoresist layer is formed on the first surface covering the semiconductor device unit, and the photoresist layer is patterned to expose a target cleavage region between two adjacent semiconductor device units; wherein the width of the target cleavage region is smaller than the width of the initial cleavage region. The first carrier substrate is etched in the target cleavage region between two adjacent semiconductor device units, and the etching remains on the metal layer. The metal layer is etched in the target cut area between two adjacent semiconductor device units to obtain the metal structure corresponding to each semiconductor device unit. Remove the photoresist layer covering the semiconductor device unit; The second carrier substrate is debonded to obtain multiple separate chip components.

2. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The process of thinning the first carrier substrate in the thickness direction from the second surface includes: The thickness of the first carrier substrate after thinning is t2, which satisfies: 50μm≤t2≤200μm.

3. The method for manufacturing a chip assembly as described in claim 1, characterized in that, Temporarily bonding the metal layer to the second carrier substrate includes: The metal layer is temporarily bonded to the second carrier substrate using a temporary bonding film; The temporary bonding film has adhesive properties on both opposite sides, and the first carrier substrate and the second carrier substrate are respectively adhered to the opposite opposite sides of the temporary bonding film.

4. The method for manufacturing a chip assembly as described in claim 3, characterized in that, The temporary bonding film includes a photosensitive material, which is removed by light irradiation.

5. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The second carrier substrate includes a glass substrate.

6. The method for manufacturing a chip assembly as described in claim 3, characterized in that, Also includes: After completing the step of debonding the second carrier substrate, a support film is attached to the side of the metal layer away from the first carrier substrate.

7. The method for manufacturing a chip assembly as described in claim 6, characterized in that, The support film is a UV film, and the material of the support film includes at least one of PVC, PET or PP.

8. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The method for etching the first carrier substrate in the target cut area between two adjacent semiconductor device units includes: The first substrate is etched using a deep reactive ion etching process in the target cut area between two adjacent semiconductor device units to obtain an etched groove.

9. The method for manufacturing a chip assembly as described in claim 8, characterized in that, In the thickness direction of the first substrate, the projection width w of the etching groove on the first surface is perpendicular to the extension direction of the etching groove. The depth d of the etching groove satisfies: 10≤d / w≤30, 2μm≤w≤20μm; 50μm≤d≤200μm.

10. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The method for etching the metal layer in a target cut-out region between two adjacent semiconductor device units includes: The metal layer is etched using a wet chemical etching process in the target cut area between two adjacent semiconductor device units.

11. The method for manufacturing a chip assembly as described in claim 10, characterized in that, In the wet chemical etching process, a chemical etching liquid is used to etch the metal layer, and the chemical etching liquid includes at least one of phosphoric acid, nitric acid or hydrofluoric acid.

12. The method for manufacturing a chip assembly as described in claim 1, characterized in that, The metal layer is made of at least one of Ti, Cr, TiW, Ni, Ag, Al, Cu, or Au; When the metal layer is made of multiple materials, the structure of the metal layer is a multi-layered structure of multiple materials.

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