A semiconductor device and a method for manufacturing a semiconductor device

Abstract

The embodiment of the present application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device provided by the embodiment of the present application comprises a substrate, a buffer layer arranged on one side of the substrate, an electron transport layer arranged on the side, away from the substrate, of the buffer layer, a semiconductor doped layer arranged on the side, away from the substrate, of the electron transport layer, an interrupt layer arranged on the side, away from the substrate, of the semiconductor doped layer, a gate arranged on the side, away from the substrate, of the interrupt layer, and the interrupt layer at least partially covers the semiconductor doped layer in the thickness direction of the semiconductor device. The technical scheme provided by the embodiment solves the problem that the semiconductor device has low gate control ability and limits or reduces the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0002] With the development of semiconductor technology, people have increasingly higher requirements for the performance of integrated circuits. Hydrogen gas is deposited in thin films, but hydrogen can easily diffuse into the underlying epitaxial film, reducing the gate control capability of the semiconductor device and thus limiting or reducing its performance. Summary of the Invention

[0003] This invention provides a semiconductor device and a method for manufacturing a semiconductor device to solve the problem that semiconductor devices have low gate control capability, which limits or reduces the performance of semiconductor devices.

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution:

[0005] This invention provides a semiconductor device, comprising:

[0006] Substrate;

[0007] A buffer layer disposed on one side of the substrate;

[0008] An electron transport layer disposed on the side of the buffer layer away from the substrate;

[0009] A semiconductor doped layer disposed on the side of the electron transport layer away from the substrate;

[0010] An interruption layer disposed on the side of the semiconductor doped layer away from the substrate;

[0011] The gate is located on the side of the interrupt layer away from the substrate;

[0012] Along the thickness direction of the semiconductor device, the interrupt layer at least partially covers the semiconductor doped layer.

[0013] Optionally, the material of the interrupt layer may include nitrogen, helium, or a nitrogen-containing semiconductor material.

[0014] Optionally, the interruption layer is formed by pulsed plasma doping.

[0015] Optionally, the semiconductor doped layer includes a P-type doped layer, which includes a Mg-doped GaN layer;

[0016] The buffer layer is made of GaN;

[0017] Materials for the electron transport layer include AlGaN;

[0018] The gate material includes titanium nitride, tantalum nitride, or tungsten nitride.

[0019] Optional semiconductor devices also include:

[0020] A passivation layer is disposed on the side of the gate away from the substrate.

[0021] Optionally, the passivation layer may be made of oxides or nitrides.

[0022] Optionally, the thickness of the interrupted layer can range from 1 nm to 3 nm.

[0023] Optional semiconductor devices also include:

[0024] A first semiconductor layer is disposed between a buffer layer and an electron transport layer;

[0025] The material of the first semiconductor layer includes aluminum nitride.

[0026] According to another aspect of the present invention, this embodiment provides a method for fabricating a semiconductor device, comprising:

[0027] Provide substrate;

[0028] A buffer layer is formed on one side of the substrate;

[0029] An electron transport layer is formed on the side of the buffer layer away from the substrate;

[0030] A semiconductor doped layer is formed on the side of the electron transport layer away from the substrate;

[0031] A break layer is formed by doping the semiconductor doped layer on the side away from the substrate; wherein, along the thickness direction of the semiconductor device, the break layer at least partially covers the semiconductor doped layer;

[0032] A gate is formed on the side of the interrupted layer away from the substrate.

[0033] Optionally, after forming the gate on the side of the semiconductor doped layer away from the substrate, the method further includes:

[0034] Pattern the gate, the interrupt layer, and the semiconductor doped layer;

[0035] A passivation layer is formed on the side of the patterned gate away from the substrate.

[0036] The semiconductor device provided in this invention features an interrupt layer between the semiconductor doped layer and the gate. This interrupt layer at least partially covers the semiconductor doped layer along its thickness direction, protecting it and effectively blocking hydrogen (H) penetration during hydride gas thin-film deposition in subsequent processes such as gate fabrication or cleaning. This prevents H from combining with metal ions in the semiconductor doped layer. This arrangement allows for a higher doping concentration in the semiconductor doped layer, thereby improving the gate voltage control capability, reducing the threshold voltage, and enhancing the stability of the semiconductor device. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of the present invention and these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the deposition depth and concentration of the interrupt layer of a semiconductor device provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0042] Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0043] Figure 6 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0044] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0045] Based on the above-mentioned technical problems, this embodiment proposes the following solutions:

[0046] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. See also... Figure 1 The semiconductor device provided in this embodiment of the invention includes: a substrate 1; a buffer layer 2 disposed on one side of the substrate 1; an electron transport layer 3 disposed on the side of the buffer layer 2 away from the substrate 1; a semiconductor doped layer 4 disposed on the side of the electron transport layer 3 away from the substrate 1; an interrupt layer 5 disposed on the side of the semiconductor doped layer 4 away from the substrate 1; and a gate disposed on the side of the interrupt layer 5 away from the substrate 1. Along the thickness direction N1 of the semiconductor device, the interrupt layer 5 at least partially covers the semiconductor doped layer 4.

[0047] Specifically, substrate 1 may include Si substrate 1, SiC substrate 1, or sapphire substrate 1, etc. Buffer layer 2 may include a nitride semiconductor layer. Electron transport layer 3 is used to transport electrons. Semiconductor doped layer 4 may include a GaN layer doped with P, Mg, etc. Because semiconductor doped layer 4 contains ions of metals such as Mg, in subsequent processes, H readily combines with ions of metals such as Mg to undergo passivation, for example, Mg-H passivation. This reduces the doping efficiency of Mg ions in semiconductor doped layer 4, increases the H doping concentration in semiconductor doped layer 4, and results in a low Hall concentration in semiconductor doped layer 4. When the semiconductor device is powered on, the low concentration of Mg ions in semiconductor doped layer 4 results in a smaller current, affecting the gate voltage control capability of the semiconductor device and causing the threshold voltage of the semiconductor device to be higher.

[0048] Interruption layer 5 can be a nitrogen-doped layer. Since the atomic mass of interruption layer 5 is greater than that of hydrogen, by setting interruption layer 5 on the side of semiconductor doped layer 4 away from substrate 1, along the thickness direction N1 of the semiconductor device, interruption layer 5 at least partially covers semiconductor doped layer 4, thus effectively blocking the deposition of hydrogen from the side of semiconductor doped layer 4 away from substrate 1. During the thin film deposition of hydride gas in subsequent processes such as gate fabrication and cleaning of the semiconductor device, interruption layer 5 effectively blocks the transmission of hydrogen. This configuration allows for a higher doping concentration in semiconductor doped layer 4, thereby improving the gate voltage control capability of the semiconductor device, reducing the threshold voltage of the semiconductor device, and improving the stability of the semiconductor device.

[0049] The semiconductor device provided in this embodiment has an interrupt layer 5 disposed between the semiconductor doped layer 4 and the gate, and the interrupt layer 5 at least partially covers the semiconductor doped layer 4 along the thickness direction N1 of the semiconductor device. This interrupt layer 5 protects the semiconductor doped layer 4, effectively blocking the penetration of hydrogen (H) during the thin film deposition of hydride gas in subsequent processes such as gate fabrication or cleaning, preventing H from combining with metal ions in the semiconductor doped layer 4. This arrangement allows for a higher doping concentration in the semiconductor doped layer 4, thereby improving the gate voltage control capability of the semiconductor device, reducing the threshold voltage of the semiconductor device, and improving the stability of the semiconductor device.

[0050] Optionally, based on the above embodiments, see also... Figure 1 The material of interrupt layer 5 includes helium or nitrogen-containing semiconductor materials.

[0051] Specifically, since the interrupt layer 5 is disposed between the gate and the semiconductor doped layer 4, and since the material of the interrupt layer 5 includes nitrogen, helium, or a nitrogen-containing semiconductor material, the mass of the atomic nuclei of the interrupt layer 5 material can be greater than the mass of the H atom nucleus. This can effectively prevent H from depositing into the semiconductor doped layer 4 and avoid introducing hydrogen doping from gases such as NH3. Preferably, the material of the interrupt layer 5 includes nitrogen. Since nitrogen is a neutral material, the contact between the interrupt layer 5 and the semiconductor doped layer 4 will not affect the polarity of the semiconductor doped layer 4, further improving the stability of the semiconductor device and enhancing the gate voltage control capability of the semiconductor device.

[0052] Optionally, based on the above embodiments, see also... Figure 1 Interruption layer 5 is formed by pulsed plasma doping.

[0053] Specifically, pulsed plasma nitriding doping can effectively reduce plasma damage and maintain the original quality of the epitaxial semiconductor doped layer 4, such as the P-GaN film. Since the semiconductor doped layer 4 is relatively thick, the nitrogen doping dosage used in this invention can be adjusted according to actual process requirements.

[0054] Optionally, based on the above embodiments, see also... Figure 1 The semiconductor doped layer 4 includes a P-type doped layer, which includes a GaN layer doped with Mg; the material of the buffer layer 2 includes GaN; the material of the electron transport layer 3 includes AlGaN; and the material of the gate includes titanium nitride, tantalum nitride, or tungsten nitride.

[0055] Specifically, semiconductor doped layer 4 includes a P-type doped layer, which in turn includes a Mg-doped GaN layer, thus doping semiconductor doped layer 4 with Mg. Buffer layer 2 is made of GaN; electron transport layer 3 is made of AlGaN; and the gate is made of titanium nitride, tantalum nitride, or tungsten nitride. This arrangement improves the stability of the semiconductor device. Since interrupt layer 5 is positioned between the Mg-doped GaN layer and the gate (made of titanium nitride, tantalum nitride, or tungsten nitride), it effectively prevents the formation of Mg-H passivation bonds, ensuring the quality of the epitaxial P-GaN layer film. This arrangement further improves the gate voltage control capability of the semiconductor device, further reduces the threshold voltage of the semiconductor device, and improves the stability of the semiconductor device.

[0056] Optional, Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 2 The semiconductor device may also include a passivation layer 6, which is disposed on the side of the gate away from the substrate 1.

[0057] Specifically, the passivation layer 6 provides protection. By placing the passivation layer 6 on the side of the gate away from the substrate 1, the gate can be better protected, resulting in better gate stability of the semiconductor device and further improving the stability of the semiconductor device.

[0058] Optionally, based on the above embodiments, see also... Figure 2 The material of the passivation layer 6 may include oxides or nitrides.

[0059] Specifically, this configuration allows the passivation layer 6 to form an oxide or nitride film on the side of the gate away from the substrate 1, thereby improving the oxidation resistance of the gate, further enhancing the gate voltage control capability of the gate, and improving the stability of the semiconductor device.

[0060] Optional, Figure 3 This is a schematic diagram of the deposition depth and concentration of the interrupted layer of a semiconductor device according to an embodiment of the present invention. Based on the above embodiments, and in conjunction with... Figure 2 and Figure 3 The thickness of interrupted layer 5 ranges from 1 nm to 3 nm.

[0061] Specifically, this configuration allows for a higher nitride doping concentration in interrupt layer 5, resulting in a more uniform film layer. This effectively blocks H deposition, prevents the formation of Mg-H passivation bonds, reduces the threshold voltage of the semiconductor device, improves the gate voltage control capability of the semiconductor device, and further enhances the stability of the semiconductor device.

[0062] It should be noted that, Figure 3 As exemplarily shown, 10 represents the doping concentration of the semiconductor doped layer in a conventional semiconductor device, and 20 represents the relationship between the deposition depth of the interrupt layer and the doping concentration of the semiconductor doped layer in the semiconductor device provided in this embodiment. The deposition depth of the interrupt layer corresponds to the thickness of the interrupt layer in the semiconductor device. Figure 3 It is known that the thickness range of the interrupt layer 5 is 1 nm to 5 nm, and the doping concentration of the semiconductor doped layer is significantly better than that of existing semiconductor devices. Preferably, when the thickness range of the interrupt layer 5 is 1 nm to 3 nm, the doping concentration of the semiconductor doped layer is relatively high, which can effectively block the deposition of H, avoid the formation of Mg-H passivation bonds, effectively reduce the threshold voltage of the semiconductor device, better improve the gate voltage control capability of the semiconductor device, and further improve the stability of the semiconductor device.

[0063] Optional, Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 4 The semiconductor device may further include: a first semiconductor layer 7 disposed between the buffer layer 2 and the electron transport layer 3; the material of the first semiconductor layer 7 includes aluminum nitride.

[0064] Specifically, a first semiconductor layer 7 is disposed between the buffer layer 2 and the electron transport layer 3. The first semiconductor layer 7 and the electron transport layer 3 can form a two-dimensional electronic system, thereby increasing the current density of the semiconductor device.

[0065] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Based on the above embodiments, and in conjunction with... Figure 1 and Figure 5 The method for fabricating a semiconductor device provided in this embodiment includes:

[0066] S101, Provide substrate 1.

[0067] S102, A buffer layer 2 is formed on one side of the substrate 1.

[0068] S103, An electron transport layer 3 is formed on the side of the buffer layer 2 away from the substrate 1.

[0069] S104. A semiconductor doped layer 4 is formed on the side of the electron transport layer 3 away from the substrate 1.

[0070] S105, doping is performed on the side of the semiconductor doped layer 4 away from the substrate 1 to form an interrupt layer 5; wherein, along the thickness direction N1 of the semiconductor device, the interrupt layer 5 at least partially covers the semiconductor doped layer 4.

[0071] S106. A gate is formed on the side of the interrupt layer 5 away from the substrate 1.

[0072] Optionally, based on the above embodiments, Figure 6 This is a flowchart of another method for fabricating a semiconductor device according to an embodiment of the present invention. (In conjunction with...) Figure 2 and Figure 6 The method for fabricating a semiconductor device provided in this embodiment includes:

[0073] S101, Provide substrate 1.

[0074] S102, A buffer layer 2 is formed on one side of the substrate 1.

[0075] S103, an electron transport layer 3 is formed on the side of the buffer layer 2 away from the substrate 1.

[0076] S104. A semiconductor doped layer 4 is formed on the side of the electron transport layer 3 away from the substrate 1.

[0077] S105, doping is performed on the side of the semiconductor doped layer 4 away from the substrate 1 to form an interrupt layer 5; wherein, along the thickness direction N1 of the semiconductor device, the interrupt layer 5 at least partially covers the semiconductor doped layer 4.

[0078] S106. A gate is formed on the side of the interrupt layer 5 away from the substrate 1.

[0079] S201, Pattern the gate, the interrupt layer 5 and the semiconductor doped layer 4;

[0080] S202, A passivation layer 6 is formed on the side of the patterned gate away from the substrate 1.

[0081] In one alternative implementation, an interruption layer 5 is formed on the side of the semiconductor doped layer 4 away from the substrate 1, which may include forming the interruption layer 5 by pulsed plasma doping.

[0082] In another alternative implementation, after forming a passivation layer 6 on the side of the patterned gate away from the substrate 1, the method further includes forming a source and a drain on the side of the passivation layer away from the substrate.

[0083] The semiconductor device fabrication method provided in this embodiment deposits an interrupt layer 5 between the semiconductor doped layer 4 and the gate, and the interrupt layer 5 at least partially covers the semiconductor doped layer 4 along the thickness direction N1 of the semiconductor device. This allows the interrupt layer 5 to protect the semiconductor doped layer 4, so that during the thin film deposition of hydride gas in subsequent processes such as gate fabrication or cleaning, the interrupt layer 5 can effectively block the penetration of H and prevent H from combining with metal ions in the semiconductor doped layer 4.

[0084] Furthermore, the semiconductor device fabrication method provided in this embodiment employs pulsed plasma nitriding doping to form the interrupt layer 5, which effectively reduces plasma damage and maintains the original quality of the epitaxial semiconductor doped layer 4, such as the P-GaN thin film. This configuration improves the gate voltage control capability of the semiconductor device fabricated by the method provided in this embodiment, reduces the threshold voltage of the semiconductor device, and improves the stability of the semiconductor device.

[0085] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A buffer layer disposed on one side of the substrate; An electron transport layer is disposed on the side of the buffer layer away from the substrate; A semiconductor doped layer disposed on the side of the electron transport layer away from the substrate; An interruption layer disposed on the side of the semiconductor doped layer away from the substrate; A gate is disposed on the side of the interrupt layer away from the substrate; Along the thickness direction of the semiconductor device, the interrupt layer at least partially covers the semiconductor doped layer; The interruption layer is formed by pulsed plasma nitriding doping of the semiconductor doped layer, which includes a P-type doped layer, and the P-type doped layer includes a GaN layer doped with Mg.

2. The semiconductor device according to claim 1, characterized in that, The material of the buffer layer includes GaN; The electron transport layer is made of AlGaN; The gate material includes titanium nitride, tantalum nitride, or tungsten nitride.

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A passivation layer is disposed on the side of the gate away from the substrate.

4. The semiconductor device according to claim 3, characterized in that, The passivation layer is made of an oxide or a nitride.

5. The semiconductor device according to claim 1, characterized in that, The thickness of the interrupted layer ranges from 1 nm to 3 nm.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A first semiconductor layer is disposed between the buffer layer and the electron transport layer; The material of the first semiconductor layer includes aluminum nitride.

7. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A buffer layer is formed on one side of the substrate; An electron transport layer is formed on the side of the buffer layer away from the substrate; A semiconductor doped layer is formed on the side of the electron transport layer away from the substrate; A break layer is formed by doping the semiconductor doped layer on the side away from the substrate; wherein, along the thickness direction of the semiconductor device, the break layer at least partially covers the semiconductor doped layer; A gate is formed on the side of the interrupt layer away from the substrate; the interrupt layer is formed by pulsed plasma nitriding doping of the semiconductor doped layer, the semiconductor doped layer including a P-type doped layer, the P-type doped layer including a Mg-doped GaN layer.

8. The method according to claim 7, characterized in that, After forming the gate on the side of the semiconductor doped layer away from the substrate, the method further includes: Pattern the gate, the interrupt layer, and the semiconductor doped layer; A passivation layer is formed on the side of the patterned gate away from the substrate.

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