High reliability chiplet packaging structure based on adapter plate

Abstract

This invention discloses a high-reliability chiplet packaging structure based on an adapter board, comprising: a packaging substrate; an adapter board located on one side of the packaging substrate, with a first solder ball disposed between the packaging substrate and the adapter board, and an array of the first solder balls arranged between the packaging substrate and the adapter board; multiple bare chips located on the side of the adapter board away from the packaging substrate, with a second solder ball disposed between the adapter board and the bare chips, and an array of the second solder balls arranged between the adapter board and the bare chips; multiple conductive vias disposed on the adapter board, the first solder balls and the second solder balls being electrically connected through the conductive vias, and the second solder balls being soldered to the bare chips; and adhesive, at least partially located in the edge region of the adapter board, used to fix the packaging substrate and the adapter board, provide structural support for the adapter board, release stress on the adapter board, and significantly reduce warpage of the adapter board; along a direction perpendicular to the packaging substrate, the orthographic projection of the adhesive does not overlap with the orthographic projection of the first solder balls. This invention can solve the problem of poor reliability of the adapter board and soldering structure at weak points in the chiplet structure.

Description

Technical Field

[0001] This invention belongs to the field of advanced electronic packaging technology, specifically relating to a high-reliability chiplet packaging structure based on an adapter board. Background Technology

[0002] Chiplet technology is an innovative integrated circuit design methodology that has emerged in recent years. It aims to overcome the limitations of traditional monolithic design and achieve a significant breakthrough in integrated circuits in the post-Moore's Law era. Chiplet technology divides a system-on-a-chip (SoC) into smaller chips and reassembles different chips or components of different sources, sizes, materials, and functions into the system. This can significantly improve the overall yield of the chip, reduce cost-effectiveness and design barriers, shorten time to market, and improve efficiency.

[0003] While chiplet technology offers significant advantages, it also presents numerous challenges. Due to its widespread use in mobile electronic devices, and the integration of dies of varying origins, sizes, materials, and functions into a single package via an adapter board, the close stacking of multiple dies introduces serious drop and thermal reliability issues. Particularly with the advancement of chiplet technology and the increase in the number of integrated dies, the adapter board, as a critical location in chiplet technology, is more susceptible to failure due to drop or thermal reliability problems. The original method of simply connecting and supporting the adapter board using soldered structures is no longer sufficient to meet reliability requirements. A structure is needed that can support the adapter board and improve the drop and thermal reliability of the packaging system to mitigate the failure risk of this critical location in chiplet packaging.

[0004] Therefore, there is an urgent need for a highly reliable chiplet packaging structure to overcome the drop and thermal reliability problems of the aforementioned technologies in the adapter board and soldering structure. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a high-reliability chiplet packaging structure based on an adapter board. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a high-reliability chiplet package structure based on an adapter board, comprising:

[0007] Packaging substrate;

[0008] An adapter board is located on one side of the packaging substrate. A first solder ball is disposed between the packaging substrate and the adapter board. An array of the first solder balls is arranged between the packaging substrate and the adapter board.

[0009] Multiple bare chips are located on the side of the adapter board away from the packaging substrate. A second solder ball is disposed between the adapter board and the bare chips. The second solder ball array is arranged between the adapter board and the bare chips. Multiple conductive holes are disposed on the adapter board. The first solder ball and the second solder ball are electrically connected through the conductive holes. The second solder ball is soldered to the bare chip.

[0010] The adhesive, at least partially located in the edge region of the adapter board, is used to bond the encapsulation substrate and the adapter board; the orthographic projection of the adhesive does not overlap with the orthographic projection of the first solder ball in a direction perpendicular to the encapsulation substrate.

[0011] The beneficial effects of this invention are:

[0012] This invention provides a high-reliability chiplet packaging structure based on an adapter board, comprising a packaging substrate, an adapter board, and multiple bare chips. The packaging substrate and the adapter board are soldered together via first solder balls, and the adapter board and the bare chips are soldered together via second solder balls. Conductive vias are provided on the adapter board to achieve electrical connection between the first and second solder balls, further realizing the electrical connection between the packaging substrate and the bare chips, thus achieving protection and assembly functions. To ensure packaging reliability, an adhesive is also provided, located on the edge area of ​​the adapter board, for bonding the packaging substrate and the adapter board. The adhesive bonding process does not affect the placement of the first solder balls. The adhesive is used to fix the packaging substrate and the adapter board, provide structural support for the adapter board, release stress on the adapter board, and significantly reduce adapter board warpage. This solves the problem of poor reliability of the adapter board and soldering structure in dangerous locations in chiplet structures, and has a significant promoting effect on improving the thermal and mechanical reliability of advanced packaging and chiplet technology.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a high-reliability chiplet packaging structure based on an adapter board provided in an embodiment of the present invention;

[0015] Figure 2 This is a partial schematic diagram of a high-reliability chiplet packaging structure based on an adapter board provided in an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of a bare chip provided in an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of a second solder ball provided in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of an adapter plate and conductive holes provided in an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of a first solder ball provided in an embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of a packaging substrate provided in an embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of an adhesive provided in an embodiment of the present invention;

[0022] Figure 9 This is another schematic diagram of the adhesive provided in an embodiment of the present invention;

[0023] Figure 10 This is another schematic diagram of the high-reliability Chiplet packaging structure based on the adapter board provided in the embodiment of the present invention. Detailed Implementation

[0024] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0025] In existing technologies, the increased number of integrated dies makes the adapter board, a critical location in chiplet technology, more susceptible to failure due to drop or thermal reliability issues. This invention proposes a high-reliability chiplet packaging structure based on an adapter board. Utilizing 3D integrated chiplet technology, it integrates multiple dies at high density and low cost through vias, solder balls, and the adapter board, achieving electrical interconnection. The adhesive between the adapter board and the substrate significantly reduces deformation and stress at critical locations on the adapter board under thermal and drop conditions, effectively mitigating stress and deformation concentration at these locations, thereby substantially improving the reliability of the chiplet packaging structure at critical locations.

[0026] Please see Figures 1-6 As shown, Figure 1 This is a schematic diagram of a high-reliability chiplet packaging structure based on an adapter board provided in an embodiment of the present invention. Figure 2 This is a partial schematic diagram of a high-reliability chiplet packaging structure based on an adapter board provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a bare chip provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of a second solder ball provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of an adapter plate and conductive holes provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of a first solder ball provided in an embodiment of the present invention. The present invention provides a high-reliability chiplet package structure based on an adapter board, comprising:

[0027] Packaging substrate 10;

[0028] The adapter board 20 is located on one side of the packaging substrate 10, and a first solder ball 31 is disposed between the packaging substrate 10 and the adapter board 20. The first solder ball 31 is arranged in an array between the packaging substrate 10 and the adapter board 20.

[0029] Multiple bare chips 40 are located on the side of the adapter board 20 away from the packaging substrate 10, and a second solder ball 32 is disposed between the adapter board 20 and the bare chip 40. The second solder ball 32 is arranged in an array between the adapter board 20 and the bare chip 40. Multiple conductive holes 33 are disposed on the adapter board 20. The first solder ball 31 and the second solder ball 32 are electrically connected through the conductive holes 33, and the second solder ball 32 is soldered to the bare chip 40.

[0030] The adhesive 50 is located at least partially in the edge region of the adapter plate 20 and is used to bond the encapsulation substrate 10 and the adapter plate 20; the orthographic projection of the adhesive 50 and the orthographic projection of the first solder ball 31 do not overlap in the direction perpendicular to the encapsulation substrate.

[0031] Specifically, the present invention provides a high-reliability chiplet packaging structure based on an adapter board, comprising a packaging substrate 10, an adapter board 20, and multiple bare chips 40. The packaging substrate 10 and the adapter board 20 are soldered together by first solder balls 31, and the adapter board 20 and the bare chips 40 are soldered together by second solder balls 32. The adapter board 20 has conductive holes 33 for electrical connection between the first solder balls 31 and the second solder balls 32, further realizing the electrical connection between the packaging substrate 10 and the bare chips 40, achieving the functions of protection and assembly. To ensure the reliability of the packaging, an adhesive 50 is also provided, disposed on the edge area of ​​the adapter board 20, for bonding the packaging substrate 10. The adapter board 20 provides structural support, relieves stress on the adapter board, and significantly reduces warpage. It is understood that the process of bonding the packaging substrate 10 to the adapter board 20 with the adhesive 50 does not affect the placement of the first solder ball 31. By using the adhesive 50, which can be epoxy resin, and employing a dispensing process to bond the packaging substrate 10 to the adapter board 20, the structure is simple, chip utilization is high, the process is simple, and the cost is low. Furthermore, it can further address the poor reliability of the adapter board and soldering structure in dangerous locations within the chiplet structure, thus significantly promoting the improvement of thermal and mechanical reliability in advanced packaging and chiplet technology.

[0032] Optionally, in this embodiment, three bare chips 40 are arranged side by side: bare chip a, bare chip b, and bare chip c. The bare chips 40 can be bare chips of different sources, sizes, materials, and functions, so that different bare chips 40 can use the optimal process technology, thereby reducing costs and improving efficiency.

[0033] Optionally, in this embodiment, the conductive hole 33 is a through hole filled with conductive metal, and signal transmission between the bare chip 40 and the packaging substrate 10 is realized through vertical interconnection.

[0034] Optionally, in this embodiment, both the packaging substrate 10 and the adapter plate 20 are made of silicon.

[0035] Optionally, in this embodiment, the adhesive 50 is made based on the existing dispensing process that is mostly used for board-level circuits. It can be directly applied or quickly applied to the product after modification. The process is simple and the cost is low.

[0036] It should be noted that, Figure 1 The embodiments shown only schematically illustrate the positional relationship between the packaging substrate 10, the adapter plate 20, and the multiple bare chips 40, and do not represent their actual dimensions; Figure 2 The embodiment shown only schematically illustrates the positional relationship between the first solder ball 31, the second solder ball 32, and the conductive hole 33, and does not represent their actual size. The bare chip 40 achieves electrical connection with the packaging substrate 10 through the first solder ball 31, the conductive hole 33, and the second solder ball 32. Figure 3 The embodiment shown is only a schematic diagram of the bare chip 40 and does not represent its actual size. Figure 3 The bare chip 40 has three parallel sections, and multiple parallel sections can also be set, depending on the manufacturing requirements. Figure 4 The embodiment shown is only schematically illustrating one form of the arrangement of the second solder ball 32 array and does not represent its actual size; Figure 5 The embodiments shown are only schematic representations of the arrangement of the adapter plate 20 and the conductive hole 33, and do not represent their actual dimensions; Figure 6 The embodiment shown is only schematically illustrating one form of the array arrangement of the first solder balls 31 and does not represent its actual size.

[0037] In an optional embodiment of the present invention, please refer to Figures 7-8 As shown, and in combination Figure 1 As shown, Figure 7 This is a schematic diagram of a packaging substrate provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of an adhesive provided in an embodiment of the present invention. Along the direction perpendicular to the encapsulation substrate, the orthographic projection of the adapter plate 20 is rectangular, and the adhesive 50 is located at the edge region of the corner of the adapter plate 20.

[0038] For details, please continue to see Figure 7 and Figure 8 As shown, and in combination Figure 1As shown, in this embodiment, adhesive 50 is disposed at the corners of the top surface of the encapsulation substrate 10 and the bottom surface of the adapter plate 20. Adhesive 50 also adheres to the side surface of the adapter plate 20 in the vertical direction. Its function is to provide mechanical support for the dangerous positions of the adapter plate 20, namely the four corners, so that the warping of the adapter plate 20 under thermal and drop conditions is greatly reduced. The good thermal coupling performance and ductility of adhesive 50 significantly reduce the thermal stress and mechanical impact stress of the adapter plate 20.

[0039] Understandably, applying adhesive 50 only to the corner edge areas of the adapter plate 20 can save materials.

[0040] It should be noted that, Figure 7 The embodiments shown are only schematic representations of the structure of the packaging substrate 10 and do not represent its specific dimensions; Figure 8 The illustrated embodiment only shows one form of adhesive 50 and does not represent its actual size.

[0041] In an optional embodiment of the present invention, please refer to Figure 9 As shown, Figure 9 This is another schematic diagram of the adhesive provided in the embodiment of the present invention. Along the direction perpendicular to the packaging substrate, the orthographic projection of the adapter plate 20 is rectangular, and the adhesive 50 is located in the edge region of the side of the adapter plate 20, and at least in the edge region of the opposite side.

[0042] For details, please continue to see Figure 9 As shown, in this embodiment, adhesive 50 is disposed at the edges of the top surface of the encapsulation substrate 10 and the bottom surface of the adapter plate 20. Adhesive 50 also adheres to the side surface of the adapter plate 20 in the vertical direction. Its function is to provide mechanical support for the dangerous positions of the adapter plate 20, i.e., the opposite edges, so that the warping of the adapter plate 20 under thermal and drop conditions is greatly reduced, and the bonding strength is improved. The good thermal coupling performance and ductility of adhesive 50 significantly reduce the thermal stress and mechanical impact stress of the adapter plate 20.

[0043] It should be noted that, Figure 9 The illustrated embodiment only schematically shows that adhesive 50 is provided on the two horizontal sides; or, adhesive can also be provided on the two vertical sides; or, adhesive 50 is provided on both the horizontal and vertical sides.

[0044] In an optional embodiment of the present invention, please continue to refer to Figure 1 As shown, the adhesive 50 at least partially covers at least one first surface of the edge region of the adapter plate 20, wherein the first surface is parallel to the encapsulation substrate 10.

[0045] For details, please continue to see Figure 1As shown, in this embodiment, the adhesive 50 at least partially covers at least one first surface of the edge region of the adapter plate 20. That is, the adhesive 50 is disposed between the lower surface of the adapter plate 20 and the upper surface of the packaging substrate 10, and the first surface is either the lower surface or the upper surface of the adapter plate 20. It can be understood that the adhesive 50 at least bonds the lower surface of the adapter plate 20 to the upper surface of the packaging substrate 10, or the adhesive 50 at least bonds the upper surface of the adapter plate 20 to the upper surface of the packaging substrate 10. It should be noted that the case where one surface of the adapter plate 20 is bonded to the packaging substrate 10 is applicable when the number of bare chips 40 stacked is small.

[0046] In an optional embodiment of the present invention, please continue to refer to Figure 9 As shown, the adhesive 50 at least partially covers two first surfaces of the edge region of the adapter plate 20, wherein the first surfaces are parallel to the encapsulation substrate 10.

[0047] For details, please continue to see Figure 9 As shown, in this embodiment, the adhesive 50 at least partially covers the two first surfaces of the edge region of the adapter plate 20. That is, the adhesive 50 is provided on both the upper and lower surfaces of the adapter plate 20. This is suitable for cases where a large number of bare chips 40 are stacked. It can significantly reduce the warping of the adapter plate 20 under thermal and drop conditions, improve the bonding strength and support for the adapter plate 20, and thus prevent the adapter plate 20 from cracking, poor contact, or even overall failure due to large warping or stress.

[0048] In an optional embodiment of the present invention, please refer to Figure 10 As shown, Figure 10 This is another schematic diagram of a high-reliability chiplet packaging structure based on an adapter board provided in an embodiment of the present invention. In the direction perpendicular to the packaging substrate, multiple layers of bare chips 40 are stacked, and a second solder ball 32 is provided between two adjacent bare chip layers 40.

[0049] Along the direction perpendicular to the packaging substrate 10, the projected area of ​​the adhesive 50 is proportional to the number of bare chips 40 stacked.

[0050] For details, please continue to see Figure 10 As shown in this embodiment, as the number of bare chips 40 stacked increases, in order to ensure the reliability of bonding, the bonding area of ​​adhesive 50 is increased to ensure the bonding strength and further ensure the reliability of packaging.

[0051] In an optional embodiment of the present invention, the ratio of the area of ​​the orthographic projection of the adhesive 50 to the thickness of the adhesive 50 along the direction perpendicular to the packaging substrate 10 is 1000 to 3500.

[0052] Specifically, in this embodiment, as the number of bare chips 40 stacked increases, the bonding area of ​​adhesive 50 increases. However, the bonding area cannot be increased indefinitely. At this time, it is necessary to consider limiting the bonding area and thickness of adhesive 50 so that the maximum total deformation and maximum equivalent stress of the adapter plate 20 are minimized. Otherwise, when the area-to-thickness ratio is low, the probability of generating large stress and cracks increases significantly, and when the area-to-thickness ratio is high, the probability of generating large deformation leading to warping failure increases significantly.

[0053] Optionally, in this embodiment, the area of ​​the adapter plate 20 is 392 mm². 2 The thickness of the adapter plate 20 is 0.18mm, and the ratio of the bonding area of ​​the adhesive 50 to the thickness of the adhesive 50 is 2177.777.

[0054] It should be noted that as the number of stacked layers (40) of the bare die increases, the length and width of the adhesive (50) should be increased, but care should be taken to avoid contact with the internal solder balls. Simultaneously, as the number of stacked layers continues to increase, the area-to-thickness ratio should be reduced to improve reliability.

[0055] In an optional embodiment of the invention, the coefficient of thermal expansion of adhesive 50 is less than 55 ppm / K.

[0056] Specifically, in this embodiment, both the adapter board 20 and the packaging substrate 10 are made of silicon and are bonded together using St8202 adhesive.

[0057] In an optional embodiment of the present invention, redistribution RDLs are provided on both the packaging substrate 10 and the adapter plate 20. A plurality of through redistribution RDL layers and a first solder ball 31 are provided at the position corresponding to the position of the conductive hole 33 on the bottom surface of the adapter plate 20 for electrical interconnection. A plurality of through redistribution RDL layers and a second solder ball 32 are provided at the position corresponding to the position of the conductive hole 33 on the top surface of the adapter plate 20 for electrical interconnection.

[0058] In an optional embodiment of the present invention, the beneficial effects of the packaging structure of the above-described embodiments of the present invention are verified through simulation experiments.

[0059] The finite element simulation results in Ansys Workbench software comparing the packaging structure before and after adding adhesive 50 showed that after adding adhesive 50, the maximum total deformation of the adapter plate 20 in the drop test decreased from 0.04186 mm to 0.01721 mm, a reduction of 59.3%; the maximum total deformation at the four dangerous corners of the adapter plate 20 decreased from 0.04186 mm to 0.00084 mm, a reduction of 97.9%; the maximum equivalent stress of the adapter plate 20 decreased from 397.54 MPa to 119.65 MPa, a reduction of 69.9%; and after adding adhesive 50, the maximum total deformation at the dangerous locations of the adapter plate 20 under thermal cycling conditions decreased from 0.01108 mm to 0.00480 mm, a reduction of 57.7%. Therefore, the present invention can significantly reduce the total deformation and stress at dangerous locations in multi-chip Chiplet / SiP system-in-package structures, thereby improving the reliability of such packages. In this way, the adhesive 50 in the present invention provides fixed support for the corners of the adapter board 20. Compared with the traditional base filler used for chip soldering, corner bonding is more suitable for thinner, larger-area adapter boards 20 with many soldering structures. There is no problem of loose bonding with the soldering structure, which can improve the yield of the package structure.

[0060] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0062] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-reliability chiplet packaging structure based on an adapter board, characterized in that, include: Packaging substrate; An adapter board is located on one side of the packaging substrate, and a first solder ball is disposed between the packaging substrate and the adapter board. The first solder ball array is arranged between the packaging substrate and the adapter board. Multiple bare chips are located on the side of the adapter board away from the packaging substrate. A second solder ball is disposed between the adapter board and the bare chips. The second solder ball array is arranged between the adapter board and the bare chips. Multiple conductive holes are disposed on the adapter board. The first solder ball and the second solder ball are electrically connected through the conductive holes. The second solder ball is soldered to the bare chip. An adhesive, at least partially located in the edge region of the adapter plate, is used to bond the encapsulation substrate to the adapter plate; Along a direction perpendicular to the packaging substrate, the orthographic projection of the adhesive does not overlap with the orthographic projection of the first solder ball.

2. The high-reliability chiplet packaging structure based on an adapter board according to claim 1, characterized in that, Along a direction perpendicular to the packaging substrate, the orthographic projection of the adapter plate is rectangular, and the adhesive is located at the edge region of the corner of the adapter plate.

3. The high-reliability chiplet packaging structure based on an adapter board according to claim 1, characterized in that, Along a direction perpendicular to the packaging substrate, the orthographic projection of the adapter plate is rectangular, and the adhesive is located at the edge region of the edge of the adapter plate, and at least at the edge region of the opposite edge.

4. The high-reliability chiplet packaging structure based on an adapter board according to claim 2 or 3, characterized in that, The adhesive at least partially covers at least one first surface of the edge region of the adapter plate, wherein the first surface is parallel to the encapsulation substrate.

5. The high-reliability chiplet packaging structure based on an adapter board according to claim 2 or 3, characterized in that, The adhesive at least partially covers two first surfaces of the edge region of the adapter plate, wherein the first surfaces are parallel to the encapsulation substrate.

6. The high-reliability chiplet packaging structure based on an adapter board according to claim 1, characterized in that, Along a direction perpendicular to the packaging substrate, the bare chip is stacked in multiple layers, and a second solder ball is disposed between two adjacent bare chip layers; Along a direction perpendicular to the packaging substrate, the projected area of ​​the adhesive is proportional to the number of bare chips stacked.

7. The high-reliability chiplet packaging structure based on an adapter board according to claim 6, characterized in that, Along a direction perpendicular to the packaging substrate, the ratio of the area of ​​the orthographic projection of the adhesive to the thickness of the adhesive is 1000 to 3500.

8. The high-reliability chiplet packaging structure based on an adapter board according to claim 1, characterized in that, The coefficient of thermal expansion of the adhesive is less than 55 ppm / K.

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