semiconductor structure

Abstract

This disclosure relates to the field of semiconductor technology, providing a semiconductor structure comprising: a plurality of word lines extending along a first direction and spaced apart along a third direction; a plurality of semiconductor channels extending along a second direction and spaced apart along a third direction, with the word lines surrounding the semiconductor channels along the third direction upward, the first direction, the second direction, and the third direction intersecting each other; a stepped structure including a plurality of steps, the steps being in contact with the word lines, the top surface height of any step being different from the top surface height of another step along the third direction upward, and the steps being arranged in an array along the first and second directions, with adjacent steps being electrically insulated from each other; and a plurality of contact structures, the contact structures being in contact with the steps, with any two contact structures spaced apart from each other. This disclosure at least helps to reduce interference between adjacent word lines while reducing the semiconductor structure layout area.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Technology

[0002] In two-dimensional or planar semiconductor devices, memory cells are arranged horizontally. Therefore, the integration density of two-dimensional or planar semiconductor devices can be determined by the area occupied by a single memory cell. Consequently, the integration density of two-dimensional or planar semiconductor devices is greatly affected by the technology used to form fine patterns, limiting the potential for further increases in integration density. Therefore, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.

[0003] However, the layout of memory cells and the interconnection of various functional devices in current three-dimensional semiconductor devices require completely new designs. For example, while saving the layout area of ​​semiconductor devices, how to lead out word lines in semiconductor devices to achieve electrical connection with peripheral logic circuits is an urgent issue to consider. Summary of the Invention

[0004] This disclosure provides a semiconductor structure that at least helps to reduce interference between adjacent word lines while reducing the semiconductor structure layout area.

[0005] This disclosure provides a semiconductor structure, comprising: a plurality of word lines extending along a first direction and spaced apart along a third direction; a plurality of semiconductor channels extending along a second direction and spaced apart along the third direction, the word lines surrounding the semiconductor channels along the third direction upwards, the first direction, the second direction, and the third direction intersecting each other; a stepped structure including a plurality of steps, the steps being in contact with the word lines, the top surface height of any step being different from the top surface height of another step along the third direction upwards, and the steps being arranged in an array along the first direction and the second direction, and adjacent steps being electrically insulated from each other; and a plurality of contact structures, the contact structures being in contact with the steps, and any two contact structures being spaced apart from each other.

[0006] In some embodiments, the semiconductor channels are arranged along the first direction and the third direction array, and the word lines surround the plurality of semiconductor channels arranged along the first direction.

[0007] In some embodiments, along a direction away from the letter line, the top surface height of the plurality of steps arranged in the first direction gradually decreases, and the top surface height of the plurality of steps arranged in the second direction also gradually decreases.

[0008] In some embodiments, the steps include a plurality of step groups arranged along the first direction, and the step groups include a plurality of steps arranged along the second direction. The step group closer to the letter line is a first step group, and the step group adjacent to the side of the first step group away from the letter line is a second step group. The step with the lowest top surface height in the first step group is a first reference step, and the step with the highest top surface height in the second step group is a second reference step. The top surface height of the first reference step is higher than the top surface height of the second reference step.

[0009] In some embodiments, along the third direction upwards, the top surface height of the step is flush with the top surface height of the letter line structure.

[0010] In some embodiments, the top surface of the contact structure is flush with the third direction, and the step includes a plurality of first steps arranged along the first direction, and a plurality of contact structures that are in contact with and connected to the plurality of first steps are arranged at intervals along the second direction.

[0011] In some embodiments, the contact structure includes: a conductive post and a lead-out layer, one end of the conductive post being in contact with the step, and the other end of the conductive post being in contact with the lead-out layer, the lead-out layer extending along the first direction and arranged at intervals along the second direction.

[0012] In some embodiments, the semiconductor structure further includes: bit lines that are contacted and connected to a plurality of semiconductor channels arranged along the third direction.

[0013] In some embodiments, the semiconductor structure further includes: a plurality of capacitor structures, the capacitor structures being contacted and connected to the side of the semiconductor channel away from the bit line, the capacitor structures extending along the second direction.

[0014] In some embodiments, the second direction and the third direction constitute a reference plane, the plurality of capacitor structures constitute a capacitor region, and the orthographic projection of the stepped structure on the reference plane at least partially coincides with the orthographic projection of the capacitor region on the reference plane.

[0015] In some embodiments, along the second direction, the bit line includes opposing first and second ends; the semiconductor channel includes: a plurality of first semiconductor channels contacting and connected to the first end, and a plurality of second semiconductor channels contacting and connected to the second end; the word line includes: a plurality of first word lines surrounding the first semiconductor channel, and a plurality of second word lines surrounding the second semiconductor channel, wherein along the first direction, the first word line and the second word line each have opposing first and second sides; the step structure includes: a first step structure contacting and connected to the first word line, and a second step structure contacting and connected to the second word line, wherein the first step structure is contacted and connected to one of the first side or the second side, and the second step structure is contacted and connected to the other of the first side or the second side.

[0016] In some embodiments, the bit line, the word line, the step structure, the contact structure, and the capacitor structure constitute a memory cell group; the semiconductor structure includes a plurality of the memory cell groups spaced apart along the second direction.

[0017] In some embodiments, the contact structure includes: a first contact structure that is in contact with the first step structure, and a second contact structure that is in contact with the second step structure; the semiconductor structure further includes: a first word line driver located on the side of the first step structure away from the first word line, and the first word line driver is electrically connected to all the first contact structures; and a second word line driver located on the side of the second step structure away from the second word line, and the second word line driver is electrically connected to all the second contact structures.

[0018] In some embodiments, the semiconductor structure further includes: a first sensing amplifier electrically connected to the first contact structure; and a second sensing amplifier electrically connected to the second contact structure.

[0019] In some embodiments, along the third upward direction, there is a first interval between adjacent steps, and the step structure further includes: a plurality of insulating layers, one of the insulating layers at least filling one of the first intervals.

[0020] The technical solution provided in this disclosure has at least the following advantages:

[0021] With word lines spaced apart along a third direction, different word lines are located in different height ranges along this direction. The steps in the stepped structure connect to the word lines, and along this direction, the top height of any step differs from that of another step. This ensures a one-to-one correspondence between steps and word lines, allowing the word lines to be led out through the steps. Furthermore, contact structures connect to the steps to further lead out the word lines, and the spacing between any two contact structures helps prevent contact with contact structures corresponding to different word lines, reducing interference between different word lines. In addition, the steps are arrayed along the first and second directions, avoiding the stepped structure extending only along either direction. This makes efficient use of layout space and helps reduce the total layout area of ​​the semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1 to 4 These are schematic diagrams of four three-dimensional structures of semiconductor structures provided in the embodiments of this disclosure;

[0024] Figure 5 for Figure 3 and Figure 4 A three-dimensional schematic diagram of the stepped structure in the provided semiconductor structure;

[0025] Figure 6 A top view schematic diagram of the stepped structure and contact structure in a semiconductor structure provided in an embodiment of this disclosure;

[0026] Figure 7 A three-dimensional structural diagram of a semiconductor structure;

[0027] Figure 8 This is a top view schematic diagram of the bit line, word line, and semiconductor channel in a semiconductor structure provided in an embodiment of this disclosure.

[0028] Figure 9 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0029] As can be seen from the background technology, the way word lines are electrically connected to peripheral logic circuits in semiconductor devices needs to be optimized.

[0030] This disclosure provides a semiconductor structure in which word lines are spaced apart along a third direction. Different word lines are located at different height ranges along this direction. Steps in the stepped structure are in contact with the word lines, and along the third direction, the top surface height of any step differs from that of another step. This facilitates a one-to-one correspondence between steps and word lines, allowing the word lines to be led out through the steps. Furthermore, contact structures are in contact with the steps to further lead out the word lines. Any two contact structures are spaced apart to prevent contact with contact structures corresponding to different word lines, thus reducing interference between different word lines. In addition, the steps are arrayed along a first direction and a second direction, avoiding the stepped structure extending only along either direction. This rationally utilizes the layout space and helps reduce the total layout area of ​​the semiconductor structure.

[0031] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0032] This disclosure provides a semiconductor structure according to one embodiment. The manufacturing method of the semiconductor structure provided by this disclosure will be described in detail below with reference to the accompanying drawings. Figures 1 to 4 These are schematic diagrams of four three-dimensional structures of semiconductor structures provided in the embodiments of this disclosure; Figure 5 for Figure 3 and Figure 4 A three-dimensional schematic diagram of the stepped structure in the provided semiconductor structure; Figure 6 A top view schematic diagram of the stepped structure and contact structure in a semiconductor structure provided in an embodiment of this disclosure; Figure 7 A three-dimensional structural diagram of a semiconductor structure; Figure 8 This is a top view schematic diagram of the bit line, word line, and semiconductor channel in a semiconductor structure provided in an embodiment of this disclosure. Figure 9 A top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0033] It should be noted that, for ease of description and clear illustration of the semiconductor structure, Figures 1 to 6 as well as Figure 8 and Figure 9 These are partial structural diagrams of the semiconductor structures provided in the embodiments of this disclosure. Furthermore, to more clearly show the distribution of steps in the stepped structure, Figure 1Only a portion of the contact structure is shown in the diagram. Figure 3 The contact structure is not shown in the diagram.

[0034] refer to Figures 1 to 5 The semiconductor structure includes: a plurality of word lines 100 extending along a first direction X and spaced apart along a third direction Z; a plurality of semiconductor channels 101 extending along a second direction Y and spaced apart along a third direction Z, with the word lines 100 surrounding the semiconductor channels 101 along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersecting each other; a stepped structure 102 including a plurality of steps 112, the steps 112 being in contact with the word lines 100, with the top surface height of any step 112 being different from the top surface height of another step 112 along the third direction Z, and the steps 112 being arranged in an array along the first direction X and the second direction Y, and adjacent steps 112 being electrically insulated from each other; and a plurality of contact structures 103, the contact structures 103 being in contact with the steps 112, and any two contact structures 103 being spaced apart from each other.

[0035] It should be noted that the reference Figure 1 and Figure 2 The word line 100 includes a gate dielectric layer 110 and a gate 120. The gate dielectric layer 110 surrounds a portion of the sidewall of the semiconductor channel 101, and the gate dielectric layer 110 corresponds one-to-one with the semiconductor channel 101. The gate 120 extends along a first direction X and surrounds the sidewall of the gate dielectric layer 110. The gate dielectric layer 110 is made of an insulating material, and the gate 120 is made of a conductive material.

[0036] In some embodiments, the stepped structure 102 includes sub-steps 122 arranged along a first direction X and / or a second direction Y, and some of the sub-steps 122 constitute a step 112.

[0037] Figure 1 and Figure 2The diagram only shows four character lines 100 arranged at Z intervals along the third direction. Along the direction from the contact structure 103 to the step 112, they include the first character line, the second character line, the third character line, and the fourth character line in sequence. The steps 112, which are set on the same level as the first character line, include one sub-step 122; the steps 112, which are set on the same level as the second character line, include two sub-steps 122, and one more sub-step 122 along the first direction X compared to the one sub-step 122 corresponding to the first character line, and the contact structure 103 corresponding to the second character line is in contact with the additional sub-step 122; the steps 112, which are set on the same level as the third character line, include three sub-steps 122, and one more sub-step 122 along the second direction Y compared to the two sub-steps 122 corresponding to the second character line, and the contact structure 103 corresponding to the third character line is in contact with the additional sub-step 122; the steps 112, which are set on the same level as the fourth character line, include four sub-steps 122, and one more sub-step 122 along the first direction X compared to the three sub-steps 122 corresponding to the third character line, and the contact structure 103 corresponding to the fourth character line is in contact with the additional sub-step 122. In this way, the step 112 is arranged in an array along the first direction X and the second direction Y, and the two contact structures 103 are spaced apart from each other, which helps to prevent contact with the contact structures 103 corresponding to different word lines 100, thereby reducing interference between different word lines 100.

[0038] It should be noted that, Figure 1 and Figure 2 This example uses only four word lines 100; in practical applications, there is no limitation on the number of word lines 100 included in the semiconductor structure. Furthermore, Figure 1 and Figure 2 In order to show the difference between the steps 112 that are in contact with the word lines 100 located in different layers, the difference is presented by the number and arrangement of the sub-steps 122 contained in the steps 112 located in different layers. In practical applications, a single step 112 can be composed of multiple independent sub-steps 122, that is, multiple sub-steps 122 are prepared separately, or a single step 112 itself is an integral structure. The sub-steps 122 are only features defined to show the differences between different steps 112, that is, the multiple sub-steps 122 that make up a single step 112 are an integral structure.

[0039] Figure 3 and Figure 4 The image only shows eight character lines 100 arranged at Z intervals along the third direction, and references... Figure 5In step 112, a maximum of 2 sub-steps 122 are arranged along the first direction X and a maximum of 4 sub-steps 122 are arranged along the second direction Y. Moreover, the number of sub-steps 122 with exposed top surfaces in the step structure 102 is 8. The top surfaces of these 8 sub-steps 122 are in contact with different contact structures 103 to provide signals to different word lines 100 through different contact structures 103.

[0040] It should be noted that, Figure 3 and Figure 4 This example uses only eight word lines 100; in practical applications, there is no limitation on the number of word lines 100 included in the semiconductor structure. Furthermore, Figures 3 to 5 In order to show the difference between the steps 112 that are in contact with the word lines 100 located in different layers, the difference is presented by the number and arrangement of the sub-steps 122 contained in the steps 112 located in different layers. In practical applications, a single step 112 can be composed of multiple independent sub-steps 122, that is, multiple sub-steps 122 are prepared separately, or a single step 112 itself is an integral structure. The sub-steps 122 are only features defined to show the differences between different steps 112, that is, the multiple sub-steps 122 that make up a single step 112 are an integral structure.

[0041] In some embodiments, the steps 112 in the stepped structure 102 correspond one-to-one with the word lines 100, that is, one step 112 is in contact with one word line 100, so that different contact structures 103 can provide signals to different word lines 100 through different steps 112.

[0042] In some embodiments, continue to refer to Figures 1 to 4 Semiconductor channels 101 are arranged in an array along a first direction X and a third direction Z. Word lines 100 surround the multiple semiconductor channels 101 arranged along the first direction X. Thus, along the third direction Z, multiple semiconductor channels 101 located on the same layer are controlled by the same word line 100, and multiple semiconductor channels 101 located on different layers are controlled by different word lines 100. It should be noted that... Figure 1 and Figure 2 Taking the character line 100 surrounding three semiconductor channels 101 arranged along the first direction X as an example, Figure 3 and Figure 4 Taking the example of four semiconductor channels 101 arranged along the first direction X around the word line 100, in actual applications, the number of semiconductor channels 101 arranged along the first direction X around the same word line 100 is not displayed, such as 6 or 8, etc.

[0043] In some embodiments, reference Figure 5Along the direction away from the character line 100, the top surface height of several steps 112 arranged along the first direction X gradually decreases, and the top surface height of several steps 112 arranged along the second direction Y also gradually decreases. In this way, on the one hand, an array arrangement of steps 112 along the first direction X and the second direction Y is achieved; on the other hand, along the third direction Z, it is beneficial to ensure that the top surface height of any step 112 is different from the top surface height of another step 112. It should be noted that... Figures 1 to 5 In the middle, along the direction away from the character line 100, the top surface height of several steps 112 arranged along the first direction X all show a gradually decreasing trend, and the top surface height of several steps 112 arranged along the second direction Y also shows a gradually decreasing trend. In practical applications, there is no restriction on the variation trend of the top surface height of different steps 112 in the stepped structure 102 along the first direction X and the second direction Y, as long as the top surface height of any step 112 is different from the top surface height of another step 112.

[0044] Among them, continue to refer to Figure 3 and Figure 5 Step 112 includes several step groups arranged along the first direction X, and step groups include several steps 112 arranged along the second direction Y. The step group closest to the word line 100 is the first step group 132, and the step group adjacent to the side of the first step group 132 away from the word line 100 is the second step group 142. The step 112 with the lowest top surface height in the first step group 132 is the first reference step 1, and the step 112 with the highest top surface height in the second step group 142 is the second reference step 162. The top surface height of the first reference step 152 is higher than the top surface height of the second reference step 162.

[0045] It should be noted that, Figures 3 to 5 The stepped structure 102 shown is only one specific example, that is Figure 5 One set of steps includes four steps 112, and the staircase structure 102 includes two sets of steps. In practical applications, there are no restrictions on the arrangement of different steps 112 in the staircase structure 102, as long as the top surface height of any step 112 is different from the top surface height of another step 112. For example, in one example, the staircase can also include several sets of steps arranged along a second direction, and each set of steps includes several steps arranged along a first direction. For example, when it is necessary for the eight letter lines to contact and connect with eight steps with different top surface heights, the staircase structure 102 can include four sets of steps along the second direction, and each set of steps includes two steps 112.

[0046] In some embodiments, reference Figure 5Along the third direction Z, there is a first interval between adjacent steps 112. The step structure 102 also includes a plurality of insulating layers 107, each insulating layer 107 filling at least one first interval. In this way, electrical insulation between different steps 112 is achieved through the insulating layers 107.

[0047] In some embodiments, reference Figures 1 to 4 Along the Z-direction, the top surface height of step 112 is flush with the top surface height of word line 100. This has two advantages: firstly, it allows one end face of step 112 to fully align with one end face of word line 100, increasing the contact area between step 112 and word line 100 and reducing contact resistance; secondly, the flush alignment of the top surface height of step 112 with the top surface height of word line 100 improves the overall stability of the semiconductor structure and allows for simultaneous fabrication of step 112 and word line 100, simplifying the semiconductor fabrication process.

[0048] In some embodiments, reference Figure 6 Along the third direction Z, the top surface of the contact structure 103 is flush with the height of the step 112, which includes a number of first steps 172 arranged along the first direction X, and a number of contact structures 103 that are in contact with and connected to the number of first steps 172 are arranged at intervals along the second direction Y.

[0049] It is understandable that several first steps 172 arranged along the first direction X are located on different layers, and the cross section perpendicular to the third direction Z is used as the first reference plane. The orthographic projections of several first steps 172 on the first reference plane overlap. In this way, several contact structures 103 that are in contact with several first steps 172 are arranged at intervals along the second direction Y. This helps to avoid the overlap of the orthographic projections of contact structures 103 that are in contact with different first steps 172 on the first reference plane. When the top surfaces of the contact structures 103 are at the same height, it avoids interference caused by contact between different contact structures 103, so that any two contact structures 103 are spaced apart from each other to prevent contact with contact structures 103 corresponding to different word lines 100.

[0050] It should be noted that, Figure 6Taking the stepped structure 102, comprising 64 steps 112 arranged in an 8x8 array as an example, that is, 8 steps 112 are arranged along the first direction X and 8 steps 112 are arranged along the second direction Y. In practical applications, there is no limit to the number of steps 112 included in the stepped structure 102, as long as the number of steps 112 is consistent with the number of letter lines 100. Moreover, in practical applications, there is no limit to the number of steps 112 arranged along the first direction X and the second direction Y; the arrangement of steps 112 along the first direction X and the second direction Y can be designed according to actual needs.

[0051] refer to Figure 7 The semiconductor structure may include: a plurality of word lines 100 extending along a first direction X and spaced apart along a third direction Z; a plurality of semiconductor channels 101 extending along a second direction Y and spaced apart along a third direction Z, with the word lines 100 surrounding the semiconductor channels 101 along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersecting each other. Furthermore... Figure 7 In the first direction X, different word lines 100 have different extension lengths, so connecting posts 130 can be set at the points where the extension lengths of different word lines 100 differ. Subsequently, different connecting posts 130 are connected to different conductive layers (not shown in the figure) to provide signals to different word lines 100 through different conductive layers.

[0052] However, the section perpendicular to the third direction Z is the first reference plane. Figure 7 If the orthographic projections of the four word lines 100 on the first reference plane overlap, then the following situation exists: the connecting post 130 that contacts and connects to different word lines 100 has the same coordinate in the second direction Y. When the conductive layer that subsequently contacts and connects to the connecting post 130 extends along the first direction X, if the top surfaces of different conductive layers are flush, that is, the coordinates of the contact points between different conductive layers and word lines 100 are the same in the third direction Z, since the coordinates of different connecting posts 130 are the same in the second direction Y, the coordinates of the contact points between different conductive layers and word lines 100 are also the same in the second direction Y. Therefore, the coordinates of the contact points between different conductive layers and word lines 100 are the same in the second direction Y and the same in the third direction Z, so that different conductive layers will contact each other when extending along the first direction X.

[0053] Moreover, by extending different character lines 100 along the first direction X, different connecting posts 130 are spaced apart in the third direction Z. As the number of character lines 100 increases, the overall layout area of ​​multiple character lines 100 in the first direction X will gradually increase.

[0054] also, Figure 7 The semiconductor structure includes bit line 104 and capacitor structure 105, and bit line 104 and capacitor structure 105 are connected to... Figures 1 to 4 Similar to those in the text, I will not elaborate further here.

[0055] refer to Figure 1 and Figure 2 In the semiconductor structure, the steps 112 in the stepped structure 102 are arranged in an array along the first direction X and the second direction Y. (Comparative Reference) Figure 7 as well as Figure 1 and Figure 2 , Figure 1 and Figure 2 In the semiconductor structure, as the number of word lines 100 increases, the steps 112 can be arranged along both the first direction X and the second direction Y, instead of just along one direction. This allows for the rational use of the layout space of the semiconductor structure and reduces the total layout area of ​​the semiconductor structure.

[0056] refer to Figures 1 to 5 In a semiconductor structure, along the third direction Z, the top surface height of any step 112 is different from the top surface height of another step 112. This facilitates a one-to-one correspondence between steps 112 and word lines 100, meaning that a step 112 and a word line 100 can be located in the same layer. Furthermore, referring to... Figure 6 Several contact structures 103, which are in contact with several first steps 172, are arranged at intervals along the second direction Y.

[0057] Comparison Reference Figure 7 as well as Figures 1 to 6 , Figures 1 to 6 In the provided semiconductor structure, the contact points of different contact structures 103 and steps 112 have different coordinates in the first direction X and in the second direction Y. Therefore, when the top surface of the contact structure 103 is flush with the top surface and the contact structure 103 extends along the first direction X, there will be no contact between different contact structures 103, so as to ensure that any two contact structures 103 are spaced apart from each other. This helps to prevent contact between contact structures 103 corresponding to different word lines 100, thereby reducing interference between different word lines 100.

[0058] It should be noted that when the number of word lines 100 in the semiconductor structure is small, by... Figure 7 The way in which the different word lines 100 extend along the first direction X makes the different connecting posts 130 spaced apart from each other in the third direction Z, and controls the different heights of the different connecting posts 130 along the third direction Z, can also prevent them from contacting the conductive layers corresponding to the different word lines 100, thereby reducing interference between the different word lines 100.

[0059] In some embodiments, reference Figures 1 to 4The contact structure 103 may include conductive posts 113 and lead-out layers 123. One end of the conductive post 113 is in contact with the step 112, and the other end of the conductive post 113 is in contact with the lead-out layer 123. The lead-out layer 123 extends along a first direction X and along a second direction Y, and the lead-out layers 123 are arranged at intervals. It can be understood that the conductive posts 113 are spaced apart from each other, and the lead-out layers 123 are spaced apart from each other, thereby achieving mutual spacing between the contact structure 103 composed of conductive posts 113 and lead-out layers 123.

[0060] In some embodiments, reference Figures 1 to 4 The semiconductor structure may also include: bit lines 104, which are contacted and connected to a plurality of semiconductor channels 101 arranged along the third direction Z.

[0061] It should be noted that, Figure 1 and Figure 2 Taking the example of a semiconductor structure comprising four semiconductor channels 101 arranged along the third direction Z and three bit lines 104, the number of such channels 101 is four. Figure 3 and Figure 4 In this example, the number of semiconductor channels 101 arranged along the third direction Z is 8, and the semiconductor structure includes 4 bit lines 104. In practical applications, there is no limit to the number of semiconductor channels 101 arranged along the third direction Z, or the number of bit lines 104 included in the semiconductor structure; both can be reasonably set according to actual needs.

[0062] In some embodiments, reference Figures 1 to 4 The semiconductor structure may further include: a plurality of capacitor structures 105, wherein the capacitor structures 105 are contacted and connected to the side of the semiconductor channel 101 away from the bit line 104, and the capacitor structures 105 extend along the second direction Y.

[0063] In some embodiments, reference Figures 3 to 5 The stepped structure 102 may include sub-steps 122 arranged along a first direction X and / or a second direction Y, wherein the number of sub-steps 122 arranged along the second direction Y is greater than the number arranged along the first direction X. Since the capacitor structure 105 occupies a larger layout length in the second direction Y, see reference... Figures 3 to 5 This ensures that the number of sub-steps 122 arranged along the second direction Y in the stepped structure 102 is greater than the number arranged along the first direction X. This also ensures that the stepped structure 102 occupies as much layout length as possible in the second direction Y, so that more stepped structures 102 are located in the area directly opposite the capacitor structure 105. This is beneficial to reduce the layout length of the semiconductor structure in the first direction X without increasing the layout length of the semiconductor structure in the second direction Y, thereby reducing the layout length of the semiconductor structure in the first direction X, achieving reasonable utilization of layout space and reducing the total layout area of ​​the semiconductor structure.

[0064] The following is Figure 5 For an example, the arrangement of sub-steps 122 will be explained in detail. Please refer to [reference needed]. Figure 5 The number of sub-steps 122 contained in each step 112 on different levels is different. In the first step group 132, the sub-steps 122 in each step 112 are arranged only along the second direction Y. In the second step group 142, the sub-steps 122 in each step 112 are arranged along both the first direction X and the second direction Y. In practical applications, some steps 112 may also have sub-steps 122 arranged only along the first direction X.

[0065] It should be noted that, Figures 1 to 4 This diagram only illustrates the general structure of capacitor structure 105 and does not restrict the positional relationships of the upper electrode layer, capacitor dielectric layer, and lower electrode layer in capacitor structure 105. Furthermore, for clarity and visual appeal, Figure 3 and Figure 4 The semiconductor channel 101 is characterized by a combined structure 106 (reference). Figure 1 ) and capacitor structure 105 (reference) Figure 1 ).

[0066] In some embodiments, reference Figures 1 to 5 The second direction Y and the third direction Z form a reference plane. A plurality of capacitor structures 105 constitute a capacitor region. The orthographic projection of the stepped structure 102 onto the reference plane at least partially coincides with the orthographic projection of the capacitor region onto the reference plane, meaning that the stepped structure 102 is at least partially located in the region directly opposite the capacitor region. Thus, under the premise that the layout length of the semiconductor structure in the second direction Y is determined by the layout length of the capacitor region in the second direction Y, it is possible to arrange as many stepped structures 102 as possible along the second direction without increasing the layout length of the stepped structure 102 in the first direction X. This facilitates reducing the layout length of the stepped structure 102 in the first direction X without increasing the layout length of the semiconductor structure in the second direction Y, thereby reducing the layout length of the semiconductor structure in the first direction X, achieving rational utilization of the layout space and reducing the total layout area of ​​the semiconductor structure.

[0067] In some embodiments, in conjunction with reference Figure 8 and Figure 9 Along the second direction Y, bit line 104 includes a first end 114 and a second end 124 opposite to each other; semiconductor channel 101 (reference) Figure 1 It may include: a plurality of first semiconductor channels 111 connected to the first terminal 114, and a plurality of second semiconductor channels 121 connected to the second terminal 124; word line 100 (reference) Figure 1The first word line 140 may include a plurality of first word lines 140 surrounding the first semiconductor channel 111 and a plurality of second word lines 150 surrounding the second semiconductor channel 121, wherein along the first direction X, the first word lines 140 and the second word lines 150 each have opposing first sides 160 and second sides 170; a stepped structure 102 (see reference). Figure 1 It includes: a first step structure 182 that is in contact with the first letter 140, and a second step structure 192 that is in contact with the second letter 150, wherein the first step structure 182 is in contact with one of the first side 160 or the second side 170, and the second step structure 192 is in contact with the other of the first side 160 or the second side 170.

[0068] Understandably, capacitor structure 105 (reference) Figure 1 It may also include: a first capacitor structure (not shown in the figure) that is in contact with the first semiconductor channel 111, and a second capacitor structure (not shown in the figure) that is in contact with the second semiconductor channel 121.

[0069] Thus, both ends of the bit line 104 along the second direction Y can form different transistor structures with different word lines 100 and semiconductor channels 101. The transistor structures on both sides form multiple memory cells with the corresponding capacitor structures on both sides, which is beneficial to further improve the integration density of the semiconductor structure.

[0070] It should be noted that, Figure 9 The position line in the middle of the line is marked with position line 104 (reference). Figure 1 The area where ) is located, Figure 9 In the example, the first stepped structure 182 is connected to the first side 160, and the second stepped structure 192 is connected to the second side 170. In practical applications, the first stepped structure 182 can be connected to the second side 170, and the second stepped structure 192 can be connected to the first side 160. Furthermore, Figure 8 It can be Figure 9 A partial top view of a stepped structure 102.

[0071] In some embodiments, in conjunction with reference Figure 1 and Figure 9 Bit line 104, word line 100, step structure 102, contact structure 103 and capacitor structure 105 constitute a memory cell group 108; the semiconductor structure includes a plurality of memory cell groups 108 arranged at intervals along the second direction Y.

[0072] It should be noted that, Figure 9Taking the semiconductor structure including eight memory cell groups 108 spaced apart along the second direction Y as an example, in practical applications, the number of memory cell groups 108 spaced apart along the second direction Y in the semiconductor structure is not limited, and the number of memory cell groups 108 can be reasonably set according to the storage capacity requirements of the semiconductor structure.

[0073] In some embodiments, in conjunction with reference Figure 6 , Figure 8 and Figure 9 The contact structure 103 may include: a first contact structure (not shown) that is in contact with the first step structure 182, and a second contact structure (not shown) that is in contact with the second step structure 192; the semiconductor structure may also include: a first word line driver 118 located on the side of the first step structure 182 away from the first word line 140, and the first word line driver 118 is electrically connected to all the first contact structures; a second word line driver 128 located on the side of the second step structure 192 away from the second word line 150, and the second word line driver 128 is electrically connected to all the second contact structures.

[0074] Understandably, the first word line driver 118 is used to provide a signal to the first word line 140 through the first contact structure, and the second word line driver 128 is used to provide a signal to the second word line 150 through the second contact structure.

[0075] In some embodiments, continue to refer to Figure 9 The semiconductor structure may further include: a first sensing amplifier 109 electrically connected to the first contact structure; and a second sensing amplifier 119 electrically connected to the second contact structure.

[0076] It should be noted that, Figure 9 The examples illustrate how the first word line driver 118 and the second word line driver 128 are located on either side of the memory cell group 108 along the first direction X, i.e., on the left and right sides respectively, and how the first sensing amplifier 109 and the second sensing amplifier 119 are located on either side of the memory cell group 108 along the second direction Y, i.e., on the top and bottom sides respectively. In practical applications, the positional relationship between the first word line driver 118, the second word line driver 128, the first sensing amplifier 109, and the second sensing amplifier 119 and the memory cell group 108 is not restricted. It is only necessary to satisfy that the first word line driver 118 is electrically connected to all first contact structures, the second word line driver 128 is electrically connected to all second contact structures, the first sensing amplifier 109 is electrically connected to the first contact structure, and the second sensing amplifier 119 is electrically connected to the second contact structure.

[0077] In summary, with word lines 100 arranged at intervals along the third direction Z, different word lines 100 are located in different height ranges along the third direction Z. The steps 112 in the stepped structure 102 are in contact with the word lines 100, and along the third direction Z, the top surface height of any step 112 is different from that of another step 112. This facilitates a one-to-one correspondence between the steps 112 and the word lines 100, allowing the word lines 100 to be led out through the steps 112. Furthermore, the contact structures 103 are in contact with the steps 112 to further lead out the word lines 100. The spacing between any two contact structures 103 helps prevent contact with contact structures 103 corresponding to different word lines 100, thus reducing interference between different word lines 100. In addition, the steps 112 are arranged in an array along the first direction X and the second direction Y, avoiding the stepped structure 102 extending only along the first direction X or the second direction Y, thus making reasonable use of the layout space and helping to reduce the total layout area of ​​the semiconductor structure.

[0078] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: Several character lines extending along a first direction and spaced apart along a third direction; A plurality of semiconductor channels extending along a second direction and spaced apart along the third direction, upward along the third direction, the word line encircling the semiconductor channels, the first direction, the second direction and the third direction intersecting each other; The structure includes a series of steps, which are in contact with the letter lines and extend upwards along the third direction. The top surface height of any step is different from the top surface height of another step. The steps are arranged in an array along the first direction and the second direction, and adjacent steps are electrically insulated from each other. A plurality of contact structures are provided, wherein the contact structures are in contact with the step, and any two contact structures are spaced apart from each other.

2. The semiconductor structure of claim 1, wherein, The semiconductor channels are arranged along the first direction and the third direction array, and the word lines surround the plurality of semiconductor channels arranged along the first direction.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, Along the direction away from the letter line, the top surface height of the plurality of steps arranged along the first direction gradually decreases, and the top surface height of the plurality of steps arranged along the second direction also gradually decreases.

4. The semiconductor structure as described in claim 3, characterized in that, The steps include several groups of steps arranged along the first direction, and several groups of steps arranged along the second direction. The group of steps closer to the letter line is the first group of steps, and the group of steps adjacent to the side of the first group of steps away from the letter line is the second group of steps. The step with the lowest top surface height in the first group of steps is the first reference step, and the step with the highest top surface height in the second group of steps is the second reference step. The top surface height of the first reference step is higher than the top surface height of the second reference step.

5. The semiconductor structure as described in claim 1 or 2, characterized in that, Moving upwards along the third direction, the top surface height of the step is level with the top surface height of the letter structure.

6. The semiconductor structure as described in claim 1 or 2, characterized in that, Along the third direction upward, the top surface of the contact structure is flush with the height, and the step includes a plurality of first steps arranged along the first direction, and a plurality of contact structures that are in contact with and connected to the plurality of first steps are arranged at intervals along the second direction.

7. The semiconductor structure as described in claim 1 or 2, characterized in that, The contact structure includes a conductive post and a lead-out layer. One end of the conductive post is in contact with the step, and the other end of the conductive post is in contact with the lead-out layer. The lead-out layer extends along the first direction and is arranged at intervals along the second direction.

8. The semiconductor structure as described in claim 1 or 2, characterized in that, Also includes: Bit lines are contacted and connected to a plurality of semiconductor channels arranged along the third direction.

9. The semiconductor structure as described in claim 8, characterized in that, Also includes: A plurality of capacitor structures are connected in contact with the side of the semiconductor channel away from the bit line, and the capacitor structures extend along the second direction.

10. The semiconductor structure as described in claim 9, characterized in that, The second direction and the third direction form a reference plane, and the plurality of capacitor structures form a capacitor region. The orthographic projection of the stepped structure on the reference plane and the orthographic projection of the capacitor region on the reference plane at least partially coincide.

11. The semiconductor structure as described in claim 9, characterized in that, Along the second direction, the bit line includes opposing first and second ends; the semiconductor channel includes: a plurality of first semiconductor channels contacting and connected to the first end, and a plurality of second semiconductor channels contacting and connected to the second end; the word line includes: a plurality of first word lines surrounding the first semiconductor channels, and a plurality of second word lines surrounding the second semiconductor channels, wherein along the first direction, the first word lines and the second word lines each have opposing first and second sides; the step structure includes: a first step structure contacting and connected to the first word lines, and a second step structure contacting and connected to the second word lines, wherein the first step structure is contacted and connected to one of the first side or the second side, and the second step structure is contacted and connected to the other of the first side or the second side.

12. The semiconductor structure as claimed in claim 11, characterized in that, The bit line, the word line, the step structure, the contact structure, and the capacitor structure constitute a memory cell group; the semiconductor structure includes a plurality of memory cell groups spaced apart along the second direction.

13. The semiconductor structure as described in claim 11 or 12, characterized in that, The contact structure includes: a first contact structure that is in contact with the first stepped structure, and a second contact structure that is in contact with the second stepped structure; The semiconductor structure also includes: The first word line driver is located on the side of the first stepped structure away from the first word line, and the first word line driver is electrically connected to all the first contact structures. The second word line driver is located on the side of the second step structure away from the second word line, and the second word line driver is electrically connected to all the second contact structures.

14. The semiconductor structure as described in claim 13, characterized in that, Also includes: A first sensing amplifier is electrically connected to the first contact structure; The second sensing amplifier is electrically connected to the second contact structure.

15. The semiconductor structure as described in claim 1 or 2, characterized in that, The stepped structure includes sub-steps arranged along the first direction and / or the second direction, wherein the number of sub-steps arranged along the second direction is greater than the number arranged along the first direction.

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