A test structure and its formation method, a semiconductor memory

Abstract

This disclosure provides a test structure and its formation method, as well as a semiconductor memory. The test structure includes multiple word lines and multiple bit lines, with a vertical transistor formed at the intersection of each word line and each bit line. The test structure includes a first region and a second region, with the second region located outside the first region. The word lines in the first region and the word lines in the second region are not connected, and the bit lines in the first region and the bit lines in the second region are not connected. Multiple vertical transistors located in the first region together form a test array, with the vertical transistor located in the middle of the test array being the device under test. In this way, by using the vertical transistors in the first region to form a small-sized test array, the influence of high impedance on the word lines / bit lines on the test results is reduced, allowing the test results to more accurately characterize the performance of the device under test.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to a test structure and a method for forming the same, and a semiconductor memory. Background Technology

[0002] Vertical transistors (VGAAs) offer advantages in miniaturization, high performance, and low power consumption, and are considered a key core technology for next-generation integrated circuits. However, the performance of VGAs is more susceptible to the influence of bit line resistance and word line resistance. Therefore, when testing VGAs, it is necessary to minimize the impact of bit line and word line resistance as much as possible, focusing instead on the performance of the VGA itself. Summary of the Invention

[0003] This disclosure provides a test structure and its formation method, as well as a semiconductor memory, which utilizes vertical transistors in a first region to form a small-sized test array, thereby improving the testing performance of vertical transistors.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a test structure comprising multiple word lines and multiple bit lines, wherein the intersection of each word line and each bit line forms a vertical transistor; the test structure comprises a first region and a second region, wherein the second region is outside the first region, the word lines in the first region are not connected to the word lines in the second region, and the bit lines in the first region are not connected to the bit lines in the second region; multiple vertical transistors located in the first region together form a test array, and the vertical transistor located in the middle of the test array is the device under test.

[0006] In some embodiments, the test structure further includes a gate contact node and a source contact node; the gate contact node is located in the first region and is connected to the control terminal of the device under test via a word line; the source contact node is located in the first region and is connected to the first terminal of the device under test via a bit line.

[0007] In some embodiments, the test structure further includes a first metal layer, a second metal layer, and a third metal layer; the first metal layer covers and connects to the gate contact node, and extends to the outside of the second region; the second metal layer covers and connects to the source contact node, and extends to the outside of the second region; the third metal layer is connected to the second end of the device under test, and extends to the outside of the second region; wherein the first metal layer, the second metal layer, and the third metal layer each extend in different directions toward the second region, and the first metal layer, the second metal layer, and the third metal layer do not intersect each other.

[0008] In some embodiments, the first metal layer is used to connect the gate of the device under test, the second metal layer is used to connect the source of the device under test, and the third metal layer is used to connect the drain of the device under test.

[0009] In some embodiments, the width of the first metal layer in the bit line direction covers three word lines, and the first metal layer does not cover the test array; the width of the second metal layer in the word line direction covers three bit lines, and the second metal layer does not cover the test array.

[0010] In some embodiments, the size of the test array is an (m×n) array, where m and n are both positive integers, and m and n may be equal or unequal; wherein the values ​​of m and n include at least any one of the following: 3, 4, 5, 9, 16.

[0011] Secondly, embodiments of this disclosure provide a method for forming a test structure, the method comprising:

[0012] A test structure is provided, and the test structure is patterned to form a first region and a second region; wherein the test structure includes multiple word lines and multiple bit lines, and the intersection of each word line and each bit line forms a vertical transistor, the word lines in the first region are not connected to the word lines in the second region, and the bit lines in the first region are not connected to the bit lines in the second region;

[0013] A test array is formed using multiple vertical transistors in the first region, and the vertical transistor located in the middle of the test array is the device under test.

[0014] In some embodiments, patterning the test structure to form a first region and a second region includes:

[0015] A target bitline pattern is formed and transferred to the bitline layer in the test structure; wherein the target bitline pattern includes a first bitline pattern located in a first region and a second bitline pattern located in a second region; multiple bitlines are formed based on the first bitline pattern and the second bitline pattern; a target wordline pattern is formed and transferred to the wordline layer in the test structure; wherein the target wordline pattern includes a first wordline pattern located in a first region and a second wordline pattern located in a second region; multiple wordlines are formed based on the first wordline pattern and the second wordline pattern.

[0016] In some embodiments, forming the target bit line pattern includes:

[0017] Multiple bitline patterns are formed on the test structure;

[0018] A first mask pattern is formed in the first region, and a second mask pattern is formed in the second region; wherein the first mask pattern and the second mask pattern are not connected, the first mask pattern covers the test array and extends outward along the bit line direction; the multiple bit line patterns are trimmed based on the first mask pattern and the second mask pattern to obtain the first bit line pattern and the second bit line pattern.

[0019] In some embodiments, forming the target letter line pattern includes:

[0020] Multiple character line patterns are formed on the test structure; a third mask pattern is formed in the first region, and a fourth mask pattern is formed in the second region; wherein the third mask pattern and the fourth mask pattern are not connected, the third mask pattern covers the test array and extends outward along the character line direction; the multiple character line patterns are trimmed based on the third mask pattern and the fourth mask pattern to obtain the first character line pattern and the second character line pattern.

[0021] In some embodiments, forming a test array using a plurality of vertical transistors in the first region includes:

[0022] A first target contact pattern is formed in the first region, and the test structure is etched based on the first target contact pattern to expose the drain of the device under test along the bit line direction; a second target contact pattern is formed in the first region, and the test structure is etched based on the second target contact pattern to expose the drain of the device under test along the word line direction; a third metal layer is formed over the drain of the device under test.

[0023] In some embodiments, forming a first target contact pattern in the first region includes:

[0024] In the first region, multiple first contact patterns are formed along the word line direction; a fifth mask pattern is formed; wherein the fifth mask pattern covers the test array and extends to both sides along the bit line direction; the multiple first contact patterns are trimmed based on the fifth mask pattern to obtain the first target contact pattern.

[0025] In some embodiments, forming a second target contact pattern in the first region includes:

[0026] In the first region, multiple second contact patterns are formed along the bit line direction; a sixth mask pattern is formed; wherein the sixth mask pattern covers the test array; the multiple second contact patterns are trimmed based on the sixth mask pattern to obtain the second target contact pattern.

[0027] In some embodiments, forming a test array using a plurality of vertical transistors in the first region further includes:

[0028] The test structure is etched to expose the gate contact node; and a first metal layer is formed over the gate contact node; wherein the gate contact node is connected to the gate of the device under test via a word line; and the test structure is etched to expose the source contact node; and a second metal layer is formed over the source contact node; wherein the source contact node is connected to the source of the device under test via a bit line; wherein the first metal layer, the second metal layer, and the third metal layer all extend from the first region to the second region, and the first metal layer, the second metal layer, and the third metal layer each extend in different directions towards the second region, and the first metal layer, the second metal layer, and the third metal layer do not intersect each other.

[0029] Thirdly, embodiments of this disclosure provide a semiconductor memory that includes the test structure described in the first aspect.

[0030] This disclosure provides a test structure and its formation method, as well as a semiconductor memory. The test structure includes multiple word lines and multiple bit lines, with a vertical transistor formed at the intersection of each word line and each bit line. The test structure includes a first region and a second region, with the second region located outside the first region. The word lines in the first region and the word lines in the second region are not connected, and the bit lines in the first region and the bit lines in the second region are not connected. Multiple vertical transistors located in the first region together form a test array, with the vertical transistor located in the middle of the test array being the device under test. In this way, by using the vertical transistors in the first region to form a small-sized test array, the influence of high impedance on the word lines / bit lines on the test results is reduced, allowing the test results to more accurately characterize the performance of the device under test. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a vertical transistor structure.

[0032] Figure 2 This is a schematic diagram of a test structure;

[0033] Figure 3 This is a schematic diagram of abnormal test results for a vertical transistor.

[0034] Figure 4 A schematic diagram of a test structure provided in an embodiment of this disclosure;

[0035] Figure 5 A schematic diagram of another test structure provided in an embodiment of this disclosure;

[0036] Figure 6 A flowchart illustrating a method for forming a test structure according to an embodiment of this disclosure;

[0037] Figure 7A A schematic diagram of the formation process of a test structure provided in this embodiment of the disclosure. Figure 1 ;

[0038] Figure 7B A schematic diagram of the formation process of a test structure provided in this embodiment of the disclosure. Figure 2 ;

[0039] Figure 7C A schematic diagram of the formation process of a test structure provided in this embodiment of the disclosure. Figure 3 ;

[0040] Figure 7D A schematic diagram of the formation process of a test structure provided in this embodiment of the disclosure. Figure 4 ;

[0041] Figure 7E A schematic diagram of the formation process of a test structure provided in this embodiment of the disclosure. Figure 5 ;

[0042] Figure 7F A schematic diagram of the formation process of a test structure provided in this embodiment of the disclosure. Figure 6 ;

[0043] Figure 7G Schematic diagram seven illustrating the formation process of a test structure provided in this embodiment of the disclosure;

[0044] Figure 8 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0045] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0047] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0048] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0049] See Figure 1 The diagram illustrates a vertical gate-all-aspect (VGAA) transistor, specifically a vertical gate-all-aspect junctionless (GNA) N-type transistor. In the device's minimum structure, 4F2, the channel diameter of this transistor is only 15 nanometers. Specifically, Figure 1 (a) in the diagram is a partial three-dimensional structural diagram of a vertical transistor. Figure 1 (b) in the diagram is a cross-sectional view along the direction of the letter lines. Figure 1 (c) in the diagram is a cross-sectional view along the position line direction. For example... Figure 1As shown, vertical transistors employ buried bit lines and self-aligned isolated bit lines. For vertical transistors, the channel extends vertically above the substrate, and the gate completely surrounds the channel region located above the substrate, effectively reducing the transistor's size.

[0050] In semiconductor memories, test structures are incorporated. These test structures share the same basic structure as the memory array but are specifically designed for testing. Each test structure requires test endpoints to be routed from corresponding positions on the word lines and bit lines to assess transistor performance. See also... Figure 2 It shows a schematic diagram of a test structure. For example... Figure 2 As shown, the test structure consists of multiple word lines and multiple bit lines. A vertical transistor is formed at the intersection of each bit line and each word line. Since the vertical transistors in the middle region have better performance and are the most representative, they are generally selected as the device under test. For the device under test, a test gate needs to be led out from the word line at the edge, and a test source (connected to a current source) needs to be led out from the bit line at the edge. The current under different operating conditions is obtained from the drain of the device under test to understand its performance.

[0051] However, due to the structure of vertical transistors, they are more susceptible to the effects of high impedance on bit lines / word lines. See also Figure 3 This illustrates a schematic diagram of an abnormal test result for a vertical transistor. Figure 3 In the diagram, the horizontal axis (X-axis) represents the word line voltage (VWL), and the vertical axis (Y-axis) represents the bit line current (IBL) / transistor current (INC). Voltage is measured in volts (V), and current is measured in microamps (μA). Curve 1 indicates how the transistor current (i.e., the actual current of the device) changes with the word line current, and curve 2 indicates how the bit line current (i.e., the current obtained from the test results) changes with the word line voltage. Figure 3 As shown, curves 1 and 2 are not completely corresponding. In other words, during the testing of vertical transistors, the high impedance on the bit lines / word lines will affect the final test results, causing the test results to not accurately represent the actual performance of the vertical transistors.

[0052] Based on this, this embodiment provides a test structure including multiple word lines and multiple bit lines, with each word line and each bit line forming a vertical transistor at their intersection. The test structure includes a first region and a second region, with the second region outside the first region. The word lines in the first region and the word lines in the second region are not connected, and the bit lines in the first region and the bit lines in the second region are not connected. Multiple vertical transistors located in the first region together form a test array, with the vertical transistor located in the middle of the test array being the device under test. In this way, by using the vertical transistors in the first region to form a small-sized test array, the influence of high impedance on the word lines / bit lines on the test results is reduced, enabling the test results to more accurately characterize the performance of the device under test.

[0053] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0054] In one embodiment of this disclosure, see Figure 4 This illustrates a schematic diagram of a test structure 10 provided in an embodiment of this disclosure. For example... Figure 4 As shown, test structure 10 includes multiple word lines (e.g. Figure 4 Word lines 1, word lines 2, etc.) and multiple bit lines (e.g.) Figure 4 Bit line 1, bit line 2, etc., and the intersection of each word line and each bit line forms a vertical transistor ( Figure 4 (Only one vertical transistor is marked in the image);

[0055] The test structure 10 includes a first region 11 and a second region 12, with the second region 12 outside the first region 11. The word lines in the first region 11 are not connected to the word lines in the second region 12, and the bit lines in the first region 11 are not connected to the bit lines in the second region 12. Multiple vertical transistors located in the first region 11 together form a test array, and the vertical transistor 13 located in the middle of the test array is the device under test.

[0056] It should be noted that the test structure provided in this disclosure is applied to semiconductor memory. The test structure can also be called a Testkey. By testing the test structure, the performance of the related device can be understood.

[0057] In this embodiment of the disclosure, the test structure 10 is divided into two independent regions: a first region 11 and a second region 12. The vertical transistors in the first region 11 can form a small-sized test array. The device under test can be connected to the corresponding test endpoints through shorter word lines / bit lines, which reduces the impact of high impedance on the word lines / bit lines on the test results, making the test results better characterize the performance of the device under test and improving the accuracy of the test results.

[0058] Here, the specific location between the first region 11 and the second region 12 can be determined based on the actual application scenario. Figure 4 In this embodiment, the outer edge of the first region 11 forms the inner edge of the second region 12, meaning that the second region 12 surrounds the outside of the first region 11, but this does not constitute a limitation. In another embodiment, the first region 11 may occupy a corner of the test structure 10, in which case the second region 12 does not completely surround the first region 11; in yet another embodiment, the first region 11 and the second region 12 are arranged side by side, and so on.

[0059] It should be noted that the size of the test array in the first region 11 can be determined according to the actual application scenario. Figure 4 The test array is shown as a (3×3) array. However, the test array can also be a (5×5), (4×5), (5×9), (16×16), etc. That is, the size of the test array is an (m×n) array, where m and n are both positive integers, and m and n may be equal or unequal; wherein the values ​​of m and n include at least one of the following: 3, 4, 5, 9, 16.

[0060] In some embodiments, such as Figure 5 As shown, the test structure 10 also includes a gate contact node 131 and a source contact node 132; the gate contact node 131 is located in the first region and is connected to the control terminal of the device under test 13 via a word line; the source contact node 132 is located in the first region and is connected to the first terminal of the device under test 13 via a bit line.

[0061] In some embodiments, such as Figure 5 As shown, the test structure 10 further includes a first metal layer 141, a second metal layer 142, and a third metal layer 143; the first metal layer 141 covers the gate contact node 131 and extends to the outside of the second region 12; the second metal layer 142 covers the source contact node 132 and extends to the outside of the second region 12; the third metal layer 143 is connected to the second end of the device under test 13 and extends to the outside of the second region 12.

[0062] It should be noted that the first metal layer 141, the second metal layer 142, and the third metal layer 143 extend in different directions toward the second region 12. For example, as shown... Figure 5As shown, the first metal layer 141 extends to the second region 12 along the bit line direction, the second metal layer 142 extends upward to the second region 12 along the bit line direction, and the third metal layer 143 extends downward to the second region 12 along the bit line direction. However, this is not a limitation; the first metal layer 141, the second metal layer 142, and the third metal layer 143 can extend to the second region 12 in any direction as long as they do not intersect each other.

[0063] It should be noted that the first metal layer 141 is used to connect the gate of the device under test, the second metal layer 142 is used to connect the source of the device under test, and the third metal layer 143 is used to connect the drain of the device under test.

[0064] In some embodiments, such as Figure 5 As shown, the first metal layer 141 covers three word lines in the word line direction, but does not cover the test array; the second metal layer 142 covers three bit lines in the word line direction, but also does not cover the test array. Furthermore, the third metal layer 143 covers three bit lines in the word line direction, and covers rows i to m in the test array, where i refers to the row containing the device under test.

[0065] This disclosure provides a test structure including multiple word lines and multiple bit lines, with each word line and bit line intersection forming a vertical transistor. The test structure includes a first region and a second region, with the second region outside the first region. Word lines in the first region and bit lines in the second region are not connected, and the bit lines in the first region and second region are not connected. Multiple vertical transistors located in the first region together form a test array, with the vertical transistor located in the middle of the test array being the device under test (DUT). In this way, by using only the first region to form a small array of test keys, the DUT can be connected to the metal layer (at the test endpoint) through shorter word lines / bit lines, reducing the impact of high impedance on the word lines / bit lines on the test results. This makes the test results more focused on the performance of the DUT, improving the accuracy of the test results.

[0066] In another embodiment of this disclosure, see Figure 6 The diagram illustrates a flowchart of a method for forming a test structure 10 according to an embodiment of this disclosure. Figure 6 As shown, the method may include:

[0067] S201: A test structure is provided, wherein the patterned test structure forms a first region and a second region; wherein the test structure includes multiple word lines and multiple bit lines, and the intersection of each word line and each bit line forms a vertical transistor, the word lines in the first region are not connected to the word lines in the second region, and the bit lines in the first region are not connected to the bit lines in the second region.

[0068] It should be noted that the forming method provided in this embodiment is used to form a small array of Testkeys, namely the aforementioned test structure 10.

[0069] S202: A test array is formed using multiple vertical transistors in the first region, and the vertical transistor located in the middle of the test array is the device under test.

[0070] In this way, through patterning, the test structure is divided into a first region and a second region. Subsequently, the vertical transistors in the first region are used to form a small-sized test array, so that the device under test can be connected to the corresponding test endpoints through shorter word lines / bit lines. This reduces the impact of high impedance on word lines / bit lines on the test results, making the test results more focused on the performance of the device under test and improving the accuracy of the test results.

[0071] Taking the second region surrounding the first region as an example, see [link / reference]. Figures 7A-7F The diagram illustrates the formation process of a test structure provided in an embodiment of this disclosure. The following is in conjunction with... Figures 7A-7F The specific fabrication process of the test structure is explained.

[0072] It should be noted that, for the test structure, the bit lines are located below the word lines. Therefore, during the patterning process, the bit lines are formed first, and then the word lines are formed.

[0073] Therefore, in some embodiments, the patterned test structure forming a first region and a second region may include:

[0074] A target bit line pattern is formed and transferred to the bit line layer in the test structure; wherein, the target bit line pattern includes a first bit line pattern located in a first region and a second bit line pattern located in a second region; multiple bit lines are formed based on the first bit line pattern and the second bit line pattern;

[0075] A target character line pattern is formed and transferred to the character line layer in the test structure; wherein, the target character line pattern includes a first character line pattern located in a first region and a second character line pattern located in a second region; based on the first character line pattern and the second character line pattern, multiple character lines are formed.

[0076] In one specific embodiment, such as Figure 7A The diagram illustrates the process of forming the target bitline pattern. The formation of the target bitline pattern includes:

[0077] Multiple bitline patterns 31 are formed on the test structure. Figure 7A(Only one bitline pattern is labeled); a first mask pattern 321 is formed in the first region, and a second mask pattern 322 is formed in the second region; wherein, the first mask pattern 321 and the second mask pattern 322 are not connected, and the first mask pattern 321 covers the test array and extends outward along the bitline direction.

[0078] Based on the first mask pattern 321 and the second mask pattern 322, multiple bit line patterns 31 are modified to obtain the first bit line pattern 331 and the second bit line pattern 332.

[0079] It should be noted that multiple bit line patterns 31 are first printed onto the test structure using photolithography. Then, the bit line patterns 31 are trimmed (cut), retaining only those bit line patterns covered by the first mask pattern 321 (i.e., the first bit line pattern 331) and those covered by the second mask pattern 322 (i.e., the second bit line pattern 332). Thus, multiple bit lines are formed on the bit line layer of the test structure based on the first bit line pattern 331 and the second bit line pattern 332. Here, the first bit line pattern 331 and the second bit line pattern 332 are not connected and are independent of each other.

[0080] In one specific embodiment, such as Figure 7B The diagram illustrates the process of forming the target character line pattern. Forming the target character line pattern may include:

[0081] Multiple character line patterns 34 are formed on the test structure. Figure 7B (Only one character line pattern is labeled); a third mask pattern 351 is formed in the first region, and a fourth mask pattern 352 is formed in the second region; wherein, the third mask pattern 351 and the fourth mask pattern 352 are not connected, and the third mask pattern 351 covers the test array and extends outward along the character line direction.

[0082] Based on the third mask pattern 351 and the fourth mask pattern 352, multiple character line patterns 34 are modified to obtain the first character line pattern 361 and the second character line pattern 362.

[0083] It should be noted that multiple character line patterns 34 are first printed onto the test structure using photolithography. Then, the character line patterns 34 are trimmed (cut), retaining only those covered by the third mask pattern 351 (i.e., the first character line pattern 361) and those covered by the fourth mask pattern 352 (i.e., the second character line pattern 362). Thus, multiple character lines are formed on the corresponding character line layers based on the first character line pattern 361 and the second character line pattern 362. Here, the first character line pattern 361 and the second character line pattern 362 are not connected and are independent of each other.

[0084] In another embodiment, word line opening is also involved in the process of forming word lines to achieve segmentation of the test structure and segmentation of the test array. Figure 7C A schematic diagram showing the location of the character line opening is provided. (For example...) Figure 7C As shown, the method further includes: forming a word line etch opening (WEO) pattern to define the word line opening area; and forming an array of word line openings (AWO) to define the word line metal formation area. That is, during the word line trimming process, the WEO needs to be trimmed first to separate the test structure from other external structures, and then the AWO needs to be trimmed to separate the first region and the second region (test array).

[0085] It should be understood that the detailed word line formation process and bit line formation process are relatively mature, and will not be described in detail in the embodiments disclosed herein.

[0086] After the word lines and bit lines are formed, a first metal layer is formed in the test structure to bring out the drain of the device under test.

[0087] In some embodiments, forming a test array using a plurality of vertical transistors in the first region includes:

[0088] A first target contact pattern is formed in the first region, and the test structure is etched based on the first target contact pattern to expose the drain of the device under test along the bit line direction; a second target contact pattern is formed in the first region, and the test structure is etched based on the second target contact pattern to expose the drain of the device under test along the word line direction; a third metal layer is formed over the drain of the device under test.

[0089] In some embodiments, such as Figure 7D The diagram illustrates the process of forming the first target contact pattern. Forming the first target contact pattern 43 in the first region includes:

[0090] In the first region, multiple first contact patterns 41 are formed along the direction of the letter lines. Figure 7D (Only one first contact pattern is labeled); a fifth mask pattern 42 is formed; wherein the fifth mask pattern 42 covers the test array and extends to both sides along the bit line direction; based on the fifth mask pattern 42, multiple first contact patterns 41 are trimmed to obtain the first target contact pattern 43.

[0091] In some embodiments, such as Figure 7E As shown, forming the second target contact pattern 46 in the first region includes:

[0092] In the first region, multiple second contact patterns 44 are formed along the bit line direction. Figure 7E(Only one second contact pattern is labeled); a sixth mask pattern 45 is formed; wherein the sixth mask pattern 45 covers the test array; based on the sixth mask pattern 45, multiple second contact patterns 41 are modified to obtain the second target contact pattern 46.

[0093] In this way, the drain at the top of the device under test is exposed by exposure etching along two directions (word line direction and bit line direction), thereby forming a third metal layer.

[0094] After forming the first metal layer, a second and third metal layer need to be formed to bring out the gate and source of the device under test. Therefore, as... Figure 7F and Figure 7G The diagram illustrates the formation process of the first and second metal layers. The method of forming a test array using multiple vertical transistors in the first region further includes:

[0095] The test structure is etched to expose the gate contact node 131; and a first metal layer 141 is formed over the gate contact node 131; wherein the gate contact node 131 is connected to the gate of the device under test via a word line; and,

[0096] The test structure is etched to expose the source contact node 132; and a second metal layer 142 is formed on top of the source contact node 132; wherein the source contact node 132 is connected to the source of the device under test through word lines.

[0097] It should be noted that the first metal layer 141, the second metal layer 142, and the third metal layer 143 all extend from the first region to the second region, and the extension directions of the first metal layer 141, the second metal layer 142, and the third metal layer 143 towards the second region are different, and the first metal layer 141, the second metal layer 142, and the third metal layer 143 do not intersect with each other. Furthermore, the order in which the first metal layer 141 and the second metal layer 142 are formed needs to be determined according to the actual process scenario.

[0098] Thus, the first metal layer 141 is used to connect the gate of the device under test, the second metal layer 142 is used to connect the source of the device under test, and the third metal layer 143 is used to connect the drain of the device under test, so as to test the device under test.

[0099] It should be understood that, Figures 7F to 7G In this process, all the aforementioned mask patterns, letter line patterns, bit line patterns, contact patterns, etc., are retained, simply to maintain the position of different patterns / elements within the overall test structure. Additionally, in Figures 7A to 7G The size and shape of various patterns can be adjusted according to the actual application scenario. The embodiments disclosed herein are for illustrative purposes only and are not intended to limit the specific application.

[0100] This disclosure provides a method for forming a test structure, comprising: providing a test structure; patterning the test structure to form a first region and a second region; wherein the test structure includes multiple word lines and multiple bit lines, and a vertical transistor is formed at the intersection of each word line and each bit line; the word lines in the first region are not connected to the word lines in the second region, and the bit lines in the first region are not connected to the bit lines in the second region; a test array is formed using the multiple vertical transistors in the first region, and the vertical transistor located in the middle of the test array is the device under test. In this way, by using the vertical transistors in the first region to form a small-sized test array (or test key), the device under test can be connected to the metal layer (at the test endpoint) through shorter word lines / bit lines, reducing the impact of high impedance on the word lines / bit lines on the test results, making the test results more focused on the performance of the device under test, and improving the accuracy of the test results.

[0101] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 8 This illustrates a schematic diagram of the structural composition of a semiconductor memory 50 provided in an embodiment of this disclosure. For example... Figure 8 As shown, the semiconductor memory 50 may include a test structure 10 as described in any of the foregoing embodiments.

[0102] In this way, for the semiconductor memory 50, the device under test (vertical transistor) in the test structure can be connected to the metal layer (at the test endpoint) through shorter word lines / bit lines, which improves the impact of high resistance on the word lines / bit lines on the test results, and makes the test results more focused on the performance of the device under test.

[0103] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0104] It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A test structure, characterized in that, The test structure includes multiple word lines and multiple bit lines, and the intersection of each word line and each bit line forms a vertical transistor; The test structure includes a first region and a second region, with the second region located outside the first region. The word lines in the first region are not connected to the word lines in the second region, and the bit lines in the first region are not connected to the bit lines in the second region. Multiple vertical transistors located in the first region together form a test array, and the vertical transistor located in the middle of the test array is the device under test.

2. The test structure according to claim 1, characterized in that, The test structure also includes a gate contact node and a source contact node; The gate contact node is located in the first region, and the gate contact node is connected to the control terminal of the device under test via a word line; The source contact node is located in the first region, and the source contact node is connected to the first end of the device under test via a bit line.

3. The test structure according to claim 2, characterized in that, The test structure also includes a first metal layer, a second metal layer, and a third metal layer; The first metal layer covers the gate contact node and extends to the outside of the second region; The second metal layer covers the source contact node and extends to the outside of the second region; The third metal layer is connected to the second end of the device under test, and the third metal layer extends to the outside of the second region; The first metal layer, the second metal layer, and the third metal layer each extend in different directions toward the second region, and the first metal layer, the second metal layer, and the third metal layer do not intersect each other.

4. The test structure according to claim 3, characterized in that, The first metal layer is used to connect the gate of the device under test, the second metal layer is used to connect the source of the device under test, and the third metal layer is used to connect the drain of the device under test.

5. The test structure according to claim 3, characterized in that, The width of the first metal layer in the bit line direction covers three word lines, and the first metal layer does not cover the test array; The second metal layer covers three bit lines in the word line direction, but does not cover the test array.

6. The test structure according to any one of claims 1-5, characterized in that, The test array is an (m×n) array, where m and n are both positive integers, and m and n may be equal or unequal. The values ​​of m and n include at least one of the following: 3, 4, 5, 9, 16.

7. A method for forming a test structure, characterized in that, The method includes: A test structure is provided, and the test structure is patterned to form a first region and a second region; wherein the test structure includes multiple word lines and multiple bit lines, and the intersection of each word line and each bit line forms a vertical transistor, the word lines in the first region are not connected to the word lines in the second region, and the bit lines in the first region are not connected to the bit lines in the second region; A test array is formed using multiple vertical transistors in the first region, and the vertical transistor located in the middle of the test array is the device under test.

8. The forming method according to claim 7, characterized in that, The patterning of the test structure to form a first region and a second region includes: A target bit line pattern is formed and the target bit line pattern is transferred to the bit line layer in the test structure; wherein, the target bit line pattern includes a first bit line pattern located in a first region and a second bit line pattern located in a second region; Multiple bit lines are formed based on the first bit line pattern and the second bit line pattern; A target character line pattern is formed, and the target character line pattern is transferred to the character line layer in the test structure; wherein, the target character line pattern includes a first character line pattern located in a first region and a second character line pattern located in a second region; Multiple character lines are formed based on the first and second character line patterns.

9. The forming method according to claim 8, characterized in that, The formation of the target bit line pattern includes: Multiple bitline patterns are formed on the test structure; A first mask pattern is formed in the first region, and a second mask pattern is formed in the second region; wherein the first mask pattern and the second mask pattern are not connected, and the first mask pattern covers the test array and extends outward along the bit line direction; The multiple bit line patterns are modified based on the first mask pattern and the second mask pattern to obtain the first bit line pattern and the second bit line pattern.

10. The forming method according to claim 8, characterized in that, The process of forming the target character line pattern includes: Multiple letter-line patterns are formed on the test structure; A third mask pattern is formed in the first region, and a fourth mask pattern is formed in the second region; wherein the third mask pattern and the fourth mask pattern are not connected, and the third mask pattern covers the test array and extends outward along the word line direction; Based on the third and fourth mask patterns, the multiple character line patterns are modified to obtain the first character line pattern and the second character line pattern.

11. The forming method according to claim 7, characterized in that, The method of forming a test array using multiple vertical transistors in the first region includes: A first target contact pattern is formed in the first region, and the test structure is etched based on the first target contact pattern to expose the drain of the device under test along the bit line direction; A second target contact pattern is formed in the first region, and the test structure is etched based on the second target contact pattern to expose the drain of the device under test along the word line direction; A third metal layer is formed over the drain of the device under test.

12. The forming method according to claim 11, characterized in that, The step of forming a first target contact pattern in the first region includes: In the first region, multiple first contact patterns are formed along the direction of the letter lines; A fifth mask pattern is formed; wherein the fifth mask pattern covers the test array and extends to both sides along the bit line direction; The first target contact pattern is obtained by modifying the multiple first contact patterns based on the fifth mask pattern.

13. The forming method according to claim 11, characterized in that, The step of forming a second target contact pattern in the first region includes: In the first region, multiple second contact patterns are formed along the bit line direction; A sixth mask pattern is formed; wherein the sixth mask pattern covers the test array; The multiple second contact patterns are modified based on the sixth mask pattern to obtain the second target contact pattern.

14. The forming method according to claim 11, characterized in that, The method of forming a test array using multiple vertical transistors in the first region further includes: The test structure is etched to expose the gate contact nodes; and a first metal layer is formed over the gate contact nodes; wherein the gate contact nodes are connected to the gate of the device under test via word lines; and, The test structure is etched to expose the source contact node; and a second metal layer is formed on top of the source contact node; wherein the source contact node is connected to the source of the device under test through a bit line; The first metal layer, the second metal layer, and the third metal layer all extend from the first region to the second region, and the first metal layer, the second metal layer, and the third metal layer each extend in different directions to the second region, and the first metal layer, the second metal layer, and the third metal layer do not intersect each other.

15. A semiconductor memory, characterized in that, Includes the test structure as described in any one of claims 1 to 6.

Images