Electrostatic protection structure, chip

Abstract

The present disclosure relates to the technical field of semiconductor, and provides an electrostatic protection structure and a chip. The electrostatic protection structure comprises a semiconductor substrate, an N-type well, a P-type well, a first N-type doped part, a first P-type doped part, a second P-type doped part and a second N-type doped part. The N-type well and the P-type well are located in the semiconductor substrate. The first N-type doped part and the second P-type doped part are located in the P-type well, and the first P-type doped part and the second N-type doped part are located in the N-type well. The first N-type doped part is a T-shaped structure, the first P-type doped part is a U-shaped structure, and part of the structure of the first N-type doped part is located in the U-shaped opening of the first P-type doped part. The second P-type doped part is located on the side of the first N-type doped part away from the first P-type doped part, and the second N-type doped part is located on the side of the first P-type doped part away from the first N-type doped part. The second P-type doped part and the second N-type doped part are electrically connected. The electrostatic protection structure has a small size.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an electrostatic discharge protection structure and a chip. Background Technology

[0002] Chips typically require an electrostatic discharge (ESD) protection circuit to discharge static electricity from the chip and prevent damage to the core circuitry.

[0003] In related technologies, the layout area of ​​the electrostatic protection structure used to form the electrostatic protection circuit is relatively large, which is not conducive to chip design.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] According to one aspect of this disclosure, an electrostatic discharge (ESD) protection structure is provided, comprising: a semiconductor substrate, an N-type well, a P-type well, a first N-type doped portion, a first P-type doped portion, a second P-type doped portion, and a second N-type doped portion. The N-type well is located within the semiconductor substrate; the P-type well is located within the semiconductor substrate. The first N-type doped portion is located within the P-type well, and the first N-type doped portion includes a first extension and a second extension connected to each other; wherein the orthographic projection of the first extension on a target projection plane extends along a first direction, and the orthographic projection of the second extension on the target projection plane extends along a second direction, the target projection plane is parallel to the plane containing the semiconductor substrate, and the first direction and the second direction intersect. The first P-type doped portion is located within the N-type well. The first P-type doped portion includes a third extension, a fourth extension, and a fifth extension connecting the third and fourth extensions. The orthographic projections of the third and fourth extensions on the target projection plane both extend along the second direction. The orthographic projection of the second extension on the target projection plane is located between the orthographic projections of the third and fourth extensions on the target projection plane. The orthographic projection of the fifth extension on the target projection plane is located on the side where the orthographic projection of the second extension on the target projection plane is furthest from the orthographic projection of the first extension on the target projection plane. The second P-type doped portion is located within the P-type well. The orthographic projection of the second P-type doped portion on the target projection plane extends along the first direction and is located on the side where the orthographic projection of the first N-type doped portion on the target projection plane is furthest from the orthographic projection of the first P-type doped portion on the target projection plane. The second N-type doped portion is located within the N-type well. The orthographic projection of the second N-type doped portion on the target projection surface extends along the first direction and is located on the side of the first P-type doped portion on the target projection surface that is away from the orthographic projection of the first N-type doped portion on the target projection surface. The second P-type doped portion and the second N-type doped portion are electrically connected.

[0006] In one exemplary embodiment of this disclosure, the electrostatic protection structure further includes: a third N-type doped portion and a third P-type doped portion. The third N-type doped portion is located within the P-type well, and the orthographic projection of the third N-type doped portion on the target projection surface and the orthographic projection of the first N-type doped portion on the target projection surface are spaced apart in the first direction; wherein, the third N-type doped portion includes a sixth extension portion and a seventh extension portion connected to each other, the orthographic projection of the sixth extension portion on the target projection surface extends along the first direction, and the orthographic projection of the seventh extension portion on the target projection surface extends along the second direction. The third P-type doped portion is located within the N-type well. The orthographic projection of the third P-type doped portion on the target projection plane is spaced apart from the orthographic projection of the first P-type doped portion on the target projection plane in the first direction. The third P-type doped portion includes an eighth extension, a ninth extension, and a tenth extension connected between the eighth and ninth extensions. The orthographic projections of the eighth and ninth extensions on the target projection plane both extend along the second direction. The orthographic projection of the seventh extension on the target projection plane is located between the orthographic projections of the eighth and ninth extensions on the target projection plane. The orthographic projection of the tenth extension on the target projection plane is located on the side of the seventh extension away from the orthographic projection of the sixth extension on the target projection plane. The orthographic projection of the second P-type doped portion on the target projection surface is located on the side of the orthographic projection of the third N-type doped portion on the target projection surface that is far from the orthographic projection of the third P-type doped portion on the target projection surface; the orthographic projection of the second N-type doped portion on the target projection surface is located on the side of the orthographic projection of the third P-type doped portion on the target projection surface that is far from the orthographic projection of the third N-type doped portion on the target projection surface.

[0007] In one exemplary embodiment of this disclosure, a portion of the structure of the first extension and at least a portion of the structure of the third extension are disposed opposite to each other in the second direction; a portion of the structure of the first extension and at least a portion of the structure of the fourth extension are disposed opposite to each other in the second direction; a portion of the structure of the sixth extension and at least a portion of the structure of the eighth extension are disposed opposite to each other in the second direction; and a portion of the structure of the sixth extension and at least a portion of the structure of the ninth extension are disposed opposite to each other in the second direction.

[0008] In one exemplary embodiment of this disclosure, the P-type well includes: a first well region, a second well region, and a third well region. The orthographic projection of the first well region on the target projection surface extends along a first direction. The second well region is connected to the first well region, and the orthographic projection of the second well region on the target projection surface extends along a second direction. The third well region is connected to the first well region, and the orthographic projection of the third well region on the target projection surface extends along the second direction. The orthographic projections of the third well region and the second well region on the target projection surface are located on the same side of the orthographic projection of the first well region on the target projection surface. The first extension, the sixth extension, and the second P-type doped portion are located in the first well region, the second extension is located in the second well region, and the seventh extension is located in the third well region.

[0009] In one exemplary embodiment of this disclosure, a portion of the structure of the first extension and the second P-type doped portion are disposed opposite to each other in the second direction; a portion of the structure of the sixth extension and the second P-type doped portion are disposed opposite to each other in the second direction; a portion of the structure of the fifth extension and the second N-type doped portion are disposed opposite to each other in the second direction; and a portion of the structure of the tenth extension and the second N-type doped portion are disposed opposite to each other in the second direction.

[0010] In one exemplary embodiment of this disclosure, the orthographic projection of the N-type well on the target projection surface surrounds the orthographic projection of the P-type well on the target projection surface; the semiconductor substrate is a P-type semiconductor substrate, and the electrostatic protection structure further includes an N-type deep well, which is isolated between the semiconductor substrate and the P-type well.

[0011] In one exemplary embodiment of this disclosure, the electrostatic protection structure further includes: an annular doped portion, the orthographic projection of the annular doped portion on the target projection surface surrounding the orthographic projection of the N-type well on the target projection surface and the orthographic projection of the P-type well on the target projection surface; the doping type of the annular doped portion is the same as the doping type of the semiconductor substrate.

[0012] According to one aspect of this disclosure, a chip is provided, wherein the chip includes the electrostatic protection structure described above.

[0013] In one exemplary embodiment of this disclosure, the chip includes a first terminal and a second terminal, the first terminal being connected to the first N-type doped portion and the second terminal being connected to the first P-type doped portion.

[0014] In one exemplary embodiment of this disclosure, the chip includes a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal; the first terminal is the high-level power supply terminal, and the second terminal is the signal transmission terminal; or, the first terminal is the signal transmission terminal, and the second terminal is the low-level power supply terminal; or, the first terminal is the high-level power supply terminal, and the second terminal is the low-level power supply terminal.

[0015] In one exemplary embodiment of this disclosure, the chip includes a low-level power supply terminal and a signal transmission terminal; when the electrostatic protection structure includes a third P-type doped portion and a third N-type doped portion, the signal transmission terminal is connected to the first P-type doped portion and the third N-type doped portion, and the low-level power supply terminal is connected to the first N-type doped portion and the third P-type doped portion.

[0016] In one exemplary embodiment of this disclosure, the signal transmission terminal includes a signal output terminal and a signal input terminal. The chip includes a plurality of electrostatic discharge (ESD) protection structures, including a first ESD protection structure and a second ESD protection structure. The first P-type doped portion and the third N-type doped portion of the first ESD protection structure are connected to the signal input terminal, and the first N-type doped portion and the third P-type doped portion of the first ESD protection structure are connected to the low-level power supply terminal. The first P-type doped portion and the third N-type doped portion of the second ESD protection structure are connected to the signal output terminal, and the first N-type doped portion and the third P-type doped portion of the second ESD protection structure are connected to the low-level power supply terminal.

[0017] In one exemplary embodiment of this disclosure, the chip includes a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal; when the electrostatic protection structure includes a third P-type doped portion and a third N-type doped portion, the signal transmission terminal is connected to the first P-type doped portion and the third N-type doped portion, the high-level power supply terminal is connected to the first N-type doped portion, and the low-level power supply terminal is connected to the third P-type doped portion.

[0018] In an exemplary embodiment of this disclosure, the signal transmission terminal includes a signal output terminal and a signal input terminal. The chip includes a plurality of electrostatic discharge (ESD) protection structures, including a first ESD protection structure and a second ESD protection structure. The first P-type doped portion and the third N-type doped portion of the first ESD protection structure are connected to the signal input terminal. The first N-type doped portion of the first ESD protection structure is connected to the high-level power supply terminal, and the third P-type doped portion of the first ESD protection structure is connected to the low-level power supply terminal. The first P-type doped portion and the third N-type doped portion of the second ESD protection structure are connected to the signal output terminal. The first N-type doped portion of the second ESD protection structure is connected to the high-level power supply terminal, and the third P-type doped portion of the second ESD protection structure is connected to the low-level power supply terminal.

[0019] In one exemplary embodiment of this disclosure, the chip is a dynamic random access memory or a static random access memory.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 This is an equivalent circuit diagram of an exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0023] Figure 2 This is a structural diagram illustrating an exemplary embodiment of the electrostatic protection structure disclosed herein.

[0024] Figure 3 for Figure 2 Structural layout of the central well region;

[0025] Figure 4 for Figure 2 Structural layout of the intermediate doped region;

[0026] Figure 5 for Figure 2 The electrostatic protection structure shown is a cross-sectional view along the dashed line AA.

[0027] Figure 6 for Figure 2 Structural layout of the intermediate-deep well;

[0028] Figure 7 This is a schematic diagram of the structure of an exemplary embodiment of the chip disclosed herein;

[0029] Figure 8 This is a schematic diagram of the structure in another exemplary embodiment of the chip disclosed herein;

[0030] Figure 9 This is a schematic diagram of the clamping circuit in an exemplary embodiment of the chip disclosed herein;

[0031] Figure 10 This is a schematic diagram of the clamping circuit in another exemplary embodiment of the chip disclosed herein. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0033] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the icon's arrangement is flipped so that it is upside down, the component described as "up" will become the component described as "down." Other relative terms such as "high," "low," "top," "bottom," "left," and "right" also have similar meanings. When a structure is "up" of another structure, it may mean that the structure is integrally located on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0034] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0035] This exemplary embodiment first provides an electrostatic discharge protection circuit, such as Figure 1 The diagram shown is an equivalent circuit diagram of an exemplary embodiment of the electrostatic discharge (ESD) protection circuit of this disclosure. The ESD protection circuit may include a PNP transistor Q1, an NPN transistor Q2, a first diode D1, and a second diode D2. The emitter of the PNP transistor Q1 is connected to the first signal terminal V1, and the base and collector of the PNP transistor Q1 are connected to node K. The emitter of the NPN transistor Q2 is connected to the second signal terminal V2, and the base and collector of the NPN transistor Q2 are connected to node K. The anode of the first diode D1 is connected to the first signal terminal V1, and the cathode of the first diode D1 is connected to node K. The anode of the second diode D2 is connected to node K, and the cathode of the second diode D2 is connected to the second signal terminal V2.

[0036] This electrostatic discharge (ESD) protection circuit can quickly discharge static electricity from the first signal terminal V1 to the second signal terminal V2. When static electricity occurs at the first signal terminal V1, the first diode D1 and the second diode D2 conduct first. Due to the impedance of the first diode D1, a voltage difference is generated between the first signal terminal V1 and node K, triggering the PNP transistor Q1 to conduct. Similarly, due to the impedance of the second diode D2, a voltage difference is generated between the second signal terminal V2 and node K, triggering the NPN transistor Q2 to conduct. Because the threshold voltages of the first diode D1 and the second diode D2 are relatively small, this ESD protection circuit can have a relatively small trigger voltage.

[0037] like Figure 2-5 As shown, Figure 2 This is a structural layout diagram of an exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 3 for Figure 2 Structural layout of the central well region Figure 4 for Figure 2 Structural layout of the doped region. Figure 5 for Figure 2The diagram shows a cross-sectional view of the electrostatic discharge (ESD) protection structure along the dashed line AA. The ESD protection structure may include: a semiconductor substrate Psub, an N-type well NW, a P-type well PW, a first N-type doped portion N1, a first P-type doped portion P1, a second P-type doped portion P2, and a second N-type doped portion N2. The N-type well NW is located within the semiconductor substrate Psub; the P-type well PW is located within the semiconductor substrate Psub. The first N-type doped portion N1 is located within the P-type well PW, and the first N-type doped portion N1 includes a first extension N11 and a second extension N12 connected to each other. The orthographic projection of the first extension N11 onto the target projection plane can extend along a first direction X, and the orthographic projection of the second extension N12 onto the target projection plane can extend along a second direction Y. The target projection plane is parallel to the plane containing the semiconductor substrate Psub, and the first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y can be perpendicular. The first P-type doped portion P1 is located within the N-type well NW. The first P-type doped portion P1 includes a third extension P13, a fourth extension P14, and a fifth extension P15 connected between the third extension P13 and the fourth extension P14. The orthographic projections of the third extension P13 and the fourth extension P14 on the target projection plane both extend along the second direction Y. The orthographic projection of the second extension N12 on the target projection plane is located between the orthographic projections of the third extension P13 and the fourth extension P14 on the target projection plane. The orthographic projection of the fifth extension P15 on the target projection plane is located on the side of the second extension N12 on the target projection plane that is away from the orthographic projection of the first extension N11 on the target projection plane. The second P-type doped portion P2 is located within the P-type well PW. The orthographic projection of the second P-type doped portion P2 onto the target projection plane extends along the first direction X and is located on the side where the orthographic projection of the first N-type doped portion N1 onto the target projection plane is away from the orthographic projection of the first P-type doped portion P1 onto the target projection plane. The second N-type doped portion N2 is located within the N-type well NW. The orthographic projection of the second N-type doped portion N2 onto the target projection plane extends along the first direction X and is located on the side where the orthographic projection of the first P-type doped portion P1 onto the target projection plane is away from the orthographic projection of the first N-type doped portion N1 onto the plane containing the semiconductor substrate Psub. The second P-type doped portion P2 and the second N-type doped portion N2 are electrically connected.

[0038] Figure 2 The electrostatic protection structure shown may include Figure 1The electrostatic discharge (ESD) protection circuit is shown. In this circuit, the first P-type doped portion P1 forms the emitter of a PNP transistor Q1, the N-type well NW forms the base of Q1, and the P-type well forms the collector. Similarly, the first N-type doped portion N1 forms the emitter of an NPN transistor Q2, the P-type well PW forms the base, and the N-type well NW forms the collector. The first P-type doped portion P1 forms the anode of a first diode D1, and the N-type well NW forms the cathode. The P-type well PW forms the anode of a second diode D2, and the first N-type doped portion N1 forms the cathode. The second P-type doped portion P2 and the second N-type doped portion N2 are electrically connected to connect the N-type well NW and the P-type well PW, thereby connecting the cathode of the first diode D1 and the anode of the second diode D2.

[0039] In this exemplary embodiment, the second P-type doped portion P2 and the second N-type doped portion N2 can be connected by a conductive line Line, which can be formed on the surface of the semiconductor substrate.

[0040] like Figure 2-5 As shown in this exemplary embodiment, the first N-type doped portion N1 has a "T"-shaped structure, the first P-type doped portion P1 has a "U"-shaped structure, and the second extension N12 of the first N-type doped portion N1 is inserted into the "U"-shaped opening of the first P-type doped portion P1. In this exemplary embodiment, the first extension N11 and the second extension N12 together form the emitter of the NPN transistor Q2; the third extension P13, the fourth extension P14, and the fifth extension P15 together form the emitter of the PNP transistor Q1. Compared to the related art where the N-type and P-type doped portions are set as strips, this arrangement can increase the effective size of the PNP transistor Q1 and the NPN transistor Q2 within a limited space, thereby increasing the speed at which the conductive channels formed by the PNP transistor Q1 and the NPN transistor Q2 release static electricity while reducing the trigger voltage. Furthermore, in this exemplary embodiment, the orthographic projection of the second N-type doped portion N2 on the target projection plane and the orthographic projection of the second P-type doped portion P2 on the target projection plane both extend along the first direction X, and the second P-type doped portion P2 and the second N-type doped portion are respectively disposed on both sides of the PNP transistor Q1 and the NPN transistor Q2 in the second direction Y. This arrangement can further reduce the size of the electrostatic protection structure in the first direction X.

[0041] It should be noted that the plane containing the semiconductor substrate Psub can be understood as the plane containing the side of the semiconductor substrate Psub facing away from the first N-type doped portion N1. In this exemplary embodiment, the semiconductor substrate Psub can be a P-type semiconductor substrate. In this exemplary embodiment, the P-type well formed in the P-type semiconductor substrate Psub can be directly formed from a portion of the structure of the P-type semiconductor substrate Psub, that is, it is not necessary to further dope the P-type semiconductor substrate Psub when forming the P-type well. It should be understood that in other exemplary embodiments, the semiconductor substrate can also be an N-type semiconductor substrate, and correspondingly, the N-type well formed in the N-type semiconductor substrate can be directly formed from a portion of the structure of the N-type semiconductor substrate.

[0042] like Figure 2-5 As shown, the electrostatic protection structure may further include: a third N-type doped portion N3 and a third P-type doped portion P3. The third N-type doped portion N3 is located within the P-type well PW, and the orthographic projection of the third N-type doped portion N3 on the target projection plane and the orthographic projection of the first N-type doped portion N1 on the target projection plane are spaced apart in the first direction X; wherein, the third N-type doped portion N3 includes a sixth extension portion N36 and a seventh extension portion N37 connected to each other, the orthographic projection of the sixth extension portion N36 on the target projection plane extends along the first direction X, and the orthographic projection of the seventh extension portion N37 on the target projection plane extends along the second direction Y. The third P-type doped portion P3 is located within the N-type well NW. The orthographic projection of the third P-type doped portion P3 onto the target projection plane is spaced apart from the orthographic projection of the first P-type doped portion P1 onto the target projection plane in the first direction X. The third P-type doped portion P3 includes an eighth extension P38, a ninth extension P39, and a tenth extension P310 connecting the eighth extension P38 and the ninth extension P39. The orthographic projections of the eighth extension P38 and the ninth extension P39 onto the target projection plane both extend along the second direction Y. The orthographic projection of the seventh extension N37 onto the target projection plane is located between the orthographic projections of the eighth extension P38 and the ninth extension P39 onto the target projection plane. The orthographic projection of the tenth extension P310 onto the target projection plane is located on the side of the orthographic projection of the seventh extension N37 onto the target projection plane that is away from the orthographic projection of the sixth extension N36 onto the target projection plane.

[0043] In this exemplary embodiment, as Figure 2-5 As shown, the electrostatic protection structure can include two sets of... Figure 1The electrostatic discharge (ESD) protection circuit shown can be further divided into two groups: the third P-type doped portion P3 and the third N-type doped portion N3. The third P-type doped portion P3 can be used to form the emitter of a PNP transistor Q1, the N-type well NW can be used to form the base of Q1, and the P-type well can be used to form the collector of Q1. Similarly, the third N-type doped portion N3 can be used to form the emitter of an NPN transistor Q2, the P-type well PW can be used to form the base of Q2, and the N-type well NW can be used to form the collector of Q2. Furthermore, the third P-type doped portion P3 can be used to form the anode of a first diode D1, and the N-type well NW can be used to form the cathode of D1. Finally, the P-type well PW can be used to form the anode of a second diode D2, and the third N-type doped portion N3 can be used to form the cathode of D2.

[0044] In this exemplary embodiment, as Figure 2-5 As shown, the sixth extension N36 and the seventh extension N37 together form the emitter of the NPN transistor Q2; the eighth extension P38, the ninth extension P39, and the tenth extension P310 together form the emitter of the PNP transistor Q1. This arrangement can also improve the speed at which the conductive channel formed by the PNP transistor Q1 and the NPN transistor Q2 releases static electricity, while reducing the trigger voltage.

[0045] In this exemplary embodiment, as Figure 2-5 As shown, the orthographic projections of the first P-type doped portion P1 and the third P-type doped portion P3 on the target projection plane can be symmetrically arranged along the dashed line BB; the orthographic projections of the first N-type doped portion N1 and the third N-type doped portion N3 on the target projection plane can also be symmetrically arranged along the dashed line BB. The extension length of the orthographic projection of the second extension portion N12 on the target projection plane can be greater than the extension length of the orthographic projection of the first extension portion N11 on the target projection plane, and the extension length of the orthographic projection of the seventh extension portion N37 on the target projection plane can be greater than the extension length of the orthographic projection of the sixth extension portion N36 on the target projection plane.

[0046] In this exemplary embodiment, as Figure 2-5 As shown, the orthographic projection of the second P-type doped portion P2 on the target projection surface is located on the side of the orthographic projection of the third N-type doped portion N3 on the target projection surface that is far away from the orthographic projection of the third P-type doped portion P3 on the target projection surface; the orthographic projection of the second N-type doped portion N2 on the target projection surface is located on the side of the orthographic projection of the third P-type doped portion P3 on the target projection surface that is far away from the orthographic projection of the third N-type doped portion N3 on the target projection surface.

[0047] In this exemplary embodiment, as Figure 2-5As shown, a portion of the structure of the first extension N11 and at least a portion of the structure of the third extension P13 are arranged opposite to each other in the second direction Y; a portion of the structure of the first extension N11 and at least a portion of the structure of the fourth extension P14 are arranged opposite to each other in the second direction Y; a portion of the structure of the sixth extension N36 and at least a portion of the structure of the eighth extension P38 are arranged opposite to each other in the second direction Y; and a portion of the structure of the sixth extension N36 and at least a portion of the structure of the ninth extension P39 are arranged opposite to each other in the second direction Y. It should be noted that, in this exemplary embodiment, the arrangement of structure A and structure B opposite to each other in a certain direction can be understood as follows: the area covered by the orthographic projection of structure A on the target projection plane moving infinitely in that direction coincides with the area covered by the orthographic projection of structure B on the target projection plane moving infinitely in that direction. This arrangement can further reduce the size of the electrostatic protection structure in the first direction X.

[0048] In this exemplary embodiment, as Figure 2-5 As shown, at least a portion of the structure of the first extension N11 and at least a portion of the structure of the sixth extension N36 can be arranged opposite each other in the first direction X. For example, the first extension N11 and the sixth extension N36 can be arranged opposite each other in the first direction X; at least a portion of the structure of the fifth extension N15 and at least a portion of the structure of the tenth extension N310 can be arranged opposite each other in the first direction X. For example, the fifth extension N15 and the tenth extension N310 can be arranged opposite each other in the first direction X. This arrangement can reduce the size of the electrostatic protection structure in the second direction Y.

[0049] In this exemplary embodiment, as Figure 2-5 As shown, at least a portion of the structure of the first extension N11 and a portion of the structure of the second P-type doped portion P2 are arranged opposite each other in the second direction Y; at least a portion of the structure of the sixth extension N36 and a portion of the structure of the second P-type doped portion P2 are arranged opposite each other in the second direction Y; at least a portion of the structure of the fifth extension P15 and a portion of the structure of the second N-type doped portion N2 are arranged opposite each other in the second direction Y; and at least a portion of the structure of the tenth extension P310 and a portion of the structure of the second N-type doped portion N2 are arranged opposite each other in the second direction Y. This arrangement ensures that the electrostatic protection structure has a small size in the first direction X, and also ensures that the second N-type doped portion N2 and the second P-type doped portion P2 have a certain extension length, thereby reducing the contact resistance between the cathode of the first diode D1 and the anode of the second diode D2.

[0050] In this exemplary embodiment, as Figure 2-5As shown, the P-type well PW includes: a first well region PW1, a second well region PW2, and a third well region PW3. The orthographic projection of the first well region PW1 on the target projection plane can extend along the first direction X. The second well region PW2 is connected to the first well region PW1, and the orthographic projection of the second well region PW2 on the target projection plane can extend along the second direction Y. The third well region PW3 is connected to the first well region PW1, and the orthographic projection of the third well region PW3 on the target projection plane can extend along the second direction Y. The orthographic projections of the third well region PW3 and the second well region PW2 on the target projection plane are located on the same side of the orthographic projection of the first well region PW1 on the target projection plane. The first extension N11, the sixth extension N36, and the second P-type doped region P2 can be located in the first well region PW1, the second extension N12 can be located in the second well region PW2, and the seventh extension N37 can be located in the third well region PW3.

[0051] In this exemplary embodiment, as Figure 2-5 As shown, the electrostatic discharge (ESD) protection structure may further include: a ring-shaped doped portion PC, the orthographic projection of the ring-shaped doped portion PC on the target projection plane surrounding the orthographic projections of the N-type well NW and the P-type well PW on the target projection plane; the doping type of the ring-shaped doped portion PC is the same as the doping type of the semiconductor substrate Psub. The ring-shaped doped portion PC can be connected to a stable power supply terminal, for example, the ring-shaped doped portion PC can be grounded, which allows the ESD protection structure to be electrically isolated from other structures on the semiconductor substrate.

[0052] In this exemplary embodiment, as Figure 5 As shown, adjacent doped regions can be isolated by a barrier wall (STI).

[0053] In this exemplary embodiment, as Figure 2-6 As shown, Figure 6 for Figure 2The structural layout of the deep well is shown. The orthographic projection of the N-type well NW on the target projection plane surrounds the orthographic projection of the P-type well PW on the target projection plane. The semiconductor substrate Psub can be a P-type semiconductor substrate. The electrostatic discharge (ESD) protection structure may further include an N-type deep well DNW, which is isolated between the semiconductor substrate Psub and the P-type well PW. The N-type deep well DNW can form a PN junction with the P-type semiconductor substrate, thereby improving the leakage current problem from the P-type well PW to the semiconductor substrate Psub. It should be understood that in other exemplary embodiments, when the semiconductor substrate is an N-type semiconductor substrate, the ESD protection structure may include a P-type deep well, which can be isolated between the N-type well and the N-type semiconductor substrate Psub. The P-type deep well can form a PN junction with the N-type well, thereby similarly improving the leakage current problem from the N-type well to the semiconductor substrate Psub. In addition, the deep well can also provide noise shielding for the components in the N-type well NW and the P-type well PW.

[0054] In this exemplary embodiment, the doping concentration of the doped well (e.g., P-type well, N-type well, N-type deep well) may be less than the doping concentration of the doped portion (e.g., first N-type doped portion, first P-type doped portion, second N-type doped portion, second P-type doped portion, third N-type doped portion, third P-type doped portion, ring doped portion).

[0055] In other exemplary embodiments, the electrostatic protection structure may include only one set Figure 1 The electrostatic discharge (ESD) protection circuit shown may, correspondingly, exclude the third P-type doped portion P3 and the third N-type doped portion N3.

[0056] This exemplary embodiment also provides a chip, wherein the chip may include the electrostatic protection structure described above.

[0057] In this exemplary embodiment, the chip may include a first terminal and a second terminal. The first terminal may be connected to the first N-type doped portion N1, and the second terminal may be connected to the first P-type doped portion P1. In this exemplary embodiment, the chip may include a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal. The first terminal may be the high-level power supply terminal, and the second terminal may be the signal transmission terminal; or, the first terminal may be the signal transmission terminal, and the second terminal may be the low-level power supply terminal; or, the first terminal may be the high-level power supply terminal, and the second terminal may be the low-level power supply terminal. The signal transmission terminal may include one of a signal input terminal and a signal output terminal.

[0058] like Figure 7The diagram shown is a structural schematic of an exemplary embodiment of the chip disclosed herein. The chip may include a high-level power supply terminal Vdd, a low-level power supply terminal Vss, a signal transmission terminal, and a core processing circuit CT. The signal transmission terminal may include a signal output terminal OUT and a signal input terminal IN. In this exemplary embodiment, the chip may include multiple... Figure 2 The electrostatic discharge (ESD) protection structure shown may include: a first ESD protection structure ESD1 and a second ESD protection structure ESD2. The first P-type doped portion and the third N-type doped portion of the first ESD protection structure ESD1 are connected to the signal input terminal IN, the first N-type doped portion of the first ESD protection structure ESD1 is connected to the high-level power supply terminal Vdd, and the third P-type doped portion of the first ESD protection structure ESD1 is connected to the low-level power supply terminal Vss. The first P-type doped portion and the third N-type doped portion of the second ESD protection structure ESD2 are connected to the signal output terminal OUT, the first N-type doped portion of the second ESD protection structure ESD2 is connected to the high-level power supply terminal Vdd, and the third P-type doped portion of the second ESD protection structure ESD2 is connected to the low-level power supply terminal Vss. It should be noted that the low-level power supply terminal Vss can be the ground terminal of the chip containing the ESD protection structure, and the high-level power supply terminal Vdd can be the power supply terminal of the chip containing the ESD protection structure.

[0059] Specifically, the low-level power supply terminal Vss can release static electricity to the signal input terminal IN through the first electrostatic discharge protection structure ESD1; the signal input terminal IN can release static electricity to the high-level power supply terminal Vdd through the first electrostatic discharge protection structure ESD1; the signal output terminal OUT can release static electricity to the high-level power supply terminal Vdd through the second electrostatic discharge protection structure ESD2; and the low-level power supply terminal Vss can release static electricity to the signal output terminal OUT through the second electrostatic discharge protection structure ESD2.

[0060] like Figure 8 The diagram shown is a structural schematic of another exemplary embodiment of the chip disclosed herein. This chip may also include a high-level power supply terminal Vdd, a low-level power supply terminal Vss, a signal transmission terminal, and a core processing circuit CT. The signal transmission terminal includes a signal output terminal OUT and a signal input terminal IN. In this exemplary embodiment, the chip may include a first electrostatic discharge (ESD) protection structure ESD1, a second ESD protection structure ESD2, a third ESD protection structure ESD3, and a fourth ESD protection structure ESD4. At least some of the ESD protection structures in the first ESD protection structure ESD1, the second ESD protection structure ESD2, the third ESD protection structure ESD3, and the fourth ESD protection structure ESD4 may be the aforementioned ESD protection structures. The aforementioned ESD protection structures may include one or two sets. Figure 1The electrostatic discharge (ESD) protection circuit is shown. For example, the structures of the second ESD protection structure ESD2 and the fourth ESD protection structure ESD4 can be as follows: Figure 2 As shown. In the second electrostatic discharge (ESD) protection structure ESD2, the first P-type doped portion and the third N-type doped portion are connected to the signal input terminal IN, and the first N-type doped portion and the third P-type doped portion are connected to the low-level power supply terminal Vss. In the fourth ESD protection structure ESD4, the first P-type doped portion and the third N-type doped portion are connected to the signal output terminal OUT, and the first N-type doped portion and the third P-type doped portion are connected to the low-level power supply terminal Vss. The low-level power supply terminal Vss and the signal input terminal IN can be bidirectionally discharged through the second ESD protection structure ESD2; the low-level power supply terminal Vss and the signal output terminal OUT can be bidirectionally discharged through the fourth ESD protection structure ESD4. The first ESD protection structure ESD1 and the third ESD protection structure ESD3 may include diode structures. In the first ESD protection structure ESD1, the anode of the diode is connected to the signal input terminal IN, and the cathode of the diode is connected to the high-level power supply terminal Vdd; in the third ESD protection structure ESD3, the anode of the diode is connected to the signal output terminal OUT, and the cathode of the diode is connected to the high-level power supply terminal Vdd.

[0061] In this exemplary embodiment, the chip can be a dynamic random access memory (DRAM) or a static random access memory (SRAM). It should be understood that the chip can also be other types of chips, and it can also include other signal transmission terminals, which can also release static electricity through the aforementioned electrostatic protection structure.

[0062] like Figure 7 , 8 As shown, the chip may also include a clamping circuit PCP, such as Figure 9The diagram shows a schematic of a clamping circuit in an exemplary embodiment of the chip disclosed herein. The clamping circuit pcp may include a capacitor C, a resistor R, and an N-type transistor NM. The capacitor C is connected between the high-level power supply terminal Vdd and node M, the resistor R is connected between node M and the low-level power supply terminal Vss, the gate of the N-type transistor NM is connected to node M, the first terminal of the N-type transistor NM is connected to the high-level power supply terminal Vdd, and the second terminal of the N-type transistor NM is connected to the low-level power supply terminal Vss. The semiconductor substrate of the N-type transistor NM may be connected to the second terminal of the N-type transistor NM. When static electricity occurs at the high-level power supply terminal Vdd, the voltage at Vdd increases. Under the coupling effect of capacitor C, the potential of node M increases, and the N-type transistor NM turns on. The high-level power supply terminal Vdd can release static electricity to the low-level power supply terminal Vss through the N-type transistor NM. It should be understood that in other exemplary embodiments, the semiconductor substrate of the N-type transistor NM may also be connected to the gate of the N-type transistor NM, thereby the N-type transistor NM can form a substrate driving transistor, which can be used to release a large electrostatic current.

[0063] like Figure 10 The diagram shown is a schematic representation of a clamping circuit in another exemplary embodiment of the chip disclosed herein. The clamping circuit may include a capacitor C, a resistor R, a P-type transistor PM, a first N-type transistor NM1, and a second N-type transistor NM2. The resistor R is connected between the high-level power supply terminal Vdd and the first node G1; the capacitor C is connected between the first node G1 and the low-level power supply terminal Vss; the first terminal of the P-type transistor PM is connected to the high-level power supply terminal Vdd, the second terminal is connected to the second node G2, and the gate is connected to the first node G1; the first terminal of the first N-type transistor NM1 is connected to the second node G2, the second terminal is connected to the low-level power supply terminal Vss, and the gate is connected to the first node G1; the first terminal of the second N-type transistor NM2 is connected to the high-level power supply terminal Vdd, the second terminal is connected to the low-level power supply terminal Vss, and the gate is connected to the second node G2. When static electricity occurs at the high-level power supply terminal Vdd, a high-frequency alternating current is formed between the high-level power supply terminal Vdd and the low-level power supply terminal Vss. Under the action of the high-frequency alternating current, the impedance of capacitor C decreases, the first node G1 is pulled low by the low-level power supply terminal Vss, the P-type transistor PM is turned on, the high-level power supply terminal Vdd inputs a high-level signal to the second node G2, the second N-type transistor NM2 is turned on, and the high-level power supply terminal Vdd releases static electricity to the low-level power supply terminal Vss through the second N-type transistor NM2.

[0064] This exemplary embodiment cleverly integrates the electrostatic discharge (ESD) protection structure and clamping circuitry, achieving full-chip ESD protection. The ESD protection structure employs a novel layout method, featuring small area, low trigger voltage, strong anti-latch-up capability, high ESD protection capability, and small capacitance. This ESD protection structure can be used for ESD protection in low-voltage, high-speed integrated circuit products.

[0065] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0066] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. An electrostatic protection structure, wherein, The electrostatic protection structure includes: Semiconductor substrate; An N-type well, wherein the N-type well is located within the semiconductor substrate; P-type well, wherein the P-type well is located within the semiconductor substrate; The first N-type doped portion is located within the P-type well, and the first N-type doped portion includes a first extension and a second extension connected to each other. Wherein, the orthographic projection of the first extension on the target projection surface extends along a first direction, the orthographic projection of the second extension on the target projection surface extends along a second direction, the target projection surface is parallel to the plane where the semiconductor substrate is located, and the first direction and the second direction intersect. A first P-type doped portion is located within the N-type well. The first P-type doped portion includes a third extension, a fourth extension, and a fifth extension connected between the third extension and the fourth extension. Wherein, the orthographic projections of the third extension and the fourth extension on the target projection surface both extend along the second direction, and the orthographic projection of the second extension on the target projection surface is located between the orthographic projections of the third extension and the fourth extension on the target projection surface, and the orthographic projection of the fifth extension on the target projection surface is located on the side of the orthographic projection of the second extension on the target projection surface that is far away from the orthographic projection of the first extension on the target projection surface; The second P-type doped portion is located in the P-type well. The orthographic projection of the second P-type doped portion on the target projection surface extends along the first direction and is located on the side where the orthographic projection of the first N-type doped portion on the target projection surface is far away from the orthographic projection of the first P-type doped portion on the target projection surface. The second N-type doped portion is located in the N-type well. The orthographic projection of the second N-type doped portion on the target projection surface extends along the first direction and is located on the side of the first P-type doped portion on the target projection surface that is away from the orthographic projection of the first N-type doped portion on the target projection surface. The second P-type doped portion and the second N-type doped portion are electrically connected.

2. The electrostatic protection structure according to claim 1, wherein, The electrostatic protection structure also includes: The third N-type doped portion is located in the P-type well, and the orthographic projection of the third N-type doped portion on the target projection plane and the orthographic projection of the first N-type doped portion on the target projection plane are spaced apart in the first direction. The third N-type doped portion includes a sixth extension portion and a seventh extension portion connected in series. The orthographic projection of the sixth extension portion on the target projection surface extends along the first direction, and the orthographic projection of the seventh extension portion on the target projection surface extends along the second direction. The third P-type doped portion is located in the N-type well, and the orthographic projection of the third P-type doped portion on the target projection plane and the orthographic projection of the first P-type doped portion on the target projection plane are spaced apart in the first direction. The third P-type doped portion includes an eighth extension, a ninth extension, and a tenth extension connected between the eighth and ninth extensions. The orthographic projections of the eighth and ninth extensions on the target projection plane both extend along the second direction. The orthographic projection of the seventh extension on the target projection plane is located between the orthographic projections of the eighth and ninth extensions on the target projection plane. The orthographic projection of the tenth extension on the target projection plane is located on the side of the seventh extension on the target projection plane that is away from the orthographic projection of the sixth extension on the target projection plane. The orthographic projection of the second P-type doped portion on the target projection plane is located on the side of the orthographic projection of the third N-type doped portion on the target projection plane that is far away from the orthographic projection of the third P-type doped portion on the target projection plane; The orthographic projection of the second N-type doped portion on the target projection plane is located on the side of the orthographic projection of the third P-type doped portion on the target projection plane that is far away from the orthographic projection of the third N-type doped portion on the target projection plane.

3. The electrostatic protection structure according to claim 2, wherein, A portion of the structure of the first extension and at least a portion of the structure of the third extension are disposed opposite to each other in the second direction, and a portion of the structure of the first extension and at least a portion of the structure of the fourth extension are disposed opposite to each other in the second direction; A portion of the structure of the sixth extension and at least a portion of the structure of the eighth extension are disposed opposite to each other in the second direction, and a portion of the structure of the sixth extension and at least a portion of the structure of the ninth extension are disposed opposite to each other in the second direction.

4. The electrostatic protection structure according to claim 2, wherein, The P-type well includes: A first well region, wherein the orthographic projection of the first well region onto the target projection plane extends along the first direction; The second well region is connected to the first well region, and the orthographic projection of the second well region on the target projection plane extends along the second direction; A third well region is connected to the first well region. The orthographic projection of the third well region on the target projection plane extends along the second direction, and the orthographic projection of the third well region on the target projection plane and the orthographic projection of the second well region on the target projection plane are located on the same side of the orthographic projection of the first well region on the target projection plane. The first extension, the sixth extension, and the second P-type doped portion are located in the first well region, the second extension is located in the second well region, and the seventh extension is located in the third well region.

5. The electrostatic protection structure according to claim 2, wherein, At least a portion of the structure of the first extension and a portion of the structure of the second P-type doped portion are disposed opposite to each other in the second direction; at least a portion of the structure of the sixth extension and a portion of the structure of the second P-type doped portion are disposed opposite to each other in the second direction. At least a portion of the structure of the fifth extension and a portion of the structure of the second N-type doped portion are disposed opposite to each other in the second direction, and at least a portion of the structure of the tenth extension and a portion of the structure of the second N-type doped portion are disposed opposite to each other in the second direction.

6. The electrostatic protection structure according to any one of claims 1-5, wherein, The orthographic projection of the N-type well on the target projection plane surrounds the orthographic projection of the P-type well on the target projection plane; The semiconductor substrate is a P-type semiconductor substrate, and the electrostatic protection structure further includes: The N-type deep well is isolated between the semiconductor substrate and the P-type well.

7. The electrostatic protection structure according to any one of claims 1-5, wherein, The electrostatic protection structure also includes: A ring-shaped doped portion, the orthographic projection of which surrounds the orthographic projection of the N-type well and the orthographic projection of the P-type well on the target projection plane; The doping type of the ring-shaped doped portion is the same as the doping type of the semiconductor substrate.

8. A chip, wherein, The chip includes the electrostatic protection structure as described in any one of claims 1-7.

9. The chip according to claim 8, wherein, The chip includes a first end and a second end, the first end being connected to the first N-type doped part, and the second end being connected to the first P-type doped part.

10. The chip according to claim 9, wherein, The chip includes a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal; The first end is the high-level power supply end, and the second end is the signal transmission end; Alternatively, the first end may be the signal transmission end, and the second end may be the low-level power supply end; Alternatively, the first terminal may be the high-level power supply terminal, and the second terminal may be the low-level power supply terminal.

11. The chip according to claim 8, wherein, The chip includes a low-level power supply terminal and a signal transmission terminal; When the electrostatic protection structure includes a third P-type doped part and a third N-type doped part, the signal transmission terminal is connected to the first P-type doped part and the third N-type doped part, and the low-level power supply terminal is connected to the first N-type doped part and the third P-type doped part.

12. The chip according to claim 11, wherein, The signal transmission terminal includes a signal output terminal and a signal input terminal, and the chip includes multiple electrostatic discharge (ESD) protection structures, the multiple ESD protection structures including: A first electrostatic discharge (ESD) protection structure, wherein the first P-type doped portion and the third N-type doped portion of the first ESD protection structure are connected to the signal input terminal, and the first N-type doped portion and the third P-type doped portion of the first ESD protection structure are connected to the low-level power supply terminal. The second electrostatic discharge (ESD) protection structure has a first P-type doped portion and a third N-type doped portion connected to the signal output terminal, and the first N-type doped portion and the third P-type doped portion connected to the low-level power supply terminal.

13. The chip according to claim 8, wherein, The chip includes a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal; When the electrostatic protection structure includes a third P-type doped part and a third N-type doped part, the signal transmission terminal is connected to the first P-type doped part and the third N-type doped part, the high-level power supply terminal is connected to the first N-type doped part, and the low-level power supply terminal is connected to the third P-type doped part.

14. The chip according to claim 13, wherein, The signal transmission terminal includes a signal output terminal and a signal input terminal, and the chip includes multiple electrostatic discharge (ESD) protection structures, the multiple ESD protection structures including: A first electrostatic discharge (ESD) protection structure, wherein the first P-type doped portion and the third N-type doped portion of the first ESD protection structure are connected to the signal input terminal, the first N-type doped portion of the first ESD protection structure is connected to the high-level power supply terminal, and the third P-type doped portion of the first ESD protection structure is connected to the low-level power supply terminal. The second electrostatic discharge (ESD) protection structure has a first P-type doped portion and a third N-type doped portion connected to the signal output terminal, the first N-type doped portion connected to the high-level power supply terminal, and the third P-type doped portion connected to the low-level power supply terminal.

15. The chip according to claim 8, wherein, The chip is a dynamic random access memory or a static random access memory.

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