A semiconductor structure and a method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate and a first isolation trench located within the substrate; a first insulating layer covering the bottom surface and lower portion of the sidewalls of the first isolation trench; a second insulating layer covering the upper portion of the sidewalls of the first isolation trench; and a third insulating layer, at least partially located between the first insulating layer and the second insulating layer, to isolate the first insulating layer and the second insulating layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] A semiconductor structure typically includes a substrate, multiple transistors located on the substrate, and an isolation structure located within the substrate to isolate the transistors. Transistors typically employ a planar gate structure, with the gate structure and isolation structure having an intersection.

[0003] However, as semiconductor structures continue to evolve towards miniaturization and high integration, the electric field between transistor channel regions increases rapidly, generating many hot electrons. This leads to the hot electron-induced punch-through (HEIP) effect, where hot electrons are trapped within the isolation structure, degrading the transistor's turn-off characteristics and reducing the performance of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, including: Substrate and a first isolation trench located within the substrate; A first insulating layer covers the bottom surface and the lower part of the sidewalls of the first isolation trench; A second insulating layer covers the upper part of the sidewall of the first isolation trench; A third insulating layer, at least partially located between the first insulating layer and the second insulating layer, is used to isolate the first insulating layer and the second insulating layer.

[0005] In some embodiments, the materials of the first insulating layer and the second insulating layer comprise nitrides, and the material of the third insulating layer comprises oxides.

[0006] In some embodiments, the ratio of the height of the first insulating layer to the height of the second insulating layer is between 2 and 6, and the ratio of the height of the portion of the third insulating layer located between the first and second insulating layers to the height of the second insulating layer is between 0.3 and 0.7.

[0007] In some embodiments, the thickness of the first insulating layer and the second insulating layer is 5-30 nm.

[0008] In some embodiments, it also includes: A fourth insulating layer is located between the inner wall of the first isolation trench and the first insulating layer, and the fourth insulating layer covers the bottom surface and the lower part of the side wall of the first isolation trench. A first filler layer fills the recess defined by the first insulating layer within the first isolation trench.

[0009] In some embodiments, the third insulating layer includes a bottom layer and a sidewall layer, the bottom layer covering the top of the fourth insulating layer, the first insulating layer and the first filler layer, and the sidewall layer being located between the upper sidewall of the first isolation trench and the second insulating layer.

[0010] In some embodiments, it also includes: A second filler layer fills the depression defined within the first isolation trench by the bottom layer of the second insulating layer and the third insulating layer.

[0011] In some embodiments, it also includes: The second isolation trench includes a first sub-trench and a second sub-trench, wherein the width of the second sub-trench is greater than the width of the first sub-trench.

[0012] In some embodiments, the fourth insulating layer covers the bottom surface and lower part of the sidewall of the second sub-trench, the first insulating layer fills the recess defined by the fourth insulating layer in the second sub-trench; the third insulating layer covers the upper part of the sidewall of the second sub-trench and the top of the fourth insulating layer and the first insulating layer; the second filling layer fills the recess defined by the third insulating layer in the second sub-trench.

[0013] In some embodiments, the first isolation trench is located in the core region or peripheral region of the device and is used to isolate the selection transistor, and the second isolation trench is located in the device cell region and is used to isolate the memory cell.

[0014] This disclosure also provides a method for manufacturing a semiconductor structure, including: Provide substrate; The substrate is etched to form a first isolation trench; A first insulating layer is formed, which covers the bottom surface and the lower part of the sidewall of the first isolation trench; A third insulating layer is formed above the first insulating layer, the third insulating layer at least covering the top of the first insulating layer; A second insulating layer is formed above the third insulating layer, the second insulating layer covering the upper part of the sidewall of the first isolation trench, and the third insulating layer isolates the first insulating layer and the second insulating layer.

[0015] In some embodiments, the step of etching the substrate to form the first isolation trench further includes: The substrate is etched to form a second isolation trench, the second isolation trench including a first sub-trench and a second sub-trench, the width of the second sub-trench being greater than the width of the first sub-trench.

[0016] In some embodiments, prior to forming the first insulating layer, the method further includes: A fourth insulating material layer is formed, which covers the inner surfaces of the first isolation trench and the second sub-trench and fills the first sub-trench.

[0017] In some embodiments, forming the first insulating layer includes: A first insulating material layer is formed, which covers the fourth insulating material layer and fills the second sub-groove; A first filler material layer is formed, which covers the first insulating material layer and fills the first isolation trench; The first filling material layer, the first insulating material layer, and the fourth insulating material layer are etched such that the top of the first insulating material layer, the fourth insulating material layer, and the first filling material layer is lower than the upper surface of the substrate, thereby forming the first insulating layer, the fourth insulating layer, and the first filling layer.

[0018] In some embodiments, forming the third insulating layer includes: A third insulating material layer is formed, and the third insulating material layer is etched to form a third insulating layer covering the top of the fourth insulating layer, the first insulating layer and the first filling layer, as well as the upper part of the sidewalls of the first isolation trench and the second sub-trench. The portion of the third insulating layer in the first isolation trench defines a first accommodating cavity, and the portion of the third insulating layer in the second sub-trench defines a second accommodating cavity.

[0019] In some embodiments, forming the second insulating layer includes: A second insulating material layer is formed, which covers the bottom surface and sidewalls of the first accommodating cavity and fills the second accommodating cavity; The second insulating material layer is etched to remove the second insulating material layer located in the second accommodating cavity and the second insulating material layer covering the bottom surface of the first accommodating cavity, so as to form a second insulating layer covering the sidewall of the first accommodating cavity.

[0020] In some embodiments, after forming the second insulating layer, the method further includes: A second filling material layer is formed above the third insulating layer and the second insulating layer, and the second filling material layer completely fills the first accommodating cavity and the second accommodating cavity; The second filler layer is etched so that the top of the second filler layer is flush with the top of the second insulating layer, thereby forming the second filler layer.

[0021] The semiconductor structure and its manufacturing method provided in this disclosure include: a substrate and a first isolation trench located within the substrate; a first insulating layer covering the bottom surface and lower portion of the sidewalls of the first isolation trench; a second insulating layer covering the upper portion of the sidewalls of the first isolation trench; and a third insulating layer, at least partially located between the first insulating layer and the second insulating layer, to isolate the first insulating layer and the second insulating layer. This disclosure uses a third insulating layer to separate the first insulating layer and the second insulating layer, thereby separating the hot electrons trapped in the first insulating layer from those trapped in the second insulating layer. This prevents the hot electrons trapped in the second insulating layer from flowing into the first insulating layer, reducing the number of hot electrons stored in the first insulating layer. Simultaneously, the separation of the first and second insulating layers reduces the carriers for storing hot electrons compared to when the first and second insulating layers are not separated, thus effectively mitigating the HEIP effect.

[0022] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the accompanying drawings and claims. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 For along Figure 1 A schematic diagram of the cross-sectional structure taken by lines A-A' and B-B'; Figure 3 A flowchart illustrating a semiconductor structure manufacturing method provided in an embodiment of this disclosure; Figures 4 to 12 A process flow diagram of the semiconductor structure provided in the embodiments of this disclosure. Detailed Implementation

[0025] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0026] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0027] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0029] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] A semiconductor structure typically includes a substrate, multiple transistors on the substrate, isolation trenches within the substrate for isolating the transistors, and isolation structures within the isolation trenches. The transistors typically employ a planar gate structure, with the gate structure intersecting the isolation structure. The isolation structure typically includes an oxide layer covering the inner walls of the isolation trench, a nitride layer covering the oxide layer, and a fill layer filling the isolation trench.

[0032] However, as semiconductor structures continue to evolve towards miniaturization and high integration, the electric field between transistor channel regions increases rapidly, generating numerous hot electrons. These hot electrons are trapped within nitride layers capable of trapping high-energy electrons. The trapped hot electrons can attract holes to the substrate adjacent to the isolation structure, causing the effective channel length of the transistor to be less than its original length. Therefore, even without applying a voltage to the transistor's gate structure, current can flow, degrading the transistor's turn-off characteristics and increasing leakage current, thus reducing the performance of the semiconductor structure. This is the hot electron-induced punch-through effect (HEIP).

[0033] The HEIP effect is usually mitigated by increasing the thickness of the oxide layer to increase the distance between the nitride layer and the substrate; however, this increases the difficulty of forming the isolation structure.

[0034] Based on this, the following technical solutions of the embodiments of this disclosure are proposed. The specific implementation methods of this disclosure will be described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of this disclosure, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0035] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure. Figure 2 For along Figure 1 The following is a schematic diagram of the cross-sectional structure taken by lines A-A' and B-B'. (The following is combined with...) Figures 1 to 2 The semiconductor structure provided in the embodiments of this disclosure will be further described.

[0036] As shown in the figure, the semiconductor structure includes: a substrate 10 and a first isolation trench 11 located within the substrate 10; a first insulating layer 13 covering the bottom surface and lower part of the sidewalls of the first isolation trench 11; a second insulating layer 16 covering the upper part of the sidewalls of the first isolation trench 11; and a third insulating layer 15, at least partially located between the first insulating layer 13 and the second insulating layer 16, to isolate the first insulating layer 13 and the second insulating layer 16.

[0037] In practice, the semiconductor structure provided in this disclosure can be a three-dimensional dynamic random access memory (3DDRAM), but it is not limited to this, and the semiconductor structure can be any semiconductor structure.

[0038] The substrate may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0039] In one embodiment, the substrate 10 includes a device cell region 101 and a device core region or peripheral region 102. In some embodiments, a first isolation trench 11 is located in the device core region or peripheral region 102 for isolating a selection transistor. Specifically, the first isolation trench 11 defines at least one first active region AA1 within the device core region or peripheral region 102. In practice, a selection transistor with a planar gate structure, such as a P-type transistor or an N-type transistor, can be formed on the first active region AA1.

[0040] In one embodiment, the materials of the first insulating layer 13 and the second insulating layer 16 include nitrides. This disclosure uses nitrides as the materials for the first insulating layer 13 and the second insulating layer 16, thus allowing for the increase of tensile or compressive stress in the transistor channel region as needed, thereby meeting the transistor's stress requirements and improving the carrier mobility in the transistor channel region. Specifically, tensile stress creates tensile strain in the channel region, which can increase the electron mobility of N-type transistors, while compressive stress creates compressive strain in the channel region, which can increase the hole mobility of P-type transistors. The materials of the first insulating layer 13 and the second insulating layer 16 can be the same or different. In a specific embodiment, the materials of the first insulating layer 13 and the second insulating layer 16 are the same, for example, silicon nitride. However, this is not a limitation; any material that meets the above stress requirements can be used as the material for the first insulating layer 13 and the second insulating layer 16. The material of the third insulating layer 15 includes oxides, for example, silicon oxide.

[0041] The first insulating layer 13 and the second insulating layer 16 have the ability to trap hot electrons. In this embodiment, a third insulating layer 15 is used to separate the first insulating layer 13 and the second insulating layer 16, thereby separating the hot electrons trapped in the first insulating layer 13 from those trapped in the second insulating layer 16. This prevents the hot electrons trapped in the second insulating layer 16 from flowing into the first insulating layer 13, reducing the number of hot electrons stored in the first insulating layer 13. Simultaneously, since the first insulating layer 13 and the second insulating layer 16 are separated, compared to when the first insulating layer 13 and the second insulating layer 16 are not separated, the carriers for storing hot electrons in the first insulating layer 13 and the second insulating layer 16 are reduced, thus allowing them to store fewer hot electrons. This effectively mitigates the HEIP effect.

[0042] The ratio of the height of the first insulating layer 13 to the height of the second insulating layer 16 should not be too large or too small. If the ratio is too large, the first insulating layer 13 will extend to the upper part of the first isolation trench 11, and a large number of hot electrons will be stored within it. Consequently, a large number of holes will accumulate in the upper part of the first active region AA1, thus the effect of mitigating the HEIP effect is not significant. If the ratio is too small, the height of the second insulating layer 16 located above the first isolation trench 11 will be relatively high, allowing it to capture a large number of hot electrons. Consequently, a large number of holes will accumulate in the upper part of the first active region AA1, again resulting in a weak effect of mitigating the HEIP effect. In one embodiment, the ratio of the height of the first insulating layer 13 to the height of the second insulating layer 16 is between 2 and 6, specifically, for example, 3, 4, or 5.

[0043] The height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 should not be too large or too small. When the height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 is too large, the sum of the heights of the first insulating layer 13 and the second insulating layer 16 is small, thus the effect of the first insulating layer 13 and the second insulating layer 16 in improving the stress of the substrate 10 is not significant. When the height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 is too small, the effect of mitigating the HEIP effect is not significant. In one embodiment, the ratio of the height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 to the height of the second insulating layer 16 is in the range of 0.3 to 0.7, specifically, for example, 0.4, 0.5, 0.6, etc.

[0044] In one embodiment, the thickness of the first insulating layer 13 and the second insulating layer 16 is 5-30 nm. In some embodiments, the thickness of the first insulating layer 13 and the second insulating layer 16 is 10-25 nm. In a specific embodiment, the thickness of the first insulating layer 13 is greater than the thickness of the second insulating layer 16, and the second insulating layer 16 has a thinner thickness. In this way, fewer hot electrons can be stored in the first insulating layer 13, effectively mitigating the HEIP effect.

[0045] In one embodiment, the semiconductor structure further includes: a fourth insulating layer 18, located between the inner wall of the first isolation trench 11 and the first insulating layer 13, and covering the bottom surface and lower part of the sidewall of the first isolation trench 11; and a first filling layer 14, filling the recess S1 defined by the first insulating layer 13 within the first isolation trench 11. The material of the fourth insulating layer 18 can be the same as the material of the third insulating layer 15, for example, silicon oxide. The material of the first filling layer 14 can be an oxide, such as silicon oxide.

[0046] In one embodiment, the third insulating layer 15 includes a bottom layer 151 and a sidewall layer 152. The bottom layer 151 covers the top of the fourth insulating layer 18, the first insulating layer 13, and the first filler layer 14. The sidewall layer 152 is located between the upper sidewall of the first isolation trench 11 and the second insulating layer 16. In some embodiments, the third insulating layer 15 also covers the upper surface of the substrate 10.

[0047] This embodiment of the present disclosure further mitigates the HEIP effect by providing a fourth insulating layer 18 and a third insulating layer 15 between the substrate 10 and the first insulating layer 13 and the second insulating layer 16, thereby separating the substrate 10 from the first insulating layer 13 and the second insulating layer 16. Furthermore, this embodiment of the present disclosure effectively mitigates the HEIP effect by using the third insulating layer 15 to separate the first insulating layer 13 and the second insulating layer 16. Thus, it eliminates the need to additionally thicken the fourth insulating layer 18 and the third insulating layer 15, simplifying the process and improving the process window.

[0048] In one embodiment, the semiconductor structure further includes a second filling layer 17, which fills the recess S2 defined within the first isolation trench 11 by the bottom layer 151 of the second insulating layer 16 and the third insulating layer 15. The material of the second filling layer 17 may be the same as that of the first filling layer 14, for example, silicon oxide.

[0049] In one embodiment, the semiconductor structure further includes a second isolation trench 12, which includes a first sub-trench 121 and a second sub-trench 122, wherein the width of the second sub-trench 122 is greater than the width of the first sub-trench 121. Specifically, the second isolation trench 12 is located in the device cell region 101, used to isolate memory cells, and defines a plurality of mutually parallel second active regions AA2 within the device cell region 101. In actual operation, the first isolation trench 11 and the second isolation trench 12 are formed in the same process step, and the width of the first isolation trench 11 is greater than the width of the first sub-trench 121 and the second sub-trench 122. It is understood that since the width of the first isolation trench 11 and the second sub-trench 122 is greater than the width of the first sub-trench 121, under the same etching process conditions, the depth of the first isolation trench 11 and the second sub-trench 122 will be greater than the depth of the first sub-trench 121.

[0050] In one embodiment, a fourth insulating layer 18 covers the bottom surface and lower portion of the sidewalls of the second sub-groove 122; a first insulating layer 13 fills the recess S3 defined by the fourth insulating layer 18 within the second sub-groove 122; a third insulating layer 15 covers the upper portion of the sidewalls of the second sub-groove 122 and the top of the fourth insulating layer 18 and the first insulating layer 13; and a second filling layer 17 fills the recess S4 defined by the third insulating layer 15 within the second sub-groove 122. In some embodiments, the fourth insulating layer 18 fills the lower portion of the first sub-groove 121, and the third insulating layer 15 fills the upper portion of the first sub-groove 121.

[0051] This disclosure also provides a method for manufacturing a semiconductor structure, such as... Figure 3 As shown, the method includes the following steps: Step 301: Provide a substrate; Step 302: Etch the substrate to form the first isolation trench; Step 303: Form a first insulating layer, which covers the bottom surface and the lower part of the sidewall of the first isolation trench; Step 304: Form a third insulating layer over the first insulating layer, wherein the third insulating layer at least covers the top of the first insulating layer; Step 305: A second insulating layer is formed above the third insulating layer. The second insulating layer covers the upper part of the sidewall of the first isolation trench, and the third insulating layer isolates the first insulating layer and the second insulating layer.

[0052] The following is combined Figures 4 to 12 , Figure 2 The method for manufacturing the semiconductor structure according to the embodiments of this disclosure will be described in further detail, wherein, Figures 4 to 12 For each process step along Figure 1 A schematic diagram of the cross-sectional structure taken by lines A-A' and B-B'.

[0053] First, such as Figure 4 As shown, step 301 is performed to provide substrate 10.

[0054] The substrate may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0055] In one embodiment, the substrate 10 includes a device cell region 101 and a device core region or peripheral region 102. In practice, memory cells can be formed in the device cell region 101, and selection transistors can be formed in the device core region or peripheral region 102.

[0056] Next, proceed to step 302, as follows: Figure 5 As shown, the etched substrate 10 forms a first isolation trench 11.

[0057] Specifically, the first isolation trench 11 can be formed by photolithography and dry / wet etching processes. The first isolation trench 11 is formed in the core region or peripheral region 102 of the device, and defines at least one first active region AA1 in the core region or peripheral region 102. In actual operation, a selection transistor with a planar gate structure, such as a P-type transistor or an N-type transistor, can be subsequently formed on the first active region AA1.

[0058] In one embodiment, in the same step of etching the substrate 10 to form the first isolation trench 11, the method further includes etching the substrate 10 to form a second isolation trench 12. The second isolation trench 12 includes a first sub-trench 121 and a second sub-trench 122, and the width of the second sub-trench 122 is greater than the width of the first sub-trench 121. In some embodiments, the second isolation trench 12 is formed in the device cell region 101 and defines a plurality of mutually parallel second active regions AA2 within the device cell region 101. In actual operation, memory cells can be subsequently formed on the second active regions AA2, and the second isolation trench 12 is used to isolate the memory cells. In this embodiment, the first isolation trench 11 and the second isolation trench 12 are formed in the same process step, thereby reducing one mask process and simplifying the process.

[0059] In one embodiment, the width of the first isolation trench 11 is greater than the width of the first sub-trench 121 and the second sub-trench 122. It is understood that, since the width of the first isolation trench 11 and the second sub-trench 122 is greater than the width of the first sub-trench 121, under the same etching process conditions, the depth of the first isolation trench 11 and the second sub-trench 122 will be greater than the depth of the first sub-trench 121.

[0060] Next, proceed to step 303, as follows: Figures 7 to 8 As shown, a first insulating layer 13 is formed, which covers the bottom surface and the lower part of the sidewall of the first isolation trench 11.

[0061] In one embodiment, such as Figure 6 As shown, before forming the first insulating layer 13, the process further includes forming a fourth insulating material layer 18', which covers the inner surfaces of the first isolation trench 11 and the second sub-trench 122 and fills the first sub-trench 121. In some embodiments, the fourth insulating material layer 18' also covers the upper surface of the substrate 10. It is understood that because the first sub-trench 121 has a smaller depth and width, under the same deposition process conditions, the fourth insulating material layer 18' can fill the first sub-trench 121 without filling the first isolation trench 11 and the second sub-trench 122, such that the finally formed fourth insulating layer 18 fills the lower part of the first sub-trench 121. The fourth insulating material layer 18' can be formed using an atomic layer deposition (ALD) process combined with an in-situ vapor generation (ISSG) process. The material of the fourth insulating layer 18 includes oxides, such as silicon oxide.

[0062] See you again Figures 7 to 8 The formation of the first insulating layer 13 includes: A first insulating material layer 13' is formed, which covers the fourth insulating material layer 18' and fills the second sub-groove 122; A first filling material layer 14' is formed, which covers the first insulating material layer 13' and fills the first isolation trench 11; The first filling material layer 14', the first insulating material layer 13' and the fourth insulating material layer 18' are etched such that the top of the first insulating material layer 13', the fourth insulating material layer 18' and the first filling material layer 14' are lower than the upper surface of the substrate 10, thereby forming the first insulating layer 13, the fourth insulating layer 18 and the first filling layer 14.

[0063] Understandably, the second sub-trench 122 has a smaller width compared to the first isolation trench 11. Therefore, under the same deposition process conditions, the first insulating material layer 13' can fill the second sub-trench 122 without filling the first isolation trench 11. The first insulating material layer 13' and the first filling material layer 14' can be formed using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or a combination thereof. The material of the first insulating layer 13 includes nitrides, such as silicon nitride. The material of the first filling layer 14 includes oxides, such as silicon oxide.

[0064] Next, proceed to step 304, as follows: Figure 9 As shown, a third insulating layer 15 is formed above the first insulating layer 13, and the third insulating layer 15 at least covers the top of the first insulating layer 13.

[0065] Specifically, forming the third insulating layer 15 includes: forming a third insulating material layer (not shown); etching the third insulating material layer (not shown) to form a third insulating layer 15 covering the top of the fourth insulating layer 18, the first insulating layer 13, and the first filling layer 14, as well as the upper part of the sidewalls of the first isolation trench 11 and the second sub-trench 122. The portion of the third insulating layer 15 within the first isolation trench 11 defines a first accommodating cavity T1, and the portion of the third insulating layer 15 within the second sub-trench 122 defines a second accommodating cavity T2. The third insulating layer 15 also covers the upper surface of the substrate 10.

[0066] Understandably, the first sub-trench 121 has a smaller width and depth, therefore, under the same deposition process conditions, the third insulating layer 15 can fill the portion of the first sub-trench 121 not filled by the fourth insulating layer 18. The third insulating layer 15 can be formed using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or a combination thereof. The material of the third insulating layer 15 includes oxides, such as silicon oxide.

[0067] Next, proceed to step 305, as follows: Figures 10 to 11As shown, a second insulating layer 16 is formed above the third insulating layer 15. The second insulating layer 16 covers the upper part of the sidewall of the first isolation trench 11, and the third insulating layer 15 isolates the first insulating layer 13 and the second insulating layer 16.

[0068] Specifically, forming the second insulating layer 16 includes: A second insulating material layer 16' is formed, which covers the bottom surface and sidewalls of the first accommodating cavity T1 and fills the second accommodating cavity T2. The second insulating material layer 16' is etched to remove the second insulating material layer 16' located in the second accommodating cavity T2 and the second insulating material layer 16' covering the bottom surface of the first accommodating cavity T1, so as to form a second insulating layer 16 covering the sidewall of the first accommodating cavity T1.

[0069] Understandably, the width of the second sub-trench 122 is smaller than that of the first isolation trench 11. Therefore, the width of the second accommodating cavity T2 is smaller than that of the first accommodating cavity T1. Under the same deposition process conditions, the second insulating material layer 16' can fill the second accommodating cavity T2 but not the first accommodating cavity T1. The second insulating material layer 16' can be formed using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or a combination thereof.

[0070] In one embodiment, the material of the second insulating layer 16 includes a nitride. Using nitrides as the material for the first insulating layer 13 and the second insulating layer 16 in this disclosure allows for increasing the tensile or compressive stress in the transistor channel region as needed, thereby meeting the transistor's stress requirements and improving the carrier mobility in the transistor channel region. Specifically, tensile stress creates tensile strain in the channel region, which can increase the electron mobility of an N-type transistor, while compressive stress creates compressive strain in the channel region, which can increase the hole mobility of a P-type transistor. The materials of the first insulating layer 13 and the second insulating layer 16 can be the same or different. In one specific embodiment, the materials of the first insulating layer 13 and the second insulating layer 16 are the same, such as silicon nitride. However, this is not a limitation; any material that meets the above stress requirements can be used as the material for the first insulating layer 13 and the second insulating layer 16.

[0071] The first insulating layer 13 and the second insulating layer 16 have the ability to trap hot electrons. In this embodiment, a third insulating layer 15 is used to separate the first insulating layer 13 and the second insulating layer 16, thereby separating the hot electrons trapped in the first insulating layer 13 from those trapped in the second insulating layer 16. Especially during subsequent heat treatment processes, where hot electrons in the second insulating layer 16 may leak out, the presence of the third insulating layer 15 can prevent the hot electrons trapped in the second insulating layer 16 from flowing back into the first insulating layer 13. This reduces the number of hot electrons stored in the first insulating layer 13. Furthermore, since the first insulating layer 13 and the second insulating layer 16 are separated, compared to when they are not separated, the carriers for storing hot electrons in the first insulating layer 13 and the second insulating layer 16 are reduced, thus allowing them to store fewer hot electrons. This effectively mitigates the HEIP effect.

[0072] The ratio of the height of the first insulating layer 13 to the height of the second insulating layer 16 should not be too large or too small. If the ratio is too large, the first insulating layer 13 will extend to the upper part of the first isolation trench 11, and a large number of hot electrons will be stored within it. Consequently, a large number of holes will accumulate in the upper part of the first active region AA1, thus the effect of mitigating the HEIP effect is not significant. If the ratio is too small, the height of the second insulating layer 16 located above the first isolation trench 11 will be relatively high, allowing it to capture a large number of hot electrons. Consequently, a large number of holes will accumulate in the upper part of the first active region AA1, again resulting in a weak effect of mitigating the HEIP effect. In one embodiment, the ratio of the height of the first insulating layer 13 to the height of the second insulating layer 16 is between 2 and 6, specifically, for example, 3, 4, or 5.

[0073] The height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 should not be too large or too small. When the height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 is too large, the sum of the heights of the first insulating layer 13 and the second insulating layer 16 is small, thus the effect of the first insulating layer 13 and the second insulating layer 16 in improving the stress of the substrate 10 is not significant. When the height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 is too small, the effect of mitigating the HEIP effect is not significant. In one embodiment, the ratio of the height of the portion of the third insulating layer 15 located between the first insulating layer 13 and the second insulating layer 16 to the height of the second insulating layer 16 is in the range of 0.3 to 0.7, specifically, for example, 0.4, 0.5, 0.6, etc.

[0074] In one embodiment, the thickness of the first insulating layer 13 and the second insulating layer 16 is 5-30 nm. In some embodiments, the thickness of the first insulating layer 13 and the second insulating layer 16 is 10-25 nm. In a specific embodiment, the thickness of the first insulating layer 13 is greater than the thickness of the second insulating layer 16, and the second insulating layer 16 has a thinner thickness. In this way, fewer hot electrons can be stored in the first insulating layer 13, effectively mitigating the HEIP effect.

[0075] See you again Figure 11 As can be seen, the fourth insulating layer 18 and the third insulating layer 15 separate the substrate 10 from the first insulating layer 13 and the second insulating layer 16, thus further mitigating the HEIP effect. Furthermore, by using the third insulating layer 15 to separate the first insulating layer 13 and the second insulating layer 16, the embodiments of this disclosure effectively mitigate the HEIP effect without requiring additional thickness increases to the fourth insulating layer 18 and the third insulating layer 15, simplifying the process and improving the process window.

[0076] Next, as Figure 12 and Figure 2 As shown, after forming the second insulating layer 16, the method further includes: A second filling material layer 17' is formed above the third insulating layer 15 and the second insulating layer 16, and the second filling material layer 17' completely fills the first accommodating cavity T1 and the second accommodating cavity T2; The second filler layer 17' is etched so that the top of the second filler layer 17' is flush with the top of the second insulating layer 16, thereby forming the second filler layer 17.

[0077] It should be noted that those skilled in the art can change the order of the above steps without departing from the scope of protection of this disclosure. The above description is only an optional embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate and a first isolation trench and a second isolation trench located within the substrate; A first insulating layer covers the bottom surface and the lower part of the sidewalls of the first isolation trench; A first filler layer fills the recess defined by the first insulating layer within the first isolation trench; A fourth insulating layer is located between the inner wall of the first isolation trench and the first insulating layer, and the fourth insulating layer covers the bottom surface and the lower part of the side wall of the first isolation trench. A second insulating layer covers the upper part of the sidewall of the first isolation trench; A third insulating layer, at least partially located between the first insulating layer and the second insulating layer, is used to isolate the first insulating layer and the second insulating layer. The third insulating layer includes a bottom layer and a sidewall layer. The bottom layer covers the top of the fourth insulating layer, the first insulating layer, and the first filler layer. The sidewall layer is located between the upper sidewall of the first isolation trench and the second insulating layer. A second filler layer fills the recess defined within the first isolation trench by the bottom layer of the second insulating layer and the third insulating layer; The second isolation trench includes a first sub-trench and a second sub-trench, wherein the width of the second sub-trench is greater than the width of the first sub-trench. The fourth insulating layer covers the bottom surface and lower part of the sidewall of the second sub-trench, and the first insulating layer fills the recess defined by the fourth insulating layer in the second sub-trench; The third insulating layer covers the upper part of the sidewall of the second sub-trench and the top of the fourth insulating layer and the first insulating layer; The second filler layer fills the depression defined by the third insulating layer within the second sub-trench.

2. The semiconductor structure according to claim 1, characterized in that, The materials of the first insulating layer and the second insulating layer include nitrides, and the material of the third insulating layer includes oxides.

3. The semiconductor structure according to claim 1, characterized in that, The ratio of the height of the first insulating layer to the height of the second insulating layer is between 2 and 6, and the ratio of the height of the portion of the third insulating layer located between the first and second insulating layers to the height of the second insulating layer is between 0.3 and 0.

7.

4. The semiconductor structure according to claim 1, characterized in that, The thickness of the first insulating layer and the second insulating layer is 5-30 nm.

5. The semiconductor structure according to claim 1, characterized in that, The first isolation trench is located in the core or peripheral region of the device and is used to isolate the selection transistor. The second isolation trench is located in the device cell region and is used to isolate the memory cell.

6. The semiconductor structure according to claim 1, characterized in that, The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

7. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; The substrate is etched to form a first isolation trench and a second isolation trench. The second isolation trench includes a first sub-trench and a second sub-trench, and the width of the second sub-trench is greater than the width of the first sub-trench. A first insulating layer is formed, which covers the bottom surface and the lower part of the sidewall of the first isolation trench; A third insulating layer is formed above the first insulating layer, the third insulating layer at least covering the top of the first insulating layer; A second insulating layer is formed above the third insulating layer, the second insulating layer covering the upper part of the sidewall of the first isolation trench, and the third insulating layer isolates the first insulating layer and the second insulating layer. Prior to forming the first insulating layer, the method further includes: A fourth insulating material layer is formed, which covers the inner surfaces of the first isolation trench and the second sub-trench and fills the first sub-trench.

8. The method according to claim 7, characterized in that, Forming the first insulating layer includes: A first insulating material layer is formed, which covers the fourth insulating material layer and fills the second sub-groove; A first filler material layer is formed, which covers the first insulating material layer and fills the first isolation trench; The first filling material layer, the first insulating material layer, and the fourth insulating material layer are etched such that the top of the first insulating material layer, the fourth insulating material layer, and the first filling material layer is lower than the upper surface of the substrate, thereby forming the first insulating layer, the fourth insulating layer, and the first filling layer.

9. The method according to claim 8, characterized in that, The formation of the third insulating layer includes: A third insulating material layer is formed, and the third insulating material layer is etched to form a third insulating layer covering the top of the fourth insulating layer, the first insulating layer and the first filling layer, as well as the upper part of the sidewalls of the first isolation trench and the second sub-trench. The portion of the third insulating layer in the first isolation trench defines a first accommodating cavity, and the portion of the third insulating layer in the second sub-trench defines a second accommodating cavity.

10. The method according to claim 9, characterized in that, The formation of the second insulating layer includes: A second insulating material layer is formed, which covers the bottom surface and sidewalls of the first accommodating cavity and fills the second accommodating cavity; The second insulating material layer is etched to remove the second insulating material layer located in the second accommodating cavity and the second insulating material layer covering the bottom surface of the first accommodating cavity, so as to form a second insulating layer covering the sidewall of the first accommodating cavity.

11. The method according to claim 10, characterized in that, After forming the second insulating layer, the method further includes: A second filling material layer is formed above the third insulating layer and the second insulating layer, and the second filling material layer completely fills the first accommodating cavity and the second accommodating cavity; The second filler layer is etched so that the top of the second filler layer is flush with the top of the second insulating layer, thereby forming the second filler layer.

12. The method according to claim 7, characterized in that, The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

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