Cell structure of trench gate mosfet, manufacturing method thereof, and trench gate mosfet

Abstract

The present application relates to the technical field of semiconductor, in particular to a kind of trench gate MOSFET's cell structure, preparation method and trench gate MOSFET.The cell structure includes: the first semiconductor layer of first conductive type, first buried layer and first source layer, the second semiconductor layer of second conductive type, gate and trench;Second semiconductor layer is formed on the upper portion of first semiconductor layer, and trench and first buried layer are all formed in second semiconductor layer;Trench is annular structure, at least part below in annular direction, first buried layer is provided with first buried layer, and first buried layer is in contact with trench and first semiconductor layer;Gate is formed in trench;First source layer is formed in the upper portion of second semiconductor layer located in the area surrounded by trench.Deep P-type junction is formed by cell structure, and the problem that high breakdown electric field at trench corner of trench gate MOSFET can effectively solve the damage of gate oxide, to ensure the reliability of trench gate MOSFET with the cell structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a cell structure, fabrication method, and trench gate MOSFET. Background Technology

[0002] Silicon carbide (SiC) is a semiconductor material with superior physical and electrical properties, such as high electron saturation drift velocity, high critical breakdown electric field, wide bandgap, and high thermal conductivity, making it suitable for high-temperature and high-voltage power electronics applications. Among them, 4H-SiC UMOSFETs, due to their higher cell density and high mobility on the non-polar surface, exhibit lower on-resistance and higher channel density. SiC UMOSFETs can be used in high-frequency applications, possessing high maximum electron velocity, high thermal conductivity, and a high breakdown electric field. However, the high breakdown electric field at the trench corners of SiC MOSFETs can easily damage the gate oxide. Summary of the Invention

[0003] In view of this, the present invention aims to provide a cell structure, fabrication method and trench gate MOSFET, to solve or partially solve the problem of gate oxide damage caused by high breakdown electric field at the trench corner of existing SiC MOSFET.

[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0005] In a first aspect, embodiments of the present invention provide a cell structure for a trench gate MOSFET, the cell structure comprising: a first semiconductor layer of a first conductivity type, a first buried layer and a first source layer, a second semiconductor layer of a second conductivity type, a gate and a trench; the second semiconductor layer is formed on top of the first semiconductor layer, and the trench and the first buried layer are both formed within the second semiconductor layer; the trench has an annular structure, and in the annular direction, at least a portion of the trench is provided below the first buried layer, the first buried layer being in contact with the trench and the first semiconductor layer; the gate is formed within the trench; the first source layer is formed on top of the second semiconductor layer located in the region enclosed by the trench.

[0006] Optionally, the cell structure further includes a carrier storage layer of a first conductivity type, the carrier storage layer being formed within the first semiconductor layer, the upper surface of the carrier storage layer being in contact with the lower surface of the first buried layer.

[0007] Optionally, the cell structure further includes a gate oxide layer, which is formed on the inner sidewall of the trench. The gate is disposed within the gate oxide layer, and the lower surface of the gate and the lower surface of the gate oxide layer are both located at the bottom of the trench.

[0008] Optionally, the width of the first buried layer is the same as the width of the trench.

[0009] Optionally, the cell structure further includes a first metal layer and a second source layer of a second conductivity type; the first source layer has a ring structure, the second source layer is formed within the ring structure, and the second source layer is in contact with the inner end of the first source layer and the first metal layer.

[0010] Optionally, both the first source layer and the second source layer are concentrated ion implantation layers.

[0011] Optionally, the cell structure further includes an insulating oxide layer, which is formed above the second semiconductor layer, the trench, and the first source layer. A through-hole is provided in the middle of the insulating oxide layer. A portion of the first metal layer is formed in the through-hole and is in contact with the second source layer.

[0012] Optionally, the first semiconductor layer includes a substrate, a first epitaxial layer, and a second epitaxial layer, wherein the first epitaxial layer is formed on the upper surface of the substrate, and the second epitaxial layer is formed on the upper surface of the first epitaxial layer; the second semiconductor layer includes a second buried layer and a well region; the first buried layer and the second buried layer are formed on the first epitaxial layer; the trench, the well region, and the first source layer are formed on the second epitaxial layer.

[0013] Optionally, the substrate, the first epitaxial layer, and the second epitaxial layer are all silicon carbide layers.

[0014] Secondly, embodiments of the present invention provide a method for fabricating the cell structure of a trench gate MOSFET, comprising the following steps:

[0015] Provide a first semiconductor layer of a first conductivity type;

[0016] A first buried layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a trench, and a gate in the trench are prepared on the first semiconductor layer; wherein the trench and the first buried layer are both formed in the second semiconductor layer, the trench has a ring structure, and at least a portion of the trench is provided below the first buried layer in the ring direction, and the first buried layer is in contact with the trench and the first semiconductor layer.

[0017] A first source layer is fabricated on the upper part of the second semiconductor layer located in the region enclosed by the trench.

[0018] Optionally, the first semiconductor layer includes a substrate, a first epitaxial layer, and a second epitaxial layer. The steps of fabricating a first buried layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a trench, and obtaining a gate within the trench on the first semiconductor layer further include:

[0019] The first buried layer and the second buried layer are prepared on the upper part of the first epitaxial layer;

[0020] Obtain the second epitaxial layer above the first epitaxial layer;

[0021] A trench is formed in a portion of the second epitaxial layer, and a gate is obtained within the trench;

[0022] A well region is prepared in the remaining portion of the second epitaxial layer, the well region being located on the outer periphery of the trench.

[0023] Optionally, the step of preparing the first buried layer and the second buried layer on the first epitaxial layer further includes:

[0024] A carrier storage layer is fabricated in the middle of the first epitaxial layer;

[0025] A first buried layer and a second buried layer are prepared on the upper part of the first epitaxial layer; wherein the upper surface of the carrier storage layer is in contact with the lower surface of the first buried layer and the lower surface of the second buried layer.

[0026] Thirdly, embodiments of the present invention also provide a trench gate MOSFET, which includes a plurality of cell structures, the cell structures being as described above for the trench gate MOSFET.

[0027] Compared with existing technologies, the cell structure of the trench gate MOSFET described in this invention has the following advantages:

[0028] This invention discloses a cell structure for a trench gate MOSFET, wherein a second semiconductor layer is formed on top of a first semiconductor layer, and both the trench and the first buried layer are formed within the second semiconductor layer. The trench has a ring-shaped structure, and the first buried layer is disposed below at least a portion of the trench in the ring direction, with the first buried layer in contact with the trench and the first semiconductor layer. A deep P-type junction is formed at the trench, the first buried layer, and the second semiconductor layer. This deep P-type junction can effectively solve the problem of gate oxide damage caused by the high breakdown electric field at the trench corner of the trench gate MOSFET, thereby ensuring the reliability of the trench gate MOSFET with this cell structure.

[0029] Furthermore, in the operational state, current flows sequentially through the first semiconductor layer, the first buried layer, the inversion layer formed in the second semiconductor layer, and the first source layer within the cell structure. When the first buried layer is located below a portion of the trench in the annular direction, and this first buried layer is in contact with the trench and the first semiconductor layer, current flows through the portion of the cell structure with the first buried layer, while no current flows through the portion without the first buried layer. The cell structure separates the current path, reducing current density and heat generation, thereby improving the short-circuit capability of the trench gate MOSFET with this cell structure.

[0030] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0032] Figure 1 This is a partial top view of the trench gate MOSFET described in an embodiment of the present invention.

[0033] Figure 2 This is a partial top view of the cell structure of a trench gate MOSFET according to an embodiment of the present invention.

[0034] Figure 3 for Figure 2 Schematic diagram of the structure of section A-A';

[0035] Figure 4 for Figure 2 Schematic diagram of the structure at section B-B';

[0036] Figure 5 for Figure 2 Schematic diagram of the structure of section C-C';

[0037] Figure 6 This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 1 ;

[0038] Figure 7 This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 2 ;

[0039] Figure 8This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 3 ;

[0040] Figure 9 This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 4 ;

[0041] Figure 10 This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 5 ;

[0042] Figure 11 This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 6 ;

[0043] Figure 12 This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 7 ;

[0044] Figure 13 This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 8 ;

[0045] Figure 14 This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 9 ;

[0046] Figure 15 This is a schematic diagram illustrating the fabrication process of the cell structure of the trench gate MOSFET described in this embodiment of the invention. Figure 10 ;

[0047] Figure 16 This is a flowchart illustrating the steps of fabricating the cell structure of a trench gate MOSFET according to an embodiment of the present invention.

[0048] Figure 17 This is a flowchart illustrating the steps of fabricating the cell structure of a trench gate MOSFET according to another embodiment of the present invention.

[0049] Explanation of reference numerals in the attached figures:

[0050] 1 – First semiconductor layer; 2 – Carrier storage layer; 3 – First buried layer; 4 – Second semiconductor layer; 5 – Gate oxide layer; 6 – Gate; 7 – First source layer; 8 – Second source layer; 9 – Insulating oxide layer; 10 – First metal layer; 11 – Second metal layer; 12 – Substrate; 13 – First epitaxial layer; 14 – Second epitaxial layer; 15 – Connector; 16 – Through-hole; 17 – Trench;

[0051] 20-cell. Detailed Implementation

[0052] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0053] This application provides a cell structure for a trench gate MOSFET, referring to... Figure 2 It shows a top view of a single cell 20 structure, and further references Figure 3 , Figure 4 and Figure 5 , Figure 3 It shows Figure 2 Schematic diagram of the structure of section A-A'; Figure 4 It shows Figure 2 Schematic diagram of the structure at section B-B'; Figure 5 It shows Figure 2 A schematic diagram of the structure of the C-C' section.

[0054] Further reference Figures 3 to 5 As shown, the cell structure includes: a first semiconductor layer 1 of a first conductivity type, a first buried layer 3 and a first source layer 7, a second semiconductor layer 4 of a second conductivity type, a gate 6 and a trench 17; the second semiconductor layer 4 is formed on the upper part of the first semiconductor layer 1, and the trench 17 and the first buried layer 3 are both formed in the second semiconductor layer 4; the trench 17 has a ring structure, and in the ring direction, at least a portion of the trench 17 is provided below the first buried layer 3, and the first buried layer 3 is in contact with the trench 17 and the first semiconductor layer 1; the gate 6 is formed in the trench 17; the first source layer 7 is formed on the upper part of the second semiconductor layer 4 located in the region enclosed by the trench 17.

[0055] In the embodiments of this application, the first conductivity type is N-type and the second conductivity type is P-type.

[0056] In this process, P-type implantation of Al ions (aluminum ions) is performed on the upper part of the first semiconductor layer 1 to form the second semiconductor layer 4.

[0057] Reference Figure 2 As shown, the trench 17 has a ring-shaped structure. In the ring direction, at least a portion of the trench 17 is provided with a first buried layer 3 below it, including the trench 17 being provided with a first buried layer 3 below all of them; and the portion of the trench 17 being provided with a first buried layer 3 below it, which can be referred to in this case. Figure 5As shown, the bottom of the left trench 17 is provided with a first buried layer 3, while the bottom of the right trench 17 is not provided with a first buried layer 3. In this embodiment of the application, as... Figures 3 to 5 As shown, in the annular direction, a first buried layer 3 is provided below the portion of the groove 17. A, A', B, B', C, and C' represent the six sides of the hexagonal cellular structure, and the first buried layer 3 is provided at the bottom of the grooves corresponding to the sides at A, A', and C.

[0058] In the annular direction, it refers to the groove 17 in Figure 2 The direction of extension shown is the direction around the through hole 16.

[0059] In the cell structure of the trench gate MOSFET of this application embodiment, when the gate 6 has a voltage, the direction of current flow is referenced. Figure 5 As shown, the current flows sequentially through the first semiconductor layer 1, the first buried layer 3, the inversion layer formed in the second semiconductor layer 4, and the first source layer 7.

[0060] In the cell structure of the trench gate MOSFET of this embodiment, a second semiconductor layer 4 is formed on top of a first semiconductor layer 1, and a trench 17 and a first buried layer 3 are both formed within the second semiconductor layer 4. The trench 17 has a ring-shaped structure, and at least a portion of the trench 17 is provided below the first buried layer 3 in the ring direction. The first buried layer 3 is in contact with the trench 17 and the first semiconductor layer 1. A deep P-type junction is formed at the trench 17, the first buried layer 3, and the second semiconductor layer 4. This deep P-type junction can effectively solve the problem of gate oxide damage caused by the high breakdown electric field at the trench corner of the trench gate MOSFET, thereby ensuring the reliability of the trench gate MOSFET with this cell structure.

[0061] Furthermore, the cellular structure in its usage state, refer to Figure 5 As shown, in the cell structure, current flows sequentially through the first semiconductor layer 1, the first buried layer 3, the inversion layer formed in the second semiconductor layer 4, and the first source layer 7. When the first buried layer 3 is provided below a portion of the trench 17 in the annular direction, and the first buried layer 3 is in contact with the trench 17 and the first semiconductor layer 1, current flows through the portion of the cell structure with the first buried layer 3, while no current flows through the portion of the cell structure without the first buried layer 3. The cell structure separates the current path, which can reduce the current density and reduce heat generation, thereby improving the short-circuit capability of the trench gate MOSFET with this cell structure.

[0062] It is understood that the embodiments of this application do not specifically limit the extension length of the first buried layer 3 along the bottom of the trench 17. The first buried layer 3 can be set according to the current density requirements of the cell structure. For example, the extension length of the first buried layer 3 along the bottom of the trench 17 is half the length of the trench 17 in the annular direction.

[0063] Optionally, the cell structure also includes a carrier storage layer 2 of a first conductivity type, which is formed within the first semiconductor layer 1, with the upper surface of the carrier storage layer 2 in contact with the lower surface of the first buried layer 3.

[0064] Reference Figure 3 and Figure 5 As shown, when the first buried layer 3 is provided below the trench 17, the upper surface of the carrier storage layer 2 is in contact with the lower surface of the first buried layer 3 and the lower surface of the second semiconductor layer 4; (Refer to...) Figure 4 As shown, when the first buried layer 3 is not provided below the trench 17, the upper surface of the carrier storage layer 2 is in contact with the lower surface of the second semiconductor layer 4.

[0065] N-ion implantation is performed in the first semiconductor layer 1 to form a carrier storage layer 2, which can provide carriers when the trench gate MOSFET is in operation, thereby reducing the on-resistance of the trench gate MOSFET.

[0066] Optionally, the cell structure also includes a gate oxide layer 5, which is formed on the inner sidewall of the trench 17. A gate 6 is provided in the gate oxide layer 5, and the lower surface of the gate 6 and the lower surface of the gate oxide layer 5 are both located at the bottom of the trench 17.

[0067] After the trench 17 is etched, gate oxide growth and polysilicon deposition are performed. The gate oxide growth forms the gate oxide layer 5, and the polysilicon deposition forms the gate 6.

[0068] Reference Figure 5 As shown, the lower surface of the gate 6 and the lower surface of the gate oxide layer 5 are both located at the bottom of the trench 17 and are in contact with the first buried layer 3. The sidewall of the gate 6 is in contact with the inner sidewall of the gate oxide layer 5, and the outer sidewall of the gate oxide layer 5 is in contact with the second semiconductor layer 4. The sidewall of the first buried layer 3 is in contact with the second semiconductor layer 4.

[0069] Optional, refer to Figure 3 and Figure 5 As shown, the width of the first buried layer 3 is the same as the width of the trench 17. Figure 3 In this structure, the width of the first buried layer 3 is the width in the left-right direction, and the width of the trench 17 is the width in the left-right direction. The width of the first buried layer 3 is the same as the width of the trench 17, and the first buried layer 3 is located directly below the trench 17.

[0070] Optionally, the cell structure further includes a first metal layer 10 and a second source layer 8 of the second conductivity type; the first source layer 7 has a ring structure, the second source layer 8 is formed in the ring structure, and the second source layer 8 is in contact with the inner end of the first source layer 7 and the first metal layer 10.

[0071] In this process, a second source layer 8 (p+ layer) is formed by implanting concentrated Al ions into the upper part of the second semiconductor layer 4.

[0072] In the cell structure of the trench gate MOSFET of this application embodiment, when the gate 6 has a voltage, the direction of current flow is referenced. Figure 5 As shown, the current flows sequentially through the first semiconductor layer 1, the carrier storage layer 2, the first buried layer 3, the inversion layer formed in the second semiconductor layer 4, the first source layer 7, the second source layer 8, and the first metal layer 10. Among them, the first metal layer 10 serves as the drain.

[0073] Optionally, both the first source layer 7 and the second source layer 8 are concentrated ion implantation layers to form a current path between the source and drain. Furthermore, the first metal layer 10 and the second source layer 8 form an ohmic contact, which can reduce the on-resistance at the contact point between the first metal layer 10 and the second source layer 8.

[0074] Optional, refer to Figure 5 and Figure 13 As shown, the cell structure also includes an insulating oxide layer 9, which is formed above the second semiconductor layer 4, the trench 17, and the first source layer 7. A through hole 16 is provided in the middle of the insulating oxide layer 9. A portion of the first metal layer 10 is formed in the through hole 16 and is in contact with the second source layer 8.

[0075] Oxide layers are deposited on the upper surface of the second semiconductor layer 4, the upper surface of the trench 17, and the upper surface of the first source layer 7 to form an insulating oxide layer 9, which serves as a protective and electrical insulating layer.

[0076] Hole etching is performed on the insulating oxide layer 9 to form a via 16, the lower end of which is located on the upper surface of the second source layer 8.

[0077] Metal is deposited on the upper surface of the insulating oxide layer 9 to form a first metal layer 10. A portion of the first metal layer 10 is deposited in the via 16 to form a connection portion 15. The lower surface of the connection portion 15 is connected to the upper surface of the second source layer 8 so that the first metal layer 10 and the second source layer 8 are in contact.

[0078] Optionally, the first semiconductor layer 1 includes a substrate 12, a first epitaxial layer 13 and a second epitaxial layer 14, the first epitaxial layer 13 is formed on the upper surface of the substrate 12 and the second epitaxial layer 14 is formed on the upper surface of the first epitaxial layer 13; the second semiconductor layer 4 includes a second buried layer and a well region; the first buried layer 3 and the second buried layer are formed on the first epitaxial layer 13; the trench 17, the well region and the first source layer 7 are formed on the second epitaxial layer 14.

[0079] In this embodiment of the application, a first epitaxial layer 13 is grown above the substrate 12, and a second epitaxial layer 14 is grown above the first epitaxial layer 13.

[0080] During the fabrication of the cell structure, a first epitaxial layer 13 is grown above the substrate 12. N-ion implantation is performed in the middle of the first epitaxial layer 13 to form a carrier storage layer 2. N-type implantation of N-ions is performed on the upper part of the first epitaxial layer 13 to form a first buried layer 3. P-type implantation of Al-ions is performed on the upper part of the first epitaxial layer 13 to form a second buried layer.

[0081] Then, a second epitaxial layer 14 is grown on the first epitaxial layer 13. A portion of the second epitaxial layer 14 is etched with a trench 17. During this step, the first buried layer 3 needs to be aligned, ensuring that the first buried layer 3 is directly below the etched trench 17. Gate oxide is grown within the trench 17 to form the gate oxide layer 5, and polysilicon is deposited to form the gate 6. P-well implantation is performed on the remaining portion of the second epitaxial layer 14 to form a well region.

[0082] The cellular structure and the above-described preparation method of this application can effectively solve the problem of difficulty in deep P-type implantation in silicon carbide materials.

[0083] Optionally, the substrate 12, the first epitaxial layer 13, and the second epitaxial layer 14 are all made of silicon carbide. In this case, the trench gate MOSFET with this cell structure is a SiC UMOSFET.

[0084] Optionally, a second metal layer 11 is further provided below the substrate 12, which serves as the source. Specifically, the second metal layer 11 is formed by depositing metal below the substrate 12.

[0085] Optional, refer to Figure 2 As shown, the groove 17 has a hexagonal ring structure. The specific shape of the groove 17 can also be set according to the usage requirements. For example, the groove 17 can be a rectangular ring, a pentagonal ring, etc.

[0086] In the operational state, the gate 6 of the cell structure has a voltage, as referenced. Figure 5 As shown, in the cell structure, the current flows sequentially through the second metal layer 11 (source), the first semiconductor layer 1, the carrier storage layer 2, the first buried layer 3, the inversion layer formed in the second semiconductor layer 4, the first source layer 7, the second source layer 8, and the first metal layer 10 (drain).

[0087] In the cell structure of the trench gate MOSFET of this embodiment, a second semiconductor layer 4 is formed on top of a first semiconductor layer 1, and a trench 17 and a first buried layer 3 are both formed within the second semiconductor layer 4. The trench 17 has a ring-shaped structure, and at least a portion of the trench 17 is provided below the first buried layer 3 in the ring direction. The first buried layer 3 is in contact with the trench 17 and the first semiconductor layer 1. A deep P-type junction is formed at the trench 17, the first buried layer 3, and the second semiconductor layer 4. This deep P-type junction can effectively solve the problem of gate oxide damage caused by the high breakdown electric field at the trench corner of the trench gate MOSFET, thereby ensuring the reliability of the trench gate MOSFET with this cell structure.

[0088] Furthermore, the cellular structure in its usage state, refer to Figure 5 As shown, in the cell structure, the current flows sequentially through the source, the first semiconductor layer 1, the carrier storage layer 2, the first buried layer 3, the inversion layer formed in the second semiconductor layer 4, the first source layer 7, the second source layer 8, and the drain. The portion of the cell structure with the first buried layer 3 carries current, while the portion without the first buried layer 3 does not carry current. The cell structure separates the current path, which can reduce the current density and reduce heat generation, thereby improving the short-circuit capability of the trench gate MOSFET with this cell structure.

[0089] The first semiconductor layer 1 includes a substrate 12, a first epitaxial layer 13 and a second epitaxial layer 14, a first buried layer 3 and a second buried layer formed on the first epitaxial layer 13; and a trench 17, a well region and a first source layer 7 formed on the second epitaxial layer 14. This structure also solves the problem of difficulty in deep P-type implantation in silicon carbide.

[0090] This application provides a trench gate MOSFET, which includes a plurality of cell structures, as described above for a trench gate MOSFET. (Refer to...) Figure 1 As shown, several cellular structures are arranged in an array.

[0091] When the cell structure of the trench gate MOSFET in this embodiment is the cell structure described above, the problem of gate oxide damage caused by the high breakdown electric field at the trench corner of the trench gate MOSFET can be effectively solved, thereby ensuring the reliability of the trench gate MOSFET. At the same time, a first buried layer 3 is formed below the gate 6 by periodically injecting N+. The current flowing through the first buried layer 3 can separate the current path of the trench gate MOSFET, thereby improving the short-circuit capability of the trench gate MOSFET.

[0092] This application also provides a method for fabricating the cell structure of a trench gate MOSFET, the method comprising the following steps:

[0093] S01, providing a first semiconductor layer 1 of a first conductivity type.

[0094] The first semiconductor layer 1 includes a substrate 12 and a first epitaxial layer 13 located above the substrate 12. Therefore, in this step, specifically, a substrate 12 of a first conductivity type and a first epitaxial layer 13 located above the substrate 12 are provided.

[0095] The substrate 12 and the first epitaxial layer 13 are both silicon carbide material layers, and N-type implantation is performed on the substrate 12 and the first epitaxial layer 13.

[0096] S02, a first buried layer 3 of a first conductivity type, a second semiconductor layer 4 of a second conductivity type, a trench 17 are prepared on the upper part of the first semiconductor layer 1, and a gate 6 is obtained in the trench 17; wherein, the trench 17 and the first buried layer 3 are both formed in the second semiconductor layer 4, the trench 17 has a ring structure, and in the ring direction, at least a portion of the trench 17 is provided below the first buried layer 3, and the first buried layer 3 is in contact with the trench 17 and the first semiconductor layer 1.

[0097] In this step, a first buried layer 3 is provided below at least a portion of the trench 17, such that the first buried layer 3 is located directly below at least a portion of the trench 17.

[0098] In this step, gate oxide layer 5 is formed by gate oxide growth in trench 17, and gate 6 is formed by polysilicon deposition within gate oxide layer 5.

[0099] S03, a first source layer 7 is prepared on the upper part of the region enclosed by the second semiconductor layer 4 and the trench 17.

[0100] The first source layer 7 serves as a current path between the source and drain.

[0101] In this step, specifically, concentrated N ions are implanted into the upper part of the second semiconductor layer 4 in the region enclosed by the trench 17 to form the first source layer 7.

[0102] This application also provides another method for fabricating the cell structure of a trench gate MOSFET, which includes the following steps:

[0103] S11, a substrate 12 of a first conductivity type and a first epitaxial layer 13 located above the substrate 12 are provided.

[0104] In this step, a first epitaxial layer 13 is grown over the substrate 12.

[0105] Further reference Figure 6 A first epitaxial layer 13 is provided above the substrate 12.

[0106] S12, a carrier storage layer 2 is prepared in the middle of the first epitaxial layer 13.

[0107] In this step, N-ion implantation is performed in the middle of the first epitaxial layer 13 to form a carrier storage layer 2 (CSL layer). The carrier storage layer 2 is used to provide carriers when the trench gate MOSFET is operating, thereby reducing the on-resistance of the trench gate MOSFET.

[0108] S13, a first buried layer 3 and a second buried layer are prepared on the upper part of the first epitaxial layer 13; wherein, the upper surface of the carrier storage layer 2 is in contact with the lower surface of the first buried layer 3 and the lower surface of the second buried layer;

[0109] In this step, refer to Figure 7 As shown, P-type implantation of Al ions is performed on the upper part of the first epitaxial layer 13 to form a second buried layer in the second semiconductor layer. The second buried layer is used to reduce the electric field strength at the corner of the trench 17, thereby improving the gate oxide reliability.

[0110] Reference Figure 8 As shown, N-type implantation of N ions is performed on the upper part of the first epitaxial layer 13 to form a first buried layer 3, which corresponds to the area directly below the trench 17.

[0111] In another embodiment, when P-type implantation of Al ions is performed in a portion of the upper part of the first epitaxial layer 13 to form a second buried layer, N-type implantation of N ions is performed in the remaining portion of the upper part of the first epitaxial layer 13 to form a first buried layer 3.

[0112] S14, obtain the second epitaxial layer 14 above the first epitaxial layer 13.

[0113] In this step, a second epitaxial layer 14 is grown on the first epitaxial layer 13. Further refer to... Figure 9 The second epitaxial layer 14 is located above the first epitaxial layer 13, and the lower surface of the second epitaxial layer 14 is in contact with the upper surface of the first epitaxial layer 13.

[0114] S15, a trench 17 is prepared in a portion of the second epitaxial layer 14, and a gate 6 is obtained within the trench 17.

[0115] In this step, trenches 17 are etched in a portion of the second epitaxial layer 14. This step requires alignment with the first buried layer 3, ensuring that the first buried layer 3 is directly below the etched trenches 17.

[0116] Then, gate oxide growth and polysilicon deposition are performed. Specifically, gate oxide growth is performed to form the gate oxide layer 5, and polysilicon deposition is performed to form the gate 6. Further reference... Figure 10 As shown, a gate oxide layer 5 and a gate 6 are formed in the trench 17.

[0117] S16, a well region is prepared in the remaining portion of the second epitaxial layer 14, the well region being located on the outer periphery of the trench 17.

[0118] In this step, P-well implantation is performed on the remaining region of the second epitaxial layer 14 to form a well region in the second semiconductor layer, specifically a P-well region.

[0119] Further reference Figure 11 As shown, a portion of the second epitaxial layer 14 is used to etch trench 17, and the remaining portion of the second epitaxial layer 14 is implanted with P Well to form a well region, so that trench 17 is formed in the well region.

[0120] S17, the first source layer 7 is prepared in the upper part of the area enclosed by the second buried layer and the trench 17.

[0121] In this step, further refer to Figure 12 As shown, a first source layer 7 is formed by concentrated N ion implantation in the upper part of the region enclosed by trench 17 in the second buried layer.

[0122] S18, obtain the insulating oxide layer 9 above the second epitaxial layer 14, perform hole etching, and form the second source layer 8.

[0123] In this step, refer to Figure 13 As shown, an oxide layer is deposited on the upper surface of the second epitaxial layer 14 to form an insulating oxide layer 9, which serves as a protective and electrically insulating layer.

[0124] Hole etching is performed in the middle of the insulating oxide layer 9 to form a through hole 16, the lower end of which is located on the upper surface of the second epitaxial layer 14.

[0125] The through-hole 16 corresponds to the region enclosed by the annular structure of the first source layer. In this region, concentrated Al ions are implanted to form a p+ layer, which is the second source layer 8.

[0126] S19, Obtain the first metal layer 10.

[0127] In this step, refer to Figure 14 As shown, in Figure 13 The structure shown has a first metal layer 10 deposited on the front side, which serves as the drain electrode. The first metal layer 10 contacts the upper surface of the second source layer 8 through a via 16. Since the second source layer 8 is formed by implantation of concentrated Al ions, the first metal layer 10 and the second source layer 8 form an ohmic contact, which can reduce the on-resistance at the contact point between the first metal layer 10 and the second source layer 8.

[0128] S20, Obtain the second metal layer 11.

[0129] In this step, refer to Figure 15 As shown, a second metal layer 11 is deposited on the lower surface of the substrate 12 to form a metal layer 11, which serves as the source electrode.

[0130] Optionally, in one embodiment, step S18 may further be: thinning the substrate 12 and then obtaining the second metal layer 11.

[0131] The method for fabricating the cell structure of the trench gate MOSFET in this application solves the problem of difficulty in deep P-type implantation in silicon carbide.

[0132] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0133] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. For embodiments of devices, electronic devices, computer-readable storage media, and computer program products containing instructions, the descriptions are relatively simple because they are basically similar to the method embodiments; relevant parts can be referred to the descriptions of the method embodiments.

[0134] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A cell structure for a trench gate MOSFET, characterized in that, include: A first semiconductor layer (1), a first buried layer (3), and a first source layer (7) of a first conductivity type; a second semiconductor layer (4), a gate (6), and a trench (17) of a second conductivity type; The second semiconductor layer (4) is formed on the upper part of the first semiconductor layer (1), and the trench (17) and the first buried layer (3) are both formed in the second semiconductor layer (4); The trench (17) has a ring structure. In the ring direction, at least a portion of the trench (17) is provided with the first buried layer (3), and the first buried layer (3) is in contact with the trench (17) and the first semiconductor layer (1). The gate (6) is formed within the trench (17); The first source layer (7) is formed on the upper part of the region enclosed by the second semiconductor layer (4) and the trench (17); The cell structure further includes a first metal layer (10) and a second source layer (8) of the second conductivity type; the first source layer (7) is in the form of a ring structure, and the second source layer (8) is formed in the ring structure, and the second source layer (8) is in contact with the inner end of the first source layer (7) and the first metal layer (10).

2. The cell structure of the trench gate MOSFET according to claim 1, characterized in that, The cell structure further includes a carrier storage layer (2) of a first conductivity type, which is formed in the first semiconductor layer (1), and the upper surface of the carrier storage layer (2) is in contact with the lower surface of the first buried layer (3).

3. The cell structure of the trench gate MOSFET according to claim 1, characterized in that, The cell structure also includes a gate oxide layer (5), which is formed on the inner sidewall of the trench (17). The gate oxide layer (5) contains the gate (6), and the lower surface of the gate (6) and the lower surface of the gate oxide layer (5) are both located at the bottom of the trench (17).

4. The cell structure of the trench gate MOSFET according to claim 1, characterized in that, The width of the first buried layer (3) is the same as the width of the trench (17).

5. The cell structure of the trench gate MOSFET according to claim 1, characterized in that, Both the first source layer (7) and the second source layer (8) are concentrated ion implantation layers.

6. The cell structure of the trench gate MOSFET according to claim 1, characterized in that, The cell structure is further provided with an insulating oxide layer (9), which is formed above the second semiconductor layer (4), the trench (17), and the first source layer (7). A through hole (16) is provided in the middle of the insulating oxide layer (9). A portion of the first metal layer (10) is formed within the via (16) and is in contact with the second source layer (8).

7. The cell structure of the trench gate MOSFET according to claim 1, characterized in that, The first semiconductor layer (1) includes a substrate (12), a first epitaxial layer (13) and a second epitaxial layer (14), wherein the first epitaxial layer (13) is formed on the upper surface of the substrate (12) and the second epitaxial layer (14) is formed on the upper surface of the first epitaxial layer (13); the second semiconductor layer (4) includes a second buried layer and a well region; The first embedded layer (3) and the second embedded layer are formed on the first epitaxial layer (13); The trench (17), the well region, and the first source layer (7) are formed on the second epitaxial layer (14).

8. The cell structure of the trench gate MOSFET according to claim 7, characterized in that, The substrate (12), the first epitaxial layer (13) and the second epitaxial layer (14) are all silicon carbide layers.

9. A method for fabricating the cell structure of a trench gate MOSFET, characterized in that, include, A first semiconductor layer (1) of a first conductivity type is provided; A first buried layer (3) of a first conductivity type, a second semiconductor layer (4) of a second conductivity type, a trench (17) are prepared on the first semiconductor layer (1), and a gate (6) is obtained in the trench (17); wherein the trench (17) and the first buried layer (3) are both formed in the second semiconductor layer (4), the trench (17) has a ring structure, and in the ring direction, at least a portion of the trench (17) is provided below the first buried layer (3), and the first buried layer (3) is in contact with the trench (17) and the first semiconductor layer (1); A first source layer (7) is prepared on the upper part of the second semiconductor layer (4) located in the region enclosed by the trench (17).

10. The method for fabricating the cell structure of a trench gate MOSFET according to claim 9, characterized in that, The first semiconductor layer (1) includes a substrate (12), a first epitaxial layer (13), and a second epitaxial layer (14). The steps of fabricating a first buried layer (3) of a first conductivity type, a second semiconductor layer (4) of a second conductivity type, a trench (17), and obtaining a gate (6) within the trench (17) on the first semiconductor layer (1) further include: The first buried layer (3) and the second buried layer are prepared on the upper part of the first epitaxial layer (13); Obtain the second epitaxial layer (14) above the first epitaxial layer (13); A trench (17) is formed in a portion of the second epitaxial layer (14), and a gate (6) is obtained within the trench (17). A well region is prepared in the remaining portion of the second epitaxial layer (14), the well region being located on the outer periphery of the trench (17).

11. The method for fabricating the cell structure of a trench gate MOSFET according to claim 10, characterized in that, The step of preparing the first buried layer (3) and the second buried layer on the first epitaxial layer (13) further includes: A carrier storage layer (2) is prepared in the middle of the first epitaxial layer (13); The first buried layer (3) and the second buried layer are prepared on the upper part of the first epitaxial layer (13); wherein the upper surface of the carrier storage layer (2) is in contact with the lower surface of the first buried layer (3) and the lower surface of the second buried layer.

12. A trench gate MOSFET, characterized in that, It includes a plurality of cell structures, said cell structures being the cell structures of a trench gate MOSFET as described in any one of claims 1 to 8.

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