Electrostatic protection circuit and semiconductor chip
By introducing detection, control, and shutdown circuits into the electrostatic discharge (ESD) protection circuit, the problems of ESD discharge and shutdown in highly integrated semiconductor devices are solved, achieving effective ESD protection and discharge, reducing latch-up and leakage, and improving chip performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-17
- Publication Date
- 2026-06-09
AI Technical Summary
Existing electrostatic discharge protection circuits are difficult to effectively discharge static electricity and shut off in time in highly integrated semiconductor devices, leading to latch-up problems and leakage problems caused by large capacitors.
An electrostatic discharge (ESD) protection circuit is designed, comprising a detection circuit, a control circuit, a discharge transistor, and a shutdown circuit. The detection circuit outputs a signal to control the conduction and shutdown of the discharge transistor. The shutdown circuit ensures that the discharge transistor is completely discharged after a preset time before shutting off, thereby reducing latch-up. Smaller resistors and capacitors are used to reduce layout area and leakage current.
It achieves effective electrostatic protection during ESD events, avoids latch-up problems, reduces the layout area and leakage current of the electrostatic protection circuit, and improves chip performance.
Smart Images
Figure CN117317995B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, an electrostatic discharge protection circuit and a semiconductor chip. Background Technology
[0002] Static electricity is an unavoidable phenomenon in semiconductor devices. To reduce the impact of static electricity on devices, effective electrostatic discharge (ESD) protection circuits need to be designed during the semiconductor device manufacturing process. However, with the continuous development of large-scale integrated circuits and the increasing demand for high integration, the design of ESD protection circuits presents significant challenges due to the increasing precision of devices. Summary of the Invention
[0003] In view of this, the present disclosure provides an electrostatic discharge protection circuit and a semiconductor chip.
[0004] In a first aspect, embodiments of this disclosure provide an electrostatic discharge (ESD) protection circuit, the ESD protection circuit being connected to a first voltage terminal and a second voltage terminal, the ESD protection circuit comprising:
[0005] A first detection circuit is connected between the first voltage terminal and the second voltage terminal. The first detection circuit is used to output a first detection signal within a first preset time period when electrostatic charge appears on the first voltage terminal, or to output a second detection signal after the first preset time period when electrostatic charge appears on the first voltage terminal.
[0006] A control circuit is connected between the first voltage terminal and the second voltage terminal, and the input terminal of the control circuit is connected to the output terminal of the first detection circuit; the control circuit is used to output a first level when the first detection signal is received, or to output a second level when the second detection signal is received.
[0007] A discharge transistor is connected between the first voltage terminal and the second voltage terminal, and the control terminal of the discharge transistor is connected to the output terminal of the control circuit; the discharge transistor switches to the on state when the control terminal of the discharge transistor is at the first level, so as to discharge the electrostatic charge to the second voltage terminal; the discharge transistor switches to the off state when the control terminal of the discharge transistor is at the second level.
[0008] A shutdown circuit is connected between the first voltage terminal and the second voltage terminal, and the output terminal of the shutdown circuit is connected to the control terminal of the discharge transistor; the shutdown circuit is used to output a control signal after a second preset time when electrostatic charge appears on the first voltage terminal; the control signal is used to shut down the discharge transistor;
[0009] The second preset duration is greater than or equal to the first preset duration.
[0010] In some embodiments, the shutdown circuit includes:
[0011] The second detection circuit is connected between the first voltage terminal and the second voltage terminal. The second detection circuit outputs a third detection signal within a second preset time period when electrostatic charge appears on the first voltage terminal, or outputs a fourth detection signal after the second preset time period when electrostatic charge appears on the first voltage terminal.
[0012] A turn-off transistor is provided, wherein the first terminal of the turn-off transistor is connected to the second voltage terminal, the second terminal of the turn-off transistor is connected to the control terminal of the discharge transistor, and the control terminal of the turn-off transistor is connected to the output terminal of the second detection circuit; the turn-off transistor outputs the control signal after a second preset time period after an electrostatic charge appears on the first voltage terminal.
[0013] In some embodiments, within a second preset time period during which electrostatic charge appears on the first voltage terminal, the output terminal of the second detection circuit outputs a third detection signal to the control terminal of the turn-off transistor, and the turn-off transistor is in a cut-off state.
[0014] After a second preset time period following the appearance of electrostatic charge on the first voltage terminal, the output terminal of the second detection circuit outputs a fourth detection signal to the control terminal of the turn-off transistor, and the turn-off transistor is in the on state and outputs the control signal to the control terminal of the discharge transistor.
[0015] In some embodiments, the second detection circuit includes:
[0016] The second sensing resistor is connected to the first voltage terminal;
[0017] The second detection capacitor is connected between the second detection resistor and the second voltage terminal; the end of the second detection resistor connected to the second detection capacitor is the output terminal of the second detection circuit.
[0018] In some embodiments, the second detection resistor includes a polysilicon resistor or a doped region resistor.
[0019] In some embodiments, the second detection capacitor includes a MIM (Metal-Insulator-Metal) capacitor, a MOS (Metal-Oxide-Semiconductor) capacitor, and a MOM (Metal-Oxide-Metal) capacitor.
[0020] In some embodiments, the first detection circuit includes:
[0021] The first sensing resistor is connected to the first voltage terminal;
[0022] The first detection capacitor is connected between the first detection resistor and the second voltage terminal;
[0023] The end where the first detection resistor is connected to the first detection capacitor is the output terminal of the first detection circuit.
[0024] In some embodiments, the control circuit includes:
[0025] A first control switch is connected between the first voltage terminal and the control terminal of the discharge transistor; the output terminal of the first detection circuit is connected to the control terminal of the first control switch.
[0026] In some embodiments, the control circuit further includes:
[0027] A second control switch is connected between the output terminal of the first detection circuit and the second voltage terminal; the control terminal of the second control switch is connected to the control terminal of the discharge transistor.
[0028] In some embodiments, the control circuit further includes:
[0029] At least one diode is connected in series between the control terminal of the first control switch and the second terminal of the second control switch, the at least one diode being used to enable unidirectional current conduction from the control terminal of the first control switch to the second terminal of the second control switch.
[0030] In some embodiments, the control circuit further includes:
[0031] A third control switch; the control terminal of the third control switch is connected to the output terminal of the first detection circuit;
[0032] The first terminal of the third control switch is connected to the control terminal of the discharge transistor;
[0033] The second terminal of the third control switch is connected to the second voltage terminal.
[0034] In some embodiments, the control circuit further includes: a fourth control switch;
[0035] The control terminal of the fourth control switch is connected to the control terminal of the discharge transistor;
[0036] The first terminal of the fourth control switch is connected to the first voltage terminal;
[0037] The second terminal of the fourth control switch is connected to the input terminal of the control circuit.
[0038] In some embodiments, the electrostatic protection circuit further includes a delay circuit;
[0039] The delay circuit includes: an inverter group, comprising an even number of interconnected inverters;
[0040] The inverter group is connected between the first voltage terminal and the second voltage terminal;
[0041] The first end of the inverter group is connected to the output end of the first detection circuit; the second end of the inverter group is connected to the input end of the control circuit.
[0042] In some embodiments, the inverter includes:
[0043] A first inverting transistor, wherein the first terminal of the first inverting transistor is connected to the first voltage terminal;
[0044] The second inverter transistor, wherein the first terminal of the second inverter transistor is connected to the second voltage terminal;
[0045] The control terminal of the first inverting transistor is connected to the control terminal of the second inverting transistor; the second terminal of the first inverting transistor is connected to the second terminal of the second inverting transistor.
[0046] Secondly, the embodiments disclosed herein provide
[0047] A semiconductor chip, the semiconductor chip comprising:
[0048] The first voltage terminal, the second voltage terminal, and the electrostatic protection circuit as described in any of the above embodiments.
[0049] The electrostatic discharge (ESD) protection circuit proposed in this disclosure provides ESD protection during ESD events. Furthermore, by incorporating an additional shutdown circuit, this disclosure addresses the issue of the discharge circuit in ESD protection circuits being difficult to shut off within a preset time, thereby reducing latch-up. Additionally, the ESD protection circuit proposed in this disclosure can utilize smaller resistors R and capacitors C, thus reducing the layout area of the ESD protection circuit and mitigating leakage problems caused by large capacitors C. Attached Figure Description
[0050] Figure 1 A schematic diagram of the electrostatic discharge protection circuit provided in one embodiment;
[0051] Figure 2 A schematic diagram of the electrostatic protection circuit provided in yet another embodiment;
[0052] Figure 3This is a schematic diagram of the structure of an electrostatic protection circuit provided in an embodiment of the present disclosure;
[0053] Figure 4 This is a schematic diagram of another electrostatic protection circuit provided in an embodiment of the present disclosure;
[0054] Figure 5 This is a schematic diagram of another electrostatic protection circuit provided in an embodiment of the present disclosure;
[0055] Figure 6 This is a schematic diagram of another electrostatic protection circuit provided in an embodiment of the present disclosure;
[0056] Figure 7 This is a schematic diagram of another electrostatic protection circuit provided in an embodiment of the present disclosure;
[0057] Figure 8 This is a schematic diagram of the structure of a semiconductor chip provided in an embodiment of this disclosure. Detailed Implementation
[0058] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0060] Full-chip integrated circuit ESD protection typically requires an ESD protection circuit to be established between the power supply. In some embodiments, such as... Figure 1 The electrostatic discharge protection circuit 10 shown is shown. Figure 1The electrostatic discharge (ESD) protection circuit 10 shown includes a detection circuit, a control circuit, and a discharge transistor. The detection circuit includes a resistor r1 and a capacitor c1; the control circuit includes transistor p1 and transistor m1; and the discharge transistor m2 can be an NMOS transistor. The principle of this ESD protection circuit 20 is as follows: when an ESD pulse occurs at the power supply voltage terminal VDD and VSS is grounded, the output of the detection circuit outputs a first detection signal to the control circuit, and this first detection signal is a low-level signal. The low-level signal passes through the control circuit, which includes transistor p1 and transistor m1, to output a high-level signal to the discharge transistor m2. The discharge transistor m2 conducts and discharges the ESD charge, and the time available for discharging the ESD charge is determined by the product of the resistor r1 and the capacitor c1 in the detection circuit. This ESD protection circuit 10 requires a large RC (Resistor-Capacitance) constant, so capacitor c1 can be a large capacitor and resistor r1 can be a large resistor. Large capacitors and large resistors occupy a relatively large area in the chip, affecting the chip's integration density. Furthermore, as semiconductor manufacturing processes become more advanced, the oxide layer becomes thinner, so large capacitors may cause severe leakage current.
[0061] In some embodiments, the following may be adopted: Figure 2 The electrostatic discharge (ESD) protection circuit 20 is shown. This ESD protection circuit 20 includes a detection circuit 21, a control circuit 22, and a discharge transistor 23. The detection circuit 21 includes a resistor R and a capacitor C; the control circuit 22 includes PMOS transistors Mp1, Mp2, Mn1, and Mn2; and the discharge transistor 23 can be an NMOS transistor. The principle of this ESD protection circuit 20 is as follows: when an ESD pulse occurs at the power supply voltage terminal VDD and VSS is grounded, the output terminal of the detection circuit 21 outputs a first detection signal to the control circuit 22, and this first detection signal is a low-level signal. After the first detection signal passes through PMOS transistors Mp1 and Mn1, the output terminal of the control circuit 22 inputs a high-level signal to the input terminal of the discharge transistor 23, i.e., the gate of the discharge transistor 23. The discharge transistor 23 can be an NMOS transistor Mesd, which conducts when its gate voltage is high, and the ESD pulse is discharged from the VDD terminal to the VSS terminal via the discharge transistor 23.
[0062] The control circuit 22 also includes a PMOS transistor Mp2 and an NMOS transistor Mn2. The gates of Mp2 and Mn2 are connected to the output of the control circuit 22. Therefore, when the control circuit 22 outputs a high voltage, NMOS transistor Mn2 conducts when its gate voltage is high. NMOS transistor Mn2 can pull the input voltage of the control circuit down to a low voltage, and pull the input of the discharge transistor 23 up to a high voltage, thereby extending the turn-on time of the discharge transistor 23 and effectively dissipating the electrostatic pulse. However, this may prevent the discharge transistor 23 from being turned off in time, thus failing to return to its normal operating state.
[0063] This disclosure provides an electrostatic discharge protection circuit, such as... Figure 3 As shown, the electrostatic discharge (ESD) protection circuit 1000 is connected to a first voltage terminal 100 and a second voltage terminal 200. The ESD protection circuit 1000 includes:
[0064] The first detection circuit 300 is connected between the first voltage terminal 100 and the second voltage terminal 200. The first detection circuit 300 is used to output a first detection signal within a first preset time T1 when electrostatic charge appears on the first voltage terminal 100, or to output a second detection signal after the first preset time T1 when electrostatic charge appears on the first voltage terminal 100.
[0065] In some embodiments, the first voltage terminal 100 can be the power supply terminal VDD, and the second voltage terminal 200 can be the ground terminal VSS.
[0066] The first detection circuit 300 has at least one output terminal for outputting at least two detection signals. The two detection signals can be a first detection signal and a second detection signal. Within a first preset time period when electrostatic charge appears on the power supply terminal VDD, the first detection circuit 300 can output the first detection signal, and after the first preset time period when electrostatic charge appears on the power supply terminal VDD, the first detection circuit 300 can output the second detection signal.
[0067] In some embodiments, the first detection signal can be a high-level signal, represented by binary data "1", and the second detection signal can be a low-level signal, represented by binary data "0". In some embodiments, the first detection signal can be a low-level signal, represented by binary data "0", and the second detection signal can be a high-level signal, represented by binary data "1".
[0068] The electrostatic protection circuit 1000 also includes a control circuit 400, which is connected between the first voltage terminal 100 and the second voltage terminal 200. The input terminal of the control circuit 400 is connected to the output terminal of the first detection circuit 300. The control circuit 400 is used to output a first level when a first detection signal is received, or to output a second level when a second detection signal is received.
[0069] The control circuit 400 includes at least one input terminal and at least one output terminal, wherein one input terminal of the control circuit is connected to the output terminal of the first detection circuit 300, that is, the signal output by the control circuit 400 is provided by the output terminal of the first detection circuit 300.
[0070] In some embodiments, within a first preset time T1 during which electrostatic charge appears on the power supply terminal VDD, the output terminal of the first detection circuit 300 can output a first detection signal, and the input terminal of the control circuit 400 is the first detection signal, corresponding to the output of a first level by the control circuit 400. The first level is used to turn on the discharge transistor 500 to discharge the electrostatic charge; the first level can be either a high level or a low level, without limitation. In some embodiments, after the first preset time during which electrostatic charge appears on the power supply terminal VDD, the output terminal of the first detection circuit 300 can output a second detection signal, and the input terminal of the control circuit 400 is the second detection signal, corresponding to the output of the control circuit 400. The second level is used to turn off the discharge transistor 500; the second level can be either a high level or a low level, without limitation.
[0071] The electrostatic discharge protection circuit 1000 also includes a discharge transistor 500, which is connected between the first voltage terminal 100 and the second voltage terminal 200. The control terminal of the discharge transistor 500 is connected to the output terminal of the control circuit 400. When the control terminal of the discharge transistor 500 is at the first level, it switches to the on state to discharge the electrostatic charge to the second voltage terminal 200. When the control terminal of the discharge transistor 500 is at the second level, it switches to the off state.
[0072] The discharge transistor 500 can be either an NMOS or a PMOS transistor. When the discharge transistor 500 is an asymmetric NMOS transistor, its first terminal (the terminal connected to the power supply VDD) is the drain, and the drain has no lightly doped drain region (LDD structure) to reduce the on-resistance of the discharge transistor 500 and improve its electrostatic discharge capability. When the discharge transistor 500 is an asymmetric NMOS transistor, in order to further reduce the on-resistance of the discharge transistor 500, the doping concentration of the drain region can be further increased, making the drain doping concentration greater than the source doping concentration. At the same time, the area of the drain region can also be further increased, making the drain area greater than the source area.
[0073] The control terminal of the discharge transistor 500 is connected to the output terminal of the control circuit, meaning the control circuit can control the state of the discharge transistor 500. The discharge transistor 500 has at least two states: on and off.
[0074] In some embodiments, within a first preset time period during which electrostatic charge appears on the power supply terminal VDD, the output terminal of the first detection circuit can output a first detection signal, and the input terminal of the control circuit is the first detection signal, and the control circuit outputs a first level accordingly. The first level can be either a high level or a low level, and there is no limitation on this.
[0075] When the first level is high, and the discharge transistor is an NMOS transistor, the discharge transistor switches to the on state when the control terminal of the discharge transistor is at the first level.
[0076] In some embodiments, after a first preset time period following the appearance of electrostatic charge on the power supply terminal VDD, the output terminal of the first detection circuit can output a second detection signal, and the input terminal of the control circuit is the second detection signal, correspondingly outputting a second level. The second level can be either a high level or a low level, and there is no limitation thereto.
[0077] When the second level is low, and the discharge transistor 500 is an NMOS transistor, the discharge transistor 500 switches to the cutoff state when the control terminal of the discharge transistor 500 is at the second level.
[0078] The electrostatic discharge protection circuit 1000 also includes a shutdown circuit 600 connected between the first voltage terminal 100 and the second voltage terminal 200. The output terminal of the shutdown circuit 600 is connected to the control terminal of the discharge transistor 500. The shutdown circuit 600 outputs a control signal after a second preset time when electrostatic charge appears on the first voltage terminal 100. The control signal is used to shut down the discharge transistor 500.
[0079] The second preset duration is greater than or equal to the first preset duration.
[0080] The output of the shutdown circuit 600 is connected to the control terminal of the discharge transistor 500, meaning that the control terminal of the discharge transistor 500 is controlled not only by the output of the control circuit 400 but also by the output of the shutdown circuit 600. Thus, when the control circuit 400 fails to output a signal to shut down the discharge transistor 500 within a preset time, the shutdown circuit 600 can be used to turn off the discharge transistor 500.
[0081] There can be one or more shutdown circuits 600. Each shutdown circuit 600 can output a control signal after a certain period of time to shut down the discharge transistor 500. For example, the first shutdown circuit can output a control signal to the discharge transistor 500 after time T2, the second shutdown circuit can output another control signal to the discharge transistor 500 after time T3, and so on.
[0082] In one embodiment, a shutdown circuit 600 may be used, which is used to output a control signal to the discharge transistor 500 for turning off the discharge transistor 500 within a second preset time period when electrostatic charge appears on the power supply terminal VDD.
[0083] In some embodiments, the second preset duration may be longer than the first preset duration, so that the discharge transistor 500 can be completely discharged before the discharge transistor 500 is turned off.
[0084] If the electrostatic discharge protection circuit 1000 does not include a shutdown circuit 600, when an ESD event occurs, there may be a problem where the discharge transistor 500 fails to turn off, leading to latch-up, or the discharge transistor 500 may take a longer time to automatically turn off after discharging the static electricity. Both of these problems will affect the chip performance.
[0085] By setting at least one shutdown circuit 600, at least one shutdown discharge transistor 500 can be added accordingly, so that the discharge transistor 500 can be smoothly turned off after discharging the charge, reducing the occurrence of latch-up problems and thus improving the performance of the chip.
[0086] The turn-off circuit 600 is activated after a second preset duration, where the second preset duration is greater than or equal to a first preset duration. This first preset duration can be understood as the time allotted for the discharge transistor 500 to discharge static charge. If the second preset duration is less than the first preset duration, the discharge transistor 500 may be turned off before it has completely discharged the static charge, thus failing to achieve the goal of completely discharging the static charge. In this embodiment, the second preset duration is greater than or equal to the first preset duration; therefore, the discharge transistor 500 can be turned off only after the static charge has been completely discharged.
[0087] like Figure 3 As shown, when an electrostatic pulse occurs on the VDD power line and the VSS power line is grounded, the detection circuit outputs a first detection signal to the input of the control circuit 400 within a first preset time T1. The first detection signal can be a low-level signal. After the low-level signal is input to the control circuit, it outputs a high-level signal. The discharge transistor 500 can be an NMOS transistor. Under the action of the high-level input to the control circuit 400, the NMOS transistor conducts and discharges electrostatic charge.
[0088] After the second preset time T2, the shutdown circuit 600 is turned on, and the shutdown circuit 600 inputs a low level to the control terminal of the discharge transistor 500, thereby turning off the discharge transistor 500.
[0089] The electrostatic discharge (ESD) protection circuit 1000 proposed in this embodiment can provide ESD protection when an ESD event occurs. Furthermore, by incorporating an additional shutdown circuit 600, this embodiment addresses the issue of the discharge transistor 500 failing to fully turn off within a preset time, thus preventing latch-up. Moreover, the ESD protection circuit 1000 proposed in this embodiment can utilize smaller resistors R and capacitors C, thereby reducing the layout area of the ESD protection circuit 1000 and mitigating leakage problems caused by large capacitors C.
[0090] In some embodiments, such as Figure 4 As shown, the shutdown circuit 600 includes: a second detection circuit 601 connected between the first voltage terminal 100 and the second voltage terminal 200. The second detection circuit 601 outputs a third detection signal within a second preset time period during which static charge appears on the first voltage terminal 100, or outputs a fourth detection signal after the second preset time period during which static charge appears on the first voltage terminal 100.
[0091] The turn-off transistor 602 is connected to the second voltage terminal 200, and the second terminal of the turn-off transistor 602 is connected to the control terminal of the discharge transistor 500. The control terminal of the turn-off transistor 602 is connected to the output terminal of the second detection circuit 601. The turn-off transistor 602 outputs a control signal after a second preset time when electrostatic charge appears on the first voltage terminal 100.
[0092] The shutdown circuit 600 includes at least a second detection circuit 601 and a shutdown transistor 602. The second detection circuit 601 can be constructed using the same types of components as the first detection circuit 300, but the parameters of the components used in the first detection circuit 300 and the second detection circuit 601 can be different.
[0093] The control circuit 400 outputs a first level signal to the discharge transistor 500 within a first preset time period to control the discharge transistor 500 to conduct. The turn-off transistor 602 outputs a control signal to the discharge transistor 500 after a second preset time period to control the discharge transistor 500 to turn off.
[0094] It is understandable that when the first level is high, the level of the control signal can be low; when the first level is low, the level of the control signal can be high.
[0095] The turn-off transistor 602 can be the same transistor as the discharge transistor 500 or a different transistor.
[0096] The second detection module 601 of the shutdown circuit 600 is used to control the time of outputting control signals to the discharge transistor 500. By adjusting the parameters of the components in the second detection module 601, a reasonable second preset duration can be obtained.
[0097] The shutdown transistor 602 of the shutdown circuit 600 is used to input a control signal to the discharge transistor 500 after a second preset time period, which can control its shutdown.
[0098] In some embodiments, within a second preset time period during which electrostatic charge appears on the first voltage terminal, the output terminal of the second detection circuit outputs a third detection signal to the control terminal of the turn-off transistor, and the turn-off transistor is in the off state.
[0099] After a second preset time period following the appearance of electrostatic charge on the first voltage terminal, the output terminal of the second detection circuit outputs a fourth detection signal to the control terminal of the turn-off transistor, the turn-off transistor is in the on state and outputs a control signal to the control terminal of the discharge transistor.
[0100] During the second preset time period, since it is not necessary to turn off the turn-off transistor, the turn-off transistor can be in the off state, that is, it does not output any signal to the input terminal of the discharge transistor. In some embodiments, during the second preset time period, the turn-off transistor can output a signal to the discharge transistor to turn it on, and the signal level is the same as the first level.
[0101] It is understandable that the third and fourth detection signals can be opposite signals; that is, when the third detection signal is high, the fourth detection signal is low, and vice versa.
[0102] In some embodiments, such as Figure 4 As shown, the second detection circuit 601 includes:
[0103] The second sensing resistor R2 is connected to the first voltage terminal 100;
[0104] The second detection capacitor C2 is connected between the second detection resistor R2 and the second voltage terminal 200; the end where the second detection resistor R2 and the second detection capacitor C2 are connected is the output terminal of the second detection circuit 601.
[0105] The second detection circuit 601 may include at least one second detection capacitor C2 and a second detection resistor R2 connected in series.
[0106] The second preset duration is determined by the product of the capacitance value of the second detection capacitor C2 and the second detection resistor R2. Therefore, the product of the capacitance value of the second detection capacitor C2 and the second detection resistor R2 can be less than or equal to the first preset duration, which can be the time allowed for the discharge transistor 500 to discharge electrostatic charge.
[0107] If it is necessary to increase the second preset duration, this can be achieved by increasing the capacitance value of the second detection capacitor C2 and / or increasing the resistance value of the second detection resistor; if it is necessary to decrease the second preset duration, this can be achieved by decreasing the capacitance value of the second detection capacitor C2 and / or decreasing the resistance value of the second detection resistor.
[0108] In some embodiments, the second detection resistor R2 includes a polysilicon resistor or a doped region resistor.
[0109] The second sensing resistor R2 can be integrated into the circuit using CMOS technology. The polysilicon resistor is made of lightly doped polysilicon, and its resistance value can be adjusted by the concentration of the light doping. Therefore, polysilicon resistors have advantages such as a wide and adjustable resistance range and small area. That is, the second preset time can be adjusted by adjusting the concentration of the light doping in the polysilicon resistor.
[0110] In some embodiments, the second detection capacitor C2 includes a MIM capacitor, a MOS capacitor, and a MOM capacitor. The second detection capacitor C2 can be integrated into the circuit using CMOS technology.
[0111] MOS capacitors include NMOS and PMOS capacitors. A MOS capacitor uses the gate oxide layer between the gate layer and the channel as an insulating layer, the gate layer as the upper plate, and the source / drain and substrate shorted together to form the lower plate. Its capacitance value can change with the control voltage, thus allowing for capacitance adjustment and an adjustable second preset duration. MIM capacitors can be formed using different metal layers and the dielectric between them. MIM capacitors can be formed without an additional photomask, making them simple to implement. MIM capacitors have a more precise capacitance value that does not change with bias voltage, making them suitable for designing a fixed second preset duration. MOM capacitors can be constructed using interdigitated structures of the same metal layer. For the same area, the capacitance value of a MIM capacitor is smaller than that of a MOM capacitor. When the capacitance value is fixed and a smaller capacitor area is desired, MOM capacitors can be chosen.
[0112] In some embodiments, such as Figure 4 As shown, the first detection circuit 300 includes:
[0113] The first sensing resistor R1 is connected to the first voltage terminal 100;
[0114] The first detection capacitor C1 is connected between the first detection resistor R1 and the second voltage terminal 200;
[0115] The end where the first detection resistor R1 is connected to the first detection capacitor C1 is the output terminal of the first detection circuit 300.
[0116] It is understood that the first detection circuit 300 may also include at least one first detection capacitor C1 and a first detection resistor R1 connected in series. The capacitance value of the first detection capacitor C1 and the capacitance value of the second detection capacitor C2 may be the same or different, and the resistance value of the first detection resistor R1 and the resistance value of the second detection resistor R2 may be the same or different. However, the first time constant of the first detection resistor R1 and the first detection capacitor C1 may be less than or equal to the second time constant of the second detection resistor R2 and the second detection capacitor C2.
[0117] The first time constant is the first preset duration, and the second time constant is the second preset duration.
[0118] In some embodiments, the first time constant may be less than 40 ns, and the second time constant may be between 200 ns and 1 μs.
[0119] In some embodiments, such as Figure 4 As shown, the control circuit 400 includes:
[0120] The first control switch P1 is connected between the first voltage terminal 100 and the control terminal of the discharge transistor 500; the output terminal of the first detection circuit 300 is connected to the control terminal of the first control switch P1.
[0121] In some embodiments, the control circuit 400 further includes:
[0122] The second control switch M1 is connected between the output terminal of the first detection circuit 300 and the second voltage terminal 200; the control terminal of the second control switch M1 is connected to the control terminal of the discharge transistor 500.
[0123] In some embodiments, the first control switch P1 is a PMOS transistor. The first control switch P1 can toggle the input low level to a high level, thereby turning on the discharge transistor 500 so that the electrostatic charge can be released in a timely manner.
[0124] In some embodiments, the second control switch M1 is an NMOS transistor. The second control switch M1 can keep the voltage at the input terminal of the control circuit at a low voltage, preventing it from flipping to a high level, thereby extending the conduction time of the discharge transistor 500 so that the electrostatic charge can be released in a timely manner.
[0125] In some embodiments, such as Figure 5 As shown, the control circuit 400 also includes:
[0126] At least one diode 401 is connected in series between the control terminal of the first control switch P1 and the second terminal of the second control switch M1, the at least one diode being used to enable unidirectional current conduction from the control terminal of the first control switch P1 to the second terminal of the second control switch M1.
[0127] In some embodiments, at least one diode 401 is further provided between the control terminal of the first control switch P1 and the second control switch M1. For example, it can be a single diode 401 or a diode string composed of two or more diodes 401. The diode 401 can be a germanium diode (Ge diode), a silicon diode (Si diode), or a polycrystalline silicon diode, and the embodiments disclosed herein are not limited thereto.
[0128] The at least one diode 401 can be used to further improve the latch-up resistance between the first control switch P1 and the second control switch M1. If the holding voltage between the first control switch P1 and the second control switch M1 is less than the normal operating voltage, latch-up can be maintained, and a large current will flow between the first voltage terminal 100 (e.g., VDD) and the second voltage terminal 200 (e.g., VSS) until the chip is burned out. Therefore, in order to suppress latch-up, the holding voltage between the first control switch P1 and the second control switch M1 can be increased to be greater than the normal operating voltage. Here, adding at least one diode 401 is equivalent to increasing the voltage of at least one diode 401 on the basis of the original holding voltage, thereby increasing the effective holding voltage and thus better preventing latch-up.
[0129] In some embodiments, such as Figure 6 As shown, the control circuit 400 also includes:
[0130] The third control switch M3; the control terminal of the third control switch is connected to the output terminal of the first detection circuit 300;
[0131] The first terminal of the third control switch M3 is connected to the control terminal of the discharge transistor 500;
[0132] The second terminal of the third control switch M3 is connected to the second voltage terminal 200.
[0133] In some embodiments, the control circuit 400 further includes: a fourth control switch P2;
[0134] The control terminal of the fourth control switch P2 is connected to the control terminal of the discharge transistor 500;
[0135] The first terminal of the fourth control switch P2 is connected to the first voltage terminal 100;
[0136] The second terminal of the fourth control switch P2 is connected to the input terminal of the control circuit 400.
[0137] The third control switch M3 can be an NMOS transistor. The third control switch M3 can be turned on after the discharge transistor 500 discharges electrostatic charge for a certain period of time. The output terminal of the third control switch M3 is used to pull down the voltage of the input terminal of the discharge transistor 500 to a low voltage, thereby turning off the discharge transistor 500.
[0138] The fourth control switch P2 can be a PMOS transistor, and its control terminal is connected to the output terminal of the control circuit 400. The first terminal of the fourth control switch P2 is connected to the first voltage terminal 100 (e.g., VDD), and the second terminal is connected to the input terminal of the control circuit 400. The fourth control switch P2 is used to respond to the second level output by the control circuit 400 and accelerate the switching of the input voltage of the control circuit 400 from low to high voltage, so that the discharge transistor 500 can be quickly turned off by the third control switch M3 after completing the electrostatic discharge.
[0139] When no ESD occurs at the first voltage terminal 100, i.e., when maintaining a stable value for normal operation, the third control switch M3 can be turned on, thereby making the output voltage of the control circuit 400 low. The fourth control switch P2 can further pull up or maintain the input voltage of the control circuit 400 at a high voltage. This makes the control circuit 400 more capable of outputting a low voltage, thereby ensuring better turn-off of the discharge transistor 500, and thus reducing the leakage current between the first voltage terminal 100 (e.g., VDD) and the second voltage terminal 200 (e.g., VSS) during normal operation.
[0140] In some embodiments, such as Figure 7 As shown, the electrostatic protection circuit 1000 also includes a delay circuit 700.
[0141] The delay circuit 700 includes: an inverter group, comprising an even number of interconnected inverters 701;
[0142] The inverter group is connected between the first voltage terminal 100 and the second voltage terminal 200;
[0143] The first end of the inverter group is connected to the output of the first detection circuit 300; the second end of the inverter group is connected to the input of the control circuit 400.
[0144] In some embodiments, inverter 701 includes:
[0145] The first inverter transistor P3 has its first terminal connected to the first voltage terminal 100.
[0146] The second inverter transistor M4 has its first terminal connected to the second voltage terminal 200.
[0147] The control terminal of the first inverting transistor P3 is connected to the control terminal of the second inverting transistor M4; the second terminal of the first inverting transistor P3 is connected to the second terminal of the second inverting transistor M4.
[0148] In some embodiments, an even number of inverters 701 may be provided between the first detection circuit 300 and the control circuit 400. This even number of inverters 701 constitutes an inverter group, and they are connected in series. Each inverter 701 may include a first inverting transistor P3 and a second inverting transistor M4. The input of the first inverter P3 is connected to the output of the first detection circuit 300, the output of the first inverter P3 is connected to the input of the second inverter M4, and the output of the second inverter M4 (or the even-numbered inverter) is connected to the input of the control circuit 400. The inverter group provides an input buffering function.
[0149] This disclosure also provides a semiconductor chip, such as... Figure 8 As shown, the semiconductor chip 1100 includes:
[0150] The first voltage terminal 100, the second voltage terminal 200, and the electrostatic protection circuit 1000 as described in any of the above embodiments.
[0151] Any of the electrostatic discharge (ESD) protection circuits 1000 in the embodiments of this disclosure can be used in semiconductor chips 1100 or integrated circuits to provide ESD protection for the chips or integrated circuits.
[0152] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0153] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0154] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. An electrostatic discharge protection circuit, characterized in that, The electrostatic discharge (ESD) protection circuit is connected to a first voltage terminal and a second voltage terminal. The ESD protection circuit includes: A first detection circuit is connected between the first voltage terminal and the second voltage terminal. The first detection circuit is used to output a first detection signal within a first preset time period when electrostatic charge appears on the first voltage terminal, or to output a second detection signal after the first preset time period when electrostatic charge appears on the first voltage terminal. A control circuit is connected between the first voltage terminal and the second voltage terminal, and the input terminal of the control circuit is connected to the output terminal of the first detection circuit; the control circuit is used to output a first level when the first detection signal is received, or to output a second level when the second detection signal is received. A discharge transistor is connected between the first voltage terminal and the second voltage terminal, and the control terminal of the discharge transistor is connected to the output terminal of the control circuit; the discharge transistor switches to the on state when the control terminal of the discharge transistor is at the first level, so as to discharge the electrostatic charge to the second voltage terminal; the discharge transistor switches to the off state when the control terminal of the discharge transistor is at the second level. A shutdown circuit is connected between the first voltage terminal and the second voltage terminal, and the output terminal of the shutdown circuit is connected to the control terminal of the discharge transistor; the shutdown circuit is used to output a control signal after a second preset time when electrostatic charge appears on the first voltage terminal; the control signal is used to shut down the discharge transistor; The second preset duration is greater than or equal to the first preset duration.
2. The electrostatic discharge protection circuit according to claim 1, characterized in that, The shutdown circuit includes: The second detection circuit is connected between the first voltage terminal and the second voltage terminal. The second detection circuit outputs a third detection signal within a second preset time period when electrostatic charge appears on the first voltage terminal, or outputs a fourth detection signal after the second preset time period when electrostatic charge appears on the first voltage terminal. A turn-off transistor is provided, wherein the first terminal of the turn-off transistor is connected to the second voltage terminal, the second terminal of the turn-off transistor is connected to the control terminal of the discharge transistor, and the control terminal of the turn-off transistor is connected to the output terminal of the second detection circuit; the turn-off transistor outputs the control signal after a second preset time period after an electrostatic charge appears on the first voltage terminal.
3. The electrostatic protection circuit according to claim 2, characterized in that, Within a second preset time period during which electrostatic charge appears on the first voltage terminal, the output terminal of the second detection circuit outputs a third detection signal to the control terminal of the turn-off transistor, and the turn-off transistor is in the off state. After a second preset time period following the appearance of electrostatic charge on the first voltage terminal, the output terminal of the second detection circuit outputs a fourth detection signal to the control terminal of the turn-off transistor, and the turn-off transistor is in the on state and outputs the control signal to the control terminal of the discharge transistor.
4. The electrostatic protection circuit according to claim 2, characterized in that, The second detection circuit includes: The second sensing resistor is connected to the first voltage terminal; The second detection capacitor is connected between the second detection resistor and the second voltage terminal; the end of the second detection resistor connected to the second detection capacitor is the output terminal of the second detection circuit.
5. The electrostatic discharge protection circuit according to claim 4, characterized in that, The second sensing resistor includes a polysilicon resistor or a doped region resistor.
6. The electrostatic discharge protection circuit according to claim 4, characterized in that, The second detection capacitor includes a metal-insulator-metal (MIM) capacitor, a metal-oxide-semiconductor (MOS) capacitor, and a metal-oxide-metal (MOM) capacitor.
7. The electrostatic protection circuit according to claim 1, characterized in that, The first detection circuit includes: The first sensing resistor is connected to the first voltage terminal; The first detection capacitor is connected between the first detection resistor and the second voltage terminal; The end where the first detection resistor is connected to the first detection capacitor is the output terminal of the first detection circuit.
8. The electrostatic discharge protection circuit according to claim 1, characterized in that, The control circuit includes: A first control switch is connected between the first voltage terminal and the control terminal of the discharge transistor; the output terminal of the first detection circuit is connected to the control terminal of the first control switch.
9. The electrostatic discharge protection circuit according to claim 8, characterized in that, The control circuit also includes: A second control switch is connected between the output terminal of the first detection circuit and the second voltage terminal; the control terminal of the second control switch is connected to the control terminal of the discharge transistor.
10. The electrostatic discharge protection circuit according to claim 9, characterized in that, The control circuit also includes: At least one diode is connected in series between the control terminal of the first control switch and the second terminal of the second control switch, the at least one diode being used to enable unidirectional current conduction from the control terminal of the first control switch to the second terminal of the second control switch.
11. The electrostatic discharge protection circuit according to claim 9, characterized in that, The control circuit also includes: A third control switch; the control terminal of the third control switch is connected to the output terminal of the first detection circuit; The first terminal of the third control switch is connected to the control terminal of the discharge transistor; The second terminal of the third control switch is connected to the second voltage terminal.
12. The electrostatic discharge protection circuit according to claim 11, characterized in that, The control circuit also includes: a fourth control switch; The control terminal of the fourth control switch is connected to the control terminal of the discharge transistor; The first terminal of the fourth control switch is connected to the first voltage terminal; The second terminal of the fourth control switch is connected to the input terminal of the control circuit.
13. The electrostatic discharge protection circuit according to claim 1, characterized in that, The electrostatic protection circuit also includes a delay circuit; The delay circuit includes: an inverter group, comprising an even number of interconnected inverters; The inverter group is connected between the first voltage terminal and the second voltage terminal; The first end of the inverter group is connected to the output end of the first detection circuit; the second end of the inverter group is connected to the input end of the control circuit.
14. The electrostatic discharge protection circuit according to claim 13, characterized in that, The inverter includes: A first inverting transistor, wherein the first terminal of the first inverting transistor is connected to the first voltage terminal; The second inverter transistor, wherein the first terminal of the second inverter transistor is connected to the second voltage terminal; The control terminal of the first inverting transistor is connected to the control terminal of the second inverting transistor; the second terminal of the first inverting transistor is connected to the second terminal of the second inverting transistor.
15. A semiconductor chip, characterized in that, The semiconductor chip includes: The first voltage terminal, the second voltage terminal, and the electrostatic protection circuit as described in any one of claims 1 to 14.