Fast start crystal oscillator circuit with programmable injection time and adaptive start-up time to achieve high amplitude oscillation

Abstract

A first tri-state driver injects a first clock signal into the crystal through an input node during a start-up phase of the crystal oscillator, and a second tri-state driver injects a second signal into the crystal through an output node during the start-up phase. The first signal and the second signal are anti-phase signals. The crystal oscillator circuit includes a first amplifier used during start-up and steady state operation, and includes a second amplifier. After a fixed time, the injection through the input node and the output node is disabled. After the injection ends, the second amplifier is turned on if the voltage on the output node has reached a desired voltage, and turned off otherwise. If the second amplifier is turned on, the second amplifier is turned off when the voltage on the output node reaches the desired voltage.

Description

Technical Field

[0001] This application relates to crystal oscillators, and more specifically to the startup of crystal oscillators. Background Technology

[0002] Crystal oscillators (XOs) typically use Pierce oscillators because they are simple and easy to tune. Figure 1 A Pierce oscillator 100 and a corresponding model 101 are shown. The crystal oscillator 100 includes a crystal 102 and a tuning capacitor C for tuning the frequency of the crystal oscillator 100. L1 104 and C L2 106. The crystal has two terminals labeled XI and XO, one terminal 105 (node ​​XI) connected to the input of amplifier 108, and the other terminal 107 (node ​​XO) connected to the output of amplifier. The amplifier can take various forms. A popular and simple amplifier implementation uses a simple CMOS inverter, where resistor 110 (R... F To achieve maximum gain, the amplifier is biased at the threshold voltage of the inverter. However, this method lacks the ability to fully control the bias current according to the needs of certain XO applications. Another method uses an amplifier with transconductance (g) m A voltage and current amplifier. Resistor R N The effective negative resistance of 112 is calculated as follows:

[0003] Where 0 is 2π0, and 0 is the resonant frequency.

[0004] In a Pierce oscillator, oscillation occurs at the parallel resonance of the crystal, which can be determined by the following equation:

[0005]

[0006] in S It is the series resonant frequency, and together with S and S Determined by crystal structure. C T This represents dynamic capacitance. It represents the piezoelectric charge gained from crystal displacement. R S L represents the dynamic resistance and the mechanical loss in the crystal. S This represents the dynamic inductance and the moving mass in the crystal. C0 is the parallel capacitance and stray capacitance between electrodes XI and XO.

[0007]

[0008] because CL The pulling rate of the oscillation frequency caused by the change can be calculated by the following formula:

[0009]

[0010] The start time for establishing the oscillation is |R N |、R S and L S And the functions for establishing the initial and final currents in the crystal, as shown below:

[0011]

[0012] The start time for establishing oscillations can be increased by increasing |R N |and reduce C T To minimize, because L S ω0 and R S Determined by crystal structure. |i S (0)| is the initial condition for the current in the crystal and is usually determined by the step response when an oscillator bias is applied to the crystal.

[0013] Figure 2 The tuning of C is shown using two capacitor banks 202 (C1) and 204 (C2). L1 and C L2 The crystal oscillator 200 is implemented using existing technology. Control signals CP1 203 and CP2 205 adjust the capacitors to tune the capacitor bank. The establishment of oscillation in the crystal oscillator is divided into two stages: i) the start-up stage with the establishment of the oscillation index; and ii) when V XO When the voltage at the output node of the amplifier is limited, there is an intermediate stage in which the oscillation linearity is established.

[0014] During the startup phase, a high current is applied while transconductance amplifiers 206 and 208 are both "on". Control signals CE (core enable) 210 and HGE (high gain enable) 212 are both "on" during the startup phase. m The amplifier has a very high g m / I D To obtain the maximum g of the bias current m This limits the amplifier's linearity and V. XO The voltage swing. In addition, C L1 (Capacitor bank C1 202) and C L2 (Capacitor bank C2 204) is set to its minimum value during the startup phase. Comparator circuit 214 detects V. XO When does the voltage at node XO reach the threshold, where the voltage swing is measured by xG? m Amplifier 208 is limited. Comparator circuit 214 is enabled (PKE high), and input multiplexer 216 selects V. XOThe signal (PK_SEL is high). Threshold TH1 220 is used as the threshold for comparator circuit 214 during the startup phase. When V XO When the amplitude exceeds the TH1 threshold, the output PKD 223 of the comparator circuit goes high, thereby warning the controller 218 that the startup phase has ended.

[0015] In the intermediate stage, C L1 and C L2 It is set to the steady-state target value. In response to detecting the end of the startup phase, controller 218 disables xG by eliminating HGE 212. m Amplifier 208 changes PK_SEL to 0 and changes the threshold provided to the comparator circuit to TH2 222. Core transconductance amplifier (G m )206 remains on during the intermediate stage and in steady state. The bias current during the intermediate stage is much higher than the steady-state bias current, in order to make V XO The almost full swing is limited by the power supply to build up current in the crystal as quickly as possible during the intermediate phase. During the intermediate phase, the voltage V at the XI node... XI The amplitude is still very low, and the voltage across the crystal is almost V. DD / 2 amplitude sine curve (V INJ =V DD / 2). Approximate time of the intermediate stage (T) INT This assumption can be used to calculate:

[0016]

[0017] Where |i S ,target| is the target steady-state crystal current, and k is the compensation V XO The scaling factor for the gradual transition from track to track, V XO,PP Peak-to-peak value V XO Amplitude, and |i S (t=t1)| is the crystal current at the beginning of the intermediate stage.

[0018] This circuit monitors V XI To determine when the crystal current reaches |i S,target |. When the comparator circuit 214 determines V XI When the amplitude exceeds the threshold TH2 222, the intermediate stage ends. The Gm bias current changes from the intermediate setting to the steady-state setting, which was previously determined using a bias optimization loop to find a steady-state current to maintain V. XIThe amplitude is just above TH2. Typically, the steady-state bias current is much lower than the current used during the startup and intermediate phases. Controller 218 enables square buffer 224 by activating square buffer enable (SQE) signal 225 immediately after the intermediate phase ends, so that the clock can be used at CLKOUT 226.

[0019] Figure 3 A timing diagram of crystal oscillator circuit 200 is depicted. The startup phase 301 typically takes twice as long as the intermediate phase 303. For some applications, minimizing the time required for current build-up during the startup phase, and thus minimizing the total startup time of the crystal oscillator, is crucial. For example... Figure 3 As shown, at the end of the startup phase with a low output swing, V XO The amplitude is almost saturated. At the end of the intermediate phase, V XO Amplitude saturates to maximum swing. This is due to changes in bias current and disabling of xG between the startup and intermediate phases. m Amplifier, V XI and V XO There are jumps in the signal.

[0020] To improve power supply sensitivity and increase the supported power supply voltage range, Figure 4 The crystal oscillator circuit 400 shown includes a low-dropout (LDO) regulator 402, which is added to Figure 2 In the crystal oscillator circuit 200 shown, a regulator reference generator 404, directly powered by the supply voltage, provides reference and bias current to the regulator 402. Another bias generator 406 is powered by the regulated voltage Vdda (the output of the LDO regulator 402) to reduce the supply sensitivity of the generated bias current. A control signal BE is used to enable the bias of the crystal oscillator by enabling the regulator 402, regulator reference generator 404, and core bias generator 406. A control signal VADJ 408 controls / adjusts the output Vdda of the LDO regulator 402.

[0021] A CMOS inverter formed by transistors P1 and N1 implements G m Transconductance amplifier 206, where V S It is considered to be due to C D AC grounding at the oscillation frequency caused by the capacitor. For the same bias current, implementing a CMOS transconductance amplifier can make g... m The value doubles. Transistors N2, N3, P2, and P3 realize a high-gain transconductance amplifier (xG). mTransconductance amplifier 208 is configured such that N3 and P3 are used as self-cascode devices to increase the output resistance of the transconductance amplifier 208. Furthermore, the absolute values ​​of the threshold voltages of N3 and P3 are lower than those of N2 and P2. When HGE is high, switches S3 and S5 are "on" (closed), while switches S4 and S6 are "off" (open). When HGE is low, switches S3 and S5 are "off," while S4 and S6 are "on." Transistors N2 and P2 are wide to maximize usable transconductance using the bias current.

[0022] The current-mirror digital-to-analog converter (DAC) controls the bias current, where a simple current mirror 412 is used to implement the two most active core bias bits (CB[8:7]), while a cascode current mirror 414 is used to implement the remaining bits (CB[6:0]) to improve power supply sensitivity under steady-state bias, which is typically low when both MSBs are disabled. During the startup and intermediate phases, the amplifier's bias current is high to build up current in the crystal as quickly as possible. In steady state, the current DAC is set to a value that will keep the oscillation amplitude constant.

[0023] Figure 5 An example of a square buffer 224 is shown, where the input (XI) is AC coupled to make the performance of the square buffer independent of the input DC voltage. Similar to the core amplifier, the square buffer is based on a CMOS (PMOS+NMOS) design to maximize g m The current DAC 502 controls the bias current, and the decoupling capacitor 504 decouples node V. S2 AC coupled to ground. Schmitt inverter 506 follows first-stage transconductance amplifier 508 to provide greater immunity.

[0024] With L S =6mH,C S =2.64fF, C0=0.8pF, R S =14 and C L A 40MHz crystal with a voltage rating of 10pF provides an example for calculating the start-up time and energy of a crystal oscillator. S,target |=1.8mA peak value, corresponding to the voltage across the crystal (V XO -V XI The peak value of 663mV was observed. Time t1 is the time at the end of the startup phase (~110μs), where |i S (t=t1)|=0.3mA peak value. The DC current consumption during the startup phase is I. VDD,1 =1.28mA, and the DC current consumption during the intermediate stage is I VDD,INT = 1.15mA. Startup time (T) STARTUP ) and the total charge consumed from the power supply during startup (Q)STARTUP The following can be calculated:

[0025] T STARTUP =t1+T INT ≈110μs + 50μs = 160μs

[0026] Q STARTUP =t 1VDD,1 +T INTVDD,INT ≈141nC + 58nC = 199nC.

[0027] Although Figure 2 and Figure 4 The crystal oscillator circuit provides a method for starting the crystal oscillator, but further improvements are still needed to improve the crystal oscillator startup time. Summary of the Invention

[0028] Therefore, in an embodiment, a method for starting a crystal oscillator includes, during a startup phase, injecting a first clock signal into a first node of the crystal oscillator using a first tri-state driver. During the startup phase, injecting a second clock signal into a second node of the crystal using a second tri-state driver, wherein the first and second clock signals are inverted signals. In response to the end of a predetermined time period, disabling the injection of the first and second clock signals. During the startup phase and during an intermediate startup phase following the startup phase, enabling a first amplifier circuit coupled between the first and second nodes. The intermediate phase ends in response to the amplitude of the first node voltage on the first node reaching a first voltage threshold.

[0029] In another embodiment, the crystal oscillator includes an injection circuit for injecting a first signal into the crystal of the crystal oscillator through a first node and a second signal into the crystal through a second node during a startup phase for starting the crystal oscillator, wherein the first and second signals are inverted signals. A control circuit disables the injection circuit in response to the elapsed time period to stop the injection of the inverted signals. A first amplifier circuit is coupled between the first and second nodes and is used during the startup and intermediate phases. A comparator circuit compares the amplitude of the first node voltage at the first node with a first voltage threshold. When the amplitude of the first node voltage exceeds the first threshold voltage, it indicates the end of the intermediate phase.

[0030] In another embodiment, the crystal oscillator includes a first node and a second node, the first node being used for coupling to a first terminal of the crystal of the crystal oscillator, and the second node being used for coupling to a second terminal of the crystal. A first tri-state driver injects a first signal into the first node during the startup phase of the crystal oscillator, and a second tri-state driver injects a second signal into the second node during the startup phase. The first and second signals are inverted signals. A control circuit disables the first and second tri-state drivers after a predetermined time period, thereby disabling the injection and setting the corresponding outputs of the first and second tri-state drivers to high impedance. A first amplifier circuit is coupled between the first and second nodes and is used during the startup phase and during an intermediate phase following the startup phase. A second amplifier circuit is coupled between the first and second nodes and is selectively used during the startup phase. Attached Figure Description

[0031] The invention can be better understood by referring to the accompanying drawings, and its many objects, features and advantages will be apparent to those skilled in the art.

[0032] Figure 1 The Pierce oscillator and its model are shown.

[0033] Figure 2 A high-level block diagram of a crystal oscillator circuit is shown.

[0034] Figure 3 It shows the relationship with Figure 2 Timing diagrams and waveforms associated with the crystal oscillator.

[0035] Figure 4 A block diagram of a crystal oscillator including a low-dropout (LDO) regulator is shown.

[0036] Figure 5 An example of a square buffer circuit is shown.

[0037] Figure 6 It shows |δf INJ |=0ppm and |δf INJ | Expected start-up time of approximately 5000 ppm (parts per million).

[0038] Figure 7 An embodiment of a crystal oscillator using a short injection signal from a three-state driver is shown.

[0039] Figure 8 It shows that it can be used Figure 7 An example of a three-state driver with non-overlapping switches used in a crystal oscillator.

[0040] Figure 9 It shows Figure 7The timing diagram of the crystal oscillator is shown.

[0041] Figure 10 An embodiment of a crystal oscillator using a short pulse of injected signal and an optional high-gain transconductance amplifier at startup is shown.

[0042] Figure 11A It shows Figure 9 The timing diagram of the crystal oscillator shown indicates that the high-gain transconductance amplifier is not turned on after checking the voltage at the XO node.

[0043] Figure 11B It shows Figure 9 The timing diagram of the crystal oscillator shown indicates that the high-gain transconductance amplifier is turned on after checking the voltage at the XO node.

[0044] Figure 12 It shows a regulator including an LDO. Figure 10 Examples of crystal oscillators.

[0045] Figure 13 A high-level block diagram of a wireless device is shown, which includes a frequency synthesizer for generating a local oscillator signal that is also used during crystal oscillator startup.

[0046] Figure 14 A high-level block diagram of a crystal oscillator and a frequency synthesizer is shown, the frequency synthesizer including an LC oscillator used during crystal oscillator startup.

[0047] Figure 15 This is a flowchart illustrating the determination of injection parameters during initial power-on.

[0048] Figure 16 This is a flowchart illustrating the injection of a clock signal from a frequency synthesizer into a crystal oscillator, which is also used as a local oscillator for RF communications.

[0049] Using the same reference numerals in different figures to indicate similar or identical items. Detailed Implementation

[0050] The embodiments described herein inject a signal with the same frequency as the crystal during startup. When a voltage signal is injected onto the crystal at the same frequency as the crystal, a crystal current begins to build up. The current amplitude in the crystal oscillator will begin to increase linearly with time, which can be modeled by the following equation:

[0051]

[0052] Where V INJ This is the voltage amplitude of the square wave signal across the crystal. This equation is based on f INJ= f0 (which is the crystal frequency). Generally, f INJ =f0+δf INJ Furthermore, the increase in crystal current amplitude is not linear with time. When the crystal's quality factor is very high (Q = ω0L), S / R S When the injection time is much shorter than 1 / α, an expression can be found where α = R. S / (2L S ), and the injection time is related to 1 / |δf INJ Equivalent to:

[0053]

[0054] The general expression is:

[0055]

[0056] With an injection frequency error of δf INJ During the signal period, the current amplitude in the crystal gradually increases until it reaches its maximum value, and then falls back down. The maximum value can be set by π×|δf. INJ |×T MAX The equation is calculated as π / 2. This equation can be used to determine the maximum acceptable T. INJ Or the maximum acceptable |δf INJ The formula is:

[0057]

[0058] One-step injection techniques for crystal oscillator startup inject a signal into the crystal for a very short duration, followed by the use of a crystal oscillator with a low-amplitude output signal. This provides a very short startup time and very low startup energy, but the oscillation amplitude is insufficient to achieve the low phase noise and low power supply sensitivity required for, for example, radio frequency (RF) performance. This method requires an oscillator for injection, where the oscillator is tuned to a frequency very close to the crystal's oscillation frequency and varies only slightly with temperature and power supply voltage. Such applications use RC oscillators or ring oscillators (due to their small area) because these oscillators are only used during crystal oscillator startup.

[0059] Another method for crystal startup utilizes a four-step approach, including two independent injection steps, to achieve higher oscillation amplitudes. In this four-step approach, an RC-ring oscillator (RC-RO) injects a differential rail-to-rail signal into the crystal at two crystal nodes coupled to the amplifier. The injection time is very short (T0). INJ1~2μs), allowing it to support injection frequency variations of ±5000ppm across the entire frequency range. After the first step, the phase-locked loop (PLL) is turned on, and the output from the crystal oscillator is provided to the all-digital PLL (ADPLL) as a reference signal for the ADPLL, where RO is the oscillator in the ADPLL. In step 2, RO is locked to the reference signal (crystal frequency), and the digital frequency control word used to achieve the lock is stored for use in step 3. The ADPLL preferably has a very fast lock time (T). LOCK ~6μs). To make the lock-in time faster, at the beginning of step 2, the phase of RO should be aligned with the reference clock from the crystal by resetting the edge of RO to align with the reference clock.

[0060] In step 3, the PLL is turned off, and the second injection step is performed. Any changes in the injection frequency due to temperature in step 1 are compensated by the digital frequency control word determined in step 2, ensuring that the injection frequency after the PLL is within the appropriate error range of the crystal frequency f0. When the PLL is turned off, the oscillator phase remains unchanged. Since the frequency error is 0 (or close to 0) in the second injection step, the injection signal is applied to the crystal until the current amplitude in the crystal reaches the target level. In step 4, when the target level is achieved, the injection is disabled, and a steady-state bias condition is applied to keep the oscillation amplitude constant over time. Note that no method is used in this four-step process to identify the crystal current |i| that has achieved the target. S,target The process of | is a drawback.

[0061] Figure 6 The differences between the four-step method (with two separate injection steps) and the one-step injection technique described above are illustrated. Dashed lines 602 and 604 indicate the difference at |δf INJ |=0ppm (line 602) and |δf INJ In both cases where | = 5000ppm (line 604), the target crystal current |i is achieved in a one-step injection. S,target |time. In the frequency error |δf INJ With a single-step injection of 5000 ppm, the oscillations from the single-step injection do not reach the target amplitude level. Solid lines 606 and 608 represent a four-step technique with two-step injection technology, demonstrating that even for T... INJ1 ,|δf INJ |=5000ppm, the crystal oscillator also reaches the target oscillation (line 608). For the four-step process, the total start-up time is (T STARTUP =T INJ1 +T LOCK +T INJ2 Definition. For |δf INJ |=0ppm and |δf INJWhen | = 5000ppm, T INJ1 and T LOCK Almost identical. For |δf INJ When | = 5000ppm, T INJ2 This is slightly longer to compensate for the difference in current amplitude at the end of step 1. This means that the startup time will increase slightly with changes in temperature.

[0062] One drawback of the two-step technique is that it uses only a dedicated, complete ADPLL to start the crystal oscillator, which consumes a significant amount of chip area. Furthermore, there is no clear method to determine whether the target current amplitude is achieved. This means that the oscillator design cannot flexibly handle crystals with different properties.

[0063] For example Figure 2 Compared to the methods described in the document, the embodiments described herein reduce the crystal oscillator startup time. Figure 7 An embodiment of a crystal oscillator circuit 700 with fast injection and a high-current amplifier is shown. The crystal oscillator circuit 700 reduces the startup time required for the crystal oscillator to reach steady state. Figure 2 One problem with crystal startup methods is their reliance on prolonged high current consumption to enable VX at the XI and XO nodes. XI and V XO Voltage increases exponentially. Figure 2 The growth rate in the method depends on the loop gain and the L of the crystal. S .improve Figure 2 One approach is to replace the fast injection phase. Figure 2 During the startup phase, the high-gain amplifier stage (xG) is replaced with a three-state driver 702. m The driver 702 is only used for short periods of time (e.g., T). INJ The tri-state driver is active for approximately 3 μs, then is disabled and placed in high-impedance mode. The tri-state driver 702 includes a tri-state driver for the XI node and a tri-state driver for the XO node. The drive signals are two inverted rail-to-rail square wave signals. The tri-state driver receives a clock injection signal (CLKINJ) 704 and a control signal INJE 706. Figure 8 An embodiment of a tri-state driver 800 for two tri-state drivers 702 is shown. The tri-state driver 800 receives a clock injection signal (CLKINJ) 704 and a control signal INJE 706. When the injection control signal INJE 706 is low, transistors 802 and 804 are turned off, and output node 806 is at high impedance. When INJE is high, output node 806 is determined by the value on the CLKINJ signal 704. Figure 7As shown, the output of one of the three-state drivers is inverted to obtain an inverted square wave signal. In the implementation, the CLKINJ signal is inverted before being supplied to driver 800, rather than being inverted at the output.

[0064] Return to reference Figure 7 , used for C L1 The capacitor bank C1 710 and the capacitor used for C L2 The capacitor bank C2 712 is used to realize C L1 and C L2 The controller 708 uses control signals CP1 703 and CP2 705 to tune capacitor banks C1 710 and C2 712. During the startup phase, along with the transconductance amplifier G... m 718 is "on", applying a high current. During the startup phase, controller 708 activates control signal CE (core enable) 720 to turn on transconductance amplifier G. m 718. Comparator circuit 722 detects V. XI When does the voltage at node XI reach a threshold (TH) 729? Comparison circuit 722 compares the voltage at node XI with the threshold TH, and provides an active peak detection signal PKD 730 when the comparison indicates that the voltage has reached the threshold. In an embodiment, comparison circuit 722 includes a peak detector circuit that receives the voltage at node XI, followed by a comparator circuit. The peak detector circuit stores the peak voltage detected at node XI, and the comparator compares that voltage with the provided threshold. Of course, other embodiments of the comparison circuit are also possible. Controller 708 enables comparison circuit 722 by activating enable signal PKE 724. Square buffer (SQBUF) circuit 726 provides a square wave output clock signal from crystal oscillator circuit 700 when enabled. Controller 708 receives activation signal 709, for example, from control logic running another clock signal, to activate crystal oscillator circuit.

[0065] Compared to other methods, the startup phase of the crystal oscillator circuit 700 is very short (~3μs) because the crystal current increases linearly with a high slope due to the injection of rail-to-rail signals at the XI and XO nodes. During the startup phase, it is best to keep C... L1 and C L2 Keep these values ​​to a minimum to reduce the capacitive load on the drivers, thereby reducing their current consumption. The bias current of the tri-state driver 702 should be high to keep the drive signal rail-to-rail ground into the XI and XO nodes. The injection time (T) can be accurately calculated using a counter and the injection clock signal CLKINJ 704. INJ Because the implementation requires the clock to be within a certain precision (e.g., for a 40MHz crystal, |δf) INJ|<4150ppm), therefore T can be accurately determined. INJ .

[0066] Once injection is disabled, the bias current is reduced to a level used for intermediate stages, but still high enough to operate at V. XI With V XO There is a voltage gain much greater than 1 between them. Although V XI It is still very small, but with the gain of the core amplifier, V XO Rapidly growing to near-orbit, such as Figure 9 As shown.

[0067] Figure 9 The diagram illustrates three stages: injection stage 902, intermediate stage 904, and steady-state stage 906. (Reference) Figure 7 and Figure 9 Secondly, to initiate the injection phase, controller 708 activates the CE signal 720 to turn on the transconductance amplifier Gm 718. Controller 708 also activates the injection enable (INJE) signal 706 to enable the tri-state driver 702 at the start of the injection phase. During the injection phase 902, the crystal current I... XTAL Linear but rapid growth. Figure 9 This shows V during the initiation injection phase 902. XI and V XO Approaching orbit.

[0068] Controller 708 is based on the time period T determined by the timer output of timer 728. INJ The injection phase 902 ends with the completion of the injection time T. In this embodiment, the injection time T... INJ It is programmable and stored in a register or other storage location accessible to controller 708, and can be programmed via, for example, a serial interface (not shown), or determined during manufacturing testing and stored in non-volatile memory. The controller eliminates INJE, but retains CE at the start of the intermediate phase. Controller 708 targets the tuning capacitor C at the start of intermediate phase 904. L1 and C L2 Steady-state tuning is applied to minimize the capacitance change between the intermediate and steady-state stages. This is achieved by monitoring V. XI And determine V XI The end of the intermediate stage is determined when a certain threshold voltage (TH) 729 is reached. This threshold voltage is provided to the comparator circuit 722 as the comparison threshold PK_TH. When V XI When the voltage amplitude exceeds the threshold TH, the comparator circuit 722 changes the PKD signal 730 from low to high, and this signal is sent to the controller 708. After the intermediate stage ends, the controller 708 applies a steady-state bias condition to make V XI and VXO The amplitude remains stable over time. In response to the start of the steady-state phase, the controller also activates SQE to turn on the square buffer 726.

[0069] The total startup time for the injection phase and intermediate phases can be calculated as follows:

[0070]

[0071]

[0072] For example, suppose T INJ =3μs, k is the calibration coefficient ~3 / 2, V XO,PP VDD is ~1.2V, LS is ~6mH, and |i S,target |=1.8mA peak value. |i S (t=T INJ The peak value is 0.446 mA, and T STARTUP =43.6μs.

[0073] With L S =6mH,C S =2.64fF, C0=0.8pF, R S =14Ω and C L A 40MHz crystal with 10pF was used for calculation. Figure 7 Example of startup time and startup energy for the crystal oscillator circuit 700 shown. |I| = 1.8mA peak. S,target | Corresponds to the voltage across the crystal (V) XO -V XI The peak value is 663mV. Assume T... INJ = 3μs, and |i S (t=T INJ The peak DC current consumption during the startup phase is I = 0.446mA. VDD,INJ =2.56mA, and the DC current consumption during the intermediate stage is I VDD,INT = 1.15mA. Startup time (T) STARTUP ) and the total charge consumed from the power supply during startup (Q) STARTUP The following can be calculated:

[0074] T STARTUP =T INJ +T INT ≈3μs + 40.6μs = 43.6μs

[0075] Q STARTUP =T INJ I VDD,INJ +T INT IVDD,INT ≈7.7nC + 46.7nC = 54.4nC

[0076] This is Figure 2 The method shown significantly reduces T compared to STARTUP and Q STARTUP Their values ​​are 160 μs and 199 nC, respectively.

[0077] Figure 10 Another embodiment of a fast-start crystal oscillator circuit 1000 is shown, which has programmable injection time and adaptive startup time to achieve high-amplitude oscillation. Figure 7 The embodiment shown saves energy and time in starting the crystal. However, Figure 7 Implementations require an accurate injection frequency to initiate within a reasonable timeframe. In Internet of Things (IoT) applications, a device powers on once and can then enter sleep mode multiple times. During the initial power-on, startup time / energy consumption is not critical, but becomes critical when repeatedly exiting sleep mode to perform RF operations (transmit or receive). During the initial power-on of the circuit, the injected signal may not be close enough to the crystal oscillation frequency (f0)(|δf) INJ (Too large) to achieve full activation. Figure 6 The dashed line 604 in the figure illustrates this inadequate startup. Figure 10 A crystal oscillator circuit 1000 is shown, which includes a three-state driver 702 and a high-gain transconductance amplifier (xG). m The 1019 can be used for injection with a three-state driver or with a high-gain transconductance amplifier (xG). m The option of using transconductance amplifier 1019 and transconductance amplifier 718 addresses this situation. Two transconductance amplifiers can be used in place of the injection, or as a supplement to the injection. Therefore, the user can choose to use the injection, use two transconductance amplifiers, or use the injection and additionally, if necessary, use the high-gain transconductance amplifier 1019 together with amplifier 718.

[0078] exist Figure 10 In, with Figure 7 Components with the same component label have the same structure and function. If a high-gain transconductance amplifier 1019 is selected to be used during startup, the controller 1008 turns on the transconductance amplifier G. m 718 and xG m Both 1019 and 1021 apply a high current by activating control signals CE (core enable) 720 and HGE (high gain enable) 1021. The controller will apply C during the startup phase when both transconductance amplifiers are enabled. L1 and C L2 Set to the minimum value. Comparator circuit 722 detects V. XOWhen the voltage at node XO exceeds threshold TH11020, the controller enables comparator circuit 722 by activating peak enable control signal PKE 724 and selects the XO input to be supplied from input multiplexer 1023 to comparator circuit 722 along with threshold TH11020, which is used as the threshold for comparator circuit during startup. XO When the amplitude exceeds the TH1 threshold, the comparator circuit will output PKD high, thus warning the controller 218 that the startup phase has ended. The controller clears PK_SEL to select the XI node, selects TH2 1022 as the threshold input for the comparator circuit 722, and disables HGE to enter the intermediate phase. When the comparator circuit 722 detects the voltage V on the XI input... XI When the value is greater than TH2, the comparator circuit eliminates PKD to indicate to the controller that the intermediate stage has ended and the steady-state stage should begin. Therefore, when only two transconductance amplifiers are used in the startup stage, circuit 1000 is as follows: Figure 2 and Figure 3 It operates as described. However, when the crystal oscillator circuit 1000 operates in startup injection mode, only TH2 is used, and PK_SEL is set to select the XI input. Otherwise, the crystal oscillator circuit operates in startup injection mode as described above. Figure 7 and Figure 9 As stated above.

[0079] In one embodiment, by configuring the mode during power-on based on, for example, a value in a programmed storage location in non-volatile memory (NVM), a choice can be made regarding whether the startup phase is operated in a first mode using two transconductance amplifiers, including a high-gain transconductance amplifier 1019, or in a second mode using current injection with a tri-state driver 702 during the startup phase. In other embodiments, the mode selection is pin-programmable.

[0080] Another embodiment provides the flexibility to use two initiation methods when conditions permit. To provide this flexibility, the controller 1008 checks V after the injection time. XO The range. Figure 11A A timing diagram associated with such an embodiment is shown. The startup phase occurs during time period 1102. The intermediate phase occurs during time period 1104, and the steady-state phase occurs during time period 1106. XO The amplitude check causes a delay in the startup phase (~4 μs) to check the V at the XO node. XO The amplitude is higher than T H1Threshold voltage. This means that selector circuit 1023 selects node XO as the input signal for comparator circuit 722. Therefore, as shown in Figure 11, the controller enables PK_SEL at 1108 at the start of the startup phase. Furthermore, the controller enables injection by enabling INJE at 1110. Note that in response to the end of the injection period, the controller enables the comparator circuit enable signal PKE (…). Figure 11A (Not shown in the image) takes effect. Threshold T H1 A desired threshold is provided to the comparator circuit 722. Timer 728 determines the end of the injection period, which lasts for a programmable time period. The programmable time period is stored in a register or other memory location accessible to the controller 1008 and can be programmed via, for example, a serial interface (not shown), or determined and stored in non-volatile memory during manufacturing testing. If V... XO The amplitude is high enough (higher than T) H1 If the comparator circuit 722 activates PKD 730 at 1113, and the intermediate stage 1104 begins without turning on the high-gain xG. m Amplifier 1019. The controller at 1112 cancels PK_SEL to select the XI input to the comparator circuit, and during the intermediate stage, the threshold TH2 is provided to the comparator circuit. Intermediate stage 1104 and Figure 9 The intermediate stages shown are the same. When linear growth leads to V XI When the value is greater than TH2, the comparator circuit activates PKD at 1114, indicating the end of the intermediate stage. The steady-state stage begins at 1116 when the square circuit is enabled (SQE is activated), and the steady-state condition is applied to the crystal oscillator circuit.

[0081] Figure 11B The injection failure resulted in a voltage V at the XO node. XO The case is high enough. If V XO If the amplitude is not high enough to trigger the comparator circuit, the controller enables high gain (xG) by activating HGE at 1112. m Amplifier, such as Figure 11B As shown, this is to obtain an exponential increase in the crystal current amplitude until V XO Until the amplitude exceeds the threshold TH1. When V XO At TH1, the comparator circuit activates PKD at 1113, thereby signaling the end of startup phase 1102. In response to PKD activating at 1113, the controller cancels HGE at 1111 to turn off xG. m Amplifier 1019. At this point, PK_SEL is eliminated at 1112 to select node XI as the input to the comparator circuit, and threshold TH2 is provided to the comparator circuit for comparison with V.XI Comparison. Besides due to the examination of V. XO In addition to affecting the length of the startup phase, startup time can also be affected by whether HGE is enabled (xG M (Connect) to make V XO The impact of the time required to reach the desired threshold. Due to the different properties of crystals (Ls, Cs, Rs), programmable injection time facilitates optimization based on crystal properties. Compared to intermediate stages, injection provides a faster current growth in the crystal. Therefore, by increasing the injection time with low frequency error, more stringent control over the injection frequency error can be used to obtain a lower total start-up time.

[0082] Figure 12 It shows Figure 10 A more detailed block diagram of an embodiment of the crystal oscillator circuit 1000 shown is provided. Furthermore, note that the clock injection signal 1202 is passed to the controller to ensure T... INJ The precise determination. This has already been described previously. Figure 12 The various boxes in the diagram. The tri-state driver circuit 702 is shown as including tri-state drivers DRV1 and DRV2, both of which are enabled by the INJE signal, which also gates the CLKINJ signal in AND gate 1204. Note that... Figure 12 The remaining boxes in the previous section have already been discussed. Figure 4 , Figure 7 and Figure 10 It has been described.

[0083] As previously mentioned, it is undesirable to use a dedicated PLL to start the crystal oscillator because this approach consumes a large area of ​​the integrated circuit. Therefore, embodiments utilize an architecture in which a frequency synthesizer already on the integrated circuit (e.g., for radio operation) is also used as the injection source for crystal startup. This ensures that the additional integrated circuit area is not solely dedicated to crystal startup. Thus, in embodiments, the frequency synthesizer used to provide the local oscillator clock signal during normal operation also provides the clock injection signal for crystal startup. Figure 13A high-level block diagram of an embodiment of a wireless device 1300 is shown, which includes a frequency synthesizer to provide a local oscillator signal for transmission / reception. An antenna 1301 provides the RF signal to a passive network (PN) 1303 that provides impedance matching, filtering, and electrostatic discharge protection. A low-noise amplifier (LNA) 1305 amplifies the signal from the passive network 1303 without significantly reducing the signal-to-noise ratio and provides the amplified RF signal to a mixer 1307. The mixer 1307 performs frequency conversion or shifting of the RF signal using a local oscillator (LO) signal provided by an I / Q generation block 1312, which is provided by a local oscillator 1309 implemented as a frequency synthesizer. In one embodiment, the frequency synthesizer includes a phase-locked loop (PLL) with an LC voltage-controlled oscillator (VCO). During normal operation, a crystal oscillator provides a reference clock for the PLL. The frequency synthesizer will be described further herein. I / Q generation block 1312 converts the local oscillator signal from local oscillator 1309 into I and Q signals for RX mixer 1307 and transmit (TX) mixer (not shown separately in TX block 1323).

[0084] Mixer 1307 provides the down-converted output signal as a set of two signals (in-phase (Im) and quadrature (Qm) signals) to programmable gain amplifier (PGA) 108. The Im and Qm signals are analog time-domain signals. In at least one embodiment of receiver 1300, analog amplifier 1308 and a filter (not shown separately) provide amplified and filtered versions of the Im and Qm signals to analog-to-digital converter (ADC) 1310, which converts these versions of the Im and Qm signals into digital Id and digital Qd signals. Exemplary embodiments of ADC 1310 use various signal conversion techniques (e.g., delta-σ (or σ-δ) analog-to-digital conversion). ADC 1310 provides the digital Id and Qd signals to channel filter 1311, which provides digital filtering of the digital Id and Qd signals, and provides the filtered Ic and Qc signals to demodulator 1318. Demodulator 1318 performs demodulation of the digital IC and QC signals to retrieve or extract information such as data signals that are modulated (e.g., in a transmitter (not shown)) and transmitted as RF signals to antenna 1301. Demodulator 1318 provides demodulated data to data processing circuitry 1319. In embodiments, data processing circuitry 1319 performs various functions (e.g., logic, arithmetic, etc.). For example, data processing circuitry 1319 uses demodulated data from programs, routines, or algorithms (whether software, firmware, hardware, or a combination thereof) to perform desired control or data processing tasks. In embodiments, data processing circuitry includes a processor such as a microcontroller and software and / or firmware to perform the desired functions. Memory 1320 stores software and firmware used by data processing circuitry 1319 to perform various tasks and stores data supplied to or from data processing circuitry 1319. In various embodiments, memory 1320 may include various types of memory, including dynamic random access memory (DRAM), static random access memory (SRAM), and / or non-volatile memory (NVM), depending on system needs. Furthermore, while data processing circuitry can access memory 1320, in embodiments, other system components, such as the LO control block 1321, may also access memory 1320 or portions thereof. In embodiments, at least some functions of the LO control block 1321 are implemented by software / firmware running on a processor in data processing circuitry 1319. Figure 13 Transmission path 1323, using the same antenna and local oscillator as the reception path, is also shown. Transmission data can be sent from memory 1320. Details of the transmission path are well known in the art and will not be described further herein.

[0085] Figure 14An example of a frequency synthesizer 1402 that can be used as a local oscillator 1309 in an RF communication device 1300 is shown. Figure 14 As shown, the frequency synthesizer includes a PLL having a phase frequency detector (PFD) 1404, a charge pump (CP) 1406, a loop filter (LF) 1408, a divider (Div2) 1410, and a multimode divider (MMD) 1412 serving as a feedback divider for the PLL. A synthesizer controller 1416 controls the synthesizer and corresponds to an LO controller 1321. In an embodiment, the controller 1416 includes digital logic to implement the control functions described herein. In an embodiment, the control functions also utilize programmable logic, such as a microcontroller, to implement some of the control functions. The PLL also includes a voltage-controlled oscillator (VCO) 1418 implemented using an LC oscillator. The VCO 1418 is tuned using capacitors CV1 and CV2 for coarse tuning and fine tuning is achieved via a Vc control signal provided by a multiplexer 1422. Multiplexer 1422 selects the output of loop filter 1408 in closed-loop mode and the output of digital-to-analog converter (DAC) 1420 in open-loop mode for clock injection during crystal startup. If DAC 1420 is selected, it is used to fine-tune the VCO frequency. Instead of an analog PLL, in this embodiment, the PLL is an all-digital PLL (ADPLL), where the phase frequency detector, charge pump, and loop filter are replaced by a time-to-digital converter (TDC) and a digital loop filter. The analog VCO can be replaced by a digitally controlled oscillator (DCO). The DCO can simply be a VCO with a DAC to convert digital words into control voltages from the digital loop filter. Furthermore, synthesizer 1402 includes DAC 1420 used during crystal startup. During normal operation, crystal oscillator 1430 operates at the crystal frequency (f... XTAL The synthesizer controller 1416 provides a stable clock CLKOUT 1430 and sets the synthesizer to the desired TX or RX mode. For example, the synthesizer controller provides a frequency control word (FWD) to the ΣΔ modulator 1419 (also referred to as the ΔΣ modulator) to control the frequency of the VCO 1418 by adjusting the feedback divider. The synthesizer controller 1416 also provides a VCO enable (VCOE) signal, tuning values ​​CV1 and CV2 for LC capacitor settings, and a divider value NDIV. In this embodiment, the divider control for the MMD is split into an integer part provided by NDIV and a fractional part provided by FWD to the ΣΔ modulator 1419. If the DAC resolution is sufficiently good, the fractional part and the ΣΔ modulator 1419 will not be needed during injection. During normal operation, all synthesizer subblocks are enabled except that the DAC 1420 can be turned off.

[0086] In this embodiment, the crystal oscillator 1430 is similar to Figure 7 The crystal oscillator shown is labeled with the same reference numerals for similar or identical blocks. The crystal oscillator circuit 1430 includes a tri-state driver 702, tuning capacitors CP1 710 and CP2 712, a Gm amplifier 718, an xGm amplifier 1019, an XO controller 1432, and a square buffer 726. Furthermore, the crystal oscillator circuit 1430 includes components functionally corresponding to, for example... Figure 4 The regulator 1434 of the regulator 402 shown corresponds to, for example Figure 4 The variable current source 1436 of the current source 414 shown, and corresponding to, for example Figure 5 The variable current source 502 shown is a variable current source 1438. In one embodiment, VCO 1418 provides an injection clock signal during crystal startup, and DAC 1420 sets the VCO control voltage for generating the injection clock signal 704. Therefore, the same VCO used during RF transmit / receive operations is also used for crystal startup.

[0087] When the integrated circuit is powered on for the first time, the crystal oscillator startup settings are calculated and saved. Initially, the XO starts without injection because the injection frequency has not yet been set. Therefore, amplifiers Gm 718 and xGm 1019 are used for crystal startup during initial power-on. During initial power-on operation, CLKOUT 1430 is supplied to the PLL in frequency synthesizer 1402, and appropriate settings for KVW, NDIV for DAC 1420 and / or control word FWD and NDIV for ΣΔ modulator 1419 are determined to lock onto the crystal frequency f. XTAL The VCO 1418 settings are calibrated using the controller 1416. The controller 1416 stores the calibration data in a register or other memory associated with the controller 1416, such as memory 1440. The controller stores the data along with the temperature readings provided by the temperature sensor 1442 at the time of calibration. This allows the settings to be adjusted for temperature based on any temperature changes since the initial calibration during subsequent calibrations.

[0088] When the integrated circuit (IC) enters sleep mode, the crystal oscillator is powered down. As mentioned earlier, startup time / energy consumption is not critical during the initial power-up of the IC in a typical IoT application, but startup time / energy consumption becomes critical for exiting sleep mode because the IC repeatedly exits sleep mode to perform IC operations, such as RF operations (transmit or receive) or other IoT functions associated with the IC. When exiting sleep mode, the stored VCO calibration settings and the current temperature reading are used to set KVW (or FWD) such that CLKINJ is essentially equal to f XTAL(Within an acceptable error range), thus enabling injection to aid startup. Note that the LC oscillator and frequency divider (Div2 and MMD) forming the VCO are very fast, so they will essentially only be used for injection purposes during the injection time T. INJ It is active for an additional period of time (~0.3μs).

[0089] In the first embodiment, during crystal oscillator startup, the control values ​​of CV1, CV2, and MMD are set such that the frequency of CLKINJ is close to the crystal frequency f. XTAL The value of CLKINJ is set, while KVW (the input digital word of the DAC) is set to the middle range. Later, KVW fine-tunes the frequency to bring CLKINJ closer to frequency f. XTAL The tuning resolution is determined by the bit depth of the DAC 1420. At room temperature, the DAC 1420 is set close to the middle range using a KVW value to allow the DAC to compensate for temperature rises and falls. The phase frequency detector 1404, charge pump 1406, and loop filter 1408 are disabled during injection to save power, and necessary portions of the PLL are enabled and the PLL operates in open loop. Similarly, in embodiments using an ADPLL, the time-to-digital converter and digital loop filter are turned off during injection. The injection time is typically very short, T. INJ =2-3μs.

[0090] LC oscillators, such as those used in VCO 1418, exhibit a temperature drift of, for example, +100 ppm / °C. DAC 1420 should be adjusted for this temperature drift within the desired temperature range, with a margin to ensure the injection frequency is accurate. In this embodiment, a calibration loop is run periodically (e.g., every 100 wake-up events or some other suitable interval), and a temperature sensor 1442 is used to compensate for the slope of the LC oscillator frequency with temperature, reducing the temperature drift to 20 ppm / °C. For each calibration loop run, updated DAC control values ​​are stored in memory 1440 to ensure that temperature variations do not cause the clock injection frequency at crystal startup to deviate from the specified value. XTAL Too far, for example, |δf INJ |≤2000ppm. For -40°C to 125°C, the residual frequency drift with temperature is ±2000ppm. The injection time T of the embodiment with these assumptions... INJ It can be calculated as follows:

[0091]

[0092] |δf INJ ≤2000ppm

[0093]

[0094]

[0095]

[0096]

[0097] T INJ ≤250T XTAL

[0098] For T XTAL =25ns (40MHz), T INJ It should be less than 6.25 μs.

[0099] In the second embodiment, the ΣΔ modulator 1419 sets the frequency via the multimode divider 1412 instead of the VCO oscillator frequency via the DAC 1420. During normal operation, where the PLL provides a clock signal for the integrated circuit operation, such as in TX / RX mode, the synthesizer 1402 operates in closed-loop mode, where the crystal oscillator output CLKOUT 1430 provides a reference clock for PLL operation. During crystal oscillator startup, the MMD 1412 is used to set the frequency of the injected clock signal with high precision. Control signals NDIV, CV1, CV2, and the DAC are configured to provide coarse tuning for CLKINJ. The ΣΔ modulator 1419 controls the MMD 1412 such that the frequency control word FWD sets the frequency of CLKINJ to f... XTAL Therefore, the ΣΔ modulator 1419 fine-tunes the injected frequency instead of acting as a DAC. When the average frequency is f... XTAL The division ratio of the MMD divider changes very rapidly. The value of FWD is determined at initial power-on and can be compensated for temperature during periodic temperature calibration. During crystal startup, the PLL operates in open loop, with the loop filter, charge pump, and phase frequency detector off to reduce power consumption. In this embodiment, the temperature is available at power-on, and the PLL is locked to the frequency of the crystal oscillator (CLKOUT). The values ​​of NDIV and FWD determined at power-on can be used for open-loop operation, making the MMD output close to f_XTAL. Furthermore, in this embodiment, FWD and NDIV are compensated for temperature drift during operation. Therefore, if the temperature changes after power-on, the accuracy of the injected frequency remains high.

[0100] Figure 15 This is a flowchart illustrating the actions taken during the initial power-on sequence. (Reference) Figure 14 and Figure 15The power-on sequence begins at 1502 when power is applied to the integrated circuit containing frequency synthesizer 1402 and crystal oscillator 1430. Note that crystal 1401 may be packaged with the integrated circuit, but as a separate component. Part of the power-on sequence includes crystal oscillator startup. In 1506, since the PLL is not yet configured to provide the injection clock, the XO controller 1412 uses Gm and xGM amplifiers to achieve a sufficiently high amplitude oscillation. As mentioned earlier, the startup power cost of the integrated circuit is not a major issue, as IoT devices typically power on once and then enter and exit sleep states over extended periods. Once the crystal oscillator reaches a steady state in 1508, in 1510, the synthesizer controller 1416 locks the PLL to the CLKOUT signal 1430 provided by the crystal oscillator. In one embodiment, locking is achieved by altering the KVW signal (or FWD) to the DAC until the PFD indicates that the phase difference is within an acceptable level. In other embodiments, a frequency counter can be used ( Figure 14 (Not shown in the diagram), and adjust KVW (or FWD) until the frequency counter counts the same value for CLKOUT 1430 and CLKINJ 1432 within the same time period. Once the lock is achieved, in step 1512, the parameters used to achieve the lock are stored in memory 1434. In this embodiment, the memory is non-volatile, so the state is maintained when the integrated circuit enters sleep mode. Parameters include, for example, KVW, CV1, CV2, NDIV, FWD, and any other parameters that can be used to recreate an injected clock signal with a frequency matching the crystal oscillator frequency at the time of a wake-up event. The specific parameters stored vary depending on, for example, whether the frequency used for injection is fine-tuned by MMD and ∑Δ or fine-tuned by KVW. After storing the parameters, the integrated circuit continues other power-on tasks if needed, and then typically enters a power-saving state, also referred to herein as sleep mode, in which the crystal oscillator is de-energized.

[0101] Figure 16 A flowchart illustrating the use of frequency synthesizer 1402 for crystal startup is shown. In response to a wake-up event at 1602, synthesizer controller 1416 at 1604 configures the PLL for clock injection using stored parameters for XO injection and notifies XO controller 1412 that clock injection is ready. At 1606, the frequency synthesizer provides the injected clock at the crystal oscillator frequency. XO controller 1432 then uses the clock injection to start the crystal oscillator, as shown, for example, regarding... Figure 7 As described. The XO controller checks in 1608 to see the target injection time (T). INJThe system checks whether the crystal oscillator has completed its startup, and when the injection time is complete, the synthesizer is powered down in 1610 to save current consumption. Once the crystal oscillator has reached steady state in 1612, the XO controller 1432 notifies the synthesizer controller that the crystal startup is complete. The synthesizer controller 1416 configures the PLL for the operating mode in 1614, for example, for RF transmit and / or receive operations. Once the RF operation is complete in 1616, the IoT integrated circuit re-enters sleep mode in 1618 and waits for the next wake-up event in 1602, for example, when the next transmit and / or receive operation expires. When the next wake-up event occurs, the LC oscillator of the clock synthesizer is again used as the source of the injected clock for crystal oscillator startup. This helps ensure that crystal oscillator startup occurs quickly and responds to each wake-up event with lower power, which helps extend battery life.

[0102] Therefore, embodiments for achieving faster startup using less energy have been described. The description of the invention set forth herein is illustrative and not intended to limit the scope of the invention as set forth in the appended claims. Other variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for starting a crystal oscillator, comprising: During the startup phase of the startup, a first clock signal is injected into the first node of the crystal of the crystal oscillator using a first tri-state driver; During the startup phase, a second clock signal is injected into the second node of the crystal using a second tri-state driver, wherein the first clock signal and the second clock signal are inverted signals. In response to the end of a predetermined time period, the injection of the first clock signal and the second clock signal is disabled; During the startup phase and during the intermediate phase of the startup following the startup phase, a first amplifier circuit coupled between the first node and the second node is enabled. as well as The intermediate phase ends when the magnitude of the first node voltage on the first node exceeds a first voltage threshold.

2. The method according to claim 1, further comprising: During the startup phase and after the injection is disabled, the magnitude of the second node voltage on the second node is compared with a second voltage threshold to determine whether the second node voltage is greater than the second voltage threshold.

3. The method according to claim 2, further comprising: In response to the second node voltage amplitude being greater than the second voltage threshold, the intermediate stage is entered.

4. The method according to claim 2, further comprising: In response to the second node voltage amplitude not being greater than the second voltage threshold, the second amplifier coupled between the first node and the second node is turned on before the start-up phase ends.

5. The method according to claim 4, further comprising: After the second amplifier is turned on, the intermediate stage is entered in response to the second node voltage amplitude being greater than the second voltage threshold.

6. The method according to claim 5, further comprising: In response to the second node voltage amplitude being greater than the second voltage threshold, the second amplifier is turned off.

7. The method according to claim 4, further comprising: The comparison of the magnitude of the second node voltage with the second voltage threshold during the startup phase is changed to the comparison of the magnitude of the first node voltage with the first voltage threshold during the intermediate phase.

8. The method of claim 1, wherein the end of the startup phase is determined in response to the end of the predetermined time period.

9. The method according to any one of claims 1 to 8, further comprising: During the intermediate phase and the steady-state phase following the intermediate phase, the tuning capacitor of the crystal oscillator is set to a steady-state value.

10. The method according to any one of claims 1 to 8, further comprising: In response to the end of the intermediate phase, a steady-state bias condition is applied to maintain the first node voltage on the first node and the second node voltage on the second node under the desired steady-state conditions.

11. A crystal oscillator, comprising: Crystals; An injection circuit is configured to inject a first signal into the crystal of the crystal oscillator via a first node and a second signal into the crystal via a second node during a startup phase for starting the crystal oscillator, wherein the first signal and the second signal are inverted signals; A control circuit is configured to disable the injection circuit in response to the passage of a predetermined time period, thereby stopping the injection of the inverted signal; A first amplifier circuit is coupled between the first node and the second node and is used during the startup phase and the intermediate phase; as well as A comparison circuit is used to compare the amplitude of the first node voltage on the first node with a first voltage threshold, and when the amplitude of the first node voltage exceeds the first threshold voltage, it indicates the end of the intermediate stage.

12. The crystal oscillator according to claim 11, wherein, The injection circuit also includes: A first three-state driver is used to inject the first signal into the first node; and The second three-state driver is used to inject the second signal into the second node.

13. The crystal oscillator according to claim 12, wherein, The corresponding outputs of the first tri-state driver and the second tri-state driver are at high impedance when disabled.

14. The crystal oscillator according to any one of claims 11 to 13, wherein, During the startup phase, after the injection circuit is disabled, the comparison circuit compares the magnitude of the second node voltage on the second node with a second voltage threshold.

15. The crystal oscillator according to claim 14, wherein, In response to the comparator circuit indicating that the magnitude of the second node voltage is greater than the second voltage threshold, the crystal oscillator enters the intermediate phase.

16. The crystal oscillator of claim 14, further comprising: Second amplifier circuit; as well as The second amplifier circuit is turned on in response to a comparator circuit indicating that the amplitude of the second node voltage is not greater than the second voltage threshold during the startup phase and after the injection circuit is disabled.

17. The crystal oscillator according to claim 16, wherein, After the second amplifier circuit is activated, the crystal oscillator enters the intermediate stage in response to the second node voltage amplitude being greater than the second voltage threshold.

18. The crystal oscillator according to claim 17, wherein, The input of the comparator circuit is changed in response to the amplitude of the second node voltage exceeding the second voltage threshold, so as to compare the amplitude of the first node voltage with the first voltage threshold to determine the end of the intermediate stage.

19. The crystal oscillator according to any one of claims 11 to 13, wherein, The start-up phase ends upon the expiration of the predetermined time period.

20. A crystal oscillator, comprising: A first node and a second node, wherein the first node is used to couple to a first terminal of the crystal of the crystal oscillator, and the second node is used to couple to a second terminal of the crystal; A first three-state driver is used to inject a first signal into the first node during the startup phase of the crystal oscillator; A second tri-state driver is used to inject a second signal into the second node during the startup phase, wherein the first signal and the second signal are inverted signals; A control circuit is configured to disable the first tri-state driver and the second tri-state driver after a predetermined time period, thereby disabling injection and making the corresponding outputs of the first tri-state driver and the second tri-state driver high impedance; A first amplifier circuit is coupled between the first node and the second node and is used during the startup phase and the intermediate phase after the startup phase. as well as The second amplifier circuit is coupled between the first node and the second node.

21. The crystal oscillator according to claim 20, further comprising: A comparator circuit is used to compare the magnitude of the second node voltage on the second node with a startup phase voltage threshold after the injection has been disabled, wherein the second amplifier circuit is not turned on in response to the magnitude of the second node voltage exceeding the startup phase voltage threshold after the injection has been disabled, and the second amplifier circuit is turned on in response to the magnitude of the second node voltage not exceeding the startup phase voltage threshold. Wherein, in response to the second node voltage amplitude exceeding the startup phase voltage threshold after the second amplifier circuit has been turned on, the second amplifier circuit is turned off, the startup phase ends, and the intermediate phase begins; and The comparison circuit compares the magnitude of the first node voltage on the first node with an intermediate stage voltage threshold during the intermediate stage. In response to the magnitude of the first node voltage exceeding the intermediate stage voltage threshold, the intermediate stage ends and the steady-state stage begins.

Images