A signal generating circuit capable of preventing false triggering and improving the speed of a comparator
By using a current signal superposition and conversion circuit, combined with a high-power-rail high-speed PWM comparator circuit, the problems of false triggering and slow speed of PWM comparators are solved, achieving prevention of false triggering and efficient signal processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SANWEI ELECTRONIC TECH (SUZHOU) CO LTD
- Filing Date
- 2023-10-30
- Publication Date
- 2026-07-14
Smart Images
Figure CN117318673B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power control, specifically a signal generation circuit that prevents false triggering and improves comparator speed. Background Technology
[0002] In recent years, with increasingly higher demands for high performance, miniaturization, and low power consumption in various electronic devices used in both civilian and military fields, the performance requirements for integrated circuits have also been continuously increasing. As the core component of electronic devices, integrated circuit chips face increasingly stringent power supply requirements. With the continuous development of power management chips and higher market demands, the stability and efficiency of the power supply voltage directly affect the performance of the entire system.
[0003] Currently, most power management chips on the market use synchronous current-mode PWM (PWM) control DC / DC power control chips. The PWM comparator is a crucial module in the control loop of a DC / DC power chip. In current-mode controlled switching converters, one input of the PWM comparator is the output control signal of an error amplifier with slope compensation, and the other input is the inductor current information sampled from the on-resistance Rdson of the upper transistor. When the inductor current signal touches the VC signal with the slope, the PWM comparator outputs a signal to turn off the upper transistor, which is then sent to the power transistor driver circuit. The most critical aspect of a PWM comparator is its response time. If the response time is too long, the control time of the power transistor by the driver circuit will also be delayed, causing the power transistor's on-time to be longer than expected, resulting in increased output current. Simultaneously, the slow signal changes at the input terminals of the PWM comparator can easily cause false triggering under different conditions. This can lead to increased output ripple and decreased stability, or even irreversible damage to the power transistor and inductor. Furthermore, the current generated by the superimposed signal usually needs to be converted to voltage through a resistor before comparison, which also results in some power consumption. Summary of the Invention
[0004] The purpose of this invention is to provide a signal generation circuit that prevents false triggering and improves comparator speed, thereby solving the technical problems of easy triggering of PWM comparators when the switching transistor is turned on and conducting, and slow processing speed of subsequent comparators in the prior art.
[0005] To achieve the above objectives, the present invention employs the following technical methods:
[0006] A signal generation circuit that prevents false triggering and improves comparator speed includes a current signal superposition circuit, a current-to-voltage conversion circuit, and a high-power-rail high-speed PWM comparator circuit with input offset. A ramp current is input to the first signal input terminal of the current signal superposition circuit. The output voltage of the error amplifier in the DC / DC system is input to the second signal input terminal of the current signal superposition circuit. A fixed current in the DC / DC system is input to the third signal input terminal of the current signal superposition circuit. The superimposed current output terminal of the current signal superposition circuit outputs the superimposed current signal to the first signal input terminal of the current-to-voltage conversion circuit. The second signal input terminal of the current-to-voltage conversion circuit is input to the gate logic of the high-power transistor in the DC / DC system. The potential detection signal, the superimposed signal output terminal of the current-to-voltage circuit outputs the superimposed signal to the positive input terminal of the PWM comparator circuit, the negative input terminal of the PWM comparator circuit inputs the signal at the connection between the source of the upper power transistor and the external power inductor in the DC / DC system, the third signal input terminal of the PWM comparator inputs the detection signal of the gate logic potential of the upper power transistor in the DC / DC system, the control signal output terminal of the PWM comparator circuit outputs the control signal to turn off the upper power transistor in the DC / DC system, and the feedback signal output terminal of the PWM comparator circuit outputs the feedback signal used to input the third signal input terminal of the current-to-voltage circuit to control the superimposed signal output by the coupled current-to-voltage circuit.
[0007] As a limitation: the current signal superposition circuit includes a first current source, a second current source, a third current source, a first NMOS transistor, a first high-voltage transistor, a first resistor, a second resistor, and a first capacitor. One end of the first current source and the second current source are both connected to the power supply voltage. The other end of the first current source is connected to the drain of the first NMOS transistor, one end of the third current source, and the source of the first high-voltage transistor, respectively. The other end of the second current source is connected to the source of the first NMOS transistor. The source of the first NMOS transistor is connected to one end of the first resistor. The control voltage input to the gate of the first NMOS transistor is the output voltage of the error amplifier in the DC / DC system. The other end of the first resistor is grounded, and the other end of the third current source is grounded. The gate of the first high-voltage transistor is connected to one end of the first capacitor and one end of the second resistor, respectively. The other end of the first capacitor is grounded, and the other end of the second resistor is connected to the power supply. The drain of the first high-voltage transistor is the superposition current output terminal of the current signal superposition circuit.
[0008] As further defined: the current-to-voltage circuit includes a third resistor, a second high-voltage transistor, a first inverter, a second NMOS transistor, a third NMOS transistor, a diode, a Schottky diode, a buffer, a second capacitor, and a third capacitor. The input terminal of the first inverter receives the detection signal of the gate logic potential of the high-power transistor in the DC / DC system. The output terminal of the first inverter is connected to the gate of the second high-voltage transistor. The first inverter is connected to the high power rail. The drain of the second high-voltage transistor is connected to one end of the third resistor, the anode of the diode, and the cathode of the Schottky diode, respectively. The other end of the third resistor is connected to the superimposed current output terminal of the current signal superposition circuit. The cathode of the diode is connected to the input voltage, and the anode of the Schottky diode is connected to the DC / DC power rail. The source of the upper power transistor in the DC / DC system is connected to the connection point of the external power inductor. The source of the second high-voltage transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor, the drain of the third NMOS transistor, one end of the third capacitor, one end of the second capacitor, and the superimposed signal output terminal. The sources of the second and third NMOS transistors are both connected to the connection point of the source of the upper power transistor in the DC / DC system and the external power inductor. The other end of the third capacitor is connected to the feedback signal output terminal of the PWM comparator circuit. The gate of the third NMOS transistor and the input terminal of the buffer are both input to the detection signal of the gate logic potential of the upper power transistor in the DC / DC system. The output terminal of the buffer is connected to the other end of the second capacitor.
[0009] As a further definition: the high-speed PWM comparator circuit with input offset includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second inverter, a third inverter, and a fourth inverter;The gate of the first PMOS transistor PM1 is connected to the connection point between the source of the upper power transistor in the DC / DC system and the external power inductor. The gate of the second PMOS transistor is connected to the superimposed signal output terminal of the current-to-voltage circuit. The sources of both the first and second PMOS transistors are connected to the drain of the fourth PMOS transistor. The drain of the first PMOS transistor is connected to the gate of the seventh PMOS transistor, the drain of the fourth NMOS transistor, and one end of the fourth resistor. The drain of the second PMOS transistor is connected to the gate of the eighth PMOS transistor and one end of the fifth resistor. The source of the seventh PMOS transistor is connected to the gate of the fifth PMOS transistor. The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor. The drain of the seventh PMOS transistor is connected to one end of the sixth resistor and the gate of the tenth PMOS transistor. The drain of the eighth PMOS transistor is connected to one end of the eighth resistor and the gate of the ninth PMOS transistor. The other end of the sixth resistor is connected to the other end of the fifth resistor and one end of the seventh resistor. The other end of the eighth resistor is connected to the other end of the fourth resistor and one end of the ninth resistor. The other end of the seventh resistor, the source of the fourth NMOS transistor, the other end of the ninth resistor, the source of the sixth NMOS transistor, the source of the seventh NMOS transistor, and the source of the fifth NMOS transistor are all connected to the source of the ninth PMOS transistor. The negative power rail is connected to the high power rail. The gates of the fourth and fifth NMOS transistors are both input with a delayed detection signal indicating the gate logic potential of the high-power transistor. The gates of the fourth, fifth, and sixth PMOS transistors are all input with bias voltage signals. The sources of the fourth, fifth, and sixth PMOS transistors, as well as the source of the third PMOS transistor, are all connected to the positive power rail of the high power rail. The drain of the sixth PMOS transistor is connected to the sources of the ninth and tenth PMOS transistors, respectively. The drain of the ninth PMOS transistor is connected to... The drain and gate of the sixth NMOS transistor are connected. The drain of the tenth PMOS transistor is connected to the drains of the seventh, third, and fifth NMOS transistors, respectively, and the input of the second inverter. The gates of the sixth and seventh NMOS transistors are connected. The output of the second inverter is connected to the gate of the third PMOS transistor, the input of the third inverter, and the input of the fourth inverter. The output of the third inverter is the control signal output of the PWM comparator circuit, and the output of the fourth inverter is the feedback signal output of the PWM comparator circuit.
[0010] The beneficial effects achieved by this invention, due to the adoption of the above-described solution, compared with the prior art, are as follows:
[0011] This invention provides a signal generation circuit that prevents false triggering and improves comparator speed. It incorporates a current signal superposition circuit, a current-to-voltage conversion circuit, and a high-power-rail high-speed PWM comparator circuit with input offset. The current signal superposition circuit converts the voltage signal output from the DC / DC system into a current signal and superimposes them to provide a mixed control signal for subsequent circuits. The current-to-voltage conversion circuit converts the mixed current signal into a voltage signal and performs clamping and timing control to prevent false triggering. The PWM comparator circuit compares the inductor current signal and the superimposed signal, generating a control signal to turn off the upper power transistor. This effectively prevents false triggering of the PWM comparator when the upper power transistor is turned on and conducting in the DC / DC system. It significantly improves the speed of the PWM comparator without increasing power consumption or reducing comparison accuracy, and avoids the use of resistors. This invention further optimizes the system response time and dead time, thereby improving the efficiency of the entire DC / DC system. By avoiding the use of resistors, power consumption is reduced, and the speed and accuracy of the PWM comparator circuit vary very little under different temperatures and process angles. When the superimposed signal output by the current-to-voltage circuit is floating, the metastability of the superimposed signal is broken by using a coupling signal, ensuring that the superimposed signal can jump to a potential greater than that at the connection between the source of the upper power transistor and the external power inductor in the DC / DC system in a timely manner.
[0012] This invention applies to DC / DC systems. Attached Figure Description
[0013] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0014] Figure 1 This is a block diagram illustrating the principle of a signal generation circuit that prevents false triggering and improves comparator speed according to an embodiment of the present invention.
[0015] Figure 2 This is a circuit diagram of the current signal superposition circuit according to an embodiment of the present invention;
[0016] Figure 3 This is a circuit diagram of the current-to-voltage conversion circuit according to an embodiment of the present invention;
[0017] Figure 4 This is a circuit schematic diagram of a high-power-rail high-speed PWM comparator circuit with input offset according to an embodiment of the present invention;
[0018] Figure 5 The simulation results of the input and output of the comparator when a conventional signal generation circuit is applied in a BUCK-type peak current DC / DC chip are shown.
[0019] Figure 6 A local periodic diagram of a conventional signal generation circuit applied in a BUCK-type peak current DC / DC chip.
[0020] Figure 7 The simulation results of the comparator's input and output are shown in the figure when a conventional signal generation circuit with anti-false triggering function is applied in a BUCK-type peak current DC / DC chip.
[0021] Figure 8 A local periodic diagram of a conventional signal generation circuit with anti-false triggering function applied in a BUCK-type peak current DC / DC chip.
[0022] Figure 9 The simulation results of the comparator's input and output are shown in the figure when the signal generation circuit of this embodiment is applied in a BUCK-type peak current DC / DC chip.
[0023] Figure 10 This is a partial periodic diagram of the signal generation circuit of this embodiment when applied in a BUCK-type peak current DC / DC chip. Detailed Implementation
[0024] The present invention will be further described below with reference to the embodiments. However, those skilled in the art should understand that the present invention is not limited to the following embodiments. Any improvements and equivalent changes made based on the specific embodiments of the present invention are within the scope of protection of the claims of the present invention.
[0025] An embodiment of a signal generation circuit that prevents false triggering and improves comparator speed.
[0026] A signal generation circuit that prevents false triggering and improves comparator speed, such as Figure 1 As shown, it includes a current signal superposition circuit, a current-to-voltage circuit, and a high-speed PWM comparator circuit with input offset on a high power rail. The first signal input terminal of the current signal superposition circuit receives a ramp current I. slope The second signal input terminal of the current signal superposition circuit is input to the output voltage V of the error amplifier in the DC / DC system. C The third signal input terminal of the current signal superposition circuit is used to input a fixed current I in the DC / DC system. XThe superimposed current output terminal of the current signal superposition circuit outputs the superimposed current signal I_SIGMA to the first signal input terminal of the current-to-voltage circuit. The second signal input terminal of the current-to-voltage circuit inputs the detection signal INN_H of the gate logic potential of the upper power transistor in the DC / DC system. The superimposed signal output terminal of the current-to-voltage circuit outputs the superimposed signal PWM+ to the positive input terminal of the PWM comparator circuit. The negative input terminal of the PWM comparator circuit inputs the signal SW at the connection between the source of the upper power transistor and the external power inductor in the DC / DC system. The third signal input terminal of the PWM comparator inputs the detection signal INN_H of the gate logic potential of the upper power transistor in the DC / DC system. The control signal PWM_OUT1 output by the control signal output terminal of the PWM comparator circuit is the signal to turn off the upper power transistor in the DC / DC system. The feedback signal PWM_OUT2 output by the feedback signal output terminal of the PWM comparator circuit is used to input the third signal input terminal of the current-to-voltage circuit to control the superimposed signal PWM+ output by the coupled current-to-voltage circuit.
[0027] In this embodiment, the power transistor in the DC / DC system is an N-type MOS transistor.
[0028] In this embodiment, the current signal superposition circuit is as follows: Figure 2 As shown, the circuit includes a first current source I1, a second current source I2, a third current source I3, a first NMOS transistor NM1, a first high-voltage transistor HNM1, a first resistor R1, a second resistor R2, and a first capacitor C1. One end of the first current source I1 and the second current source I2 are both connected to the power supply voltage VDD. The other end of the first current source I1 is connected to the drain of the first NMOS transistor NM1, one end of the third current source I3, and the source of the first high-voltage transistor HNM1, respectively. The other end of the second current source I2 is connected to the source of the first NMOS transistor NM1. The source of the first NMOS transistor NM1 is connected to one end of the first resistor R1. The gate of the first NMOS transistor NM1 is connected to the control voltage V. C The output voltage of the error amplifier in the DC / DC system is the first resistor R1. The other end of the first resistor R1 is grounded, and the other end of the third current source I3 is grounded. The gate of the first high-voltage transistor HNM1 is connected to one end of the first capacitor C1 and one end of the second resistor R2. The other end of the first capacitor C1 is grounded, and the other end of the second resistor R2 is connected to the power supply VDD. The drain of the first high-voltage transistor HNM1 is the superimposed current output terminal of the current signal superposition circuit, which outputs the superimposed current signal I_SIGMA.
[0029] In this embodiment, the current-to-voltage conversion circuit is as follows: Figure 3As shown, the circuit includes a third resistor R3, a second high-voltage transistor HNM2, a first inverter INV1, a second NMOS transistor NM2, a third NMOS transistor NM3, a diode D1, a Schottky diode D2, a buffer, a second capacitor C2, and a third capacitor C3. The input terminal of the first inverter INV1 receives the detection signal INN_H of the gate logic potential of the upper power transistor in the DC / DC system. The output terminal of the first inverter INV1 is connected to the gate of the second high-voltage transistor HNM2. The first inverter INV1 is connected to the high power rail BST / SW. The drain of the second high-voltage transistor HNM2 is connected to one end of the third resistor R3, the anode of diode D1, and the cathode of Schottky diode D2, respectively. The other end of the third resistor R3 is connected to the superimposed current output terminal of the current signal superposition circuit, receiving the superimposed current signal I_SIGMA. The cathode of diode D1 is connected to the input voltage VIN. The anode of Schottky diode D2 is connected to the source of the upper power transistor in the DC / DC system and the external power supply. The connection point SW of the inductor is connected. The source of the second high-voltage transistor HNM2 is connected to the drain of the second NMOS transistor NM2, the gate of the second NMOS transistor NM2, the drain of the third NMOS transistor NM3, one end of the third capacitor C3, one end of the second capacitor C2, and the superimposed signal output terminal. The superimposed signal output terminal of the current-to-voltage circuit outputs the superimposed signal PWM+. The sources of the second NMOS transistor NM2 and the third NMOS transistor NM3 are both connected to the connection point SW between the source of the upper power transistor in the DC / DC system and the external power inductor. The other end of the third capacitor C3 is connected to the feedback signal output terminal of the PWM comparator circuit. The feedback signal output terminal of the PWM comparator circuit outputs the feedback signal PWM_OUT2 to the current-to-voltage circuit. The gate of the third NMOS transistor NM3 and the input terminal of the buffer BUFFER are both input to the detection signal INN_H of the gate logic potential of the upper power transistor in the DC / DC system. The output terminal of the buffer BUFFER is connected to the other end of the second capacitor C2.
[0030] In this embodiment, the PWM comparator circuit is as follows: Figure 4As shown, it includes the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4; the first PMOS transistor PM1 The gate of the first PMOS transistor PM1 is connected to the source of the second PMOS transistor PM2 at the connection point between the source and the external power inductor in the DC / DC system. The gate of the second PMOS transistor PM2 is connected to the superimposed signal output terminal of the current-to-voltage circuit. The superimposed signal output terminal of the current-to-voltage circuit outputs the superimposed signal PWM+ to the PWM comparator circuit. The sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both connected to the drain of the fourth PMOS transistor PM4. The drain of the first PMOS transistor PM1 is connected to the gate of the seventh PMOS transistor PM7, the drain of the fourth NMOS transistor NM4, and one end of the fourth resistor R4. The drain of the second PMOS transistor PM2 is connected to the gate of the eighth PMOS transistor PM8 and one end of the fifth resistor R5. The source of the seventh PMOS transistor PM7 is connected to the drain of the fifth PMOS transistor PM5 and the source of the eighth PMOS transistor PM8. The drain of the seventh PMOS transistor PM7 is connected to one end of the sixth resistor R6 and the gate of the tenth PMOS transistor PM10. The drain of the eighth PMOS transistor PM8 is connected to one end of the eighth resistor R8 and the gate of the ninth PMOS transistor PM9. The other end of the sixth resistor R6 is connected to the other end of the fifth resistor R5 and one end of the seventh resistor R7. The other end of the eighth resistor R8 is connected to the other end of the fourth resistor R4 and one end of the ninth resistor R9. The other end of the seventh resistor R7, the source of the fourth NMOS transistor NM4, the other end of the ninth resistor R9, and the sixth... The sources of NMOS transistors NM6, NM7, and NM5 are all connected to the SW terminal of the high power rail BST / SW. The gates of NMOS transistors NM4 and NM5 are both input to the delayed detection signal INN_D for the gate logic potential of the high-power transistor. The gates of PMOS transistors PM4, PM5, and PM6 are all input to the bias voltage signal PIB. The sources of PMOS transistors PM4, PM5, PM6, and PM3 are all connected to the BST terminal of the high power rail BST / SW.The drain of the sixth PMOS transistor PM6 is connected to the source of the ninth PMOS transistor PM9 and the source of the tenth PMOS transistor PM10. The drain of the ninth PMOS transistor PM9 is connected to the drain and gate of the sixth NMOS transistor NM6. The drain of the tenth PMOS transistor is connected to the drain of the seventh NMOS transistor, the drain of the third PMOS transistor PM3, the drain of the fifth NMOS transistor NM5, and the input of the second inverter INV2. The gate of the sixth NMOS transistor NM6 is connected to the gate of the seventh NMOS transistor NM7. The output of the second inverter INV2 is connected to the gate of the third PMOS transistor PM3, the input of the third inverter INV3, and the input of the fourth inverter INV4. The output of the third inverter INV3 is the control signal output of the PWM comparator circuit, outputting the control signal PWM_OUT1. The output of the fourth inverter is the feedback signal output of the PWM comparator circuit, outputting the feedback signal PWM_OUT2.
[0031] This embodiment describes the working principle of a signal generation circuit that prevents false triggering and improves comparator speed. The main function of the current signal superposition circuit is to convert the received voltage signal into a current signal and superimpose them to provide a mixed current signal for the subsequent circuit. The main function of the current-to-voltage circuit is to convert the mixed current signal into a voltage signal and perform clamping and timing control to achieve the function of preventing false triggering. The high-power rail high-speed PWM comparator circuit with input offset is used to compare the signal SW at the connection between the source of the upper power transistor and the external power inductor in the DC / DC system with the superimposed signal PWM+ output by the current-to-voltage circuit, and generate a control signal PWM_OUT1 to turn off the upper power transistor in the DC / DC system. The width-to-length ratio W / L of the first PMOS transistor PM1 is greater than the width-to-length ratio of the second PMOS transistor PM2. W refers to the gate width of the MOS transistor, L refers to the gate length of the MOS transistor, and W / L is the width-to-length ratio of the MOS transistor.
[0032] Since the PWM comparator in this embodiment operates when the power transistor is turned on in the DC / DC system, the signal compared from the high power rail BST / SW can be directly sent to the power transistor drive circuit. Compared to the PWM comparator on the low power rail, this saves the time of converting the low power rail signal into the high power rail signal required by the drive circuit, reduces the delay of the control loop transmission, further shortens the dead time, reduces the loss caused by the conduction of the lower body diode of the power transistor during the dead time, and improves the converter efficiency.
[0033] According to Kirchhoff's current theorem, the superimposed current signal I_SIGMA output from the superimposed current output terminal of the current superposition circuit is:
[0034] I_SIGMA = I C +IX -I slope1
[0035] In the formula, I_SIGMA is the superimposed current signal, I C V is the output voltage of the error amplifier in the DC / DC system. C The converted current signal, I X For a fixed current in a DC / DC system, I slope1 The first ramp current signal is generated by the first current source I1.
[0036] When the DC / DC system is running, at the start of the cycle, the high-power transistor is turned on, and at this time the output voltage V of the error amplifier is... C The gate-source voltage V of the first NMOS transistor NM1 is relatively large. GS It is also relatively large, according to
[0037]
[0038] V A =(I C +I sl o pe2 )×R1
[0039] It can be seen that I at this time C The value is relatively large; when the power transistor is turned on, I... X It is a fixed DC current; when the power transistor is turned off, I X It is zero; at the beginning of each cycle, I slope1 I slope2 Equal to zero, as the upper power transistor turns on, I slope1 I slope2 They increase continuously with fixed slopes S1 and S2 respectively; in the above formula, U n C represents the electron migration rate. OX For the gate oxide capacitance per unit area, W NM1 L is the gate width of the first NMOS transistor NM1. NM1 W is the gate length of the first NMOS transistor NM1. NM1 / L NM1 V is the width-to-length ratio of the first NMOS transistor NM1. C V is the output voltage of the error amplifier. TH1 I is the overdrive voltage of the first NMOS transistor NM1. slope2 R1 is the second ramp current signal generated by the second current source I2, and R1 is the resistance value of the first resistor R1.
[0040] When the upper power transistor is turned on, the signal SW at the connection point between the source of the upper power transistor and the external power inductor in the DC / DC system is almost equal to the input voltage VIN of the current-to-voltage converter. Since the SW potential at the connection point is high, the superimposed current signal I_SIGMA is necessarily a large current flowing from the connection point SW to ground GND. Normally, providing a resistor connected to the input voltage VIN of the current-to-voltage converter is sufficient to convert the superimposed current signal I_SIGMA into a voltage signal, which is then sent to the subsequent comparator for comparison. However, when the input voltage VIN of the current-to-voltage converter is very high, direct connection not only exceeds the drain-source withstand voltage of a typical MOSFET, burning it out, but also results in excessive power consumption due to the direct flow through the resistor. Furthermore, it generates uncontrollable instantaneous interference signals during periodic system transitions, directly affecting the input signal of the PWM comparator and causing false triggering. Therefore, in this embodiment, the mixed current signal is passed through the first high-voltage transistor HNM1 to obtain the superimposed current signal I_SIGMA. The superimposed current signal I_SIGMA is then connected to the junction SW between the source of the upper power transistor and the external power inductor via the third NMOS transistor NM3 and the Schottky diode D2, achieving the purpose of current-to-voltage conversion. When the upper power transistor in the DC / DC system is turned on, the potential of SW at the junction of the upper power transistor source and the external power inductor is pulled high, and the first high-voltage transistor HNM1 operates in the saturation region, bearing most of the voltage drop and solving the problem of ordinary MOS transistors being broken down. At this time, the current flowing through the first high-voltage transistor HNM1 is:
[0041]
[0042] In the above formula, V DD The internal power supply voltage is 3.4V, and V_MIX is... Figure 2 Voltage at the marked location, V TH2 This is the overdrive voltage of the first high-voltage transistor HNM1. At this time, the detection signal INN_H for the gate logic potential of the high-power transistor in the DC / DC system is at a low level, that is, the potential of INN_H is equal to the potential of SW. After passing through the first inverter INV1, the gate voltage of the second high-voltage transistor HNM2 is BST, BST = SW + 3.4V, and the gate-source voltage V of the second high-voltage transistor HNM2 is... GS The voltage is always greater than 3.4V. Therefore, the second high-voltage transistor HNM2 operates in the linear region when the upper power transistor is turned on, acting like a wire. The superimposed signal PWM+ output by the current-to-voltage circuit is equal to... Figure 3 The voltage at the marked V_SIGMA. For example... Figure 3As shown, the two currents I1 and I2 flow from the connection point SW between the source of the upper power transistor and the external power inductor, through the third NMOS transistor NM3 and the Schottky diode D2, to V_SIGMA, where they are superimposed to form a superimposed current I_SIGMA. This current then flows through the first high-voltage transistor HNM1 and finally into GND, resulting in:
[0043] I_SIGMA = I1 + I2
[0044] Current I1 flows through the third NMOS transistor NM3, therefore, PWM+ = SW-V TH3 The superimposed signal PWM+ output by the current-to-voltage conversion circuit is always less than the voltage at the connection point SW between the source of the power transistor and the external power inductor by the overdrive voltage V of the third NMOS transistor NM3. TH3 If the PWM comparator cannot be triggered to a high level, the power transistor will not be turned off.
[0045] As the upper power transistor turns on, it continuously charges the inductor. The inductor current at the connection point SW between the upper power transistor's source and the external power inductor continuously increases, while the voltage at SW continuously decreases. Simultaneously, the output voltage V of the error amplifier... C The current signal I that is converted from the decrease is... C The first ramp current I decreases. slope1 It keeps increasing. According to the nodal current method:
[0046] I_SIGMA = I C +I X -I slope1
[0047] The superimposed current I_SIGMA will decrease until it equals 0. At this point, the current flowing through the first high-voltage transistor HNM1 is 0. This means that as the superimposed current I_SIGMA decreases to zero, the operating state of the first high-voltage transistor HNM1 will sequentially change from the saturation region to the subthreshold region and then to the cutoff region. When the superimposed current I_SIGMA equals zero, the first high-voltage transistor HNM1 is in the cutoff region and is turned off. Simultaneously, the potential of the superimposed signal PWM+ output by the current-to-voltage circuit will continuously approach the potential at the connection point between the source of the high-voltage transistor and the external power inductor and will be in a floating state. Because there is an offset voltage at the input of the PWM comparator, when the value of SW-PWM+ equals this offset voltage, the PWM comparator flips to a high level, generating a control signal PWM_OUT1 to turn off the upper power transistor and a feedback signal PWM_OUT2 to the current-to-voltage conversion circuit. The control signal PWM_OUT1 and the feedback signal PWM_OUT2 are exactly the same. At the instant the feedback signal PWM_OUT2 flips upward, the superimposed signal PWM+ is quickly coupled to a voltage greater than the voltage at the connection point SW between the source of the upper power transistor and the external power inductor via the coupling capacitor C2. In this case, the difference between the two inputs of the PWM comparator increases rapidly, thus accelerating the circuit. The control signal PWM_OUT1 is input into the loop of the DC / DC system. After a very short delay, the upper power transistor is turned off, and the voltage at SW, the connection point between the source of the upper power transistor and the external power inductor, drops rapidly to about -0.7V. At this time, the voltage at V_MIX is greater than the voltage at SW, the connection point between the source of the upper power transistor and the external power inductor. The superimposed current I_SIGMA flows in the opposite direction, along the path I3, through the second NMOS transistor NM2, to SW, the connection point between the source of the upper power transistor and the external power inductor. Figure 3 As shown, the superimposed signal PWM+ is necessarily greater than the voltage SW at the connection between the source of the upper power transistor and the external power inductor, and the overdrive voltage V of the second NMOS transistor NM2. TH4 The PWM comparator is stably triggered to a high level.
[0048] The high-level signal output by the PWM comparator, after passing through the second inverter INV2, turns on the third PMOS transistor PM3, which in turn pulls the input of the second inverter INV2 high, forming a positive feedback path that latches the output signal to a fixed level. When the upper power transistor is turned on, the gate logic potential detection signal INN_H of the upper power transistor flips from high to low. After a delay time T0, the gate logic potential detection signal INN_D of the upper power transistor will also flip from high to low. Therefore, during this delay time, the PWM comparator does not work. That is, when the upper power transistor starts to turn on, the PWM comparator will not trigger a high level within T0, which also prevents false triggering by interference signals and ensures the minimum conduction time of the DC / DC system. When the upper power transistor is turned off, the gate logic potential detection signal INN_H of the upper power transistor flips from low to high. After a delay time T1, the gate logic potential detection signal INN_D of the upper power transistor will also flip from low to high. This causes the control signal PWM_OUT1 output by the PWM comparator to remain at a high level for a fixed time T1 before being forcibly reset to zero, and the cycle repeats.
[0049] This embodiment uses a 0.18μm BCD process to design a signal generation circuit that prevents false triggering and improves the speed of the subsequent comparator. The signal generation circuit is then applied to a BUCK-type peak current DC / DC chip. When the input voltage of the BUCK-type peak current DC / DC chip is 6V, simulations are performed using a conventional signal generation circuit, a conventional signal generation circuit with false triggering prevention function, and the signal generation circuit of this embodiment.
[0050] Depend on Figure 5 and Figure 6 It can be seen that when the upper power transistor is just turned on, the superimposed signal PWM+ output by the current-to-voltage circuit is superimposed with an interference signal. The superimposed signal PWM+ with the interference signal will cause the PWM comparator to be falsely triggered to a high level, causing the upper power transistor to be turned on and then falsely turned off by the signal, making the entire DC / DC system unable to work normally. Since the superimposed signal PWM+ and SW at the connection between the source of the upper power transistor and the external power inductor change very slowly, there is a 50ns delay from the time the superimposed signal PWM+ and SW at the connection between the source of the upper power transistor and the external power inductor are equal to the time the PWM comparator is triggered to a high level.
[0051] Depend on Figure 7 and Figure 8 It can be seen that by delaying the detection signal of the gate logic potential of the power transistor, the PWM comparator is forced not to trigger during the stage with interference signals, and the entire DC / DC system can work normally. The PWM comparator still has a delay of 50ns, which slows down the response speed of the DC / DC system and also affects the overall efficiency.
[0052] Depend on Figure 9 and Figure 10 It can be seen that by delaying the detection signal INN_H of the gate logic potential of the upper power transistor, the PWM comparator is prevented from triggering during the stage with interference signals, and the entire DC / DC system can work normally. As the superimposed current I_SIGMA continuously decreases, the PWM comparator starts comparing when the difference between the SW at the connection point between the source of the upper power transistor and the external power inductor and the superimposed signal PWM+ is less than the offset set by the PWM comparator. At the same time as the control signal PWM_OUT1 output by the PWM comparator is triggered, the superimposed signal PWM+ rapidly rises to be greater than the SW at the connection point between the source of the upper power transistor and the external power inductor, further accelerating the speed of the PWM comparator, which has almost no delay. As the upper power transistor is turned off, the SW at the connection point between the source of the upper power transistor and the external power inductor drops rapidly to about -0.7V, becoming the lowest potential. The superimposed current I_SIGMA flows in the opposite direction to the SW at the connection point between the source of the upper power transistor and the external power inductor, ensuring that the superimposed signal PWM+ is always greater than the voltage of the SW at the connection point by an overdrive voltage V. TH4 The control signal PWM_OUT1 is kept high for a stable period of time. After a certain delay, the detection signal of the gate logic potential of the power transistor forces the control signal PWM_OUT1 to zero, and so on.
Claims
1. A signal generation circuit that prevents false triggering and improves comparator speed, characterized in that, The circuit includes a current signal superposition circuit, a current-to-voltage conversion circuit, and a high-speed PWM comparator circuit with input offset. The first signal input terminal of the current signal superposition circuit receives a ramp current. The second signal input terminal receives the output voltage of the error amplifier in the DC / DC system. The third signal input terminal receives a fixed current from the DC / DC system. The superimposed current output terminal outputs the superimposed current signal to the first signal input terminal of the current-to-voltage conversion circuit. The second signal input terminal of the current-to-voltage conversion circuit receives the detection signal of the gate logic potential of the high-power transistor in the DC / DC system. The superimposed signal output terminal of the voltage-to-voltage circuit outputs a superimposed signal to the positive input terminal of the PWM comparator circuit. The negative input terminal of the PWM comparator circuit inputs the signal at the connection point between the source of the upper power transistor in the DC / DC system and the external power inductor. The third signal input terminal of the PWM comparator inputs the detection signal of the gate logic potential of the upper power transistor in the DC / DC system. The control signal output terminal of the PWM comparator circuit outputs a control signal that turns off the upper power transistor in the DC / DC system. The feedback signal output terminal of the PWM comparator circuit outputs a feedback signal that is used to input the third signal input terminal of the current-to-voltage circuit to control the superimposed signal output by the coupled current-to-voltage circuit. The current signal superposition circuit includes a first current source, a second current source, a third current source, a first NMOS transistor, a first high-voltage transistor, a first resistor, a second resistor, and a first capacitor. One end of the first and second current sources is connected to the power supply voltage. The other end of the first current source is connected to the drain of the first NMOS transistor, one end of the third current source, and the source of the first high-voltage transistor, respectively. The other end of the second current source is connected to the source of the first NMOS transistor. The source of the first NMOS transistor is connected to one end of the first resistor. The control voltage input to the gate of the first NMOS transistor is the output voltage of the error amplifier in the DC / DC system. The other end of the first resistor is grounded, and the other end of the third current source is grounded. The gate of the first high-voltage transistor is connected to one end of the first capacitor and one end of the second resistor, respectively. The other end of the first capacitor is grounded, and the other end of the second resistor is connected to the power supply. The drain of the first high-voltage transistor is the superposition current output terminal of the current signal superposition circuit.
2. The signal generation circuit for preventing false triggering and improving comparator speed according to claim 1, characterized in that, The current-to-voltage conversion circuit includes a third resistor, a second high-voltage transistor, a first inverter, a second NMOS transistor, a third NMOS transistor, a diode, a Schottky diode, a buffer, a second capacitor, and a third capacitor. The input terminal of the first inverter receives the detection signal of the gate logic potential of the high-power transistor in the DC / DC system. The output terminal of the first inverter is connected to the gate of the second high-voltage transistor. The first inverter is connected to the high-voltage power rail. The drain of the second high-voltage transistor is connected to one end of the third resistor, the anode of the diode, and the cathode of the Schottky diode, respectively. The other end of the third resistor is connected to the superimposed current output terminal of the current signal superposition circuit. The cathode of the diode is connected to the input voltage, and the anode of the Schottky diode is connected to the DC / DC system. The source of the high-voltage transistor in the DC / DC system is connected to the connection point between the source of the high-voltage transistor and the external power inductor. The source of the second high-voltage transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor, the drain of the third NMOS transistor, one end of the third capacitor, one end of the second capacitor, and the superimposed signal output terminal. The sources of the second and third NMOS transistors are both connected to the connection point between the source of the high-voltage transistor in the DC / DC system and the external power inductor. The other end of the third capacitor is connected to the feedback signal output terminal of the PWM comparator circuit. The gate of the third NMOS transistor and the input terminal of the buffer are both input to the detection signal of the gate logic potential of the high-voltage transistor in the DC / DC system. The output terminal of the buffer is connected to the other end of the second capacitor.
3. The signal generation circuit for preventing false triggering and improving comparator speed according to claim 1, characterized in that, The high-power-rail high-speed PWM comparator circuit with input offset includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second inverter, a third inverter, and a fourth inverter;The gate of the first PMOS transistor PM1 is connected to the connection point between the source of the upper power transistor in the DC / DC system and the external power inductor. The gate of the second PMOS transistor is connected to the superimposed signal output terminal of the current-to-voltage circuit. The sources of both the first and second PMOS transistors are connected to the drain of the fourth PMOS transistor. The drain of the first PMOS transistor is connected to the gate of the seventh PMOS transistor, the drain of the fourth NMOS transistor, and one end of the fourth resistor. The drain of the second PMOS transistor is connected to the gate of the eighth PMOS transistor and one end of the fifth resistor. The source of the seventh PMOS transistor is connected to the gate of the fifth PMOS transistor. The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor. The drain of the seventh PMOS transistor is connected to one end of the sixth resistor and the gate of the tenth PMOS transistor. The drain of the eighth PMOS transistor is connected to one end of the eighth resistor and the gate of the ninth PMOS transistor. The other end of the sixth resistor is connected to the other end of the fifth resistor and one end of the seventh resistor. The other end of the eighth resistor is connected to the other end of the fourth resistor and one end of the ninth resistor. The other end of the seventh resistor, the source of the fourth NMOS transistor, the other end of the ninth resistor, the source of the sixth NMOS transistor, the source of the seventh NMOS transistor, and the source of the fifth NMOS transistor are all connected to the source of the ninth PMOS transistor. The negative power rail is connected to the high power rail. The gates of the fourth and fifth NMOS transistors are both input with a delayed detection signal indicating the gate logic potential of the high-power transistor. The gates of the fourth, fifth, and sixth PMOS transistors are all input with bias voltage signals. The sources of the fourth, fifth, and sixth PMOS transistors, as well as the source of the third PMOS transistor, are all connected to the positive power rail of the high power rail. The drain of the sixth PMOS transistor is connected to the sources of the ninth and tenth PMOS transistors, respectively. The drain of the ninth PMOS transistor is connected to... The drain and gate of the sixth NMOS transistor are connected. The drain of the tenth PMOS transistor is connected to the drains of the seventh, third, and fifth NMOS transistors, respectively, and the input of the second inverter. The gates of the sixth and seventh NMOS transistors are connected. The output of the second inverter is connected to the gate of the third PMOS transistor, the input of the third inverter, and the input of the fourth inverter. The output of the third inverter is the control signal output of the PWM comparator circuit, and the output of the fourth inverter is the feedback signal output of the PWM comparator circuit.