Signal delay function circuit and vehicle
By designing a signal delay function circuit, and utilizing a combination of switch input, voltage clamping, and delay circuit, the delay processing of rising and falling edge signals was achieved, solving the problem of diverse requirements for different main control chips and reducing circuit costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING CHJ AUTOMOTIVE TECH CO LTD
- Filing Date
- 2022-06-22
- Publication Date
- 2026-08-04
AI Technical Summary
In the prior art, due to the different main control chips, electronic control units have diverse requirements for rise delay and fall delay, which ordinary delay circuits cannot meet, and configuring multiple delay circuits increases costs.
A signal delay function circuit was designed, including a switch input circuit, a voltage clamping circuit, a delay circuit, and a switch output circuit. By combining different control signals and power supply signals, the circuit can delay the rising and falling edge input signals. MOSFETs and BJTs are used to achieve level polarity switching and signal isolation.
By using a set of interfaces to meet the delay requirements of the rising and falling edges of the input signal, the application range of delay circuits is expanded and the circuit layout cost is reduced.
Smart Images
Figure CN117318678B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and in particular to a signal delay function circuit and a vehicle. Background Technology
[0002] In existing technologies, electronic control units (ECUs) need to delay input signals before inputting them to subsequent modules to avoid false triggering by transient interference signals. With the continuous development of technology, the delay processing requirements for input signals in various ECUs are becoming increasingly diverse. Because different ECUs use different main control chips, their requirements for rise and fall delays vary. In such cases, ordinary delay circuits cannot meet the requirements. To meet the delay requirements of input signals, existing technologies typically configure multiple different delay circuits for different rise and fall delays, and even multiple input / output interfaces, further increasing costs. Summary of the Invention
[0003] In view of this, the purpose of this application is to provide a signal delay function circuit and a vehicle.
[0004] To achieve the above objectives, this application provides a signal delay function circuit, including a switch input circuit, a voltage clamping circuit, a delay circuit, and a switch output circuit, wherein: the switch input circuit is used to receive an input signal and output a control signal to the voltage clamping circuit; the voltage clamping circuit is used to receive an initial power signal and the control signal and output a power signal to the delay circuit; the delay circuit is used to receive the power signal and output a delayed signal to the switch output circuit; the switch output circuit is used to receive the delayed signal and the initial power signal and output an output signal; wherein the input signal includes a rising edge input signal and a falling edge input signal, and the delay signal includes a first delay signal and a second delay signal; in response to the input signal received by the switch input circuit being a rising edge input signal, the delay circuit outputs the first delay signal; in response to the input signal received by the switch input circuit being a falling edge input signal, the delay circuit outputs the second delay signal.
[0005] Optionally, the first delayed signal is delayed for a longer period than the second delayed signal.
[0006] Optionally, the switch input circuit includes a first switch; the control terminal of the first switch is used to receive the input signal, the first terminal of the first switch is grounded, and the second terminal of the first switch is used to output the control signal.
[0007] Optionally, the voltage clamping circuit includes a second switch, a third switch, and a fourth switch; the first terminal of the fourth switch is grounded, the second terminal of the second switch, the control terminal of the third switch, and the control terminal of the fourth switch are electrically connected and are all used to receive the control signal; the first terminal of the second switch and the first terminal of the third switch are both used to receive the initial power signal, and the control terminal of the second switch is electrically connected to the first terminal of the third switch; the second terminal of the third switch and the second terminal of the fourth switch are electrically connected and are both used to output the power signal.
[0008] Optionally, the voltage clamping circuit further includes a clamping resistor; one end of the clamping resistor is used to receive the initial power signal, and the other end is electrically connected to the control terminal of the second switch and the first terminal of the third switch.
[0009] Optionally, the delay circuit includes at least one delay capacitor; one end of the delay capacitor is used to receive the power signal and output the delay signal, and the other end is grounded.
[0010] Optionally, the switch output circuit includes a fifth switch and a sixth switch; the control terminal of the fifth switch is used to receive the delay signal, the first terminal of the fifth switch is grounded, the second terminal of the fifth switch is electrically connected to the control terminal of the sixth switch, the first terminal of the sixth switch is used to receive the initial power signal, and the second terminal of the sixth switch is used to output the output signal.
[0011] Optionally, the switch output circuit further includes a first high-frequency filter capacitor and a pull-down resistor connected in parallel; the first end of the first high-frequency filter capacitor and the first end of the pull-down resistor are both electrically connected to the second end of the sixth switch, and the second end of the first high-frequency filter capacitor and the second end of the pull-down resistor are both grounded.
[0012] Optionally, it also includes an input protection circuit; the input protection circuit includes a voltage divider resistor, a second high-frequency filter capacitor, and a clamping diode connected in parallel. The first end of the voltage divider resistor, the first end of the second high-frequency filter capacitor, and the cathode of the clamping diode are all used to receive and output the input signal to the switch input circuit. The second end of the voltage divider resistor, the second end of the second high-frequency filter capacitor, and the anode of the clamping diode are all grounded.
[0013] Based on the same inventive concept, this application also provides a vehicle, which includes the signal delay function circuit described in any one of the claims.
[0014] As can be seen from the above description, the signal delay function circuit provided in this application includes a switch input circuit, a voltage clamping circuit, a delay circuit, and a switch output circuit. The switch input circuit receives an input signal and outputs a control signal to the voltage clamping circuit. The voltage clamping circuit receives an initial power signal and the control signal and outputs a power signal to the delay circuit. The delay circuit receives the power signal and outputs a delayed signal to the switch output circuit. The switch output circuit receives the delayed signal and the initial power signal and outputs an output signal. The input signal includes a rising edge input signal and a falling edge input signal, and the delay signal includes a first delay signal and a second delay signal. In response to the input signal received by the switch input circuit being a rising edge input signal, the delay circuit outputs the first delayed signal. In response to the input signal received by the switch input circuit being a falling edge input signal, the delay circuit outputs the second delayed signal. Applying the signal delay function circuit provided in this application can meet the delay requirements of the rising and falling edges of the input signal, expanding the application range of the delay circuit. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a circuit diagram of the signal delay function circuit in an embodiment of this application;
[0017] Figure 2 This is a timing diagram of the V(IN) circuit of the signal delay function circuit in an embodiment of this application;
[0018] Figure 3 This is a timing diagram of the V(M1:G) circuit of the signal delay function circuit in an embodiment of this application;
[0019] Figure 4 This is a timing diagram of the V(Q4:B) circuit of the signal delay function circuit in an embodiment of this application;
[0020] Figure 5 This is a timing diagram of the V(OUT) circuit of the signal delay function circuit in an embodiment of this application. Detailed Implementation
[0021] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0022] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0023] To facilitate understanding, the terms appearing in the embodiments of this application will be explained first:
[0024] MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor, which can be divided into two types: "N-type (enhancement-mode)" and "P-type (depletion-mode)," commonly referred to as N-MOSFET and P-MOSFET.
[0025] BJT: Bipolar Junction Transistor, which has two combinations of structures: PNP and NPN.
[0026] In view of this, one embodiment of this application provides a signal delay function circuit, such as... Figure 1 As shown, it includes a switch input circuit 10, a voltage clamping circuit 20, a delay circuit 30, and a switch output circuit 40, wherein:
[0027] The switch input circuit 10 is used to receive the input signal V(IN) and output a control signal to the voltage clamping circuit 20. The input signal V(IN) is the signal that needs to be delayed. In this embodiment, for example... Figure 1 As shown, V(IN) is simulated using V2. In one specific embodiment, the input signal includes a rising edge input signal (a signal that transitions from low to high level) and a falling edge input signal (a signal that transitions from high to low level). The switch input circuit 10 receives the input signal and, in response to the input of the rising edge input signal or the falling edge input signal, outputs control signals of different states to the voltage clamping circuit 20, respectively. Specifically, in response to the input signal being a rising edge input signal, a first control signal is output; in response to the input signal being a falling edge input signal, a second control signal is output.
[0028] The voltage clamping circuit 20 is used to receive the initial power signal and the control signal, and output the power signal to the delay circuit 30. In this embodiment, as... Figure 1As shown, the initial power signal is simulated using V1, outputting a 3.3V voltage. In actual implementation, the initial power signal is provided by a power supply chip. The model of the power supply chip can be selected from DC-DC chips from manufacturers such as TI, Maxim, and MPS, depending on the system requirements of the electronic control unit. In a specific embodiment, the voltage clamping circuit 20 receives the initial power signal and a control signal. In response to the state of the control signal, it outputs power signals of different states to the delay circuit 30. Specifically, in response to receiving a first control signal, it outputs a first power signal; in response to receiving a second control signal, it outputs a second power signal.
[0029] The delay circuit 30 is used to receive the power signal and output a delay signal to the switch output circuit 40. The delay signal includes a first delay signal and a second delay signal. In one specific embodiment, the delay circuit 30 receives the power signal and, in response to the state of the power signal, outputs a delay signal corresponding to different states to the switch output circuit 40. Specifically, in response to receiving a first power signal, it outputs a first delay signal; in response to receiving a second power signal, it outputs a second delay signal.
[0030] The switch output circuit 40 is used to receive the delayed signal and the initial power signal, and output an output signal. The switch output circuit 40 receives the delayed signal and, in response to the state of the delayed signal, outputs output signals of different states. Specifically, in response to receiving the first delayed signal after the delay, the switch output circuit 40 outputs a rising edge output signal; in response to receiving the second delayed signal, the switch output circuit 40 outputs a falling edge output signal.
[0031] By applying the signal delay function circuit provided in this application, the delay requirements of the rising and falling edges of the input signal can be met through a set of input and output interfaces, which expands the application range of the delay circuit and reduces the circuit layout cost.
[0032] In some embodiments, the first delayed signal is delayed for a longer period than the second delayed signal. In one specific embodiment, the second delayed signal is shorter and the first delayed signal is longer; in a more specific embodiment, the first delayed signal is a delayed signal, and the second delayed signal is an undelayed signal, therefore the first delayed signal is delayed for a longer period than the second delayed signal. Because the first delayed signal is delayed for a longer period than the second delayed signal, the rising edge output signal is delayed for a longer period than the falling edge output signal compared to the input signal.
[0033] By applying the embodiments provided above in this application, it is possible to realize the circuit function where the rising edge delay time of the input signal and the output signal is longer than the falling edge delay time, which meets the application requirements where the rising edge and falling edge delay times of the input signal and the output signal are different, further expanding the application range of the delay circuit and reducing the circuit layout cost.
[0034] In some embodiments, such as Figure 1 As shown, the switch input circuit 10 includes a first switch (M2 in the figure); the control terminal (gate / G pole) of the first switch is used to receive the input signal, the first terminal (source / S pole) of the first switch is grounded, and the second terminal (drain / D pole) of the first switch is used to output the control signal.
[0035] In a specific implementation, the first switch is an N-MOSFET, and the model can be 2N7002E. In one specific embodiment, as shown... Figure 1 As shown, when the input signal V(IN) is a rising edge input signal, that is, when it changes from a low level to a high level of 12V, since the S terminal is grounded, V(M2:G) = 8V for M2. Due to the fast response characteristics of the MOSFET, when the level of V(M2:G) is greater than VGS(th) = 4.5V, M2 quickly turns on, that is, it outputs the first control signal to the voltage clamping circuit 20. Similarly, when the input signal V(IN) is a falling edge input signal, that is, when it changes from a high level to a low level, M2 quickly turns off, that is, it outputs the second control signal to the voltage clamping circuit 20.
[0036] In some embodiments, such as Figure 1 As shown, the voltage clamping circuit 20 includes a second switch (Q1), a third switch (Q3), and a fourth switch (M1). The first terminal (source / S) of the fourth switch is grounded. The second terminal (collector / C) of the second switch, the control terminal (base / B) of the third switch, and the control terminal (gate / G) of the fourth switch are electrically connected and are all used to receive the control signal. The first terminal (emitter / E) of the second switch and the first terminal (emitter / E) of the third switch are both used to receive the initial power signal, and the control terminal (base / B) of the second switch is electrically connected to the first terminal of the third switch. The second terminal (collector / C) of the third switch and the second terminal (drain / D) of the fourth switch are electrically connected and are both used to output the power signal. In a specific implementation, the voltage clamping circuit 20 also includes a voltage divider resistor R5. The resistance value of R5 can be adjusted according to actual needs; the 100kΩ shown in the figure is only a reference value.
[0037] In a specific implementation, both the second and third switches are PNP BJTs, such as the BC856BW, and the fourth switch is an N-MOSFET, such as the 2N7002E. In one specific embodiment, as... Figure 1 As shown, when M2 is quickly turned on, that is, when the first control signal is output to the voltage clamping circuit 20, the voltage V (M1:G) is low, M1 is quickly turned off, and at the same time, V (Q3:B) is pulled down through R5 and M2, Q3 is turned on, that is, the first power signal is output to the delay circuit 30 using the initial power signal; similarly, when M2 is quickly turned off, that is, when the second control signal is output to the voltage clamping circuit 20, Q3 is turned off, and at the same time, M1 is quickly turned on, that is, the second power signal is output to the delay circuit 30.
[0038] The circuit in the above embodiment can achieve a double reversal of the voltage level by cascading two NMOS transistors, namely the first switch and the fourth switch, namely M1 and M2, and at the same time achieve isolation between the input signal V(IN) and the 3.3V initial power supply signal, thereby improving the system reliability.
[0039] In some embodiments, such as Figure 1 As shown, the voltage clamping circuit 20 also includes a clamping resistor R1;
[0040] One end of the clamping resistor R1 is used to receive the initial power signal, and the other end is electrically connected to the control terminal of the second switch (Q1) and the first terminal of the third switch (Q3). In a specific embodiment, R1 = 78.7kΩ. By adjusting the resistance value of R1, the current flowing through R1 can be changed. In specific implementation, the resistance value of R1 can be adjusted according to actual needs.
[0041] In one specific embodiment, such as Figure 1 As shown, according to the chip datasheet, the V(BE) of BC856BW is -0.65V. Therefore, Q1 can clamp the voltage across R1 at 0.65V, while V(Q3:E) is clamped at 3.3V-0.65V=2.65V, remaining unchanged, thus ensuring that Q3 outputs a stable power signal when it is turned on.
[0042] In one specific embodiment, such as Figure 1 As shown, the voltage clamping circuit 20 also includes a filter capacitor C1, which is used to filter the initial power supply signal.
[0043] In some embodiments, the delay circuit 30 includes at least one delay capacitor; one end of the delay capacitor is used to receive the power signal and output the delay signal, and the other end is grounded.
[0044] like Figure 1As shown, C3 and C4 are the delay capacitors, and the delay circuit 30, composed of these capacitors, is used to configure the required rise edge delay time. In a specific embodiment, when Q3 is on and M1 is off, the delay circuit 30 receives the first power signal and uses it to start charging C3 and C4. Once C3 and C4 are fully charged, the first delayed signal is output to the switch output circuit 40 to achieve the purpose of delaying the signal. Similarly, when Q3 is off and M1 is quickly turned on, the delay circuit 30 receives the second power signal, and C3 and C4 discharge quickly through M1, i.e., the second delayed signal is output to the switch output circuit 40. In a specific embodiment, C3 = 0.22uF and C4 = 0.01uF. In actual implementation, the capacitance values of the delay capacitors can be adjusted according to actual needs. Decreasing the capacitance values of C3 and C4 can reduce the signal delay time, and vice versa. In another specific embodiment, the same technical effect as multiple delay capacitors connected in parallel can be achieved by adjusting the capacitance of one delay capacitor.
[0045] In some embodiments, such as Figure 1 As shown, the switch output circuit 40 includes a fifth switch (Q4 in the figure) and a sixth switch (Q2 in the figure); the control terminal (base / B-terminal) of the fifth switch is used to receive the delay signal, the first terminal (emitter / E-terminal) of the fifth switch is grounded, the second terminal (collector / C-terminal) of the fifth switch is electrically connected to the control terminal (base / B-terminal) of the sixth switch, the first terminal (emitter / E-terminal) of the sixth switch is used to receive the initial power signal, and the second terminal (collector / C-terminal) of the sixth switch is used to output the output signal.
[0046] In one specific embodiment, the fifth switch is an NPN BJT, specifically the BC847BW model; the sixth switch is a PNP transistor, specifically the BC856BW model. In another specific embodiment, such as... Figure 1 As shown, when C3 and C4 are fully charged, they output the first delay signal to the switch output circuit 40, and V(Q4:B) begins to rise slowly. When V(Q4:B) rises to the threshold voltage VBE=0.66V for Q4 to turn on, Q4 turns on, V(Q2:B) is at a low level, Q2 turns on, and uses the initial power signal to output the rising edge output signal V(OUT). This completes the process of outputting the rising edge output signal after a delay when the input signal V(IN) is a rising edge input signal. Similarly, when C3 and C4 discharge quickly through M1, that is, when the second delay signal is output to the switch output circuit 40, Q4 turns off quickly, and then Q2 turns off quickly and outputs the falling edge output signal V(OUT). This completes the process of quickly outputting the falling edge output signal when the input signal V(IN) is a falling edge input signal.
[0047] The aforementioned first and fourth switches, cascaded together, can achieve a double flip of the voltage level polarity, and can also control the voltage level of V(Q4:B) and the voltage level of the input signal V(IN) to be of the same polarity.
[0048] Figures 2 to 5 This is a circuit function simulation timing diagram provided in an embodiment of this application. Figures 2 to 5 They simulated in turn Figure 1 The voltage timing diagram for the four nodes V(IN), V(M1:G), V(Q4:B), and V(OUT) is shown. As can be seen from the diagram, when V(IN) transitions from low to high, it takes approximately 36ms for V(OUT) to transition from low to high, meaning the time interval between the rising edges of V(IN) and V(OUT) is 36ms. Conversely, when V(IN) transitions from high to low, it takes approximately 5ms for V(OUT) to transition from high to low, meaning the time interval between the falling edges of V(IN) and V(OUT) is 5ms. This simulation verifies the circuit function of the signal delay circuit provided in this application, where the rising edge delay time of the input signal is longer than the falling edge delay time.
[0049] In some embodiments, such as Figure 1 As shown, the switch output circuit 40 further includes a first high-frequency filter capacitor C2 and a pull-down resistor R6 connected in parallel; the first terminal of the first high-frequency filter capacitor C2 and the first terminal of the pull-down resistor R6 are both electrically connected to the second terminal of the sixth switch Q2, and the second terminals of the first high-frequency filter capacitor C2 and the pull-down resistor R6 are both grounded. In a specific embodiment, C2 = 1.8nF and R6 = 22kΩ. In specific implementation, the capacitance value of the first high-frequency filter capacitor C2 and the resistance value of the pull-down resistor R6 can be adjusted according to actual needs.
[0050] In one specific embodiment, such as Figure 1 As shown, the switch output circuit 40 also includes voltage divider resistors R2, R3, and R4 for current limiting. In one specific embodiment, R2 = 47kΩ, R3 = 4.7kΩ, and R4 = 1kΩ. In actual implementation, the resistance values of voltage divider resistors R2, R3, and R4 can be adjusted according to actual needs.
[0051] In some embodiments, such as Figure 1As shown, the signal delay function circuit also includes an input protection circuit 50. The input protection circuit 50 includes a voltage divider resistor R8, a second high-frequency filter capacitor C5, and a clamping diode D1 connected in parallel. The first terminal of the voltage divider resistor R8, the first terminal of the second high-frequency filter capacitor C5, and the cathode of the clamping diode D1 are all used to receive and output the input signal to the switch input circuit. The second terminal of the voltage divider resistor R8, the second terminal of the second high-frequency filter capacitor C5, and the anode of the clamping diode D1 are all grounded. The input protection circuit 50 can perform voltage division, filtering, and clamping of the input signal, protecting the subsequent circuits from damage.
[0052] like Figure 1 As shown, the input protection circuit 50 also includes a voltage divider resistor R7. One end of the voltage divider resistor R7 is used to receive the input signal, and the other end is used to input the input signal to the parallel-connected voltage divider resistor R8, the second high-frequency filter capacitor C5, and the clamping diode D1. R8 can independently divide the input signal V(IN), and R7 and R8 can also jointly divide the input signal V(IN). The values can be set according to actual needs. In a specific embodiment, R7=3.4kΩ and R8=6.8kΩ. In specific implementation, the resistance values of the voltage divider resistors R7 and R8 can be adjusted according to the range of the input signal V(IN). For example, when the range of the input signal V(IN) is 9V~18V, after voltage division by R7=3.4kΩ and R8=6.8kΩ, it is 6V~12V, which satisfies the condition for the subsequent stage M2 to conduct.
[0053] The second high-frequency filter capacitor C5 performs high-frequency interference filtering. In one specific embodiment, C5 = 1.8nF. In actual implementation, the capacitance value of C5 can be adjusted according to actual needs.
[0054] When an overvoltage abnormality occurs in the input signal V(IN), the clamping diode D1 can clamp the VGS of M2 to within 18V, ensuring that M2 will not be damaged due to excessively high V(GS). In specific implementation, the clamping diode D1 can be a BZX84C18.
[0055] Based on the same inventive concept, corresponding to any of the above embodiments, this application also provides a vehicle, which includes the aforementioned signal delay function circuit. The vehicle of the embodiment is used to implement the corresponding signal delay function circuit in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be elaborated further here.
[0056] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0057] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.
[0058] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.
[0059] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.
[0060] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.
Claims
1. A signal delay function circuit, characterized in that, It includes a switch input circuit, a voltage clamping circuit, a delay circuit, and a switch output circuit, wherein: The switch input circuit is used to receive input signals and output control signals to the voltage clamping circuit; The voltage clamping circuit is used to receive the initial power signal and the control signal, and output the power signal to the delay circuit; The delay circuit is used to receive the power signal and output a delay signal to the switch output circuit; The switch output circuit is used to receive the delay signal and the initial power signal, and output an output signal; The input signal includes a rising edge input signal and a falling edge input signal, and the delay signal includes a first delay signal and a second delay signal; In response to the input signal received by the switch input circuit being a rising edge input signal, the delay circuit outputs a first delayed signal; in response to the input signal received by the switch input circuit being a falling edge input signal, the delay circuit outputs a second delayed signal. The delay times of the first delayed signal and the second delayed signal are different.
2. The signal delay function circuit according to claim 1, characterized in that, The first delayed signal has a longer delay time than the second delayed signal.
3. The signal delay function circuit according to claim 1, characterized in that, The switch input circuit includes a first switch; The control terminal of the first switch is used to receive the input signal, the first terminal of the first switch is grounded, and the second terminal of the first switch is used to output the control signal.
4. The signal delay function circuit according to claim 1, characterized in that, The voltage clamping circuit includes a second switch, a third switch, and a fourth switch; The first terminal of the fourth switch is grounded, and the second terminal of the second switch, the control terminal of the third switch, and the control terminal of the fourth switch are electrically connected and are all used to receive the control signal. Both the first terminal of the second switch and the first terminal of the third switch are used to receive the initial power signal, and the control terminal of the second switch is electrically connected to the first terminal of the third switch. The second terminal of the third switch is electrically connected to the second terminal of the fourth switch, and both are used to output the power signal.
5. The signal delay function circuit according to claim 4, characterized in that, The voltage clamping circuit also includes a clamping resistor; One end of the clamping resistor is used to receive the initial power signal, and the other end is electrically connected to the control terminal of the second switch and the first terminal of the third switch.
6. The signal delay function circuit according to claim 1, characterized in that, The delay circuit includes at least one delay capacitor; One end of the delay capacitor is used to receive the power signal and output the delay signal, and the other end is grounded.
7. The signal delay function circuit according to claim 1, characterized in that, The switch output circuit includes a fifth switch and a sixth switch; The control terminal of the fifth switch is used to receive the delay signal. The first terminal of the fifth switch is grounded. The second terminal of the fifth switch is electrically connected to the control terminal of the sixth switch. The first terminal of the sixth switch is used to receive the initial power signal. The second terminal of the sixth switch is used to output the output signal.
8. The signal delay function circuit according to claim 7, characterized in that, The switch output circuit also includes a first high-frequency filter capacitor and a pull-down resistor connected in parallel. The first terminal of the first high-frequency filter capacitor and the first terminal of the pull-down resistor are both electrically connected to the second terminal of the sixth switch, and the second terminal of the first high-frequency filter capacitor and the second terminal of the pull-down resistor are both grounded.
9. The signal delay function circuit according to claim 1, characterized in that, It also includes input protection circuitry; The input protection circuit includes a voltage divider resistor, a second high-frequency filter capacitor, and a clamping diode connected in parallel. The first end of the voltage divider resistor, the first end of the second high-frequency filter capacitor, and the cathode of the clamping diode are all used to receive and output the input signal to the switch input circuit. The second end of the voltage divider resistor, the second end of the second high-frequency filter capacitor, and the anode of the clamping diode are all grounded.
10. A vehicle, characterized in that, The vehicle includes the signal delay function circuit according to any one of claims 1-9.