Duty cycle correction circuit and method of operating duty cycle correction circuit

Abstract

This disclosure relates to a duty cycle correction circuit and a method for operating the duty cycle correction circuit. The duty cycle correction circuit includes a duty cycle correction circuit, an information generation circuit, and a duty cycle control circuit. The duty cycle correction circuit corrects the duty cycle of an input clock signal based on a duty cycle control code to generate an output clock signal. The information generation circuit compares an operating power supply voltage based on an operating mode to generate voltage information. The duty cycle control circuit receives the voltage information from the information generation circuit and generates the duty cycle control code including the voltage information based on the duty cycle of the output clock signal.

Description

Technical Field

[0001] Various embodiments generally relate to a semiconductor integrated circuit device and a method of operating the semiconductor integrated circuit device, and more specifically, to a duty cycle correction circuit of the semiconductor integrated circuit device and a method of operating the duty cycle correction circuit. Background Technology

[0002] Typically, semiconductor devices such as double data rate (DDR) DRAM can receive and output data based on the rising and falling edges of a clock signal. When the duty cycle of the clock signal may be significantly greater than approximately 50:50, the semiconductor device may not be able to receive and output data based on the clock signal. Therefore, the semiconductor device may include a duty cycle correction circuit configured to correct the duty cycle of the clock signal to 50:50.

[0003] The duty cycle correction circuit can control the duty cycle of the clock signal to 50:50 through the duty training operation mode. The controlled clock signal can maintain the duty cycle normally. However, for various reasons, the duty cycle correction circuit may not be able to generate a clock signal with the desired duty cycle.

[0004] Specifically, the duty cycle correction circuit can control the duty cycle of the clock signal to 50:50 through a duty cycle training operation mode. Then, the semiconductor device can perform normal operation modes such as read operations and write operations based on the clock signal. In this operation, the duty cycle of the clock signal can be maintained at 50:50. However, because the operating power supply voltage may be used in normal operation mode, the operating power supply voltage in the duty cycle training operation mode may differ from that in normal operation mode. Therefore, although the duty cycle of the clock signal can be controlled to 50:50 through the duty cycle training operation mode, the duty cycle of the clock signal in normal operation mode may still change. As a result, the semiconductor device may malfunction, causing the desired operation in normal operation mode to fail to be performed effectively due to a clock signal with a changed duty cycle. Summary of the Invention

[0005] According to an example implementation, a duty cycle correction circuit can be provided. The duty cycle correction circuit may include a duty cycle correction circuit, an information generation circuit, and a duty cycle control circuit. The duty cycle correction circuit can correct the duty cycle of an input clock signal based on a duty cycle control code to generate an output clock signal. The information generation circuit can compare the operating power supply voltage based on the operating mode to generate voltage information. The duty cycle control circuit can receive the voltage information from the information generation circuit and can generate the duty cycle control code including the voltage information based on the duty cycle of the output clock signal.

[0006] According to an example implementation, a duty cycle correction circuit can be provided. The duty cycle correction circuit may include a duty cycle correction circuit and a duty cycle control circuit. The duty cycle correction circuit can correct the duty cycle of an input clock signal based on a duty cycle control code to generate an output clock signal. The duty cycle control circuit can generate the duty cycle control code based on the duty cycle of the output clock signal, the duty cycle control code including the difference between the operating power supply voltages based on the operating mode.

[0007] According to an example embodiment, a method for operating a duty cycle correction circuit can be provided. In the method of operating the duty cycle correction circuit, a duty cycle training operation can be performed for an input clock signal. The operating power supply voltage in the duty cycle training operation can be compared with an operating power supply voltage in at least one normal operation. A duty cycle correction operation can be performed based on the comparison result to generate an output clock signal with a corrected duty cycle for the input clock signal. Attached Figure Description

[0008] The above and other aspects, features, and advantages of the subject matter of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating a duty cycle correction circuit according to an example embodiment;

[0010] Figure 2 It is shown Figure 1 A block diagram of the information generation circuit in the image;

[0011] Figure 3 This is a block diagram illustrating a duty cycle correction circuit according to an example embodiment;

[0012] Figure 4 It is shown Figure 3 A block diagram of the duty cycle control circuit in the circuit.

[0013] Figure 5 It is shown Figure 3 A block diagram of the duty cycle control circuit in the circuit.

[0014] Figure 6 This is a block diagram illustrating a duty cycle correction circuit according to an example embodiment;

[0015] Figure 7 It is shown Figure 6 A block diagram of the duty cycle control circuit in the diagram; and

[0016] Figure 8 This is a view illustrating a method of operating duty cycle correction circuit according to an example embodiment. Detailed Implementation

[0017] Various embodiments of the invention will be described in more detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). Thus, variations in the illustrated configurations and shapes are expected due to factors such as manufacturing techniques and / or tolerances. Therefore, the described embodiments should not be construed as limited to the specific configurations and shapes shown herein, but may include deviations in configuration and shape without departing from the spirit and scope of the invention as defined in the appended claims.

[0018] The invention is described herein with reference to cross-sectional and / or planar diagrams of idealized embodiments. However, these embodiments should not be construed as limiting the inventive concept. While several embodiments of the invention will be shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the invention.

[0019] Figure 1 This is a block diagram illustrating a duty cycle correction circuit according to an example embodiment.

[0020] Reference Figure 1 The duty cycle correction circuit 100 can correct the duty cycle of the input clock signal CLK_IN to generate the output clock signal CLK_OUT. Specifically, the duty cycle correction circuit 100 may include a duty correction circuit 110, an information generation circuit 120, and a duty control circuit 130.

[0021] The duty cycle correction circuit 110 can correct the duty cycle of the input clock signal CLK_IN based on the duty cycle control code CD_CTR to generate the output clock signal CLK_OUT. The duty cycle correction circuit 110 can control the driving force corresponding to the rising and falling edges of the input clock signal CLK_IN based on the duty cycle control code CD_CTR. Therefore, the duty cycle correction circuit 110 can generate an output clock signal CLK_OUT with a duty cycle of approximately 50:50 based on the duty cycle control code CD_CTR.

[0022] The information generation circuit 120 can compare the difference between operating power supply voltages V_INN based on the operating mode to generate voltage information INF_V. The information generation circuit 120 can receive a mode selection signal MD_SEL corresponding to the operating mode.

[0023] The operating modes may include a duty-free training operating mode and at least one normal operating mode. The duty-free training operating mode may include operations for setting the duty cycle of the output clock signal CLK_OUT corresponding to the input clock signal CLK_IN before entering normal operating mode. Normal operating modes may include high-power operation and low-power operation. High-power operation may consume a relatively high amount of operating power supply voltage V_INN. High-power operation may include read and write operations. Low-power operation may consume a relatively low amount of operating power supply voltage V_INN. Low-power operation may include standby operation and power-off operation.

[0024] The operating supply voltage V_INN during high-power operation can become lower than the operating supply voltage V_INN in the duty-free training mode. The operating supply voltage during low-power operation can become higher than the operating supply voltage V_INN in the duty-free training mode. Therefore, the voltage information INF_V may include information corresponding to the difference between the operating supply voltage V_INN applied in the duty-free training mode and the operating supply voltage V_INN applied in at least one normal operating mode.

[0025] The duty cycle control circuit 130 can generate the duty cycle control code CD_CTR based on the duty cycle of the output clock signal CLK_OUT. The duty cycle control circuit 130 can receive the voltage information INF_V output from the information generation circuit 120, and can output the duty cycle control code CD_CTR including the voltage information INF_V.

[0026] According to an example implementation, the duty cycle correction circuit 100 may include a voltage difference generated in the operating power supply voltage V_INN based on the operating mode in the duty cycle control code CD_CTR to perform a duty cycle correction operation. Therefore, in at least one normal operating mode, the duty cycle correction circuit 100 can control the duty cycle control code CD_CTR, which can be set in the duty cycle training operating mode, at a minimum to perform the duty cycle correction operation. As a result, the duty cycle correction circuit 100 can quickly and accurately generate an output clock signal CLK_OUT with the desired duty cycle in at least one normal operating mode.

[0027] Figure 2 It is shown Figure 1 A block diagram of the information generation circuit in the image.

[0028] Reference Figure 2The information generation circuit 120 may include a first charging circuit 210, a second charging circuit 220, and a voltage comparison circuit 230.

[0029] The first charging circuit 210 can store the operating power supply voltage V_INN as a first storage voltage V1 through a charging operation in a duty-load training operation mode. The first charging circuit 210 can be activated in the duty-load training operation mode based on the mode selection signal MD_SEL. The first charging circuit 210 may include a capacitor configured to store the operating power supply voltage V_INN in the duty-load training operation mode. Therefore, the capacitor in the first charging circuit 210 can store the operating power supply voltage V_INN in the duty-load training operation mode. The first charging circuit 210 can output the stored voltage as the first storage voltage V1. For example, the capacitor can be charged during the high period of the operating power supply voltage V_INN. Here, the first storage voltage V1 is a voltage corresponding to the amount of charge on the capacitor.

[0030] The second charging circuit 220 can store the operating power supply voltage V_INN as a second storage voltage V2 through charging operations in at least one normal operating mode. The second charging circuit 220 can be activated in at least one normal operating mode based on the mode selection signal MD_SEL. The second charging circuit 220 may include a capacitor similar to the first charging circuit 210. Therefore, the capacitor in the second charging circuit 220 can store the operating power supply voltage V_INN in at least one normal operating mode. The second charging circuit 220 can output the stored voltage as the second storage voltage V2.

[0031] The voltage comparison circuit 230 can compare the first storage voltage V1 with the second storage voltage V2 to generate voltage information INF_V. The voltage comparison circuit 230 can also compare the first storage voltage V1 output from the first charging circuit 210 with the second storage voltage V2 output from the second charging circuit 220 to generate voltage information INF_V corresponding to the voltage difference.

[0032] The first storage voltage V1 can correspond to the operating power supply voltage V_INN in the duty-load training mode. The second storage voltage V2 can correspond to at least one operating power supply voltage V_INN in the normal operating mode. Therefore, the voltage comparison circuit 230 can compare the operating power supply voltage V_INN in the duty-load training mode with the operating power supply voltage V_INN in at least one normal operating mode.

[0033] The voltage information INF_V generated from the voltage comparison circuit 230 may include information obtained by comparing the operating power supply voltage V_INN in the duty cycle training mode with at least one operating power supply voltage V_INN in the normal operating mode. The voltage information INF_V can then be provided to... Figure 1 The duty cycle control circuit 130 in the middle.

[0034] In the following text, the operation of the duty cycle correction circuit 100 according to the example embodiment can be referred to Figure 1 and Figure 2 To explain.

[0035] The duty cycle correction circuit 100 can receive the input clock signal CLK_IN in the duty cycle training operation mode. The duty cycle of the input clock signal CLK_IN may not be approximately 50:50. Therefore, the duty cycle control circuit 130 can generate the duty cycle control code CD_CTR based on the duty cycle of the output clock signal CLK_OUT. The duty cycle correction circuit 110 can correct the duty cycle of the input clock signal CLK_IN based on the duty cycle control code CD_CTR. As a result, in the duty cycle training operation mode, the duty cycle correction circuit 110 can generate an output clock signal CLK_OUT with a duty cycle of approximately 50:50. The first charging circuit 210 can store the operating power supply voltage V_INN as a first storage voltage V1 in the duty cycle training operation mode.

[0036] The second charging circuit 220 can store the operating power supply voltage V_INN as a second stored voltage V2 in at least one normal operating mode. The voltage comparison circuit 230 can compare the first stored voltage V1 stored in the duty cycle training operating mode with the second stored voltage V2 stored in at least one normal operating mode to generate voltage information INF_V. The duty cycle control circuit 130 can include the voltage information INF_V in the duty cycle control code CD_CTR to generate the duty cycle control code CD_CTR. The duty cycle correction circuit 110 can recalibrate the duty cycle of the input clock signal CLK_IN based on the duty cycle control code CD_CTR. As a result, in at least one normal operating mode, the duty cycle correction circuit 110 can generate an output clock signal CLK_OUT with a duty cycle of approximately 50:50.

[0037] Therefore, the duty cycle correction circuit 100 can include the difference between the operating power supply voltage V_INN in the duty cycle training mode and the operating power supply voltage V_INN in at least one normal operating mode in the duty cycle control code CD_CTR to perform the duty cycle correction operation quickly and accurately.

[0038] In an example implementation, the information generation circuit 120 may include a plurality of second charging circuits 220, each corresponding to a plurality of normal operating modes. A mode selection signal MD_SEL may be selectively activated based on each normal operating mode. Therefore, although not shown in the figures, each second charging circuit 220 may store a storage voltage corresponding to each normal operating mode.

[0039] In this configuration, the voltage comparison circuit 230 can compare the stored voltages corresponding to the duty cycle training mode and the normal operation mode. Therefore, the duty cycle correction circuit 100 can perform a duty cycle correction operation corresponding to each normal operation mode based on the second stored voltage V2 corresponding to each normal operation mode. Furthermore, the duty cycle correction circuit 100 can perform duty cycle correction operations corresponding to other normal operation modes based on the stored voltage corresponding to at least one of the normal operation modes.

[0040] The duty cycle control circuit 130 can generate a duty cycle control code CD_CTR through a charge / discharge operation. The duty cycle control circuit 130 may include a capacitor configured to perform a charge / discharge operation. The capacitor can store a duty cycle voltage in a duty cycle training operation mode. Therefore, the capacitors of the duty cycle control circuit 130 can commonly share a capacitor corresponding to at least one of the first charging circuit 210 and the second charging circuit 220. That is, the shared capacitor can store a first storage voltage V1 corresponding to the duty cycle training operation mode or a second storage voltage V2 corresponding to at least one normal operation mode. As a result, the duty cycle correction circuit 100 of the example embodiment can have a simple structure.

[0041] The structure for publicly shared capacitors will be explained in detail below by way of example.

[0042] Figure 3 This is a block diagram illustrating a duty cycle correction circuit according to an example embodiment.

[0043] Reference Figure 3 The duty cycle correction circuit 300 may include a duty cycle correction circuit 310 and a duty cycle control circuit 320.

[0044] The duty cycle correction circuit 310 can correct the duty cycle of the input clock signal CLK_IN based on the duty cycle control code CD_CTR to generate the output clock signal CLK_OUT.

[0045] The duty cycle control circuit 320 can generate the duty cycle control code CD_CTR based on the duty cycle of the output clock signal CLK_OUT. Based on the operating mode, the duty cycle control circuit 320 can include the difference between the operating power supply voltage V_INN in the duty cycle control code CD_CTR.

[0046] According to the example implementation, based on the operating mode, the duty cycle correction circuit 300 can include the difference between the operating power supply voltage V_INN in the duty control code CD_CTR to perform a duty cycle correction operation. Therefore, in at least one normal operating mode, the duty cycle correction circuit 300 can minimally control the duty control code CD_CTR, which can be set in the duty cycle training operating mode, to perform the duty cycle correction operation. As a result, the duty cycle correction circuit 300 can quickly and accurately generate an output clock signal CLK_OUT with the desired duty cycle in at least one normal operating mode.

[0047] Figure 4 It is shown Figure 3 The block diagram of the duty cycle control circuit.

[0048] Reference Figure 4 The duty cycle control circuit 320 may include a first charging / discharging circuit 410, a second charging / discharging circuit 420, a voltage comparison circuit 430, and a code generation circuit 440.

[0049] The first charge / discharge circuit 410 can store the duty cycle of the output clock signal CLK_OUT as a first duty cycle voltage DV1 through charge / discharge operations in a duty cycle training operation mode. The first charge / discharge circuit 410 can be activated in the duty cycle training operation mode based on the mode selection signal MD_SEL. The first charge / discharge circuit 410 may include a capacitor configured to perform charge / discharge operations based on the output clock signal CLK_OUT. Therefore, the capacitor in the first charge / discharge circuit 410 can store a voltage corresponding to the duty cycle of the output clock signal CLK_OUT during a predetermined interval in the duty cycle training operation mode. The first charge / discharge circuit 410 can output the voltage stored in the capacitor as the first duty cycle voltage DV1.

[0050] The second charge / discharge circuit 420 can store the duty cycle of the output clock signal CLK_OUT as a second duty cycle voltage DV2 through charge / discharge operations in at least one normal operating mode. The second charge / discharge circuit 420 can be activated in at least one normal operating mode based on the mode selection signal MD_SEL. The second charge / discharge circuit 420 may include a capacitor similar to the first charge / discharge circuit 410. Therefore, the capacitor in the second charge / discharge circuit 420 can store a voltage corresponding to the duty cycle of the output clock signal CLK_OUT for a predetermined interval during at least one normal operating mode. The second charge / discharge circuit 420 can output the voltage stored in the capacitor as the second duty cycle voltage DV2.

[0051] The voltage comparison circuit 430 can compare the first duty cycle voltage DV1 with the second duty cycle voltage DV2. The voltage comparison circuit 430 can also compare the first duty cycle voltage DV1 output from the first charging / discharging circuit 410 with the second duty cycle voltage DV2 output from the second charging / discharging circuit 420 to generate an output signal corresponding to the voltage difference.

[0052] The first duty cycle voltage DV1 can correspond to the duty cycle of the output clock signal CLK_OUT based on the operating power supply voltage V_INN in the duty cycle training operation mode. The second duty cycle voltage DV2 can correspond to the duty cycle of the output clock signal CLK_OUT based on the operating power supply voltage V_INN in at least one normal operation mode. Therefore, the voltage comparator circuit 430 can compare the operating power supply voltage V_INN in the duty cycle training operation mode with the operating power supply voltage V_INN in at least one normal operation mode using the first duty cycle voltage DV1 and the second duty cycle voltage DV2.

[0053] The code generation circuit 440 can encode the output signal of the voltage comparison circuit 430 to generate the duty cycle control code CD_CTR. The duty cycle control code CD_CTR generated by the code generation circuit 440 can be provided to... Figure 3 The duty cycle correction circuit 310 is used in the circuit. The duty cycle correction circuit 310 can correct the duty cycle of the input clock signal CLK_IN based on the duty cycle control code CD_CTR to output the output clock signal CLK_OUT.

[0054] In the duty cycle training mode, the code generation circuit 440 can encode the first duty cycle voltage DV1 to generate the duty cycle control code CD_CTR. In at least one normal operating mode, the code generation circuit 440 can include the difference between the first duty cycle voltage DV1 and the second duty cycle voltage DV2 in the duty cycle control code CD_CTR to encode the duty cycle control code CD_CTR. That is, in at least one normal operating mode, only the duty cycle correction operation corresponding to the difference between the first duty cycle voltage DV1 and the second duty cycle voltage DV2 can be performed. Therefore, the duty cycle control circuit 320 can perform minimal control operation for the duty cycle control code CD_CTR in at least one normal operating mode following the duty cycle training mode.

[0055] Figure 4The duty cycle correction circuit 300 can store the duty cycle of the output clock signal CLK_OUT corresponding to the operating power supply voltage V_INN as a first duty cycle voltage DV1 in the duty cycle training operation mode via charging / discharging operations. The duty cycle correction circuit 300 can also store the duty cycle of the output clock signal CLK_OUT corresponding to the operating power supply voltage V_INN as a second duty cycle voltage DV2 in at least one normal operation mode via charging / discharging operations. The duty cycle correction circuit 300 can perform a duty cycle correction operation by comparing the first duty cycle voltage DV1 with the second duty cycle voltage DV2. Therefore, the duty cycle correction circuit 300 can complete the duty cycle correction operation in at least one normal operation mode after the duty cycle training operation mode using minimal control operations for the duty cycle control code CD_CTR, thereby minimizing the time used for duty cycle correction.

[0056] The second charge / discharge circuit 420 may include multiple circuits corresponding to multiple normal operating modes. The mode selection signal MD_SEL can be selectively activated based on each normal operating mode. Therefore, although not shown in the figure, each second charge / discharge circuit 420 can store a storage voltage corresponding to each normal operating mode.

[0057] In this configuration, the voltage comparison circuit 430 can compare the duty cycle voltages corresponding to the duty cycle training mode and the normal operation mode. Therefore, the duty cycle correction circuit 300 can perform a duty cycle correction operation corresponding to each normal operation mode based on the second duty cycle voltage DV2 corresponding to each normal operation mode. Furthermore, the duty cycle correction circuit 300 can perform duty cycle correction operations corresponding to other normal operation modes based on the duty cycle voltage corresponding to at least one of the normal operation modes.

[0058] In the example implementation, the first charging / discharging circuit 410 and the second charging / discharging circuit 420 may store a first duty cycle voltage DV1 and a second duty cycle voltage DV2 to perform a duty cycle correction operation, but are not limited thereto. For example, the first charging / discharging circuit 410 may store the first duty cycle voltage DV1 for a duty cycle training operation mode. Alternatively, such as Figure 1 and Figure 2 As shown, the first charging / discharging circuit 410 can store a first stored voltage V1 corresponding to the operating power supply voltage V_INN in the duty cycle training mode. Furthermore, the second charging / discharging circuit 420 can store a second duty cycle voltage DV2 for at least one normal operating mode. Alternatively, as... Figure 1 and Figure 2As shown, the second charge / discharge circuit 420 can store a second stored voltage V2 corresponding to the operating power supply voltage V_INN of at least one normal operating mode. Therefore, the voltage comparison circuit 430 can compare the first stored voltage V1 with the second stored voltage V2 during a duty cycle correction operation for at least one normal operating mode. This can be implemented because the first duty cycle voltage DV1 and the second duty cycle voltage DV2, as well as the first stored voltage V1 and the second stored voltage V2, can include information about the operating power supply voltage V_INN for each operating mode.

[0059] Figure 5 It is shown Figure 3 The block diagram of the duty cycle control circuit.

[0060] Reference Figure 5 The duty cycle control circuit 320 may include a charging / discharging circuit 510, a code generation circuit 520, a first code storage circuit 530, a second code storage circuit 540, and a code calculation circuit 550.

[0061] The charging / discharging circuit 510 can store the duty cycle of the output clock signal CLK_OUT through charging / discharging operations in a duty cycle training operation mode. The charging / discharging circuit 510 can be activated in both the duty cycle training operation mode and at least one normal operation mode based on the mode selection signal MD_SEL. The charging / discharging circuit 510 may include a capacitor configured to perform charging / discharging operations based on the output clock signal CLK_OUT. Therefore, the charging / discharging circuit 510 can sequentially store voltages corresponding to the duty cycle of the output clock signal CLK_OUT during a predetermined interval in both the duty cycle training operation mode and at least one normal operation mode.

[0062] The code generation circuit 520 can encode the output voltage of the charging / discharging circuit 510. The code generation circuit 520 can be implemented by various example embodiments for generating codes corresponding to the input voltage.

[0063] In the duty cycle training mode, the first code storage circuit 530 can store the output code of the code generation circuit 520 as the first duty cycle code CD1. The first code storage circuit 530 can be activated in the duty cycle training mode based on the mode selection signal MD_SEL. The first code storage circuit 530 may include storage circuitry such as latches and registers. Therefore, the first code storage circuit 530 can store code corresponding to the duty cycle of the output clock signal CLK_OUT in the duty cycle training mode. Then, the first code storage circuit 530 can output the stored code as the first duty cycle code DC1.

[0064] The second code storage circuit 540 can store the output code of the code generation circuit 520 as a second duty cycle code CD2 in at least one normal operating mode. The second code storage circuit 540 can be activated in at least one normal operating mode based on the mode selection signal MD_SEL. Similar to the first code storage circuit 530, the second code storage circuit 540 may include storage circuitry such as latches, registers, etc. Therefore, the second code storage circuit 540 can store code corresponding to the duty cycle of the output clock signal CLK_OUT in at least one normal operating mode. Then, the second code storage circuit 540 can output the stored code as the second duty cycle code DC2.

[0065] The code calculation circuit 550 can calculate the first duty cycle code CD1 and the second duty cycle code CD2 to generate the duty cycle control code CD_CTR. The code calculation circuit 550 can also calculate the first duty cycle code CD1 output from the first code storage circuit 530 and the second duty cycle code CD2 output from the second code storage circuit 540 to generate the duty cycle control code CD_CTR.

[0066] The first duty cycle code CD1 can be a code corresponding to the duty cycle of the output clock signal CLK_OUT based on the operating power supply voltage V_INN in the duty cycle training operation mode. The second duty cycle code CD2 can be a code corresponding to the duty cycle of the output clock signal CLK_OUT based on the operating power supply voltage V_INN in at least one normal operation mode. As a result, the code calculation circuit 550 can calculate the difference between the operating power supply voltage V_INN in the duty cycle training operation mode and the operating power supply voltage V_INN in at least one normal operation mode to generate the duty cycle control code CD_CTR.

[0067] The duty cycle correction circuit 300 can store the duty cycle of the output clock signal CLK_OUT corresponding to the operating power supply voltage V_INN as a first duty cycle code CD1 in the duty cycle training operation mode through an encoding operation. The duty cycle correction circuit 300 can also store the duty cycle of the output clock signal CLK_OUT corresponding to the operating power supply voltage V_INN as a second duty cycle code CD2 in at least one normal operation mode through an encoding operation. The duty cycle correction circuit 300 can perform a duty cycle correction operation based on code calculations for the first duty cycle code CD1 and the second duty cycle code CD2. Therefore, the duty cycle correction circuit 300 can complete the duty cycle correction operation in at least one normal operation mode after the duty cycle training operation mode through minimal control operations for the duty cycle control code CD_CTR, thereby minimizing the time used for duty cycle correction.

[0068] The second code storage circuit 540 may include multiple circuits corresponding to multiple normal operating modes. The mode selection signal MD_SEL can be selectively activated based on each normal operating mode. Therefore, although not shown in the figure, each second code storage circuit 540 can store a duty cycle code corresponding to each normal operating mode.

[0069] In this configuration, the code calculation circuit 550 can calculate the duty cycle codes corresponding to the duty cycle training operation mode and the normal operation mode. Therefore, the duty cycle correction circuit 300 can perform a duty cycle correction operation corresponding to each normal operation mode based on the second duty cycle code CD2 corresponding to each normal operation mode. Furthermore, the duty cycle correction circuit 300 can perform duty cycle correction operations corresponding to other normal operation modes based on the duty cycle voltage corresponding to at least one of the normal operation modes.

[0070] In an example implementation, the first code storage circuit 530 and the second code storage circuit 540 may store a first duty cycle code CD1 and a second duty cycle code CD2 to perform a duty cycle correction operation. However, this disclosure is not limited thereto. For example, the first code storage circuit 530 may store a first duty cycle code CD1 for a duty cycle training operation mode. Alternatively, the first code storage circuit 530 may encode and store a first storage voltage V1 corresponding to the duty cycle training operation mode. Furthermore, the second code storage circuit 540 may store a second duty cycle code CD2 for at least one normal operation mode. Alternatively, the second code storage circuit 540 may store a second storage voltage V2 corresponding to at least one normal operation mode. Therefore, the code calculation circuit 550 may calculate the encoded first storage voltage V1 and second storage voltage V2. This can be implemented because the first duty cycle code CD1 and the second duty cycle code CD2, as well as the first storage voltage V1 and the second storage voltage V2, may include information about the operating power supply voltage V_INN for each operation mode.

[0071] Figure 6 This is a block diagram illustrating a duty cycle correction circuit according to an example embodiment.

[0072] Reference Figure 6 The duty cycle correction circuit 600 may include a duty cycle correction circuit 610 and a duty cycle control circuit 620.

[0073] The duty cycle correction circuit 610 can correct the duty cycles of the input clock signals CLK_IN and / CLK_IN based on the duty cycle control code CD_CTR to generate the output clock signals CLK_OUT and / CLK_OUT. The input clock signals CLK_IN and / CLK_IN can include a positive input clock signal CLK_IN and a negative input clock signal / CLK_IN. The positive input clock signal CLK_IN and the negative input clock signal / CLK_IN can have opposite phases. The output clock signals CLK_OUT and / CLK_OUT can include a positive output clock signal CLK_OUT and a negative output clock signal / CLK_OUT. The positive output clock signal CLK_OUT and the negative output clock signal / CLK_OUT can have opposite phases. Therefore, the duty cycle correction circuit 610 can correct the duty cycles of the positive input clock signal CLK_IN and the negative input clock signal / CLK_IN based on the duty cycle control code CD_CTR to generate the positive output clock signal CLK_OUT and the negative output clock signal / CLK_OUT.

[0074] The duty cycle control circuit 620 can generate a duty cycle control code CD_CTR based on a mode selection signal MD_SEL corresponding to a duty cycle training operation mode and at least one normal operation mode. Specifically, in the duty cycle training operation mode, the duty cycle control circuit 620 can compare the duty cycle of the positive output clock signal CLK_OUT with the duty cycle of the negative output clock signal / CLK_OUT to generate the duty cycle control code CD_CTR. In at least one normal operation mode, the duty cycle control circuit 620 can include the difference between the operating power supply voltage V_INN in the duty cycle training operation mode and at least one normal operation mode in the duty cycle control code CD_CTR.

[0075] According to an example implementation, the duty cycle correction circuit 300 may include the difference between the operating power supply voltages V_INN based on the operating mode in the duty cycle control code CD_CTR to perform a duty cycle correction operation. Therefore, in at least one normal operating mode, the duty cycle correction circuit 300 can minimally control the duty cycle control code CD_CTR, which can be set in the duty cycle training operating mode, to perform the duty cycle correction operation. As a result, the duty cycle correction circuit 600 can quickly and accurately generate an output clock signal CLK_OUT with the desired duty cycle in at least one normal operating mode.

[0076] Figure 7 It is shown Figure 6 The block diagram of the duty cycle control circuit.

[0077] Reference Figure 7The duty cycle control circuit 620 may include a first charging / discharging circuit 710, a second charging / discharging circuit 720, a voltage comparison circuit 730, and a code generation circuit 740.

[0078] The first charging / discharging circuit 710 can store the duty cycle of the positive output clock signal CLK_OUT as a first output voltage OV1 through charging / discharging operations in the duty cycle training operation mode. The first output voltage OV1 may include a voltage corresponding to the duty cycle of the positive output clock signal CLK_OUT based on the operating power supply voltage V_INN in the duty cycle training operation mode.

[0079] The second charging / discharging circuit 720 can store the duty cycle of the negative output clock signal / CLK_OUT as a second output voltage OV2 through charging / discharging operations in the duty cycle training operation mode. The second output voltage OV2 may include a voltage corresponding to the duty cycle of the negative output clock signal / CLK_OUT based on the operating power supply voltage V_INN in the duty cycle training operation mode.

[0080] The voltage comparison circuit 730 can compare the first output voltage OV1 with the second output voltage OV2. The voltage comparison circuit 730 can also compare the first output voltage OV1 stored in the first charge / discharge circuit 710 with the second output voltage OV2 stored in the second charge / discharge circuit 720 to generate an output signal corresponding to the voltage difference.

[0081] The code generation circuit 740 can be configured to generate duty cycle control code CD_CTR by encoding the output signal of the voltage comparator circuit 730. The duty cycle control code CD_CTR generated from the code generation circuit 740 can be provided to... Figure 6 The duty cycle correction circuit 610 is used in the duty cycle training operation mode. Therefore, the duty cycle correction circuit 610 can correct the duty cycle of the positive input clock signal CLK_IN and the negative input clock signal / CLK_IN based on the duty cycle control code CD_CTR to generate the positive output clock signal CLK_OUT and the negative output clock signal / CLK_OUT.

[0082] The first charging / discharging circuit 710, the second charging / discharging circuit 720, the voltage comparison circuit 730, and the code generation circuit 740 can perform operations corresponding to the duty cycle training operation mode. Hereinafter, a duty cycle correction operation in at least one normal operation mode following the duty cycle training operation mode can be shown. As described above, the duty cycle correction operation can include an operation method using a duty cycle voltage and an operation method using a stored voltage.

[0083] In the operation method using duty cycle voltage, the first charging / discharging circuit 710 and the second charging / discharging circuit 720 can store a first duty cycle voltage corresponding to the duty cycle rate of the duty cycle training operation mode and a second duty cycle voltage corresponding to at least one normal operation mode.

[0084] Specifically, the first charging / discharging circuit 710 can store the duty cycle of the duty-free training operation mode as a first duty-free voltage. Because the first charging / discharging circuit 710 can store a first output voltage OV1 corresponding to the first duty-free voltage in the duty-free training operation mode, the first charging / discharging circuit 710 can output a first output voltage OV1 that is substantially the same as the duty-free training operation mode in at least one normal operation mode. The second charging / discharging circuit 720 can store the duty cycle of at least one normal operation mode as a second duty-free voltage. The second charging / discharging circuit 720 can output the second duty-free voltage as a second output voltage OV2. See also... Figure 4 The operation for storing the second duty cycle voltage will be explained below. Therefore, for the sake of brevity, any further explanation of the storage operation can be omitted here. The voltage comparison circuit 730 can compare the first output voltage OV1 and the second output voltage OV2, which correspond to the first duty cycle voltage and the second duty cycle voltage, with each other.

[0085] Therefore, the duty cycle correction circuit 600 of the example embodiment can compare a first output voltage OV1 corresponding to a first duty cycle voltage in a duty cycle training operation mode with a second output voltage OV2 corresponding to a second duty cycle voltage in at least one normal operation mode. As described above, the difference between the first duty cycle voltage and the second duty cycle voltage can correspond to the difference between the operating power supply voltages V_INN based on the operation mode. That is, the duty cycle correction circuit 600 can perform a duty cycle correction operation based on the difference between the operating power supply voltages V_INN based on the operation mode.

[0086] In the operation method using the stored voltage, the first charging / discharging circuit 710 and the second charging / discharging circuit 720 can store a first stored voltage corresponding to the operating power supply voltage V_INN of the duty training operation mode and a second stored voltage corresponding to the operating power supply voltage V_INN of at least one normal operation mode.

[0087] Specifically, the first charging / discharging circuit 710 can store a first stored voltage corresponding to the operating power supply voltage V_INN of the duty-free training operation mode. Then, the first charging / discharging circuit 710 can output a first output voltage OV1. The second charging / discharging circuit 720 can store a second stored voltage corresponding to the operating power supply voltage V_INN of at least one normal operation mode. Then, the second charging / discharging circuit 720 can output a second output voltage OV2. See also... Figure 1and Figure 4 The operation for storing the first and second storage voltages will be explained below. Therefore, for the sake of brevity, any further explanation of the storage operation can be omitted here. The voltage comparison circuit 730 can compare the first output voltage OV1 and the second output voltage OV2, which correspond to the first and second storage voltages, with each other.

[0088] Therefore, the duty cycle correction circuit 600 of the example embodiment can compare a first output voltage OV1 corresponding to a first storage voltage in a duty cycle training operation mode with a second output voltage OV2 corresponding to a second storage voltage in at least one normal operation mode. As described above, the difference between the first storage voltage and the second storage voltage can correspond to the difference between the operating power supply voltages V_INN based on the operation mode. That is, the duty cycle correction circuit 600 can perform a duty cycle correction operation based on the difference between the operating power supply voltages V_INN based on the operation mode.

[0089] In an example implementation, the first charge / discharge circuit 710 may store a first duty-free voltage or a first stored voltage corresponding to a duty-free training operation mode. The second charge / discharge circuit 720 may store a second duty-free voltage or a second stored voltage corresponding to at least one normal operation mode. Alternatively, the duty cycle correction circuit 600 may store the first duty-free voltage or the first stored voltage corresponding to a duty-free training operation mode in the second charge / discharge circuit 720. The duty cycle correction circuit 600 may store the second duty-free voltage or the second stored voltage corresponding to at least one normal operation mode in the first charge / discharge circuit 710.

[0090] According to an example implementation, the duty cycle correction circuit 600 can compare the difference between the operating power supply voltages V_INN based on the operating mode to correct the duty cycle of the positive output clock signal CLK_OUT and the negative output clock signal / CLK_OUT corresponding to the positive input clock signal CLK_IN and the negative input clock signal / CLK_IN.

[0091] Figure 8 This is a view illustrating a method of operating duty cycle correction circuit according to an example embodiment.

[0092] Reference Figure 1 and Figure 8 The operation method 800 of the duty cycle correction circuit may include operation 810 for performing duty cycle training operation, operation 820 for comparing the difference between operating power supply voltages, and operation 830 for performing duty cycle correction operation.

[0093] Operation 810 for performing a duty cycle training operation may include performing a duty cycle training operation on an input clock signal CLK_IN. Operation 810 for forming a duty cycle training operation may include generating a duty cycle control code CD_CTR based on the duty cycle of an output clock signal CLK_OUT, and generating an output clock signal CLK_OUT with a controlled duty cycle based on the duty cycle control code CD_CTR. Operation 810 for performing a duty cycle training operation may include setting the duty cycle of the output clock signal CLK_OUT before performing at least one normal operation.

[0094] Operation 820 for comparing the difference between operating power supply voltages may include comparing the difference between the operating power supply voltage V_INN in a duty cycle training operation and at least one normal operation. Operation 820 for comparing the difference between operating power supply voltages may use at least one of a storage voltage and a duty cycle voltage.

[0095] Specifically, as mentioned above Figure 1 , Figure 4 and Figure 7 The operation 820 for comparing the difference between operating power supply voltages can use a first storage voltage V1 and a second storage voltage V2 corresponding to the operating power supply voltage V_INN in the duty cycle training operation and at least one normal operation. Furthermore, as referred to above... Figure 4 and Figure 7 The operation 820 for comparing the difference between operating power supply voltages can use a first duty cycle voltage DV1 and a second duty cycle voltage DV2 corresponding to the duty cycle of the operating power supply voltage V_INN, which includes duty cycle training operation and at least one normal operation. (Refer to the above) Figure 5 The operation 820 for comparing the difference between operating power supply voltages can use a first duty cycle code CD1 and a second duty cycle code CD2 obtained by encoding the duty cycle of the operating power supply voltage V_INN in a duty cycle training operation and at least one normal operation. The operation 820 for comparing the difference between operating power supply voltages may include generating a duty cycle control code CD_CTR based on the comparison result.

[0096] Operation 830 for performing duty cycle correction may include generating an output clock signal CLK_OUT with a corrected duty cycle for the input clock signal CLK_IN based on the comparison result of operation 820. Operation 830 for performing duty cycle correction may include generating an output clock signal CLK_OUT with a desired duty cycle based on the duty control code CD_CTR, which is the comparison result of operation 820.

[0097] According to an example implementation, the duty cycle correction circuit may include the difference between the operating power supply voltage V_INN for duty cycle training operation and at least one normal operation, to perform the duty cycle correction operation quickly and accurately.

[0098] The embodiments described above are intended to illustrate, not limit, the invention. Various alternatives and equivalents are possible. The invention is not limited to the embodiments described herein. The invention is also not limited to any particular type of semiconductor device. Other additions, deletions, or modifications based on this disclosure are apparent and are intended to fall within the scope of the appended claims.

[0099] Cross-references to related applications

[0100] This application claims priority to Korean Application No. 10-2022-0079713, filed with the Korean Intellectual Property Office on June 29, 2022, the entire contents of which are incorporated herein by reference.

Claims

1. A duty cycle correction circuit, the duty cycle correction circuit comprising: A duty cycle correction circuit, which corrects the duty cycle of the input clock signal based on a duty cycle control code and generates an output clock signal; An information generation circuit compares the operating power supply voltage based on the operating mode and generates voltage information; as well as A duty cycle control circuit receives the voltage information from the information generation circuit and generates a duty cycle control code including the voltage information based on the duty cycle of the output clock signal.

2. The duty cycle correction circuit according to claim 1, wherein, The operating modes include a duty-free training operating mode and at least one normal operating mode.

3. The duty cycle correction circuit according to claim 2, wherein, The information generation circuit includes: A first charging circuit stores the operating power supply voltage as a first storage voltage through a charging operation in the duty training operation mode. A second charging circuit, wherein the second charging circuit stores the operating power supply voltage as a second storage voltage through a charging operation in the at least one normal operating mode; and A voltage comparison circuit compares the first stored voltage with the second stored voltage to generate the voltage information.

4. The duty cycle correction circuit according to claim 3, wherein, The second charging circuit is selectively activated based on multiple normal operating modes to store the storage voltage corresponding to each normal operating mode.

5. The duty cycle correction circuit according to claim 3, wherein, At least one of the first charging circuit and the second charging circuit shares the capacitor of the duty cycle control circuit used to perform charging / discharging operations.

6. A duty cycle correction circuit, the duty cycle correction circuit comprising: A duty cycle correction circuit, which corrects the duty cycle of the input clock signal based on a duty cycle control code and generates an output clock signal; as well as A duty cycle control circuit generates a duty cycle control code based on the duty cycle of the output clock signal, the duty cycle control code including the difference between the operating power supply voltage and the operating mode.

7. The duty cycle correction circuit according to claim 6, wherein, The operating modes include a duty-free training operating mode and at least one normal operating mode.

8. The duty cycle correction circuit according to claim 7, wherein, The duty cycle control circuit includes: The first charging / discharging circuit stores the duty cycle of the output clock signal as a first duty cycle voltage through charging / discharging operations in the duty cycle training operation mode. The second charging / discharging circuit stores the duty cycle of the output clock signal as a second duty cycle voltage through charging / discharging operations in the at least one normal operating mode. A voltage comparison circuit that compares a first duty cycle voltage with a second duty cycle voltage; and A code generation circuit generates the duty cycle control code by encoding the output signal of the voltage comparison circuit.

9. The duty cycle correction circuit according to claim 8, wherein, The code generation circuit encodes the first duty-free voltage in the duty-free training operation mode to generate the duty-free control code, and In the at least one normal operating mode, the code generation circuit includes the difference between the first duty cycle voltage and the second duty cycle voltage in the duty cycle control code to encode the duty cycle control code.

10. The duty cycle correction circuit according to claim 8, wherein, The second charging / discharging circuit is selectively activated based on multiple normal operating modes to store the duty cycle voltage corresponding to each normal operating mode.

11. The duty cycle correction circuit according to claim 8, wherein, The first charging / discharging circuit stores a first stored voltage corresponding to the operating power supply voltage in the duty cycle training operation mode. The second charging / discharging circuit stores a second storage voltage corresponding to the operating power supply voltage in at least one normal operating mode, and The voltage comparison circuit compares the first stored voltage with the second stored voltage.

12. The duty cycle correction circuit according to claim 7, wherein, The duty cycle control circuit includes: A charging / discharging circuit, wherein the charging / discharging circuit stores the duty cycle of the output clock signal through charging / discharging operations; A code generation circuit that encodes the output voltage from the charging / discharging circuit; A first code storage circuit stores the output code from the code generation circuit as a first duty-free code in the duty-free training operation mode. A second code storage circuit stores the output code from the code generation circuit as a second duty cycle code in the at least one normal operating mode; and A code calculation circuit calculates the first duty cycle code and the second duty cycle code to generate the duty cycle control code.

13. The duty cycle correction circuit according to claim 12, wherein, The second code storage circuit is selectively activated based on multiple normal operating modes to store the duty cycle code corresponding to each normal operating mode.

14. The duty cycle correction circuit according to claim 12, wherein, The first code storage circuit encodes and stores the first storage voltage corresponding to the operating power supply voltage in the duty cycle training operation mode. The second code storage circuit encodes and stores a second storage voltage corresponding to the operating power supply voltage in the at least one normal operating mode, and The code calculation circuit calculates the encoded first storage voltage and the encoded second storage voltage.

15. The duty cycle correction circuit according to claim 7, wherein, The input clock signal includes a positive input clock signal and a negative input clock signal, and the output clock signal includes a positive output clock signal corresponding to the positive input clock signal and a negative output clock signal corresponding to the negative input clock signal. The duty cycle control circuit includes: In the duty cycle training operation mode, the positive output clock signal is compared with the negative output clock signal to generate the duty cycle control code, and In the at least one normal operating mode, the duty cycle control code includes the difference between the operating power supply voltage corresponding to the duty cycle training operating mode and the at least one normal operating mode.

16. The duty cycle correction circuit according to claim 15, wherein, The duty cycle control circuit includes: The first charging / discharging circuit stores the duty cycle of the positive output clock signal as the first output voltage through charging / discharging operations in the duty cycle training operation mode. The second charging / discharging circuit stores the duty cycle of the negative output clock signal as the second output voltage through charging / discharging operations in the duty cycle training operation mode. A voltage comparison circuit compares the first output voltage with the second output voltage; and A code generation circuit encodes the output signal from the voltage comparison circuit to generate the duty cycle control code.

17. The duty cycle correction circuit according to claim 16, wherein, Each of the first charging / discharging circuit and the second charging / discharging circuit stores a first duty cycle voltage corresponding to the duty cycle of the duty cycle training operation mode and a second duty cycle voltage corresponding to the duty cycle of the at least one normal operation mode. Furthermore, the voltage comparison circuit compares the first duty cycle voltage with the second duty cycle voltage.

18. The duty cycle correction circuit according to claim 16, wherein, Each of the first charging / discharging circuit and the second charging / discharging circuit stores a first storage voltage corresponding to the operating power supply voltage of the duty-free training operation mode and a second storage voltage corresponding to the operating power supply voltage of the at least one normal operation mode. The voltage comparison circuit compares the first stored voltage with the second stored voltage.

19. A method for operating a duty cycle correction circuit, the method comprising the following steps: Perform a duty cycle training operation on the input clock signal; Compare the operating power supply voltage during the duty cycle training operation with that during at least one normal operation; as well as A duty cycle correction operation is performed based on the comparison result to generate an output clock signal with a corrected duty cycle for the input clock signal.

20. The method according to claim 19, wherein, The step of comparing the operating power supply voltage includes at least one of the following steps: using a storage voltage corresponding to the operating power supply voltage of the duty training operation and the at least one normal operation, a duty voltage corresponding to the duty rate including the operating power supply voltage, and a duty code obtained by encoding the duty rate including the operating power supply voltage.

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