Gate driving device

Abstract

A gate drive device (4) includes an arithmetic circuit (11) that outputs a current command signal and switches a command value indicated by the current command signal in a manner to control a transient voltage at the time of opening and closing to a target value, a pre-driver circuit (14) that generates and outputs a drive signal corresponding to the current command signal, and a drive circuit (15) that drives a gate of a semiconductor switching element (7) based on the drive signal. The drive circuit is configured by connecting output circuits (16a to 16c) each including a structure of a Wheatstone circuit in parallel with each other, the Wheatstone circuit being a circuit in which two MOS transistors are connected in common source and common gate, and the drive circuit drives the gate of the semiconductor switching element by turning on the MOS transistors to thereby flow a gate current. The drive circuit changes the gate current by changing the number of MOS transistors to be turned on according to the command value indicated by the drive signal.

Description

Technical Field

[0001] This disclosure relates to a gate driving device for driving the gate of a semiconductor switching element. Background Technology

[0002] Currently, gate driving devices that drive the gates of semiconductor switching elements employ a technology called AGC (Active Gate Control). This type of gate driving device aims to reduce losses, noise, and prevent device failure. By adjusting the current flowing through the gate of the semiconductor switching element—the gate current—it can control the transient voltage corresponding to the voltage at the main terminal of the semiconductor switching element during switching to a desired target value. This transient voltage includes the rate of change of the main terminal voltage during switching (dV / dt) and the peak value of the main terminal voltage during switching (the surge voltage).

[0003] In the gate drive device described above, low gate current accuracy leads to increased errors in transient voltage control, potentially causing excessive surge voltages and malfunctions of the semiconductor switching element. Therefore, it is desirable for the gate drive device to control the gate current to the desired value with high precision. Furthermore, the driven element in the gate drive device is sometimes a semiconductor switching element capable of high-speed switching, such as a SiC-MOSFET. SiC is an abbreviation for Silicon Carbide. Therefore, it is desirable for the gate drive device to change the gate current at high speed.

[0004] Patent Document 1 discloses a constant current gate driver that uses an operational amplifier (OP amplifier) ​​to feedback control the current flowing in a shunt resistor located in the path of the gate current, thereby controlling the gate current of the IGBT. In this case, the OP amplifier can be controlled based on a control signal representing a command value for the gate current. Patent Document 2 discloses a digital gate driver configured with multiple drive circuits connected in parallel, controlling the gate current of the IGBT by changing the number of drive circuits turned on according to the passage of time. Furthermore, in the following description, the technologies disclosed in Patent Documents 1 and 2 will sometimes be referred to as Prior Art 1 and Prior Art 2, respectively.

[0005] Prior art literature

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2012-114587

[0008] Patent Document 2: Japanese Patent Application Publication No. 2019-154134 Summary of the Invention

[0009] In prior art 1, although the gate current can be controlled to the commanded value with high precision, the gate current cannot be switched at high speed due to the delay of the feedback loop implemented with the OP amplifier. That is, in prior art 1, it is difficult to improve the change in the actual gate current relative to the commanded value of the gate current, i.e., it is difficult to improve the responsiveness of the gate current control. In addition, in prior art 1, since an OP amplifier is required, there is also the technical problem of a corresponding increase in circuit size.

[0010] In prior art 2, the gate current can be changed by switching the MOS transistors that constitute the drive circuit on and off, thus enabling high-speed operation of the gate current and improving the responsiveness of gate current control. However, in prior art 2, due to the influence of channel length modulation of the MOS transistors that constitute the drive circuit, even if the number of transistors turned on is the same, there is a risk that the gate current will vary according to the gate-emitter voltage of the IGBT. As a result, it is difficult to improve the accuracy of the gate current.

[0011] This disclosure is made in view of the above circumstances, and its object is to provide a gate drive device that can change the gate current with high precision and improve the responsiveness of the gate current control without increasing the circuit size.

[0012] Solutions for solving technical problems

[0013] The gate driving device of this disclosure is an apparatus for driving the gate of a semiconductor switching element, wherein the gate driving device comprises: a command signal output circuit that outputs a current command signal representing a command value of a current flowing to the gate of the semiconductor switching element, i.e., a gate current; a pre-drive circuit that receives the current command signal and generates and outputs a drive signal corresponding to the current command signal; and a drive circuit that drives the gate of the semiconductor switching element based on the drive signal.

[0014] The command signal output circuit switches the command value represented by the current command signal to a desired target value by controlling the transient voltage corresponding to the voltage at the main terminal of the switching element when the semiconductor switching element is turned on or off. The drive circuit is a structure consisting of multiple output circuits connected in parallel, including a Worman circuit, where the Worman circuit is formed by connecting two MOS transistors in a common-source, common-gate configuration. The drive circuit drives the gate of the semiconductor switching element by turning on the MOS transistors of the output circuit, thereby allowing gate current to flow through them. This drive circuit structure can change the number of MOS transistors to be turned on according to the command value represented by the drive signal, thereby changing the gate current.

[0015] According to the above structure, the delay from the time point when the commanded value of the gate current changes to the time point when the actual gate current changes is mainly due to the propagation delay of the MOS transistor in the output circuit. Therefore, compared to the prior art 1, the gate current can be switched at a higher speed, that is, the responsiveness of the gate current control can be improved. Furthermore, in the above structure, since an op-amp is not required, the circuit size is not increased as in the prior art 1.

[0016] Furthermore, based on the above structure, by configuring the output circuit to include a Worman circuit formed by connecting two MOS transistors via a common source and common gate, the following effects can be obtained. Additionally, below, the MOS transistor with its source grounded side among the two MOS transistors constituting the Worman circuit will be designated as the first transistor, and a MOS transistor different from the one with its source grounded side will be designated as the second transistor.

[0017] That is, according to the above structure, the drain-source voltage on the second transistor side absorbs the fluctuations in the gate-source voltage or gate-emitter voltage of the semiconductor switching element, thus maintaining the drain-source voltage on the first transistor side at a substantially constant level. Furthermore, in this case, the value of the gate current is primarily determined by the first transistor. Therefore, according to the above structure, fluctuations in the gate current caused by changes in the gate-source voltage or gate-emitter voltage of the semiconductor switching element can be suppressed, thereby improving the accuracy of the gate current. Thus, according to the above structure, it is possible to achieve the excellent effect of highly accurate gate current control and improved responsiveness of gate current control without increasing the circuit size. Attached Figure Description

[0018] Figure 1 This is a schematic diagram showing the structure of the motor drive device according to the first embodiment.

[0019] Figure 2This is a diagram schematically showing the waveforms of each part of the semiconductor switching element in the first embodiment when it is turned off.

[0020] Figure 3 This diagram schematically illustrates the main functions of the gate driving device according to the first embodiment.

[0021] Figure 4 This is a diagram illustrating an example of the specific structure of the gate driving device according to the first embodiment.

[0022] Figure 5 This is a timing diagram used to illustrate the operation timing of each part of the gate drive device when the semiconductor switching element of the first embodiment is turned off.

[0023] Figure 6 This is a timing diagram schematically showing the waveforms of various parts of the prior art 1 when the gate current is changed during the gate opening and closing period.

[0024] Figure 7 This is a timing diagram schematically showing the waveforms of each part of the first embodiment when the gate current is changed during the gate opening and closing period.

[0025] Figure 8 This is a schematic diagram illustrating the structure of the output circuit of prior art 2.

[0026] Figure 9 This is a diagram schematically illustrating the structure of the output circuit in the first embodiment.

[0027] Figure 10 This is a graph showing the relationship between the drain current and the drain-source voltage of a MOS transistor.

[0028] Figure 11 It is a diagram showing the simulation results of prior art 2, and a diagram schematically showing the waveforms of each part when the semiconductor switching element is turned off.

[0029] Figure 12 The diagram shows the simulation results of the first embodiment and is a schematic diagram showing the waveforms of each part when the semiconductor switching element is turned off.

[0030] Figure 13 This is a diagram illustrating an example of the specific structure of the gate driving device of the first comparative example.

[0031] Figure 14 This is a timing diagram used to illustrate the operating timing of each part of the gate drive device when the semiconductor switching element of the first comparative example is turned off.

[0032] Figure 15 This is a diagram schematically illustrating the structure of the output circuit of a first variant of the first embodiment.

[0033] Figure 16 This is a diagram schematically illustrating the structure of the output circuit of a second variation of the first embodiment.

[0034] Figure 17 The diagram shows the simulation results of the second variation of the first embodiment, and the diagram schematically shows the waveforms of each part when the semiconductor switching element is turned off.

[0035] Figure 18 This is a diagram schematically illustrating the structure of the output circuit of the third variation of the first embodiment.

[0036] Figure 19 This is a diagram schematically illustrating the structure of the output circuit of the fourth variation of the first embodiment.

[0037] Figure 20 This is a diagram illustrating an example of the specific structure of the gate driving device according to the second embodiment.

[0038] Figure 21 This is a schematic diagram illustrating an example of the planar layout of the circuit elements constituting the gate driving device of the second embodiment.

[0039] Figure 22 This is a timing diagram used to illustrate the operation timing of each part of the gate drive device when the semiconductor switching element of the second embodiment is turned off.

[0040] Figure 23 This is a diagram illustrating an example of the specific structure of the gate driving device according to the third embodiment.

[0041] Figure 24 This is a timing diagram used to illustrate the operation timing of each part of the gate drive device when the semiconductor switching element of the third embodiment is turned off.

[0042] Figure 25 This is a diagram illustrating an example of the specific structure of the gate driving device according to the fourth embodiment. Detailed Implementation

[0043] Hereinafter, several embodiments will be described with reference to the accompanying drawings. Furthermore, substantially identical structures will be labeled with the same symbols in each embodiment, and descriptions will be omitted.

[0044] (First Implementation)

[0045] The following is for reference Figures 1 to 19 The first implementation method will be described below.

[0046] <Structure of Motor Drive Unit>

[0047] like Figure 1As shown, the motor drive device 1 of this embodiment is, for example, a device for driving a motor 2 mounted in a vehicle such as an automobile, and includes an inverter 3, gate drive devices 4up to 4wn, and a controller 5. The inverter 3, for example, converts the DC power supply voltage Va supplied from the vehicle's battery (i.e., DC power supply 6) through a pair of DC power lines L1 and L2 into a three-phase AC voltage (U-phase, V-phase, and W-phase) for output. The three-phase output of the inverter 3 is provided to the motor 2, thereby driving the motor 2. In this case, assuming an automotive application, the power supply voltage Va is a relatively high voltage, for example, several hundred volts.

[0048] Inverter 3 has three half-bridge circuits 3u, 3v, and 3w respectively connected between DC power lines L1 and L2. Half-bridge circuit 3u has a semiconductor switching element 7up forming its upper arm and a semiconductor switching element 7un forming its lower arm. Half-bridge circuit 3v has a semiconductor switching element 7vp forming its upper arm and a semiconductor switching element 7vn forming its lower arm. Half-bridge circuit 3w has a semiconductor switching element 7wp forming its upper arm and a semiconductor switching element 7wn forming its lower arm.

[0049] Semiconductor switching elements 7up to 7wn are all power devices such as SiC-MOSFETs. In this case, the structure includes an N-channel MOSFET and a freewheeling diode connected in reverse parallel with the source side as the anode between the drain and source of the MOSFET. Alternatively, in this case, a freewheeling diode is provided as a different element from the MOSFET, but the body diode of the MOSFET can also be used as a freewheeling diode.

[0050] The drains of semiconductor switching elements 7up, 7vp, and 7wp are all connected to the DC power supply line L1 on the high-potential side. The sources of semiconductor switching elements 7up, 7vp, and 7wp are connected to the drains of semiconductor switching elements 7un, 7vn, and 7wn, respectively. The sources of semiconductor switching elements 7un, 7vn, and 7wn are all connected to the DC power supply line L2 on the low-potential side.

[0051] The interconnection point Nu of semiconductor switching elements 7up and 7un functions as the output terminal of the U phase of inverter 3 and is connected to motor 2. The interconnection point Nv of semiconductor switching elements 7vp and 7vn functions as the output terminal of the V phase of inverter 3 and is connected to motor 2. The interconnection point Nw of semiconductor switching elements 7wp and 7wn functions as the output terminal of the W phase of inverter 3 and is connected to motor 2.

[0052] Gate driving device 4up drives the gate of semiconductor switching element 7up, which forms the upper arm of half-bridge circuit 3u. Gate driving device 4un drives the gate of semiconductor switching element 7un, which forms the lower arm of half-bridge circuit 3u. Gate driving device 4vp drives the gate of semiconductor switching element 7vp, which forms the upper arm of half-bridge circuit 3v. Gate driving device 4vn drives the gate of semiconductor switching element 7vn, which forms the lower arm of half-bridge circuit 3v. Gate driving device 4wp drives the gate of semiconductor switching element 7wp, which forms the upper arm of half-bridge circuit 3w. Gate driving device 4wn drives the gate of semiconductor switching element 7wn, which forms the lower arm of half-bridge circuit 3w.

[0053] In this case, the gate drive devices 4up to 4wn have the same structure, and the semiconductor switching elements 7up to 7wn have the same structure. Therefore, in this specification, where it is not necessary to distinguish between the gate drive devices 4up to 4wn and the semiconductor switching elements 7up to 7wn, the last letters are omitted and they are referred to collectively. The controller 5 is, for example, a structure including a microcomputer, and controls the drive of the motor 2 by controlling the operation of the half-bridge circuits 3u to 3w that constitute the inverter 3.

[0054] The controller 5 is provided with detection signals representing the three-phase output current of the inverter 3 detected by current sensors 8u, 8v, and 8w, in other words, the detected values ​​of the three-phase current flowing into the motor 2, and detection signals representing the detected values ​​of the rotation angle of the motor 2 detected by the resolver 9. Based on these detection signals, the controller generates and outputs command signals Sa that instruct the operation of the gate drive devices 4up to 4wn in a manner that makes the current flowing into the motor 2 consistent with the desired target current and makes the rotation angle of the motor 2 consistent with the desired target rotation angle.

[0055] The gate drive device 4 performs PWM control on the drive of the semiconductor switching element 7 based on the command signal Sa provided by the controller 5. PWM stands for Pulse Width Modulation. The command signal Sa is a binary signal; for example, a high level indicates a turn-on command for the semiconductor switching element 7, and a low level indicates a turn-off command. In this case, the semiconductor switching element 7 constituting the upper bridge arm and the semiconductor switching element 7 constituting the lower bridge arm are complementary in being turned on and off. Therefore, when the semiconductor switching element 7 constituting the upper bridge arm is turned on, the semiconductor switching element 7 constituting the lower bridge arm is turned off, and vice versa.

[0056] In the above structure, the drain-source voltage Vds of the semiconductor switching element 7 is equivalent to the voltage of the main terminal of the semiconductor switching element 7. Furthermore, in the above structure, the drain current Id is equivalent to the current flowing between the main terminals of the semiconductor switching element 7. In this specification, the drain current Id and the drain-source voltage Vds are sometimes simply referred to as current Id and voltage Vds, respectively.

[0057] When the semiconductor switching element 7 is switched on or off, specifically when the semiconductor switching element 7 is turned off, the waveforms of each part become... Figure 2 The waveform shown. Additionally, in Figure 2 The diagram illustrates the waveforms of each part corresponding to the semiconductor switching element 7 constituting the lower bridge arm, but the semiconductor switching element 7 constituting the upper bridge arm also exhibits the same waveform. The cutoff voltage Vds_off when the semiconductor switching element 7 is turned off is approximately equal to the power supply voltage Va.

[0058] The peak value Vds_p of the voltage Vds when disconnected corresponds to the peak value of the voltage at the main terminal when the semiconductor switching element 7 is switched on or off. The peak value Vds_p is the value obtained by adding the voltage ΔVds to the cutoff voltage Vds_off, and is equal to the surge voltage superimposed on the semiconductor switching element 7. Therefore, in the following description, the peak value Vds_p is sometimes referred to as the surge voltage Vsrg. In this case, the slope of the voltage Vds when disconnected, i.e., the slew rate, corresponds to the rate of change of the voltage at the main terminal when the semiconductor switching element 7 is switched on or off. Furthermore, in this specification, the slope of the voltage Vds when disconnected is sometimes referred to as the rate of change dV / dt.

[0059] The surge voltage Vsrg and the rate of change dV / dt mentioned above are both transient voltages corresponding to the voltage at the main terminal of the semiconductor switching element 7 when it is switched on or off. The gate drive device 4 of this embodiment, by having the various functions described later, is able to control such transient voltages to a desired target value.

[0060] <Main functions of gate driving devices>

[0061] Next, refer to Figure 3 The main functions of the gate drive device 4 will be explained. Figure 3 In the following sections, the main functions of the gate driving device 4 are represented in the form of function blocks. The specific implementation methods for each function will be described later. Figure 3As shown, the gate driving device 4 includes an arithmetic circuit 11, a turn-on driving unit 12, and a turn-off driving unit 13. The arithmetic circuit 11 is a circuit that outputs a current command signal representing the command value of the current flowing to the gate of the semiconductor switching element 7, i.e., the gate current Ig, and functions as a command signal output circuit.

[0062] The turn-on drive unit 12 is a structure for turning on the semiconductor switching element 7, and the cut-off drive unit 13 is a structure for turning off the semiconductor switching element 7. The turn-on drive unit 12 and the cut-off drive unit 13 have substantially the same structure, and their operation is also substantially the same except for the difference between turning on and off. Therefore, in the following description, given the substantially identical structure and operation of the turn-on drive unit 12 and the cut-off drive unit 13, the description of the cut-off drive unit 13 will be omitted.

[0063] The cutoff drive unit 13 includes a pre-drive circuit 14 and a drive circuit 15. The pre-drive circuit 14 receives a current command signal from the arithmetic circuit 11 and generates and outputs a drive signal corresponding to the current command signal. The drive circuit 15 drives the gate of the semiconductor switching element 7 based on the drive signal output from the pre-drive circuit 14. The arithmetic circuit 11 switches the command value represented by the current command signal to control the aforementioned transient voltage to the desired target value.

[0064] The driving circuit 15 is constructed by connecting three output circuits 16a, 16b, and 16c, which include a Worman circuit structure, in parallel. The Worman circuit is a circuit formed by connecting two MOS transistors in a cascode configuration. The driving circuit 15 drives the gate of the semiconductor switching element 7 by turning on the MOS transistors in the output circuits 16a, 16b, and 16c, thereby allowing gate current Ig to flow through them. The driving circuit 15 changes the number of MOS transistors to be turned on according to the command value represented by the driving signal output from the pre-driving circuit 14, i.e., the command value represented by the current command signal output from the arithmetic circuit 11, thereby changing the gate current Ig.

[0065] The pre-drive circuit 14 includes three output buffers 17a, 17b, and 17c, respectively, which are configured to correspond to the three output circuits 16a, 16b, and 16c of the drive circuit 15. In this case, the three output circuits 16a, 16b, and 16c of the drive circuit 15 are configured with different current capabilities. Furthermore, in this case, the three output buffers 17a, 17b, and 17c each have a buffering capacity corresponding to the current capability of the corresponding output circuits 16a, 16b, and 16c.

[0066] In addition, the pre-drive circuit 14 generates and outputs a drive signal in such a way that the first delay time required for the MOS transistors of the output circuits 16a to 16c of the drive circuit 15 to change from off to on is longer than the second delay time required for the MOS transistors of the output circuits 16a to 16c of the drive circuit 15 to change from on to off.

[0067] <Specific Structure of Gate Driving Device>

[0068] As a specific structure of the gate driving device 4, for example, it can adopt Figure 4 An example structure as shown. In this case, the gate drive device 4 is constructed as a semiconductor integrated circuit, i.e., an IC. Figure 4 As shown, a signal Sb representing the element association information associated with the semiconductor switching element 7 is input to the arithmetic circuit 11. The element association information includes at least one of the following: current Id, power supply voltage Va, surge voltage Vsrg, temperature of the semiconductor switching element 7, temperature of the gate drive device 4, and rate of change dV / dt. The arithmetic circuit 11 calculates the command value of the gate current Ig based on the element association information represented by the signal Sb.

[0069] The arithmetic circuit 11 provides the instruction signal Sa output from the controller 5. When the arithmetic circuit 11 receives the instruction signal Sa indicating the turn-on instruction, that is, when the gate of the semiconductor switching element 7 is to be turned on, the arithmetic circuit 11 outputs the current instruction signal on the turn-on drive unit 12. The current instruction signal on the turn-on side is a signal indicating the instruction value of the gate current Ig, i.e., the gate current Ig_on, used to turn on the gate of the semiconductor switching element 7, and includes multiple instruction signals, specifically three turn-on instruction signals IGN1[0], IGN1[1], and IGN1[2].

[0070] That is, the current command signal on the turn-on side is composed of a 3-bit turn-on command signal IGN1[2:0]. The 3-bit turn-on command signal IGN1[2:0] corresponds to the three output circuits 16a to 16c provided in the drive circuit 15 of the turn-on drive unit 12, respectively. The three turn-on command signals IGN1[2:0] are binary signals having a first level indicating the turn-on of the corresponding output circuits 16a to 16c and a second level indicating the cut-off of the MOS transistors. In addition, in this embodiment, regarding the turn-on command signal IGN1[2:0], the first level is, for example, 0V, which is a relatively low level, and the second level is, for example, 5V, which is a relatively high level.

[0071] When the arithmetic circuit 11 receives the instruction signal Sa indicating a disconnection instruction, that is, when the gate of the semiconductor switching element 7 is to be turned off, it outputs the current instruction signal on the disconnection side to the cutoff drive unit 13. The current instruction signal on the disconnection side indicates the instruction value for making the gate of the semiconductor switching element 7 disconnected, namely the gate current Ig_off, and includes multiple instruction signals, specifically three cutoff instruction signals IGOFF1[0], IGOFF1[1], and IGOFF1[2].

[0072] That is, the current command signal on the disconnect side is composed of a 3-bit cutoff command signal IGOFF1[2:0]. The 3-bit cutoff command signal IGOFF1[2:0] corresponds to the three output circuits 16a to 16c provided in the drive circuit 15 of the cutoff drive unit 13. The three cutoff command signals IGOFF1[2:0] are binary signals having a first level indicating the conduction of the corresponding output circuits 16a to 16c MOS transistors and a second level indicating the cutoff of the MOS transistors. In addition, in this embodiment, regarding the cutoff command signal IGOFF1[2:0], the first level is, for example, 5V, which is a relatively high level, and the second level is, for example, 0V, which is a relatively low level.

[0073] Both the on-side and off-side current command signals represent command values ​​for gate currents Ig of order two or higher. That is, the arithmetic circuit 11 switches the command values ​​represented by the on-side and off-side current command signals to order two or higher in a manner that controls the aforementioned transient voltage to the desired target value. The on-side current command signal output from the arithmetic circuit 11 is provided to the pre-drive circuit 14 of the turn-on drive unit 12. Furthermore, the off-side current command signal output from the arithmetic circuit 11 is provided to the pre-drive circuit 14 of the cut-off drive unit 13.

[0074] The pre-drive circuit 14 of the turn-on drive unit 12 is input with a turn-on command signal IGN1[2:0] and generates and outputs a drive signal on the turn-on side corresponding to the turn-on command signal IGN1[2:0]. The drive signal on the turn-on side includes multiple binary turn-on drive signals, specifically including three turn-on drive signals IGN2[0], IGN2[1], and IGN2[2]. That is, the drive signal on the turn-on side includes a 3-bit turn-on drive signal IGN2[2:0]. In addition, in this embodiment, regarding the turn-on drive signal IGN2[2:0], the first level is, for example, 15V, which is a relatively low level, and the second level is, for example, 20V, which is a relatively high level.

[0075] The pre-drive circuit 14 of the cutoff drive unit 13 is input with a cutoff command signal IGOFF1[2:0] and generates and outputs a drive signal on the disconnect side corresponding to the cutoff command signal IGOFF1[2:0]. The drive signal on the disconnect side includes multiple binary cutoff drive signals, specifically including three cutoff drive signals IGOFF2[0], IGOFF2[1], and IGOFF2[2]. That is, the drive signal on the disconnect side includes a 3-bit cutoff drive signal IGOFF2[2:0]. In addition, in this embodiment, regarding the cutoff drive signal IGOFF2[2:0], the first level is, for example, 0V, which is a relatively high level, and the second level is, for example, -5V, which is a relatively low level.

[0076] The pre-drive circuit 14 includes a glitch suppression unit 21, a level shift unit 22, and a buffer unit 17. The glitch suppression unit 21 outputs a signal for each signal of the cutoff command signal IGOFF1[2:0], such that the edge transitioning from the second level to the first level (i.e., the turn-on command edge) is delayed by a predetermined time compared to the edge transitioning from the first level to the second level (i.e., the cutoff command edge). The glitch suppression unit 21 includes three glitch suppression circuits 21a, 21b, and 21c.

[0077] Input the cutoff command signal IGOFF1[0] to the glitch suppression circuit 21a. The glitch suppression circuit 21a outputs a signal that delays the turn-on command edge by a specified time compared to the cutoff command edge in response to the cutoff command signal IGOFF1[0]. Input the cutoff command signal IGOFF1[1] to the glitch suppression circuit 21b. The glitch suppression circuit 21b outputs a signal that delays the turn-on command edge by a specified time compared to the cutoff command edge in response to the cutoff command signal IGOFF1[1]. Input the cutoff command signal IGOFF1[2] to the glitch suppression circuit 21c. The glitch suppression circuit 21c outputs a signal that delays the turn-on command edge by a specified time compared to the cutoff command edge in response to the cutoff command signal IGOFF1[2].

[0078] Each of the glitch suppression circuits 21a-21c includes an AND circuit 24 and a CR filter 23 formed by a resistor and a capacitor. One terminal of the resistor is connected to node Na, which serves as the input terminal of the glitch suppression circuits 21a-21c, and the other terminal is connected to ground, which serves as the reference potential of the circuit, via the capacitor. One input terminal of the AND circuit 24 is connected to node Na, and the other input terminal is connected to the junction of the resistor and the capacitor. The output terminal of the AND circuit 24 serves as the output terminal of the glitch suppression circuits 21a-21c.

[0079] The glitch suppression circuits 21a-21c described above can output signals that delay both the turn-on command edge and the turn-off command edge in response to the input cutoff command signal IGOFF1[2:0]. In other words, they can output signals that impart a delay time to both the turn-on command edge and the turn-off command edge. In this case, the delay time imparted to the turn-on command edge in the signals output from the glitch suppression circuits 21a-21c corresponds to the aforementioned first delay time, and the delay time imparted to the turn-off command edge corresponds to the second delay time. That is, in this case, the first delay time imparted to the turn-on command edge in the signals output from the glitch suppression circuits 21a-21c is longer than the second delay time imparted to the turn-off command edge.

[0080] The level conversion unit 22 outputs a signal whose level has been converted from the signals output from the glitch suppression circuits 21a to 21c. The level conversion unit 22 includes three level conversion circuits 22a, 22b, and 22c. The output signal of the glitch suppression circuit 21a, i.e., the signal that gives a delay time to the cutoff command signal IGOFF1[0], is input to the level conversion circuit 22a. The level conversion circuit 22a outputs a signal whose level has been converted from the input signal.

[0081] The output signal of the glitch suppression circuit 21b, which is the signal that gives a delay time to the cutoff command signal IGOFF1[1], is input to the level conversion circuit 22b. The level conversion circuit 22b outputs a signal whose level has been converted for such an input signal. The output signal of the glitch suppression circuit 21c, which is the signal that gives a delay time to the cutoff command signal IGOFF1[2], is input to the level conversion circuit 22c. The level conversion circuit 22c outputs a signal whose level has been converted for such an input signal.

[0082] The level conversion circuits 22a to 22c provided in the pre-drive circuit 14 of the turn-on drive unit 12 are configured to output a signal after level conversion of an input signal that varies between 0V and 5V to a signal that varies between 15V and 20V. The level conversion circuits 22a to 22c provided in the pre-drive circuit 14 of the cut-off drive unit 13 are configured to output a signal after level conversion of an input signal that varies between 0V and 5V to a signal that varies between -5V and 0V.

[0083] The reason for providing such a level conversion unit 22 in the pre-drive circuit 14 is as follows. Specifically, for example, when the semiconductor switching element 7 is a SiC-MOSFET, a gate drive voltage of approximately 20V is recommended to suppress on-resistance during conduction, and a gate drive voltage of approximately -5V is recommended to prevent mis-turn-on. On the other hand, in conventional IC processes used when the gate drive device 4 is configured as an IC, the gate-source breakdown voltage of the MOSFET is typically, for example, 5V or 3.3V.

[0084] When the gate drive device 4, configured as an IC, is required to push-pull output 20V and -5V for gate drive of the semiconductor switching element 7, which is a SiC-MOSFET, the gate withstand voltage of the MOS transistor provided in the drive circuit 15, which is the output transistor, needs to be at least about 25V. Furthermore, considering the excessive voltage fluctuations in reality, the gate withstand voltage needs a margin of at least 10V. Therefore, in this embodiment, the gate withstand voltage of the MOS transistor provided in the drive circuit 15 is set to about 5V, which is typical in IC manufacturing processes. And in order to achieve such a voltage as the gate drive voltage when the semiconductor switching element 7 is turned on and off, a level conversion unit 22 is provided in the pre-drive circuit 14.

[0085] The buffer section 17 includes three output buffers 17a, 17b, and 17c. Output buffer 17a receives the output signal from the input level conversion circuit 22a and outputs a signal corresponding to the input signal to the output circuit 16a of the drive circuit 15. Output buffer 17b receives the output signal from the input level conversion circuit 22b and outputs a signal corresponding to the input signal to the output circuit 16b of the drive circuit 15. Output buffer 17a receives the output signal from the input level conversion circuit 22c and outputs a signal corresponding to the input signal to the output circuit 16c of the drive circuit 15.

[0086] The output signals of the output buffers 17a to 17c provided in the pre-drive circuit 14 of the turn-on drive unit 12 are respectively called turn-on drive signals IGON2[0], IGON2[1], and IGON2[2]. The output signals of the output buffers 17a to 17c provided in the pre-drive circuit 14 of the cut-off drive unit 13 are respectively called cut-off drive signals IGOFF2[0], IGOFF2[1], and IGOFF2[2].

[0087] Output buffers 17a to 17c each have a buffering capacity, i.e., an output capacity, corresponding to the current capability of the corresponding output circuits 16a to 16c. The buffering capacity of such output buffers 17a to 17c is determined by the size of the output buffers 17a to 17c, and more specifically by the size of the transistors disposed inside the output buffers 17a to 17c.

[0088] The driving circuit 15 is configured to provide a constant current drive to the gate of the semiconductor switching element 7. As previously described, the driving circuit 15 includes three output circuits 16a, 16b, and 16c connected in parallel. Output circuit 16a includes a Worman circuit 25a formed by connecting two MOS transistors M1a and M2a via a common source and common gate connection. The gates of the MOS transistors M1a and M2a are connected together.

[0089] Output circuit 16b includes a Waldman circuit 25b formed by connecting two MOS transistors M1b and M2b via a common source and common gate connection. The gates of MOS transistors M1b and M2b are connected together. Output circuit 16c includes a Waldman circuit 25c formed by connecting two MOS transistors M1c and M2c via a common source and common gate connection. The gates of MOS transistors M1c and M2c are connected together.

[0090] The MOS transistors M1a to M2c in the turn-on drive section 12 are all P-channel MOS transistors. The turn-on drive signal IGON2 output from the pre-drive circuit 14 is provided to the common gate of MOS transistors M1a and M2a [0]. The turn-on drive signal IGON2 output from the pre-drive circuit 14 is provided to the common gate of MOS transistors M1b and M2b [1]. The turn-on drive signal IGON2 output from the pre-drive circuit 14 is provided to the common gate of MOS transistors M1c and M2c [2].

[0091] The sources of MOS transistors M1a, M1b, and M1c in the turn-on drive unit 12 are commonly connected and connected to voltage line 26, which receives the voltage Vb. The drains of MOS transistors M1a, M1b, and M1c in the turn-on drive unit 12 are respectively connected to the sources of MOS transistors M2a, M2b, and M2c in the turn-on drive unit 12. The drains of MOS transistors M2a, M2b, and M2c in the turn-on drive unit 12 are commonly connected and connected to the gate of the semiconductor switching element 7. The voltage Vb is a voltage with the source potential of the semiconductor switching element 7 as a reference, and is a voltage sufficiently high than the gate threshold voltage of the semiconductor switching element 7. In this embodiment, the voltage Vb is, for example, 20V.

[0092] According to the above structure, the MOS transistors M1a to M2c of the output circuits 16a to 16c of the drive unit 12 are turned on and off according to the level of the drive signal IGN2[2:0]. That is, the MOS transistors M1a and M2a of the output circuit 16a are turned on when the drive signal IGN2[0] is low and turned off when the drive signal IGN2[0] is high. In other words, the output circuit 16a is turned on when the drive signal IGN2[0] is low and turned off when the drive signal IGN2[0] is high.

[0093] Furthermore, the MOS transistors M1b and M2b of the output circuit 16b are turned on when the turn-on drive signal IGN2[1] is low and turned off when the turn-on drive signal IGN2[1] is high. In other words, the output circuit 16b is turned on when the turn-on drive signal IGN2[1] is low and turned off when the turn-on drive signal IGN2[1] is high. Furthermore, the MOS transistors M1c and M2c of the output circuit 16c are turned on when the turn-on drive signal IGN2[2] is low and turned off when the turn-on drive signal IGN2[2] is high. In other words, the output circuit 16c is turned on when the turn-on drive signal IGN2[2] is low and turned off when the turn-on drive signal IGN2[2] is high.

[0094] The MOS transistors M1a to M2c in the cutoff drive section 13 are all N-channel MOS transistors. A cutoff drive signal IGOFF2 output from the pre-drive circuit 14 is provided to the common gate of MOS transistors M1a and M2a [0]. A cutoff drive signal IGOFF2 output from the pre-drive circuit 14 is provided to the common gate of MOS transistors M1b and M2b [1]. A cutoff drive signal IGOFF2 output from the pre-drive circuit 14 is provided to the common gate of MOS transistors M1c and M2c [2].

[0095] The sources of MOS transistors M1a, M1b, and M1c in the cutoff drive section 13 are commonly connected and connected to voltage line 27, which receives the voltage Vc. The drains of MOS transistors M1a, M1b, and M1c in the cutoff drive section 13 are respectively connected to the sources of MOS transistors M2a, M2b, and M2c in the cutoff drive section 13. The drains of MOS transistors M2a, M2b, and M2c in the cutoff drive section 13 are commonly connected and connected to the gate of the semiconductor switching element 7. The voltage Vc is a voltage that is at the same potential as or lower than the source potential of the semiconductor switching element 7. In this embodiment, the voltage Vc is, for example, -5V.

[0096] According to the above structure, the MOS transistors M1a to M2c of the output circuits 16a to 16c of the cutoff drive unit 13 are turned on and off according to the level of the cutoff drive signal IGOFF2[2:0]. That is, the MOS transistors M1a and M2a of the output circuit 16a are turned on when the cutoff drive signal IGOFF2[0] is high and turned off when the cutoff drive signal IGOFF2[0] is low. In other words, the output circuit 16a is turned on when the cutoff drive signal IGOFF2[0] is high and turned off when the cutoff drive signal IGOFF2[0] is low.

[0097] In addition, the MOS transistors M1b and M2b of the output circuit 16b are turned on when the cutoff drive signal IGOFF2[1] is high and turned off when the cutoff drive signal IGOFF2[1] is low. In other words, the output circuit 16b is turned on when the cutoff drive signal IGOFF2[1] is high and turned off when the cutoff drive signal IGOFF2[1] is low.

[0098] In addition, the MOS transistors M1c and M2c of the output circuit 16c are turned on when the cutoff drive signal IGOFF2[2] is high and turned off when the cutoff drive signal IGOFF2[2] is low. In other words, the output circuit 16c is turned on when the cutoff drive signal IGOFF2[2] is high and turned off when the cutoff drive signal IGOFF2[2] is low.

[0099] According to the above structure, at least one of the output circuits 16a, 16b, and 16c of the drive unit 12 is turned on, thereby allowing the gate current Ig_on to flow and turning on the semiconductor switching element 7. In this case, by saturating the MOS transistors M1a to M2c, a constant current source operation can be performed, and the gate current Ig_on can be kept fixed. Furthermore, in the above structure, the current value of the gate current Ig_on can be changed according to the number of turned-on output circuits 16a, 16b, and 16c.

[0100] Furthermore, according to the above structure, by turning on at least one of the output circuits 16a, 16b, and 16c of the cutoff drive unit 13, the gate current Ig_off flows through, thereby turning off the semiconductor switching element 7. In this case, by saturating the MOS transistors M1a to M2c, a constant current source operation can be performed, and the gate current Ig_off can be kept fixed. Moreover, in the above structure, the current value of the gate current Ig_off can be changed according to the number of output circuits 16a, 16b, and 16c that are turned on.

[0101] Output circuits 16a to 16c are configured with different current capabilities. Specifically, the current capabilities of each of output circuits 16a to 16c are set to a ratio of 2 to the power of N, where N is 0, ..., k-1, k, and k is a predetermined natural number. In this embodiment, the ratio of the current capabilities of output circuits 16a to 16c is set such that when the current capability of output circuit 16a is set to "1", the current capability of output circuit 16b is "2" and the current capability of output circuit 16c is "4". In this embodiment, the ratio of the current capabilities of output circuits 16a to 16c is set as follows.

[0102] That is, in this case, the MOS transistors constituting the Walman circuit have different sizes. Specifically, the size of each MOS transistor is set such that when the size of MOS transistors M1a and M2a constituting the Walman circuit 25a constituting the output circuit 16a is set to "1", the size of MOS transistors M1b and M2b constituting the Walman circuit 25b constituting the output circuit 16b is set to "2" and the size of MOS transistors M1c and M2c constituting the Walman circuit 25c constituting the output circuit 16c is set to "4".

[0103] Based on the above structure, the gate current Ig can be changed to eight different values. Specifically, based on the above structure, when the gate current Ig is set to "1" when the output circuit 16a is turned on and the output circuits 16b and 16c are turned off, the gate current Ig can be changed in eight levels: "0", "1", "2", "3", "4", "5", "6", and "7".

[0104] <Timing of each part during opening and closing>

[0105] Next, refer to Figure 5 The operating timing of each part of the gate drive device 4 when the semiconductor switching element 7 is turned on and off will be explained. Furthermore, in various embodiments, including this embodiment, the operating timing of each part is explained using the case where the semiconductor switching element 7 is off as an example. However, the operating timing of each part when the semiconductor switching element 7 is turned on is generally the same, except for the difference between on and off states. Additionally, in Figure 5 In the instruction signal Sa, the period representing the level of the turn-on instruction is marked as "ON", and the period representing the level of the turn-off instruction is marked as "OFF".

[0106] In addition, Figure 5In this process, the command value of the gate current Ig_off calculated by the arithmetic circuit 11 is used as the calculation result, and this value is represented as the aforementioned changeable 8th-order value. In this case, the arithmetic circuit 11 switches the command value of the gate current Ig_off represented by the current command signal in three stages in the form of "6" → "3" → "4". When the controller 5 provides the command signal Sa indicating the turn-on command at time point t0, the arithmetic circuit 11 outputs the current command signal on the off side, that is, the 3-bit turn-off command signal IGOFF1[2:0], to the pre-drive circuit 14.

[0107] Subsequently, the pre-drive circuit 14 receives the 3-bit cutoff command signal IGOFF1[2:0], but their propagation times differ due to propagation path differences, component deviations, etc. In this case, the pre-drive circuit 14 outputs a 3-bit cutoff drive signal IGOFF2[2:0] through the operation of the glitch suppression unit 21, causing the turn-on command edge to be delayed by a predetermined time compared to the cutoff command edge. For ease of explanation, the second delay time assigned to the cutoff command edge is assumed to be zero. Furthermore, in... Figure 5 In this context, the first delay time assigned to the edge of the turn-on command is denoted as td1.

[0108] In this case, when the command value of the gate current Ig_off is switched, although there are periods Ta and Tb during which the gate current Ig_off changes to a value deviating from the command value due to the influence of glitches, the glitch suppression unit 21 implements a countermeasure that delays the turn-on command edge by a predetermined time compared to the turn-off command edge. As a result, the generation of glitches that cause the gate current Ig_off to change to a value larger than the command value can be prevented. Furthermore, a glitch refers to a sharp, pulse-like waveform generated due to the difference in signal delay time.

[0109] Based on the embodiment described above, the following effects can be obtained. First, refer to... Figure 6 and Figure 7 This will explain the effects that can be obtained by the gate driving device 4 of this embodiment, as clearly demonstrated by comparison with prior art 1. Furthermore, here, the advantages of prior art 1 will be discussed... Figure 1 The structure is compared with the gate drive device 4 of this embodiment. In the structure of the prior art 1, by changing the value of the reference voltage Vref of the reference power supply 32, the voltage applied to the shunt resistor 20, that is, the voltage "Vcc-Vm" obtained by subtracting the voltage Vm of the flip-flop input terminal of the OP amplifier 34 from the power supply voltage Vcc of the power supply 40, can be changed. As a result, the gate current of the load 10, which is the IGBT, can be operated.

[0110] like Figure 6As shown, in the prior art 1 with such a structure, if the gate current Ig is changed during the gate switching period, the gate current Ig cannot be switched at a high speed due to the delay in the feedback loop generated by the OP amplifier 34. Specifically, as Figure 6 As shown, in prior art 1, when the gate current Ig is changed, it may take more than 100 ns until the gate current Ig reaches the desired value. Furthermore, in Figure 6 and Figure 7 In the diagram, the ideal waveform of the gate current Ig is represented by a dashed line.

[0111] In contrast, in the gate driving device 4 of this embodiment, the main reason for the delay from the time point when the command value of the gate current Ig changes to the time point when the actual gate current Ig changes is the propagation delay of the MOS transistors M1a to M2c in the output circuits 16a to 16c. Therefore, compared with the prior art 1, the gate current Ig can be switched at a higher speed, that is, the responsiveness of the gate current Ig control can be improved. Specifically, as Figure 7 As shown, in the gate driving device 4 of this embodiment, when the gate current Ig is changed, it is possible to achieve a design where the delay time until the gate current Ig reaches the desired value is suppressed to about 10 ns. Furthermore, in the gate driving device 4 of this embodiment, an operational amplifier is not required, thus avoiding the increase in circuit size as in the prior art 1.

[0112] Next, refer to Figures 8-12 This will explain the effects that can be obtained by the gate driving device 4 of this embodiment, as clearly demonstrated by comparison with prior art 2. Furthermore, Figure 8 and Figure 9 Output circuit 16a is selected from one of the multiple parallel-connected output circuits 16a to 16c on the disconnected side. In prior art 2, the gate current Ig can be controlled by changing the number of output circuits that are turned on, similar to this embodiment. However, in prior art 2, the output circuit is composed of a single MOS transistor. That is, the output circuit of prior art 2 is as follows: Figure 8 As shown, the output circuit 16a of this embodiment omits the structure of the MOS transistor M2a.

[0113] In this configuration, the drain of the MOS transistor M1a is connected to the gate of the semiconductor switching element 7. In this structure, the saturation current of the MOS transistor M1a varies according to the voltage Vds of the MOS transistor M1a due to the channel length modulation effect. That is, as... Figure 10As shown, the saturation current Id of the MOS transistor M1a should ideally not change with voltage Vds, but in reality, it varies with voltage Vds due to channel length modulation. Furthermore, in Figure 10 In the diagram, the actual saturation current is represented by a solid line, and the ideal saturation current is represented by a dashed line.

[0114] When the gate current Ig flows, i.e. during the period when the gate current Ig is output, the gate-source voltage Vgs of the semiconductor switching element 7 changes, and correspondingly, the voltage Vds of the MOS transistor M1a also changes. As a result, the current Id of the MOS transistor M1a changes, and it is impossible to output a fixed gate current Ig. That is, in the prior art 2, the accuracy of the gate current Ig is low. In addition, in the following description, the gate-source voltage Vgs is sometimes simply referred to as voltage Vgs.

[0115] In contrast, the output circuit 16a of this embodiment is as follows: Figure 9 The diagram shows a structure where two MOS transistors, M1a and M2a, are connected in a common-source, common-gate configuration. With this structure, the drain-source voltage Vds2 of the MOS transistor M2a, which is different from the source-ground side, absorbs fluctuations in the voltage Vgs of the semiconductor switching element 7. Therefore, the drain-source voltage Vds1 of the MOS transistor M1a, which is on the source-ground side, can remain approximately constant. Furthermore, in this case, the value of the gate current Ig is primarily determined by the MOS transistor M1a.

[0116] Therefore, according to the structure of this embodiment, even with channel length modulation, fluctuations in the gate current Ig associated with changes in the voltage Vgs of the semiconductor switching element 7 can be suppressed, thus improving the accuracy of the gate current Ig compared to the prior art 2. Regarding these effects obtainable by this embodiment, [further details can be provided]. Figure 11 and Figure 12 The simulation results shown provide a clearer picture. Furthermore, Figure 11 and Figure 12 The prior art 2 and this embodiment show the voltage and current waveforms of each part of the semiconductor switching element 7 when it is turned off.

[0117] like Figure 11 and Figure 12 As shown, when observing the period during which the voltage Vgs changes from 15V to 0V, the gate current Ig changes by about 17% in the prior art 2, but only by about 5% in this embodiment. In the prior art 2, the reason for the increased change in the gate current Ig is that the voltage Vds of the MOS transistor M1a changes according to the change in the voltage Vgs of the semiconductor switching element 7.

[0118] In contrast, in this embodiment, such as Figure 12 As shown, the voltage Vds2 of the cascode MOS transistor M2a varies according to the voltage Vgs of the semiconductor switching element 7. In other words, the MOS transistor M2a bears the variation in the voltage Vgs of the semiconductor switching element 7. Therefore, the voltage Vds1 of the MOS transistor M1a, which mainly determines the value of the gate current Ig, remains approximately constant regardless of the variation in the voltage Vgs of the semiconductor switching element 7. As a result, variations in the gate current Ig can be suppressed. Furthermore, in Figure 12 In the diagram, voltage Vds1 is represented by a solid line, and voltage Vds2 is represented by a dashed line.

[0119] Furthermore, in the structure of prior art 2, multiple pre-drive circuits are required to improve the switching resolution of the gate current Ig, thus increasing the circuit size. Specifically, in the structure of prior art 2, 63 output circuits are required to perform 64-level switching of the gate current Ig, and 63 pre-drive circuits are also required to drive these 63 output circuits. Additionally, the drive circuit 12 and pre-driver 18 in prior art 2 correspond to the circuits constituting the output circuits 16a to 16c and the pre-drive circuit 14 in this embodiment.

[0120] In contrast, in this embodiment, the current capability of each of the multiple output circuits 16a to 16c, more specifically the size of the MOS transistors M1a to M2c, is set to a ratio of 2 to the power of N. Therefore, assuming that the gate current Ig needs to be switched in 64 stages as in the prior art 2, only six structures identical to those of the output circuits 16a to 16c are needed, as are six structures identical to those of the circuits constituting the pre-drive circuit 14. Thus, according to this embodiment, while setting the switching resolution of the gate current Ig to the same level, the circuit size can be reduced compared to the prior art 2.

[0121] Furthermore, for the reasons mentioned above, level conversion circuits 22a to 22c are often provided in the pre-drive circuit 14. Because level conversion circuits 22a to 22c require a certain withstand voltage, their circuit size tends to increase. Therefore, the effect of reducing circuit size obtained by this embodiment is particularly significant when level conversion circuits 22a to 22c are provided in the pre-drive circuit 14. As explained above, according to the structure of this embodiment, excellent effects can be achieved, such as the ability to change the gate current Ig with high precision and improve the responsiveness of gate current Ig control without increasing the circuit size.

[0122] In this embodiment, the pre-drive circuit 14 includes multiple output buffers 17a-17c, each corresponding to one of the multiple output circuits 16a-16c of the drive circuit 15. Furthermore, each of the multiple output circuits 16a-16c is configured with different current capabilities, and each of the multiple output buffers 17a-17c has a buffering capacity corresponding to the current capability of its corresponding output circuit 16a-16c. With this structure, the propagation delays of the MOS transistors M1a-M2c in the output circuits 16a-16c can be equalized, thus ensuring that the turn-on and turn-off times of each MOS transistor M1a-M2c are consistent. As a result, the generation of glitches can be suppressed.

[0123] The pre-drive circuit 14 includes a glitch suppression section 21 for delaying the edge of the transition from the second level to the first level (i.e., the turn-on command edge) compared to the edge of the transition from the first level to the second level (i.e., the turn-off command edge) for each of the multiple command signals. Thus, the pre-drive circuit 14 generates and outputs a drive signal such that the first delay time required for the MOS transistors M1a to M2c to transition from turn-off to turn-on is longer than the second delay time required for the MOS transistors M1a to M2c to transition from turn-on to turn-off.

[0124] Hereinafter, the effects obtained by this structure will be explained while comparing the structure of this embodiment with that of the first comparative example, which does not have the burr suppression part 21. Figure 13 Only the structure of the disconnected side of the gate drive device in the first comparative example is shown. Figure 13 As shown, the pre-drive circuit 14A of the first comparative example differs from the pre-drive circuit 14 of this embodiment in that it omits the glitch suppression unit 21. In this case, the cutoff command signal IGOFF1[2:0] is directly input to the level conversion unit 22.

[0125] In the structure of the first comparative example, the cutoff drive signal IGOFF2[2:0] output from the pre-drive circuit 14A is obtained by assigning a delay time corresponding to the propagation delay of each path to the cutoff command signal IGOFF1[2:0]. Therefore, as Figure 14 As shown, due to the difference in propagation delay between paths, there is a spike in the gate current Ig_off, which changes towards a value larger than the command value. That is, there is a period Tc during which an excessively large gate current Ig_off is generated. In the case of an excessively large gate current Ig_off, the semiconductor switching element 7 may fail due to an excessively large surge voltage Vsrg, and peripheral equipment may malfunction due to increased EMI.

[0126] In contrast, in this embodiment, a countermeasure is implemented using the glitch suppression section 21 provided in the pre-drive circuit 14 to delay the turn-on command edge of the drive signal IGOFF2[2:0] by a predetermined time compared to the turn-off command edge. As a result, the generation of glitch that causes the gate current Ig_off to change to a value larger than the command value can be reliably avoided. Therefore, according to this embodiment, the excessive generation of gate current can be suppressed, thereby preventing the generation of excessive surge voltage Vsrg and the increase of EMI.

[0127] In this embodiment, the gates of the two MOS transistors in each of the Worman circuits 25a to 25c are connected together. This eliminates the need for an additional bias voltage circuit, thus enabling the suppression of gate current Ig fluctuations using the simplest possible structure.

[0128] <Variations related to command signal output circuits>

[0129] In this embodiment, the instruction signal output circuit employs an arithmetic circuit 11 that outputs a current instruction signal representing the result of calculating the instruction value of the gate current Ig based on the element association information. However, it is also possible, for example, to employ a structure that outputs a current instruction signal representing the instruction value of the predetermined gate current Ig, as in the prior art 2.

[0130] In this embodiment, the arithmetic circuit 11, which functions as an instruction signal output circuit, is structured to output a 3-bit turn-on instruction signal IGON1[2:0] and a 3-bit turn-off instruction signal IGOFF1[2:0]. However, as an instruction signal output circuit, it is acceptable to output a current instruction signal consisting of multiple instruction signals, i.e., a current instruction signal composed of two or more instruction signals.

[0131] In this embodiment, the arithmetic circuit 11, which functions as a command signal output circuit, can switch the command value represented by the current command signal on the on side and the off side to a second-order or higher level. However, such switching of command value may also apply only to one of the on side and the off side. For example, if the surge voltage Vsrg on the off side is much larger than that on the on side, the switching of command value may be applied only to the off side.

[0132] <Variations related to the pre-drive circuit>

[0133] In this embodiment, the glitch suppression circuits 21a-21c include a CR filter 23 and an AND circuit 24, but their specific structures can be appropriately modified as long as they can achieve the same function. In this embodiment, the glitch suppression section 21 is disposed in front of the level conversion section 22, but it can also be disposed in the rear of the level conversion section 22.

[0134] In this embodiment, glitch suppression circuits 21a to 21c are provided in such a way that they correspond to each of the multiple command signals, i.e., the multiple output circuits 16a to 16c. However, glitch suppression circuits can also be provided in a way that they correspond to at least one of the multiple command signals. For example, the glitch suppression circuit can be provided in a way that it corresponds only to the output circuit 16c, which has the largest MOS transistor among the output circuits 16a to 16c. In this case, the glitch suppression effect can be maintained, and thus the generation of excessive gate current Ig can be suppressed.

[0135] In this embodiment, the pre-drive circuit 14 has a structure including a level conversion unit 22, but the level conversion unit 22 can be provided as needed or omitted. In this embodiment, a method is used to set the buffering capacity of the output buffers 17a to 17c to a desired value based on their sizes. However, a method can also be used where multiple small output buffers are connected in parallel according to their respective output circuits 16a to 16c, and the buffering capacity is set to a desired value by adjusting the number of these connected output buffers.

[0136] <Variations related to drive circuits>

[0137] In this embodiment, the two MOS transistors constituting the output circuits 16a to 16c are set to have the same size, but they can also be set to have different sizes. Furthermore, when the two MOS transistors are set to different sizes, the gate current Ig is limited by the MOS transistor with the smaller saturation current. In this embodiment, the current capability of each of the output circuits 16a to 16c is set to a ratio of 2 to the power of N, but it can also be set to various ratios such as "1:10".

[0138] In this embodiment, the two MOS transistors constituting the Worman circuits 25a to 25c have their gates connected together, meaning that the same gate voltage is provided to both MOS transistors constituting the Worman circuits 25a to 25c. However, various modifications can be made to the structure used to provide the gate voltage to these two MOS transistors. Several modifications related to the structure used to provide the gate voltage to the aforementioned two MOS transistors will be described below.

[0139] Furthermore, in the following description, the various modifications will be explained using MOS transistors M1a and M2a, which constitute the cutoff drive section 13 of the two MOS transistors constituting the Worman circuits 25a to 25c, as examples. Also, in the following description, the MOS transistor with its source ground side in the two MOS transistors constituting the Worman circuits 25a to 25c will be designated as the first transistor, and a MOS transistor different from the one with its source ground side will be designated as the second transistor. Therefore, in the following description, MOS transistor M1a will sometimes be referred to as the first transistor M1a, and MOS transistor M2a will sometimes be referred to as the second transistor M2a.

[0140] [1] First variation

[0141] like Figure 15 As shown, in the structure of the first modified example, a cutoff drive signal IGOFF2[0] is provided as a drive signal to the gate of the first transistor M1a. Although omitted in the description of the above embodiment, a power supply voltage VDD1 is supplied to the output buffers 17a to 17c of the pre-drive circuit 14 to turn on the corresponding MOS transistors of the output circuits 16a to 16c. In this case, a fixed voltage is applied to the gate of the second transistor M2a, which is the same as the power supply voltage VDD1 that turns on the first transistor M1a. With this structure, the second transistor M2a on the gate ground side always operates in the on state.

[0142] According to this first modification, the following effect can be obtained. That is, in the structure of the first embodiment, when the gate current Ig is output, the pre-drive circuit 14 needs to turn on both the first transistor M1a and the second transistor M2a. In contrast, in the first modification, when the gate current Ig is output, the pre-drive circuit 14 only needs to turn on the first transistor M1a.

[0143] Therefore, according to the first variation, compared to the first embodiment, the input capacitance of the capacitive load to be driven by the pre-drive circuit 14, i.e., the MOS transistor to be driven, is reduced to about 1 / 2, enabling a faster output of the gate current Ig. Furthermore, according to the first variation, if the responsiveness is sufficient, the size of the output buffer 17a of the pre-drive circuit 14 can be reduced compared to the first embodiment to achieve circuit miniaturization.

[0144] [2] Second variation

[0145] like Figure 16 As shown, the second variant is relative to Figure 15The first variation shown differs in that the voltage supplied to the gate of the second transistor M2a is changed. In this case, a power supply voltage VDD2 is applied to the gate of the second transistor M2a. The value of the power supply voltage VDD2 is set based on the following considerations. Furthermore, hereinafter, the gate-source voltage of the first transistor M1a is sometimes referred to as voltage Vgs1 and the gate-source voltage of the second transistor M2a is sometimes referred to as voltage Vgs2. Additionally, hereinafter, the drain-source voltage of the first transistor M1a is sometimes referred to as voltage Vds1 and the drain-source voltage of the second transistor M2a is sometimes referred to as voltage Vds2.

[0146] That is, the second variation is a structure that aims to increase the voltage Vgs2 compared to the voltage Vgs1, i.e., to provide a higher voltage to the gate of the second transistor M2a than to the gate of the first transistor M1a. Therefore, the power supply voltage VDD2 needs to be a higher voltage than the power supply voltage VDD1. That is, the power supply voltages VDD1 and VDD2 need to satisfy the relationship of equation (1) below.

[0147] VDD1<VDD2…(1)

[0148] On the other hand, in order to achieve the aforementioned Wolman action, that is, in order to achieve the action that the voltage Vds2 follows the change of the voltage Vgs of the semiconductor switching element 7 so that the voltage Vds1 is relatively fixed and independent of the change of the voltage Vgs of the semiconductor switching element 7, the voltage Vgs2 needs to be smaller than the voltage Vgs1. That is, the voltages Vgs1 and Vgs2 need to satisfy the relationship of the following equation (2).

[0149] Vgs2<Vgs1…(2)

[0150] Furthermore, in order to keep the gate current Ig fixed, the first transistor M1a needs to operate in the saturation region. In order for the first transistor M1a to operate in the saturation region, the voltages of the first transistor M1a need to satisfy the following relationship (3). Wherein, Vth is the gate threshold voltage of the first transistor M1a.

[0151] Vds1>Vgs1-Vth=VDD1-Vth...(3)

[0152] Based on equation (3) above, we derive equation (4) below, which represents the voltage Vgs.

[0153] Vgs2=VDD2-Vds1<VDD2-VDD1+Vth...(4)

[0154] Based on equations (2) and (4) above, equation (5) is derived below.

[0155] VDD2-VDD1+Vth<VDD1…(5)

[0156] If equation (5) above is transformed, it becomes equation (6) below.

[0157] VDD2<2×VDD1-Vth…(6)

[0158] Based on equations (1) and (6) above, equation (7) is derived below.

[0159] VDD1<VDD2<2×VDD1-Vth…(7)

[0160] The power supply voltage VDD2 becomes a voltage that satisfies the relationship in equation (7) above. That is, the power supply voltage VDD2 becomes a fixed voltage that is higher than the power supply voltage VDD1 and lower than the voltage obtained by subtracting the gate threshold voltage Vth of the first transistor M1a from twice the power supply voltage VDD1. With this structure, similar to the first variant, the second transistor M2a on the gate ground side also always operates in the on state.

[0161] According to this second modification, in addition to the same effects as the first modification, the following further effects can be obtained: According to the second modification, a higher voltage Vgs2 can be applied to the second transistor M2a compared to the first modification, resulting in a larger gate current Ig being output. In other words, according to the second modification, given a design that aims to output a specified gate current Ig, the size of the MOS transistors M1a and M2a in the output circuit 16a can be reduced compared to the first modification. Consequently, the size of the output buffer 17a of the pre-drive circuit 14 can also be minimized, thus enabling significant miniaturization of the circuit.

[0162] The second variation is able to output a larger gate current Ig than the first variation, based on the fact that... Figure 17 The simulation results shown also clearly demonstrate this. Furthermore, in Figure 17 In the diagram, the waveforms corresponding to the first modified example and the gate current Ig of the semiconductor switching element 7 are represented by solid lines, while the waveforms corresponding to the second modified example are represented by dashed lines. Furthermore, in... Figure 17 In the diagram, the output of the output buffer 17a of the pre-drive circuit 14, i.e. the voltage Vgs1 of the first transistor M1a, is represented by a solid line, and the power supply voltage VDD2, i.e. the voltage Vgs2 of the second transistor M2a, is represented by a dashed line.

[0163] In this case, the power supply voltage VDD1 in the structures of the first and second modifications is set to 5V, and the power supply voltage VDD2 in the structure of the second modification is set to 6V. Therefore, as Figure 17As shown, in the second variation, the voltage Vgs2 of the second transistor M2a is 1V higher than the voltage Vgs1 of the first transistor M1a, that is, 1V higher than the voltage Vgs2 of the second transistor M2a in the first variation. Therefore, in the second variation, compared to the first variation, for example when the voltage Vgs of the semiconductor switching element 7 is 10V, the output gate current Ig increases by approximately 39%.

[0164] [3] Third variation

[0165] like Figure 18 As shown, the third variation is relative to Figure 15 The first variant shown differs in that the voltage supplied to the gate of the second transistor M2a is changed and a Zener diode ZD1 is added. In this case, a power supply voltage VDD3 is applied to the gate of the second transistor M2a. As shown in equation (8) below, the power supply voltage VDD3 becomes a fixed voltage that is higher than the power supply voltage VDD1.

[0166] VDD1<VDD3…(8)

[0167] In this case, the Worman circuit 25a also includes a Zener diode ZD1 connected between the gate and source of the second transistor M2a. As shown in equation (9) below, the Zener voltage Vz of the Zener diode ZD1 becomes a voltage lower than the power supply voltage VDD1.

[0168] Vz<VDD1…(9)

[0169] With this structure, similar to the second modification, the second transistor M2a on the gate-ground side also operates in a always-on state. Furthermore, in the above structure, the voltage Vgs2 of the second transistor M2a is limited by the Zener diode ZD1 to a voltage lower than the power supply voltage VDD1, that is, a voltage lower than the voltage Vgs1 of the first transistor M1a. Therefore, the third modification can also achieve the same effect as the second modification. Moreover, the structure used to limit the voltage Vgs2 is not limited to the Zener diode ZD1; any structure that can achieve the same function can be modified appropriately.

[0170] [3] Fourth variation

[0171] like Figure 19 As shown, the fourth variation is relative to Figure 15The first variant shown differs in that it changes the voltage supplied to the gate of the second transistor M2a. The Walman circuit 25a also includes a level-shifting circuit 29. The level-shifting circuit 29 outputs a signal that has level-shifted the cutoff drive signal IGOFF2[0] to a higher voltage. The output signal of the level-shifting circuit 29 is supplied to the gate of the second transistor M2a. That is, in this case, a signal that has level-shifted the cutoff drive voltage IGOFF2[2:0], which serves as the drive signal, to a higher voltage is supplied to the gate of the second transistor M2a. According to this structure, the second transistor M2a switches between the on and off states at the same time as the first transistor M1a.

[0172] In this case, the level conversion circuit 29 outputs a signal that raises the high level of the cutoff drive signal IGOFF[2:0] from the power supply voltage VDD1 to the power supply voltage VDD4. The voltage value of the power supply voltage VDD4 can be set in the same way as the power supply voltage VDD2 in the second variation. Furthermore, the voltage value of the power supply voltage VDD4 can be set in the same way as the power supply voltage VDD3 in the third variation. However, in this case, the same Zener diode ZD1 as in the third variation needs to be added.

[0173] According to the fourth variation, a higher voltage Vgs2 can be applied to the second transistor M2a compared to the first variation, resulting in a larger gate current Ig being output. In other words, according to the fourth variation, given a design that outputs a specified gate current Ig, the size of the MOS transistors M1a and M2a in the output circuit 16a can be reduced compared to the first variation. Consequently, the size of the output buffer 17a in the pre-drive circuit 14 can also be reduced, thus enabling a significant miniaturization of the circuit.

[0174] (Second Implementation)

[0175] The following is for reference Figures 20-22 The following describes a second embodiment that alters the specific structure of the gate driving device compared to the first embodiment.

[0176] <Specific Structure of Gate Driving Device>

[0177] like Figure 20 As shown, the gate driving device 31 of this embodiment differs from the gate driving device 4 of the first embodiment in that it includes a pre-driving circuit 32 instead of a pre-driving circuit 14 and a driving circuit 33 instead of a driving circuit 15. Furthermore, in Figure 20 Only the structure of the disconnect side of the gate drive device 31 is shown, but the structure of the on side can also adopt the same structure as the disconnect side.

[0178] The pre-drive circuit 32 differs from the pre-drive circuit 14 in that it replaces the glitch suppression unit 21 and has a glitch suppression unit 34, etc. Although the glitch suppression unit 34 has three glitch suppression circuits 34a, 34b, and 34c that perform the same function as the glitch suppression unit 21, their circuit structures are different from those of the glitch suppression unit 21. That is, the glitch suppression circuits 34a to 34c differ from the glitch suppression circuits 21a to 21c in that they replace the CR filter 23 and have two-stage connected flip-flops 35 and 36, etc.

[0179] The input terminals of the first-stage flip-flop 35 become the input terminals of the glitch suppression circuits 34a to 34c, and are given the cutoff command signal IGOFF1[2:0]. The output terminal of flip-flop 35 is connected to the input terminal of the second-stage flip-flop 36, and also to one input terminal of the AND circuit 24. The output terminal of the second-stage flip-flop 36 is connected to the other input terminal of the AND circuit 24. A clock signal CLK is input to each clock terminal of flip-flops 35 and 36. The output terminal of the AND circuit 24 becomes the output terminal of the glitch suppression circuits 34a to 34c.

[0180] Although drive circuit 33 has three output circuits 37a, 37b, and 37c that perform the same function as drive circuit 15, their circuit structures differ from those of drive circuit 15. In this case, the three output circuits 37a to 37c each have a different number of Worman circuits. Output circuit 37a has a Worman circuit 38a formed by connecting two MOS transistors M31a and M32a in a common-source, common-gate configuration. That is, output circuit 37a has one Worman circuit 38a.

[0181] Output circuit 37b includes two sets of Waldman circuits 38b formed by connecting two MOS transistors M31b and M32b via a common source and common gate connection. That is, output circuit 37b includes two Waldman circuits 38b. Output circuit 37c includes four sets of Waldman circuits 38c formed by connecting two MOS transistors M31c and M32c via a common source and common gate connection. That is, output circuit 37c includes four Waldman circuits 38c.

[0182] MOS transistors M31a to M32c are all N-channel MOS transistors. The gates of MOS transistors M31a and M32a in output circuit 37a are connected together, and the cutoff drive signal IGOFF2 output from pre-drive circuit 32 is provided to these connected gates [0]. The gates of MOS transistors M31b and M32b in output circuit 37b are connected together, and the cutoff drive signal IGOFF2 output from pre-drive circuit 32 is provided to these connected gates [1]. The gates of MOS transistors M31c and M32c in output circuit 37c are connected together, and the cutoff drive signal IGOFF2 output from pre-drive circuit 32 is provided to these connected gates [2].

[0183] The sources of MOS transistors M31a, M31b, and M31c are commonly connected and connected to voltage line 27, which receives the voltage Vc. The drains of MOS transistors M31a, M31b, and M31c are respectively connected to the sources of MOS transistors M32a, M32b, and M32c. The drains of MOS transistors M32a, M32b, and M32c are commonly connected and connected to the gate of semiconductor switching element 7.

[0184] Thus, output circuit 37a is structured as a single Worman circuit 38a, output circuit 37b is structured as two Worman circuits 38b connected in parallel, and output circuit 37c is structured as four Worman circuits 38c connected in parallel. The MOS transistors M31a to M32c in output circuits 37a to 37c are similarly turned on and off according to the level of the cutoff drive signal IGOFF2[2:0], as in the output circuits 16a to 16c of the first embodiment.

[0185] With the above structure, similar to the structure of the first embodiment, the semiconductor switching element 7 is turned off by turning on at least one of the output circuits 37a to 37c, allowing the gate current Ig_off to flow through it. In this case, a constant current source operation can be performed by saturating the MOS transistors M31a to M32c, and the gate current Ig_off can be kept fixed. Furthermore, with the above structure, the current value of the gate current Ig_off can be changed according to the number of output circuits 37a to 37c that are turned on.

[0186] The current capability of each of the output circuits 37a to 37c is set to a power of 2 ratio, similar to that of the output circuits 16a to 16c in the first embodiment. In this embodiment, the ratio of the current capabilities of each of the output circuits 37a to 37c is set as follows: That is, in this case, the MOS transistors M31a to M32c constituting the Worman circuits 38a to 38c have the same size. However, in this case, each of the three output circuits 37a to 37c has a different number of Worman circuits.

[0187] Specifically, output circuit 37a includes one Walman circuit 38a, output circuit 37b includes two Walman circuits 38b connected in parallel, and output circuit 37c includes four Walman circuits 38c connected in parallel. That is, in this embodiment, the number of parallel Walman circuits 38a in output circuit 37a is "1", the number of parallel Walman circuits 38b in output circuit 37b is "2", and the number of parallel Walman circuits 38c in output circuit 37c is "4". With the above structure, the gate current Ig can be changed to eight different types in the same way as in the first embodiment.

[0188] <Layout example of pre-drive circuit and drive circuit>

[0189] The planar layout of the circuit elements constituting the pre-driving circuit 32 and the driving circuit 33 can, for example, adopt... Figure 21 The configuration shown is as follows. Figure 21 As shown, the centroids are configured such that the centroids of regions Tr1 of the MOS transistors M31a and M32a to form the Waltmann circuit 38a, the two regions Tr2 of the MOS transistors M31b and M32b to form the Waltmann circuit 38b, and the four regions Tr3 of the MOS transistors M31c and M32c to form the Waltmann circuit 38c are each a single point.

[0190] With this configuration, deviations in the gate current Ig caused by in-plane characteristic deviations can be eliminated. Furthermore, it can suppress the generation of glitches caused by characteristic deviations in the input capacitances of the MOS transistors M31a to M32c that constitute the output circuits 37a to 37c.

[0191] The regions PD1 (corresponding to the output circuit 37a of the drive circuit 33), PD2 (corresponding to the output circuit 37b of the drive circuit 33), and PD3 (corresponding to the output circuit 37c of the drive circuit 33) in the circuit elements constituting the pre-drive circuit 32 are configured such that the lengths of the wiring used to provide drive signals from the pre-drive circuit 32 to the drive circuit 33 are consistent. Furthermore, in Figure 21In the diagram, each wiring is represented schematically using simple arrows.

[0192] With this configuration, the wiring length from the operational circuit 11 to the MOS transistors M31a to M32c of the output circuits 37a to 37c can be made consistent, that is, the wiring length can be equalized. As a result, the signal propagation delay caused by the parasitic components of the wiring can be equalized, thereby suppressing the generation of glitches.

[0193] <Timing of each part during opening and closing>

[0194] Next, refer to Figure 22 To explain the timing of the operation of each part of the gate drive device 31 when the semiconductor switching element 7 is turned on and off. In this case, the operation circuit 11 is also assumed to switch the command value of the gate current Ig_off represented by the current command signal, that is, the 3-bit cutoff command signal IGOFF1[2:0], in three stages in the form of "6" → "3" → "4".

[0195] The pre-drive circuit 32 receives 3-bit cutoff command signals IGOFF1[2:0], but their propagation times differ due to propagation path differences, component deviations, etc. In this case, similar to the first embodiment, the pre-drive circuit 32 outputs a 3-bit cutoff drive signal IGOFF2[2:0] that delays the turn-on command edge by a predetermined time compared to the cutoff command edge through the operation of the glitch suppression unit 34. Furthermore, in Figure 22 In this context, the first delay time assigned to the turn-on command edge is denoted as td1, and the second delay time assigned to the turn-off command edge is denoted as td2.

[0196] In this case, similar to the first embodiment, when switching the command value of the gate current Ig_off, there is a period Td, Te during which the gate current Ig_off changes in a way that deviates from the command value due to the influence of glitches. However, by implementing a countermeasure by delaying the turn-on command edge by a predetermined time compared to the turn-off command edge using the glitch suppression unit 34, it is possible to prevent the generation of glitches that cause the gate current Ig_off to change to the side larger than the command value.

[0197] The gate driving device 31 of this embodiment, as described above, can also achieve the same effects as the first embodiment, namely, it can achieve excellent results such as high-precision changing of the gate current Ig and improved control responsiveness of the gate current Ig without increasing the circuit size. In addition, this embodiment can also suppress the generation of glitches in the same way as the first embodiment, especially reliably avoiding the generation of glitches that cause the gate current Ig_off to change to the side larger than the command value.

[0198] (Third Implementation)

[0199] The following is for reference Figure 23 and Figure 24 This paper describes a third embodiment that changes the specific structure of the gate driving device compared to the first embodiment.

[0200] <Main functions of gate driving devices>

[0201] like Figure 23 As shown, the gate driving device 41 of this embodiment differs from the gate driving device 4 of the first embodiment in that it includes a pre-driving circuit 42 instead of a pre-driving circuit 14. Furthermore, in Figure 23 Only a portion of the structure on the disconnected side of the gate drive device 41 is shown. More specifically, only the structure corresponding to the output circuit 16a in the output circuit 16a and the pre-drive circuit 42 is shown. Other structures may also adopt the same structure as the structure shown in the figure.

[0202] The pre-drive circuit 42 differs from the pre-drive circuit 14 in that it omits the glitch suppression circuit 21a that constitutes the glitch suppression section 21 and replaces the output buffer 17a with an output buffer 43a. In this case, the level conversion circuit 22a outputs a signal that has been level-converted from the cutoff command signal IGOFF1[0]. The output buffer 43a is formed by a push-pull output CMOS circuit including transistor Q1, which is a P-channel MOS transistor, and transistor Q2, which is an N-channel MOS transistor. Alternatively, bipolar transistors can be used as transistors Q1 and Q2 that constitute the output buffer 43a, that is, the output buffer 43a can also be formed by bipolar transistors.

[0203] In this case, the size of transistor Q1 becomes smaller than the size of transistor Q2. Therefore, the pre-drive circuit 42 has a difference between its output sinking current capability and its output sourcing current capability. Specifically, the pre-drive circuit 42 outputs a relatively large sinking current capability and a relatively small sourcing current capability.

[0204] The timing of the input and output signals of the pre-drive circuit 42 described above is as follows: Figure 24 As shown. That is, according to the above structure, by relatively reducing the size of transistor Q1 in output buffer 43a, the delay time from the turn-on command edge of cutoff command signal IGOFF1[0] to the rise of cutoff drive signal IGOFF2[0] to the level that can turn on MOS transistors M1a and M2a, i.e., the first delay time td1, becomes relatively longer.

[0205] Furthermore, according to the above structure, by making the size of transistor Q2 of output buffer 43a relatively larger, the delay time from the cutoff command edge of cutoff command signal IGOFF1[0] to the cutoff drive signal IGOFF2[0] to the level that can turn off MOS transistors M1a and M2a, i.e. the second delay time td2, is relatively shorter.

[0206] Thus, the pre-drive circuit 42 of this embodiment can generate and output a drive signal in the same manner as the structure of the first embodiment, such that the first delay time required for the MOS transistors M1a and M2a of the output circuit 16a to change from off to on is longer than the second delay time required for the MOS transistors M1a and M2a of the output circuit 16a to change from on to off.

[0207] Furthermore, when applying such a pre-drive circuit 42 to the on-side structure, it is sufficient to set the size of transistor Q1 to be larger than the size of transistor Q2. As a result, the sinking current capability of the pre-drive circuit 42 is relatively reduced, while the sourcing current capability is relatively increased. Therefore, when the pre-drive circuit 42 is applied to the on-side structure, it is also possible to generate and output a drive signal in a manner that makes the first delay time required for the MOS transistors M1a and M2a of the output circuit 16a to change from off to on longer than the second delay time required for the MOS transistors M1a and M2a of the output circuit 16a to change from on to off.

[0208] The gate driving device 41 of this embodiment, as described above, can also achieve the same effects as the first embodiment, namely, it can achieve excellent results such as high-precision changing of the gate current Ig and improved control responsiveness of the gate current Ig without increasing the circuit size. Furthermore, this embodiment can also suppress glitch generation in the same way as the first embodiment, especially reliably preventing glitch generation that causes the gate current Ig_off to change to a value larger than the command value.

[0209] Furthermore, in this embodiment, instead of providing a dedicated circuit, i.e., a glitch suppression unit 21, for imparting a delay time for glitch suppression as in the first embodiment, a difference is provided between the sinking current capability and the sourcing current capability in the output buffer 43a of the pre-drive circuit 42. This allows glitch generation to be suppressed. Therefore, compared to the first embodiment, the circuit size can be reduced, i.e., circuit miniaturization can be achieved.

[0210] (Fourth Implementation)

[0211] The following is for reference Figure 25This describes a fourth embodiment that alters the specific structure of the gate driving device compared to the first embodiment.

[0212] <Specific Structure of Gate Driving Device>

[0213] like Figure 25 As shown, the gate driving device 51 of this embodiment differs from the gate driving device 4 of the first embodiment in that it includes a pre-driving circuit 52 instead of a pre-driving circuit 14. Furthermore, in Figure 25 Only the structure of the disconnect side of the gate drive device 51 is shown, but the structure of the on side can also adopt the same structure as the disconnect side.

[0214] The pre-drive circuit 52 differs from the pre-drive circuit 14 in that it has a glitch suppression unit 53 instead of a glitch suppression unit 21. In this case, the level conversion circuits 22a to 22c output signals that have been level-converted from the cutoff command signal IGOFF1[2:0]. The glitch suppression unit 53 includes a delay circuit 54 and a state determination circuit 55. The output signals of the level conversion circuits 22a to 22c are input to the delay circuit 54.

[0215] The delay circuit 54 can delay only the turn-on command edge for the input signal and the signal obtained by level conversion of the upcoming cut-off command signal IGOFF1[2:0]. Specifically, when the enable / disable signal Sc provided by the state judgment circuit 55 becomes the level indicating the output of the disable turn-on command edge, the delay circuit 54 delays the turn-on command edge and does not output it until the enable / disable signal Sc becomes the output level of the enable turn-on command edge.

[0216] The state determination circuit 55 determines the on / off state of each of the MOS transistors M1a to M2c in the output circuits 16a to 16c. Specifically, the state determination circuit 55 includes a comparator (not shown) that compares the gate voltages of each of the MOS transistors M1a to M2c with a predetermined threshold. The predetermined threshold is set to a value corresponding to the gate threshold voltage of the MOS transistors M1a to M2c. With the above structure, the state determination circuit 55 can detect, based on the output of the comparator, that the gate voltages of the MOS transistors M1a to M2c have fallen below the threshold voltage, i.e., detect that the MOS transistors M1a to M2c have switched to the off state.

[0217] The state determination circuit 55 inputs the output signals of the level conversion circuits 22a to 22c. Based on the input signals and the signal obtained by level conversion of the cutoff command signal IGOFF1[2:0], the state determination circuit 55 can detect that a command has been provided to change one of the MOS transistors M1a to M2c of the output circuits 16a to 16c from on to off.

[0218] When the state determination circuit 55 detects that an instruction has been provided to change one of the MOS transistors M1a to M2c from on to off, it outputs a permission / disable signal Sc to the delay circuit 54, indicating the output level of the instruction to disable conduction. Then, when the state determination circuit 55 detects that all the MOS transistors targeted by the instruction to change from on to off are off, it outputs a permission / disable signal Sc to the delay circuit 54, indicating the output level of the instruction to enable conduction.

[0219] According to the above structure, the pre-drive circuit 52 can output a drive signal to turn on the specified MOS transistors M1a to M2c in the output circuits 16a to 16c from being on to being off after the state judgment circuit 55 determines that the specified MOS transistors have changed to the off state.

[0220] The gate driving device 51 of this embodiment, as described above, can also achieve the same effects as the first embodiment, namely, it can achieve excellent results such as high-precision changing of the gate current Ig and improved control responsiveness of the gate current Ig without increasing the circuit size. Furthermore, similarly to the first embodiment, this embodiment can suppress the generation of glitches, and in particular, can reliably prevent the generation of glitches that cause the gate current Ig_off to change to a value larger than the command value.

[0221] Furthermore, in this embodiment, the following effects can be achieved. Specifically, in the structures of the above embodiments, considering various factors that cause deviations, the first delay time imparted as the turn-on command edge needs to be set to a relatively long time with a certain margin. In contrast, in this embodiment, the state judgment circuit 55 can directly monitor the on / off states of the MOS transistors M1a to M2c of the output circuits 16a to 16c, and based on this monitoring result, the first delay time imparted as the turn-on command edge can be limited to the necessary minimum time. Therefore, compared to the above embodiments, according to this embodiment, the MOS transistors M1a to M2c of the output circuits 16a to 16c can be driven with a shorter delay time. As a result, the time for glitch generation is suppressed to a shorter duration, and the responsiveness of the gate current Ig control can be further improved.

[0222] (Other implementation methods)

[0223] Furthermore, the present invention is not limited to the embodiments described above and in the accompanying drawings, and can be arbitrarily modified, combined, or extended without departing from its spirit. The numerical values ​​shown in the above embodiments are illustrative and are not intended to limit the invention.

[0224] The gate driving device in the above embodiments is not limited to N-channel MOSFETs, but can also be various semiconductor switching elements such as P-channel MOSFETs and IGBTs.

[0225] This disclosure is based on embodiments, but it should be understood that this disclosure is not limited to these embodiments or structures. This disclosure also includes various modifications and equivalent variations. Furthermore, various combinations or schemes, and consequently other combinations or schemes that include only one element, or that include more than one element or less, also fall within the scope and spirit of this disclosure.

Claims

1. A gate driving device for driving the gate of a semiconductor switching element, characterized in that, have: The instruction signal output circuit outputs a current instruction signal that represents the instruction value of the current flowing to the gate of the semiconductor switching element, i.e., the gate current. A pre-drive circuit takes the current command signal as input and generates a drive signal corresponding to the current command signal for output. as well as A driving circuit that drives the gate of the semiconductor switching element based on the driving signal. The command signal output circuit switches the command value represented by the current command signal in a manner that controls the transient voltage corresponding to the voltage at the main terminal of the semiconductor switching element when the semiconductor switching element is turned on or off to the desired target value. The driving circuit is a structure formed by connecting multiple output circuits, including a Worman circuit, in parallel. The Worman circuit is a circuit formed by connecting two MOS transistors with a common source and common gate. The driving circuit drives the gate of the semiconductor switching element by turning on the MOS transistors of the output circuit, thereby allowing the gate current to flow through them. The driving circuit changes the number of MOS transistors turned on according to the instruction value represented by the driving signal, thereby changing the gate current.

2. The gate driving device according to claim 1, characterized in that, The pre-drive circuit includes multiple output buffers that are respectively configured corresponding to the multiple output circuits of the drive circuit. The multiple output circuits are each configured with different current capabilities. Each of the output buffers has a buffering capacity corresponding to the current capability of its corresponding output circuit.

3. The gate driving device according to claim 2, characterized in that, The current capability of each of the multiple output circuits is set to a power of 2. N is 0, ..., k-1, k, where k is a defined natural number.

4. The gate driving device according to claim 2 or 3, characterized in that, Each of the multiple output circuits includes a Worman circuit, and the MOS transistors constituting the Worman circuits have different sizes.

5. The gate driving device according to claim 2 or 3, characterized in that, Each of the output circuits has a different number of Worman circuits, and the MOS transistors constituting the Worman circuits are all the same size.

6. The gate driving device according to any one of claims 1 to 3, characterized in that, The pre-drive circuit generates and outputs the drive signal in such a way that the first delay time required for the MOS transistor to change from off to on is longer than the second delay time required for the MOS transistor to change from on to off.

7. The gate driving device according to claim 6, characterized in that, The current command signal includes multiple command signals corresponding to the multiple output circuits respectively. The plurality of command signals are binary signals having a first level and a second level, wherein the first level is a level indicating that the MOS transistor of the corresponding output circuit is turned on, and the second level is a level indicating that the MOS transistor is turned off. The pre-drive circuit generates the drive signal by delaying the edge of the transition from the second level to the first level (i.e., the turn-on instruction edge) from the edge of the transition from the first level to the second level (i.e., the turn-off instruction edge) for each of the multiple instruction signals.

8. The gate driving device according to claim 6, characterized in that, The pre-drive circuit has a difference between its output sinking current capability and its output sourcing current capability.

9. The gate driving device according to claim 6, characterized in that, The pre-drive circuit includes a state determination circuit that determines the on / off state of each of the MOS transistors in the plurality of output circuits. After the pre-drive circuit outputs the drive signal to change the specified MOS transistor from on to off, it outputs the drive signal to change the other MOS transistors from off to on after the state determination circuit determines that the specified MOS transistor has changed to the off state.

10. The gate driving device according to any one of claims 1 to 3, characterized in that, The two MOS transistors that make up the Worman circuit are connected together at their gates.

11. The gate driving device according to any one of claims 1 to 3, characterized in that, When the MOS transistor with its source grounded side is designated as the first transistor, and the MOS transistor with its source grounded side is designated as the second transistor, in the two MOS transistors constituting the Worman circuit, The gate of the first transistor is provided with the drive signal. The gate of the second transistor is supplied with the same fixed voltage as the power supply voltage that puts the first transistor into the on state. The second transistor always operates in the on state.

12. The gate driving device according to any one of claims 1 to 3, characterized in that, When the MOS transistor with its source grounded side is designated as the first transistor, and the MOS transistor with its source grounded side is designated as the second transistor, in the two MOS transistors constituting the Worman circuit, The gate of the first transistor is provided with the drive signal. The gate of the second transistor is subjected to a fixed voltage that is higher than the power supply voltage that puts the first transistor on but lower than the voltage obtained by subtracting the gate threshold voltage of the first transistor from twice the power supply voltage. The second transistor always operates in the on state.

13. The gate driving device according to any one of claims 1 to 3, characterized in that, When the MOS transistor with its source grounded side is designated as the first transistor, and the MOS transistor with its source grounded side is designated as the second transistor, in the two MOS transistors constituting the Worman circuit, The gate of the first transistor is provided with the drive signal. The gate of the second transistor is subjected to a fixed voltage that is higher than the power supply voltage that puts the first transistor into the on state. The second transistor always operates in the on state. The Worman circuit also includes a Zener diode connected between the gate and source of the second transistor. The Zener voltage of the Zener diode is lower than the power supply voltage.

14. The gate driving device according to any one of claims 1 to 3, characterized in that, When the MOS transistor with its source grounded side is designated as the first transistor, and the MOS transistor with its source grounded side is designated as the second transistor, in the two MOS transistors constituting the Worman circuit, The gate of the first transistor is provided with the drive signal. The gate of the second transistor is provided with a signal that levels out the drive signal to a higher voltage. The second transistor is switched between the on and off states at the same time as the first transistor.

Images