An ultra-wideband input signal buffer based on current mirror multiplication transconductance technique

Abstract

The application relates to an ultra-wideband input signal buffer based on a current mirror multiplication transconductance technology, comprising a first single-side circuit, a second single-side circuit and a cross-coupled capacitor, wherein the first single-side circuit and the second single-side circuit are mirror-symmetrically arranged and have the same structure, and the cross-coupled capacitor is connected between the first single-side circuit and the second single-side circuit; the input end of the first single-side circuit is used for connecting a system front end to input a first differential signal, and the output end is used for connecting a first subsequent circuit load; the input end of the second single-side circuit is used for connecting the system front end to input a second differential signal, and the output end is used for connecting a second subsequent circuit load; the input amplitudes of the first differential signal and the second differential signal are the same, and the phases are opposite. The buffer avoids the problem of distortion caused by asymmetric driving current, effectively expands the input and output bandwidth, and simultaneously realizes a more optimal passband signal gain flatness.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency signal direct acquisition network front-end technology, specifically relating to an ultra-wideband input signal buffer based on current mirror multiplication transconductance technology. Background Technology

[0002] Currently, analog-to-digital converters (ADCs) are widely used in various fields, including communication systems, healthcare, energy harvesting, instrumentation and measurement, motor and power control, industrial automation, and defense and aerospace, becoming a key component of modern microelectronics. However, with the rapid development of CMOS VLSI manufacturing technology and wireless infrastructure, the market has placed higher design requirements on ADCs. In particular, as input frequencies gradually increase to the GHz level, the problem of input signal sampling becomes increasingly challenging. This makes the development of the RF signal direct sampling network front-end, which is the most advanced component of the ADC system, a key focus for analog designers. Its performance largely limits and determines the signal processing capability of the entire ADC system.

[0003] Ultra-wideband input signal buffers are the mainstream network front-end architecture for direct RF signal acquisition of ultra-high-speed analog-to-digital converters currently used in the industry. They do not require mixing or filtering of the input signal and can directly buffer the RF signal to the subsequent analog-to-digital converter circuit. This overcomes the shortcomings of traditional superheterodyne receiver architectures that cannot cover wideband RF signals, and thus has become the core module for realizing direct RF acquisition.

[0004] Generally, input signal buffers operating in the radio frequency range are required to possess the following three properties: 1. Good passband signal gain flatness; 2. Wide bandwidth performance suitable for input signals over a wide frequency range; 3. Good noise and distortion immunity. Please refer to [link / reference]. Figure 1 , Figure 1 The diagram shows a traditional input signal buffer architecture. This architecture operates in Class A mode and is inevitably limited by a constant bias current. As a result, it naturally provides an asymmetrical drive current that causes distortion, which can lead to severe signal distortion problems in some applications. Secondly, the traditional architecture is largely limited by the limited transconductance of a single MOSFET, making it difficult to achieve high bandwidth performance suitable for input signals over a wide frequency range.

[0005] In summary, traditional buffer architectures suffer from bandwidth limitations due to the finite transconductance of MOSFETs and distortion caused by asymmetric drive current. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides an ultra-wideband input signal buffer based on current mirror multiplication transconductance technology. This invention provides an ultra-wideband input signal buffer based on current mirror multiplication transconductance technology, comprising a first single-sided circuit, a second single-sided circuit, and a cross-coupling capacitor, wherein... The first single-sided circuit and the second single-sided circuit are mirror-symmetrically arranged and have the same structure, and the cross-coupling capacitor is connected between the first single-sided circuit and the second single-sided circuit; The input terminal of the first single-sided circuit is used to connect to the system front end to input the first differential signal, and the output terminal is used to connect to the load of the first subsequent circuit. The input terminal of the second single-sided circuit is used to connect to the system front end to input the second differential signal, and the output terminal is used to connect to the load of the second subsequent circuit. The first differential signal and the second differential signal have the same input amplitude but opposite phase.

[0007] In one embodiment of the present invention, both the first single-sided circuit and the second single-sided circuit include: a level shifting network circuit, a master-level complementary push-pull circuit, a slave-level complementary push-pull circuit, a first-layer auxiliary stage circuit, a second-layer auxiliary stage circuit, a first dynamic current amplifier circuit, and a second dynamic current amplifier circuit, wherein... The input terminal of the level shifting network circuit is used to connect to the system front end, and the output terminal is connected to the input terminal of the master stage complementary push-pull circuit, the input terminal of the slave stage complementary push-pull circuit, the input terminal of the first stacked auxiliary stage circuit, and the input terminal of the second stacked auxiliary stage circuit. The output of the primary complementary push-pull circuit is connected to the load of the subsequent circuit; the output of the secondary complementary push-pull circuit is connected to the cross-coupling capacitor. The first stacked auxiliary stage circuit is connected between the main stage complementary push-pull circuit and the first dynamic current amplifier circuit; the second stacked auxiliary stage circuit is connected between the main stage complementary push-pull circuit and the second dynamic current amplifier circuit. The first dynamic current amplifier circuit is connected across the first stacked auxiliary stage circuit and the slave complementary push-pull circuit; the second dynamic current amplifier circuit is connected across the second stacked auxiliary stage circuit and the slave complementary push-pull circuit.

[0008] In one embodiment of the present invention, the level shifting network circuit includes a first level shifting network, a second level shifting network, a third level shifting network, and a fourth level shifting network, wherein, The input terminals of both the first level shifting network and the second level shifting network are used to connect to the system front end; The output of the first level shifting network is connected to the first input of the master complementary push-pull circuit, the first input of the slave complementary push-pull circuit, and the input of the third level shifting network. The output of the second level shifting network is connected to the second input of the master complementary push-pull circuit, the second input of the slave complementary push-pull circuit, and the input of the fourth level shifting network. The output of the third level shift network is connected to the input of the first layered auxiliary stage circuit, and the output of the fourth level shift network is connected to the input of the second layered auxiliary stage circuit.

[0009] In one embodiment of the present invention, the first level shift network, the second level shift network, the third level shift network, and the fourth level shift network have the same structure, each including: a resistor, a first capacitor, and a current source, wherein, One end of the resistor is connected to one end of the first capacitor and serves as the input of the level shifting network; the other end of the resistor is connected to the other end of the first capacitor and the input of the current source and serves as the output of the level shifting network. The output terminal of the current source is grounded.

[0010] In one embodiment of the present invention, the master-level complementary push-pull circuit includes a first NMOS transistor and a first PMOS transistor, wherein, The gate of the first NMOS transistor serves as the first input terminal of the main stage complementary push-pull circuit to be connected to the output terminal of the first level shift network. The source of the first NMOS transistor is connected to the substrate of the first NMOS transistor, the source of the first PMOS transistor, and the substrate of the first PMOS transistor and serves as the output terminal of the main stage complementary push-pull circuit. The drain of the first NMOS transistor is connected to the output terminal of the first stacked auxiliary stage circuit. The gate of the first PMOS transistor serves as the second input terminal of the main stage complementary push-pull circuit to connect to the output terminal of the second level shift network, and the drain of the first PMOS transistor is connected to the output terminal of the first stacked auxiliary stage circuit.

[0011] In one embodiment of the present invention, the first stacked auxiliary stage circuit includes a second NMOS transistor, and the second stacked auxiliary stage circuit includes a second PMOS transistor. Both the second NMOS transistor and the second PMOS transistor are MOS transistors based on deep N-well technology. The gate of the second NMOS transistor serves as the input terminal of the first stacked auxiliary stage circuit to connect to the output terminal of the third level shift network. The source of the second NMOS transistor serves as the output terminal of the first stacked auxiliary stage circuit to connect to the drain of the first NMOS transistor and the substrate of the second PMOS transistor. The drain of the second NMOS transistor is connected to the first port of the first dynamic current amplifier circuit. The gate of the second PMOS transistor serves as the input terminal of the second stacked auxiliary stage circuit to connect to the output terminal of the fourth level shift network. The source of the second PMOS transistor serves as the output terminal of the second stacked auxiliary stage circuit to connect to the drain of the first PMOS transistor and the substrate of the second NMOS transistor. The drain of the second PMOS transistor is connected to the first port of the second dynamic current amplifier circuit.

[0012] In one embodiment of the present invention, the slave-level complementary push-pull circuit includes a third NMOS transistor and a third PMOS transistor, wherein, The gate of the third NMOS transistor serves as the first input terminal of the slave complementary push-pull circuit to be connected to the output terminal of the first level shift network. The drain of the third NMOS transistor is connected to the second port of the first dynamic current amplifier circuit. The source of the third NMOS transistor is connected to the substrate of the third NMOS transistor, the source of the third PMOS transistor, and the substrate of the third PMOS transistor, and serves as the output terminal of the slave complementary push-pull circuit to be connected to one end of the cross-coupling capacitor. The gate of the third PMOS transistor serves as the second input terminal of the slave complementary push-pull circuit to connect to the output terminal of the second level shift network, and the drain of the third PMOS transistor is connected to the second port of the second dynamic current amplifier circuit.

[0013] In one embodiment of the present invention, the first dynamic current amplifier circuit includes a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor, wherein the sizes of the fourth PMOS transistor and the sixth PMOS transistor are multiples of each other. The drain of the fourth PMOS transistor serves as the first port of the first dynamic current amplifier circuit. The source of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor and connected to the input power supply voltage. The gate of the fourth PMOS transistor is connected to the gate of the sixth PMOS transistor and the drain of the fifth PMOS transistor and serves as the third port of the first dynamic current amplifier circuit. The drain of the sixth PMOS transistor is connected to the source of the fifth PMOS transistor and serves as the second port of the first dynamic current amplifier circuit. The gate of the fifth PMOS transistor is connected to the first internal bias circuit.

[0014] In one embodiment of the present invention, the second dynamic current amplifier circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, wherein the sizes of the fourth NMOS transistor and the sixth NMOS transistor are multiples of each other. The drain of the fourth NMOS transistor serves as the first port of the second dynamic current amplifier circuit. The source of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor and connected to the ground terminal. The gate of the fourth NMOS transistor is connected to the gate of the sixth NMOS transistor and the drain of the fifth NMOS transistor and connected to the third port of the first dynamic current amplifier circuit. The source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor and serves as the second port of the second dynamic current amplifier circuit. The gate of the fifth NMOS transistor is connected to the second internal bias circuit.

[0015] Another embodiment of the present invention provides an analog-to-digital converter system, comprising: a buffer, a second capacitor, a third capacitor, a first ADC back-end, and a second ADC back-end, wherein, The buffer is an ultra-wideband input signal buffer based on current mirror multiplication transconductance technology as described in the above embodiment. The first input terminal of the buffer is used to connect to the system front end to input a first differential signal, and the second input terminal is used to connect to the system front end to input a second differential signal. The first output terminal of the buffer is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the input terminal of the back end of the first ADC. The second output terminal of the buffer is connected to one end of the third capacitor, and the other end of the third capacitor is connected to the input terminal of the back end of the second ADC.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The first and second single-sided circuits of the buffer of the present invention have the same structure and are mirror-symmetrical in position. They are used to input differential signals with the same amplitude and opposite phase, respectively. This avoids the distortion problem caused by asymmetrical drive current, can eliminate even harmonics, reduce common-mode noise, effectively expand the input and output bandwidth, and achieve better passband signal gain flatness.

[0017] 2. The single-sided circuit of this invention uses a level shifting network circuit as a signal bootstrap network to replace the RC bootstrap network in the traditional architecture, realizing the bootstrap and buffering functions of the passband input signal, achieving the effect that the output of the input buffer can completely follow the input signal from DC to ultra-high frequency, and overcoming the problem of low-frequency signal loss caused by the high-pass filtering of the RC network in the traditional architecture.

[0018] 3. In the single-sided circuit of the present invention, the master-stage complementary push-pull circuit can multiply the equivalent input transconductance of the transistor. Based on this, a slave-stage complementary push-pull circuit, a first dynamic current amplifier circuit, a second dynamic current amplifier circuit, and a cross-coupling capacitor are designed to work together to realize the replication and multiplication of the dynamic current and inject it into the master-stage complementary push-pull circuit, thereby causing the equivalent input transconductance of the transistor in the master-stage complementary push-pull circuit to be multiplied twice, and finally expanding the overall output bandwidth of the system.

[0019] 4. In the stacked auxiliary stage circuit of the present invention, the second NMOS transistor and the second PMOS transistor are MOS transistors based on deep N-well technology, and the source of the second NMOS transistor is connected to the substrate of the second PMOS transistor, and the source of the second PMOS transistor is connected to the substrate of the second NMOS transistor. The substrates of the transistors are respectively connected to the sources of complementary transistors that are symmetrical to their own positions. This not only prevents the PN junction in the transistor from being forward biased, but also reduces the nonlinear capacitance C. SB The effect of this also achieves resistance balance in the buffering process, making the positive and negative driving capabilities more symmetrical, and ultimately improving the linearity performance of the buffer.

[0020] 5. The dynamic current amplifier circuit of the present invention uses the fifth PMOS transistor as an auxiliary transistor to form a feedback loop in the first dynamic current amplifier circuit and the fifth NMOS transistor as an auxiliary transistor to form a feedback loop in the second dynamic current amplifier circuit. This not only reduces the impact of the extra pole on the system bandwidth performance, but also improves the accuracy of the current mirror circuit in replicating the dynamic current, and eliminates the instability that may be caused by voltage ringing. Attached Figure Description

[0021] Figure 1 This is a diagram of a traditional input signal buffer architecture. Figure 2 This is a schematic diagram of the structure of an ultrawideband input signal buffer based on current mirror multiplication transconductance technology provided in an embodiment of the present invention; Figure 3 A single-sided circuit schematic diagram of a novel differential push-pull ultrawideband input signal buffer based on current mirror multiplication transconductance technology provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a level shifting network provided in an embodiment of the present invention; Figure 5 A circuit schematic diagram of the first dynamic current amplifier circuit provided in an embodiment of the present invention; Figure 6 A circuit schematic diagram of the second dynamic current amplifier circuit provided in an embodiment of the present invention; Figure 7A flowchart illustrating the operation of a novel differential push-pull ultrawideband input signal buffer architecture based on current mirror multiplication transconductance technology provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of an analog-to-digital converter system provided in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0023] Example 1 Please see Figure 2 , Figure 2 This is a schematic diagram of an ultra-wideband input signal buffer based on current mirror multiplication transconductance technology provided in an embodiment of the present invention. This buffer enables direct sampling of radio frequency signals, providing a high-quality input signal that is accurately replicated and buffered at high speed for the back-end sample-and-hold circuit, thereby improving the overall performance of the analog-to-digital conversion system. It can be implemented using 28nm CMOS process technology.

[0024] This embodiment of the differential push-pull buffer includes a first single-sided circuit, a second single-sided circuit, and a cross-coupling capacitor C1. The first and second single-sided circuits are mirror-symmetrically arranged and have the same structure. The cross-coupling capacitor C1 is connected between the first and second single-sided circuits. The input terminal of the first single-sided circuit is used to connect to the system front-end to input the first differential signal VIN+, and the output terminal is used to connect to the load of the first subsequent stage circuit. The input terminal of the second single-sided circuit is used to connect to the system front-end to input the second differential signal VIN-, and the output terminal is used to connect to the load of the second subsequent stage circuit. The input amplitudes of the first differential signal VIN+ and the second differential signal VIN- are the same, but their phases are opposite.

[0025] In this embodiment, the first and second single-sided circuits of the buffer have the same structure and are mirror-symmetrical in position. They are used to input differential signals with the same amplitude but opposite phase, respectively. This avoids the distortion problem caused by asymmetrical drive current, eliminates even harmonics, reduces common-mode noise, effectively expands the input and output bandwidth, and achieves better passband signal gain flatness.

[0026] Please see Figure 3 , Figure 3 The schematic diagram of a single-sided circuit of a novel differential push-pull ultrawideband input signal buffer based on current mirror multiplication transconductance technology provided in an embodiment of the present invention.

[0027] like Figure 3As shown, both the first single-sided circuit and the second single-sided circuit include: a level shifting network circuit 1, a master stage complementary push-pull circuit 2, a slave stage complementary push-pull circuit 3, a first stacked auxiliary stage circuit 4, a second stacked auxiliary stage circuit 5, a first dynamic current amplifier circuit PIA1, and a second dynamic current amplifier circuit NIA1. The input of the level shifting network circuit 1 is connected to the system front end, and its output is connected to the input of the master stage complementary push-pull circuit 2, the slave stage complementary push-pull circuit 3, the first layer auxiliary stage circuit 4, and the second layer auxiliary stage circuit 5. The output of the master stage complementary push-pull circuit 2 is connected to the input of the load of the subsequent circuit. The output of the slave stage complementary push-pull circuit 3 is connected to the cross-coupling capacitor C1. The first layer auxiliary stage circuit 4 is connected between the master stage complementary push-pull circuit 2 and the first dynamic current amplifier circuit PIA1. The second layer auxiliary stage circuit 5 is connected between the master stage complementary push-pull circuit 2 and the second dynamic current amplifier circuit NIA1. The first dynamic current amplifier circuit PIA1 is connected across the first layer auxiliary stage circuit 4 and the slave stage complementary push-pull circuit 3. The second dynamic current amplifier circuit NIA1 is connected across the second layer auxiliary stage circuit 5 and the slave stage complementary push-pull circuit 3.

[0028] Specifically, level shifting network circuit 1 is used to bootstrap and buffer the passband input signal to obtain a bootstrap signal. Slave-stage complementary push-pull circuit 3 is used to generate a dynamic current flowing through cross-coupling capacitor C1 based on changes in the bootstrap signal. First-layer auxiliary stage circuit 4 and second-layer auxiliary stage circuit 5 are both used to replicate and buffer the bootstrap signal to obtain a replication buffer current. First dynamic current amplifier circuit PIA1 and second dynamic current amplifier circuit NIA1 are both used to replicate and multiply the dynamic current flowing through the cross-coupling capacitor to obtain a replication multiplied current, which is then injected into the master-stage complementary push-pull circuit 2. The master-stage complementary push-pull circuit 2 is used to sense the input voltage, replicate and buffer the bootstrap signal, replication buffer current, and replication multiplied current, and output the replicated and buffered input signal to the load of the subsequent circuit for further processing. Understandably, the master-level complementary push-pull circuit 2 and the slave-level complementary push-pull circuit 3 are used to replicate and buffer the passband input signal, which refers to any frequency input signal from low frequency to high frequency. The level shifting network circuit 1 is used to bootstrap the passband input signal to the cascade auxiliary circuit. The first cascade auxiliary circuit 4 and the second cascade auxiliary circuit 5 are used to reduce the non-ideal effects of the master-level complementary push-pull circuit. The first dynamic current amplifier circuit PIA1 and the second dynamic current amplifier circuit NIA1 are used to replicate and multiply the current of the slave-level complementary push-pull circuit to the master-level complementary push-pull circuit, thereby achieving a double multiplication of the equivalent transconductance of the master-level complementary push-pull circuit. The cross-coupling capacitor C1 is used to provide the dynamic coupling current injected into the current amplifier circuit.

[0029] In this embodiment, the single-sided circuit uses a level shifting network circuit as a signal bootstrap network to replace the RC bootstrap network in the traditional architecture. This achieves bootstrap and buffering functions for the passband input signal, and enables the output of the input buffer to completely follow DC to ultra-high frequency input signals. This overcomes the problem of low-frequency signal loss caused by high-pass filtering of the RC network in the traditional architecture.

[0030] In one specific embodiment, the level shifting network circuit 1 includes a first level shifting network LS1, a second level shifting network LS2, a third level shifting network LS3, and a fourth level shifting network LS4. The input terminals of both the first level shifting network LS1 and the second level shifting network LS2 are used to connect to the system front end to input differential signals. The output terminal of the first level shifting network LS1 is connected to the first input terminal of the master-level complementary push-pull circuit 2, the first input terminal of the slave-level complementary push-pull circuit 3, and the input terminal of the third level shifting network LS3. The output terminal of the second level shifting network LS2 is connected to the second input terminal of the master-level complementary push-pull circuit 2, the second input terminal of the slave-level complementary push-pull circuit 3, and the input terminal of the fourth level shifting network LS4. The output terminal of the third level shifting network LS3 is connected to the input terminal of the first cascaded auxiliary stage circuit 4, and the output terminal of the fourth level shifting network LS4 is connected to the input terminal of the second cascaded auxiliary stage circuit 5.

[0031] Please see Figure 4 , Figure 4 This is a schematic diagram of a level shifting network provided in an embodiment of the present invention.

[0032] like Figure 4 As shown, the first level shift network LS1, the second level shift network LS2, the third level shift network LS3, and the fourth level shift network LS4 have the same structure, each including: a resistor R, a first capacitor C2, and a current source Is. One end of the resistor R is connected to one end of the first capacitor C2 and serves as the input terminal VIN of the level shift network; the other end of the resistor R is connected to the other end of the first capacitor C2 and the input terminal of the current source Is and serves as the output terminal VOUTB of the level shift network; the output terminal of the current source Is is grounded.

[0033] It can be understood that each of the level shifting networks LS1-4 consists of a set of capacitors and resistors connected in parallel, and then connected in series with a current source that provides bias current. The first level shifting network LS1 is an N1-type level shifting network that biases the master-level complementary push-pull circuit 2 and the slave-level complementary push-pull circuit 3. The second level shifting network LS2 is a P1-type level shifting network that biases the master-level complementary push-pull circuit 2 and the slave-level complementary push-pull circuit 3. The third level shifting network LS3 is an N2-type level shifting network that biases the first-layer auxiliary stage circuit 4. The fourth level shifting network LS4 is a P2-type level shifting network that biases the second-layer auxiliary stage circuit 5.

[0034] In one specific embodiment, the master-level complementary push-pull circuit 2 includes a first NMOS transistor M1 and a first PMOS transistor M2. The gate of the first NMOS transistor M1 serves as the first input terminal of the master-level complementary push-pull circuit 2, connected to the output terminal of the first level shift network LS1. The source of the first NMOS transistor M1 is connected to the substrate of the first NMOS transistor M1, the source of the first PMOS transistor M2, and the substrate of the first PMOS transistor M2, and also serves as the output terminal of the master-level complementary push-pull circuit 2. The drain of the first NMOS transistor M1 is connected to the output terminal of the first stacked auxiliary stage circuit 4. The gate of the first PMOS transistor M2 serves as the second input terminal of the master-level complementary push-pull circuit 2, connected to the output terminal of the second level shift network LS2. The drain of the first PMOS transistor M2 is connected to the output terminal of the second stacked auxiliary stage circuit 5.

[0035] The slave-level complementary push-pull circuit 3 includes a third NMOS transistor M7 and a third PMOS transistor M8. The gate of the third NMOS transistor M7 serves as the input of the first stacked auxiliary stage circuit 4, connected to the output of the first level shift network LS1. The drain of the third NMOS transistor M7 is connected to the second port X1 of the first dynamic current amplifier circuit PIA1. The source of the third NMOS transistor M7 is connected to the substrate of the third NMOS transistor M7, the source of the third PMOS transistor M8, and the substrate of the third PMOS transistor M8, and also serves as the output of the slave-level complementary push-pull circuit 3, connected to one end of the cross-coupling capacitor C1. The gate of the third PMOS transistor M8 serves as the second input of the slave-level complementary push-pull circuit 3, connected to the output of the second level shift network LS2. The drain of the third PMOS transistor M8 is connected to the second port X2 of the second dynamic current amplifier circuit NIA1.

[0036] It is understandable that both the master-level complementary push-pull circuit 2 and the slave-level complementary push-pull circuit 3 are composed of a set of NMOS and PMOS transistors connected in series with complementary performance and source-to-source connections. This can double the equivalent transconductance of the buffer. When the transconductance of the NMOS transistor is equal to that of the PMOS transistor, it is beneficial to widen the input bandwidth. The substrates of the NMOS and PMOS transistors are respectively connected to their corresponding sources, which helps to reduce the impact of source-substrate voltage V. SB With the input signal V IN The changes in the voltage reduce harmonic distortion caused by the voltage drop, while also reducing the bulk effect and improving the linearity of the buffer. It should be noted that in the 28nm CMOS process, PMOS and NMOS transistors have almost perfect symmetrical complementary characteristics in terms of device characteristics, including bandwidth, capacitance, and unit current transconductance. This allows the circuit to provide good symmetrical drive characteristics, meaning that approximately equal load drive strength can be obtained regardless of which side provides the current.

[0037] In the single-sided circuit of this embodiment, the main stage complementary push-pull circuit adopts an architecture of NMOS and PMOS transistors in series push-pull instead of the traditional architecture of a single type of MOS transistor. This can achieve a multiplication of the equivalent input transconductance of the transistor. Based on this, a slave stage complementary push-pull circuit, a first dynamic current amplifier circuit, a second dynamic current amplifier circuit, and a cross-coupling capacitor are designed to work together to achieve the replication and multiplication of the dynamic current and inject it into the main stage complementary push-pull circuit. This results in a second multiplication of the equivalent input transconductance of the transistor in the main stage complementary push-pull circuit, ultimately expanding the overall output bandwidth of the system.

[0038] Furthermore, the first level shifting network LS1 biases the NMOS transistors of the master-level complementary push-pull circuit 2 and the slave-level complementary push-pull circuit 3, while the second level shifting network LS2 biases the PMOS transistors of the master-level complementary push-pull circuit 2 and the slave-level complementary push-pull circuit 3. The input port of the first level shifting network LS1 is connected to the system front end to input differential signals, and its output port is connected to the gates of the NMOS transistors of the master-level complementary push-pull circuit 2 and the slave-level complementary push-pull circuit 3. Similarly, the input port of the second level shifting network LS2 is connected to the system front end to input differential signals, and its output port is connected to the gates of the PMOS transistors of the master-level complementary push-pull circuit 2 and the slave-level complementary push-pull circuit 3. This connection method aims to provide appropriate static bias for the corresponding transistors, which is beneficial for ensuring the normal operation of the circuit.

[0039] Furthermore, the upper and lower plates of the cross-coupling capacitor C1 are connected to the output port of the slave-stage complementary push-pull circuit in the mirror-symmetric single-sided architecture, respectively. This output port is both the source of the NMOS transistor in the slave-stage complementary push-pull circuit and the source of the PMOS transistor in the slave-stage complementary push-pull circuit. This connects the two single-sided architectures of the differential circuit, which is beneficial to improving the efficiency of the current mirror multiplication transconductance technology. Designers can adjust the capacitance value of the cross-coupling capacitor and the current mirror ratio in the dynamic current amplifier circuit according to the actual application requirements to achieve the desired multiplication effect.

[0040] In one specific embodiment, the first stacked auxiliary stage circuit 4 includes a second NMOS transistor M3, and the second stacked auxiliary stage circuit 5 includes a second PMOS transistor M4. Both the second NMOS transistor M3 and the second PMOS transistor M4 are MOS transistors based on deep N-well technology. The gate of the second NMOS transistor M3 serves as the input terminal of the first stacked auxiliary stage circuit 4, connected to the output terminal of the third level shift network LS3. The source of the second NMOS transistor M3 serves as the output terminal of the first stacked auxiliary stage circuit 4, connected to the drain of the first NMOS transistor M1 and the substrate of the second PMOS transistor M4. The drain of the second NMOS transistor M3 is connected to the first port X4 of the first dynamic current amplifier circuit PIA1. The gate of the second PMOS transistor M4 serves as the input terminal of the second stacked auxiliary stage circuit 5, connected to the output terminal of the fourth level shift network LS4. The source of the second PMOS transistor M4 serves as the output terminal of the second stacked auxiliary stage circuit 5, connected to the drain of the first PMOS transistor M2 and the substrate of the second NMOS transistor M3. The drain of the second PMOS transistor M4 is connected to the first port X5 of the second dynamic current amplifier circuit NIA1.

[0041] It can be understood that the first-layer auxiliary stage circuit 4 is composed of auxiliary NMOS transistors stacked on top of the NMOS transistors in the main-stage complementary push-pull circuit, and the second-layer auxiliary stage circuit 5 is composed of auxiliary PMOS transistors stacked on top of the PMOS transistors in the main-stage complementary push-pull circuit. This is beneficial for maintaining constant drain-source voltages of the NMOS and PMOS transistors in the main-stage complementary push-pull circuit, reducing the influence of channel modulation effect and nonlinear capacitance C. ds The nonlinear distortion caused by the change in [variable] further improves the linearity of the buffered signal. Furthermore, both the auxiliary NMOS and auxiliary PMOS transistors utilize deep N-well (DNW) technology, with their substrates connected to their respective sources. This not only prevents PN junction forward bias during signal buffering but also reduces the impact of the nonlinear capacitor CSB on linearity by increasing the absolute value of the substrate-source voltage difference. This connection method also facilitates resistance balance during pull-up and pull-down processes, resulting in more symmetrical positive and negative drive capabilities.

[0042] Furthermore, the third level shifting network LS3 biases the NMOS transistor of the first layer auxiliary stage circuit 4, and the fourth level shifting network LS4 biases the PMOS transistor of the second layer auxiliary stage circuit 5. The input port of the third level shifting network LS3 is connected to the system front end, and the output port is connected to the gate of the NMOS transistor of the first layer auxiliary stage circuit 4; the input port of the fourth level shifting network LS4 is connected to the input signal of the system front end, and the output port is connected to the gate of the PMOS transistor of the second layer auxiliary stage circuit 5. The purpose of this connection is to bootstrap the input signal to the corresponding port of the layer auxiliary stage circuit. In addition, the layer auxiliary stage circuit can process the full-band input signal by using capacitors and resistors of appropriate values, which can avoid signal loss problems caused by filtering.

[0043] In the stacked auxiliary stage circuit of this embodiment, the second NMOS transistor and the second PMOS transistor are MOS transistors based on deep N-well technology. The source of the second NMOS transistor is connected to the substrate of the second PMOS transistor, and the source of the second PMOS transistor is connected to the substrate of the second NMOS transistor. The substrates of the transistors are respectively connected to the sources of complementary transistors that are symmetrical to their own positions. This not only prevents the PN junction in the transistor from being forward biased, but also reduces the nonlinear capacitance C. SB The effect of this also achieves resistance balance in the buffering process, making the positive and negative driving capabilities more symmetrical, and ultimately improving the linearity performance of the buffer.

[0044] Please see Figure 5 , Figure 5 The circuit diagram of the first dynamic current amplifier circuit provided in the embodiment of the present invention.

[0045] like Figure 5 As shown, the first dynamic current amplifier circuit PIA1 includes a fourth PMOS transistor M5, a fifth PMOS transistor M9, and a sixth PMOS transistor M11. The dimensions of the fourth PMOS transistor M5 and the sixth PMOS transistor M11 are multiples of each other to form a PMOS current mirror. The fifth PMOS transistor M9 is an auxiliary PMOS transistor. The drain of the fourth PMOS transistor M5 serves as the first port X4 of the first dynamic current amplifier circuit PIA1. The source of the fourth PMOS transistor M5 is connected to the source of the sixth PMOS transistor M11 and is connected to the input power supply voltage VDD. The gate of the fourth PMOS transistor M5 is connected to the gate of the sixth PMOS transistor M11 and the drain of the fifth PMOS transistor M9, serving as the third port X3 of the first dynamic current amplifier circuit PIA1. The drain of the sixth PMOS transistor M11 is connected to the source of the fifth PMOS transistor M9, serving as the second port X1 of the first dynamic current amplifier circuit PIA1. The gate of the fifth PMOS transistor M9 is connected to the first on-chip bias circuit B1.

[0046] It can be understood that the first dynamic current amplifier circuit PIA1 is composed of a set of PMOS current mirrors connected in series. The PMOS current mirror is composed of a set of PMOS transistors with sizes that are multiples of each other and an auxiliary PMOS transistor. The gate voltage of the auxiliary PMOS transistor is provided by the first internal bias circuit B1.

[0047] Please see Figure 6 , Figure 6 The circuit diagram of the second dynamic current amplifier circuit provided in the embodiment of the present invention.

[0048] like Figure 6 As shown, the second dynamic current amplifier circuit NIA1 includes a fourth NMOS transistor M6, a fifth NMOS transistor M10, and a sixth NMOS transistor M12. The dimensions of the fourth NMOS transistor M6 and the sixth NMOS transistor M12 are multiples of each other to form an NMOS current mirror. The fifth NMOS transistor M10 is an auxiliary NMOS transistor. The drain of the fourth NMOS transistor M6 serves as the first port X5 of the second dynamic current amplifier circuit NIA1. The source of the fourth NMOS transistor M6 is connected to the source of the sixth NMOS transistor M12 and is connected to ground VSS. The gate of the fourth NMOS transistor M6 is connected to the gate of the sixth NMOS transistor M12 and the drain of the fifth NMOS transistor M10, and is also connected to the third port X3 of the first dynamic current amplifier circuit PIA1. The source of the fifth NMOS transistor M10 is connected to the drain of the sixth NMOS transistor M12 and serves as the second port X2 of the second dynamic current amplifier circuit NIA1. The gate of the fifth NMOS transistor M10 is connected to the second on-chip bias circuit B2.

[0049] It can be understood that the second dynamic current amplifier circuit NIA1 is composed of a set of NMOS current mirrors connected in series. The NMOS current mirror is composed of a set of NMOS transistors with sizes that are multiples of each other and an auxiliary NMOS transistor. The gate voltage of the auxiliary NMOS transistor is provided by the second internal bias circuit B2.

[0050] In this embodiment, the gates of NMOS transistors with dimensions that are multiples of each other are interconnected and connected to the drain of the auxiliary NMOS transistor. The gates of PMOS transistors with dimensions that are multiples of each other are interconnected and connected to the drain of the auxiliary PMOS transistor. The source of the auxiliary NMOS transistor is connected to the drain of the PMOS transistor in the slave complementary push-pull circuit. The source of the auxiliary PMOS transistor is connected to the drain of the NMOS transistor in the slave complementary push-pull circuit 3. The purpose of this connection is to form a feedback loop to reduce the input resistance value at the nodes (X1 and X2), thereby reducing the impact of the additional poles brought by the newly added circuit modules on the system bandwidth performance, improving the accuracy of the current mirror circuit in replicating the dynamic current, and eliminating the instability that may be caused by voltage ringing.

[0051] In this embodiment, the substrates of NMOS transistors whose sizes are multiples of each other are connected to their respective sources, the substrates of PMOS transistors whose sizes are multiples of each other are connected to their respective sources, and the substrates of auxiliary NMOS transistors are also connected to their respective sources, and the substrates of auxiliary PMOS transistors are also connected to their respective sources. The purpose of the above connection method is to reduce the influence of the body effect, which is beneficial to improving the accuracy of the current mirror circuit in replicating the dynamic current.

[0052] In this embodiment, the dynamic current amplifier circuit uses the fifth PMOS transistor as an auxiliary transistor to form a feedback loop in the first dynamic current amplifier circuit, and the fifth NMOS transistor as an auxiliary transistor to form a feedback loop in the second dynamic current amplifier circuit. This not only reduces the impact of the extra pole on the system bandwidth performance, but also improves the accuracy of the current mirror circuit in replicating the dynamic current, while eliminating the instability that may be caused by voltage ringing.

[0053] Based on the aforementioned differential push-pull buffer, this embodiment further explains the working principle of the differential push-pull buffer. Please refer to [link / reference]. Figure 7 , Figure 7 The flowchart illustrates the operation of a novel differential push-pull ultrawideband input signal buffer architecture based on current mirror multiplication transconductance technology, as provided in this embodiment of the invention.

[0054] Since the working principles of the first and second single-sided circuits, which are mirror-symmetric, are exactly the same, this embodiment only describes the working process of the first single-sided circuit as an example, which includes two working states: static and dynamic.

[0055] In the static state, the input signal VIN+ at the system front end remains unchanged. At this time, the current source in the level shift network LS1-4 flows through resistor R, generating a voltage drop. This voltage VOUTB provides a static bias voltage to the gates of transistors M1 and M2 in the master-level complementary push-pull circuit 2 and transistors M7 and M8 in the slave-level complementary push-pull circuit 3. To avoid excessive bias voltage leading to wasted power or insufficient bias voltage causing transistors to fail to conduct, this circuit sets appropriate voltage resistance values ​​and current source currents to ensure the voltage difference in the level shift network is on the order of the static gate-source voltage VGS of a single transistor. This causes the static input common-mode voltage to first rise by the static gate-source voltage VGS and then fall by the same amount. This avoids the problem of the output voltage range being limited by the input voltage in traditional structures and ensures that the current through the transistors remains at a moderate level regardless of whether the operation is static or dynamic. Of course, the level shift network settings are relatively flexible; designers can adjust them by modifying the current mirror current or resistance value according to the actual application scenario of the buffer. At this time, the output voltage remains at the level of the output common-mode voltage.

[0056] Under dynamic conditions, when the differential input signal VIN+ at the front end of the system fluctuates, the AC input signal will be bootstrapped through the level shifting network LS1-4. The output AC voltage after bootstrapping through the LS1 and LS2 networks will be applied to the gates of transistors M1 and M2, causing the gate-source voltage VGS of transistors M1 and M2 to change accordingly. This allows the load of the next stage circuit to be charged and discharged at the output VOUTP+ of the main stage complementary push-pull circuit. Meanwhile, the AC input signal after being bootstrapping through LS1 and LS2 will undergo a second bootstrapping through the LS3 and LS4 networks and be loaded onto the gates of transistors M3 and M4. At this time, transistors M3 and M4 are equivalent to source followers. They copy and buffer the AC input voltage after the second bootstrapping to the drains of transistors M1 and M2. At this time, the drain voltage and source voltage of transistors M1 and M2 show the same trend, that is, the drain-source voltage difference is approximately equal to a constant value, which makes the signal after being copied and buffered by transistors M1 and M2 have better linearity performance.

[0057] Simultaneously, the output AC voltage after bootstrapping through the LS1 and LS2 networks will also be applied to the gates of transistors M7 and M8 in the slave complementary push-pull circuit. This will also cause a corresponding change in the gate-source voltage VGS of transistors M7 and M8. This change will generate a dynamic current in the cross-coupling capacitor C1 that spans between the left and right circuits. For example, when the input signal VIN+ at the front end of the system rises, the generated dynamic current will pass through transistor M7 and be injected into the cross-coupling capacitor C1, and then flow into the PMOS transistor of the slave complementary circuit in the right half of the circuit, and vice versa. The dynamic current flows through transistor M11 of the first dynamic current amplifier circuit PIA1 and is mirrored and amplified N times by transistor M5. The mirrored and multiplied current will be injected (when the input signal VIN+ of the system front end is high) or drawn (when the input signal VIN+ of the system front end is low) into the main stage complementary push-pull circuit 2. Finally, it is combined with the drive current generated by the main stage complementary push-pull circuit 2 to charge and discharge the load of the next stage circuit. This process realizes the further multiplication of the equivalent transconductance of the main stage complementary push-pull circuit 2, thereby completing the accurate replication and high-speed buffering of the AC input signal of the system front end.

[0058] Example 2 Based on Embodiment 1, this embodiment provides an analog-to-digital converter system. Please refer to... Figure 8 , Figure 8 This is a schematic diagram of the structure of an analog-to-digital converter system provided in an embodiment of the present invention. The analog-to-digital converter system includes: a buffer, a second capacitor CB1, a third capacitor CB2, a first ADC backend 1, and a second ADC backend 2.

[0059] The buffer adopts the ultra-wideband input signal buffer based on current mirror multiplication transconductance technology in Embodiment 1. The first input terminal of the buffer is used to connect to the system front end to input the first differential signal VIN+, and the second input terminal is used to connect to the system front end to input the second differential signal VIN-. The first output terminal of the buffer is connected to one end of the second capacitor CB1, and the other end of the second capacitor CB1 is connected to the input terminal of the first ADC backend 1. The second output terminal of the buffer is connected to one end of the third capacitor CB2, and the other end of the third capacitor CB2 is connected to the input terminal of the second ADC backend 2.

[0060] In this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0062] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0063] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An ultra-wideband input signal buffer based on current mirror multiplication transconductance technology, characterized in that, It includes a first single-sided circuit, a second single-sided circuit, and a cross-coupling capacitor (C1), wherein, The first single-sided circuit and the second single-sided circuit are mirror images of each other and have the same structure. The cross-coupling capacitor (C1) is connected between the first single-sided circuit and the second single-sided circuit. The input terminal of the first single-sided circuit is used to connect to the system front end to input the first differential signal (VIN+), and the output terminal is connected to the load of the first subsequent circuit. The input terminal of the second single-sided circuit is used to connect to the system front end to input the second differential signal (VIN-), and the output terminal is connected to the load of the second subsequent circuit. The first differential signal (VIN+) and the second differential signal (VIN-) have the same input amplitude but opposite phase. Both the first single-sided circuit and the second single-sided circuit include: a level shifting network circuit (1), a master-level complementary push-pull circuit (2), a slave-level complementary push-pull circuit (3), a first-layer auxiliary stage circuit (4), a second-layer auxiliary stage circuit (5), a first dynamic current amplifier circuit (PIA1), and a second dynamic current amplifier circuit (NIA1), wherein, The input terminal of the level shifting network circuit (1) is used to connect to the front end of the system, and the output terminal is connected to the input terminal of the master complementary push-pull circuit (2), the input terminal of the slave complementary push-pull circuit (3), the input terminal of the first stacked auxiliary stage circuit (4), and the input terminal of the second stacked auxiliary stage circuit (5). The output of the primary complementary push-pull circuit (2) is connected to the load of the subsequent circuit; the output of the secondary complementary push-pull circuit (3) is connected to the cross-coupling capacitor (C1). The first stacked auxiliary stage circuit (4) is connected between the main stage complementary push-pull circuit (2) and the first dynamic current amplifier circuit (PIA1); the second stacked auxiliary stage circuit (5) is connected between the main stage complementary push-pull circuit (2) and the second dynamic current amplifier circuit (NIA1); The first dynamic current amplifier circuit (PIA1) is connected across the first stacked auxiliary stage circuit (4) and the slave complementary push-pull circuit (3); the second dynamic current amplifier circuit (NIA1) is connected across the second stacked auxiliary stage circuit (5) and the slave complementary push-pull circuit (3).

2. The ultra-wideband input signal buffer based on current mirror multiplication transconductance technology according to claim 1, characterized in that, The level shifting network circuit (1) includes a first level shifting network (LS1), a second level shifting network (LS2), a third level shifting network (LS3), and a fourth level shifting network (LS4), wherein, The input terminals of both the first level shift network (LS1) and the second level shift network (LS2) are used to connect to the system front end; The output of the first level shift network (LS1) is connected to the first input of the master complementary push-pull circuit (2), the first input of the slave complementary push-pull circuit (3), and the input of the third level shift network (LS3). The output of the second level shift network (LS2) is connected to the second input of the master complementary push-pull circuit (2), the second input of the slave complementary push-pull circuit (3), and the input of the fourth level shift network (LS4). The output of the third level shift network (LS3) is connected to the input of the first stacked auxiliary stage circuit (4), and the output of the fourth level shift network (LS4) is connected to the input of the second stacked auxiliary stage circuit (5).

3. The ultra-wideband input signal buffer based on current mirror multiplication transconductance technology according to claim 2, characterized in that, The first level shift network (LS1), the second level shift network (LS2), the third level shift network (LS3), and the fourth level shift network (LS4) have the same structure, each including: a resistor (R), a first capacitor (C2), and a current source (Is), wherein, One end of the resistor (R) is connected to one end of the first capacitor (C2) and serves as the input terminal (VIN) of the level shifting network. The other end of the resistor (R) is connected to the other end of the first capacitor (C2) and the input terminal of the current source (Is) and serves as the output terminal (VOUTB) of the level shifting network. The output terminal of the current source (Is) is grounded.

4. The ultra-wideband input signal buffer based on current mirror multiplication transconductance technology according to claim 2, characterized in that, The main stage complementary push-pull circuit (2) includes a first NMOS transistor (M1) and a first PMOS transistor (M2), wherein, The gate of the first NMOS transistor (M1) serves as the first input terminal of the main stage complementary push-pull circuit (2) and is connected to the output terminal of the first level shift network (LS1). The source of the first NMOS transistor (M1) is connected to the substrate of the first NMOS transistor (M1), the source of the first PMOS transistor (M2), and the substrate of the first PMOS transistor (M2) and serves as the output terminal of the main stage complementary push-pull circuit (2). The drain of the first NMOS transistor (M1) is connected to the output terminal of the first stacked auxiliary stage circuit (4). The gate of the first PMOS transistor (M2) serves as the second input terminal of the main stage complementary push-pull circuit (2) to be connected to the output terminal of the second level shift network (LS2), and the drain of the first PMOS transistor (M2) is connected to the output terminal of the second stacked auxiliary stage circuit (5).

5. The ultra-wideband input signal buffer based on current mirror multiplication transconductance technology according to claim 4, characterized in that, The first stacked auxiliary stage circuit (4) includes a second NMOS transistor (M3), and the second stacked auxiliary stage circuit (5) includes a second PMOS transistor (M4). Both the second NMOS transistor (M3) and the second PMOS transistor (M4) are MOS transistors based on deep N-well technology. The gate of the second NMOS transistor (M3) serves as the input terminal of the first stacked auxiliary stage circuit (4) to connect to the output terminal of the third level shift network (LS3), the source of the second NMOS transistor (M3) serves as the output terminal of the first stacked auxiliary stage circuit (4) to connect to the drain of the first NMOS transistor (M1) and the substrate of the second PMOS transistor (M4), and the drain of the second NMOS transistor (M3) is connected to the first port (X4) of the first dynamic current amplifier circuit (PIA1). The gate of the second PMOS transistor (M4) serves as the input terminal of the second stacked auxiliary stage circuit (5) to be connected to the output terminal of the fourth level shift network (LS4). The source of the second PMOS transistor (M4) serves as the output terminal of the second stacked auxiliary stage circuit (5) to be connected to the drain of the first PMOS transistor (M2) and the substrate of the second NMOS transistor (M3). The drain of the second PMOS transistor (M4) is connected to the first port (X5) of the second dynamic current amplifier circuit (NIA1).

6. The ultra-wideband input signal buffer based on current mirror multiplication transconductance technology according to claim 2, characterized in that, The slave-level complementary push-pull circuit (3) includes a third NMOS transistor (M7) and a third PMOS transistor (M8), wherein, The gate of the third NMOS transistor (M7) serves as the first input terminal of the slave complementary push-pull circuit (3) to be connected to the output terminal of the first level shift network (LS1). The drain of the third NMOS transistor (M7) is connected to the second port (X1) of the first dynamic current amplifier circuit (PIA1). The source of the third NMOS transistor (M7) is connected to the substrate of the third NMOS transistor (M7), the source of the third PMOS transistor (M8), and the substrate of the third PMOS transistor (M8), and serves as the output terminal of the slave complementary push-pull circuit (3) to be connected to one end of the cross-coupling capacitor (C1). The gate of the third PMOS transistor (M8) serves as the second input terminal of the slave complementary push-pull circuit (3) to be connected to the output terminal of the second level shift network (LS2), and the drain of the third PMOS transistor (M8) is connected to the second port (X2) of the second dynamic current amplifier circuit (NIA1).

7. The ultra-wideband input signal buffer based on current mirror multiplication transconductance technology according to claim 2, characterized in that, The first dynamic current amplifier circuit (PIA1) includes a fourth PMOS transistor (M5), a fifth PMOS transistor (M9), and a sixth PMOS transistor (M11). The dimensions of the fourth PMOS transistor (M5) and the sixth PMOS transistor (M11) are multiples of each other. The drain of the fourth PMOS transistor (M5) serves as the first port (X4) of the first dynamic current amplifier circuit (PIA1). The source of the fourth PMOS transistor (M5) is connected to the source of the sixth PMOS transistor (M11) and connected to the input power supply voltage (VDD). The gate of the fourth PMOS transistor (M5) is connected to the gate of the sixth PMOS transistor (M11) and the drain of the fifth PMOS transistor (M9) and serves as the third port (X3) of the first dynamic current amplifier circuit (PIA1). The drain of the sixth PMOS transistor (M11) is connected to the source of the fifth PMOS transistor (M9) and serves as the second port (X1) of the first dynamic current amplifier circuit (PIA1). The gate of the fifth PMOS transistor (M9) is connected to the first on-chip bias circuit (B1).

8. The ultra-wideband input signal buffer based on current mirror multiplication transconductance technology according to claim 7, characterized in that, The second dynamic current amplifier circuit (NIA1) includes a fourth NMOS transistor (M6), a fifth NMOS transistor (M10), and a sixth NMOS transistor (M12). The dimensions of the fourth NMOS transistor (M6) and the sixth NMOS transistor (M12) are multiples of each other. The drain of the fourth NMOS transistor (M6) serves as the first port (X5) of the second dynamic current amplifier circuit (NIA1). The source of the fourth NMOS transistor (M6) is connected to the source of the sixth NMOS transistor (M12) and connected to the ground terminal (VSS). The gate of the fourth NMOS transistor (M6) is connected to the gate of the sixth NMOS transistor (M12) and the drain of the fifth NMOS transistor (M10) and connected to the third port (X3) of the first dynamic current amplifier circuit (PIA1). The source of the fifth NMOS transistor (M10) is connected to the drain of the sixth NMOS transistor (M12) and serves as the second port (X2) of the second dynamic current amplifier circuit (NIA1); The gate of the fifth NMOS transistor (M10) is connected to the second internal bias circuit (B2).

9. An analog-to-digital converter system, characterized in that, include: The components include a buffer, a second capacitor (CB1), a third capacitor (CB2), a first ADC backend (ADC backend1), and a second ADC backend (ADC backend2). The buffer is an ultra-wideband input signal buffer based on current mirror multiplication transconductance technology as described in any one of claims 1-8. The first input terminal of the buffer is used to connect to the system front end to input a first differential signal (VIN+), and the second input terminal is used to connect to the system front end to input a second differential signal (VIN-). The first output terminal of the buffer is connected to one end of the second capacitor (CB1), and the other end of the second capacitor (CB1) is connected to the input terminal of the first ADC backend1. The second output terminal of the buffer is connected to one end of the third capacitor (CB2), and the other end of the third capacitor (CB2) is connected to the input terminal of the second ADC backend (ADC backend2).

Images