A memristor-based balanced ternary nand gate circuit and nor gate circuit

Abstract

The application discloses a balanced ternary NAND gate circuit based on a memristor, which is composed of a first memristor M1, a second memristor M2, a first NMOS transistor T1, a second NMOS transistor T2, a third NMOS transistor T3 and a fourth NMOS transistor T4. DD The negative electrode of the first memristor M1 is connected with a power supply V DD The positive electrode of the second memristor M2 is connected with the drain of the first NMOS transistor T1 and the second NMOS transistor T2; the source of the third NMOS transistor T3 is connected with the drain of the fourth NMOS transistor T4; and the sources of the first NMOS transistor T1, the third NMOS transistor T3 and the fourth NMOS transistor T4 are connected with a power supply V DD The circuit structure is clear and simple, easy to realize, has a wide application range, and can effectively improve the power consumption, speed and data density of the circuit.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, specifically to a balanced ternary NAND gate circuit and an OR NOT gate circuit based on memristors. Background Technology

[0002] Over the past few decades, integrated circuit technology has developed rapidly. However, as the feature size of semiconductor transistors continues to shrink, the size of integrated circuits is gradually approaching physical limits, making the continuation of Moore's Law a challenge. One way to continue Moore's Law is to find smaller devices to replace traditional CMOS transistors. Memristors, as a new type of device with nanometer-sized dimensions, have characteristics such as low power consumption, easy integration, and compatibility with CMOS, providing a new path for continuing Moore's Law.

[0003] In existing digital logic circuit designs, there are already designs for ternary logic circuits based on memristors, mainly with two different implementation schemes: using voltage values ​​as logic variables and using resistance values ​​as logic variables. Circuits designed using voltage values ​​as logic variables operate faster and are compatible with CMOS technology; the logic gates can generate voltage outputs within one clock cycle. However, in these circuit designs, the circuit structures for NAND and NOR gates are relatively complex. For example, some designs build upon basic logic gates like ternary AND, OR, and NOT gates, further designing composite logic gates such as ternary NAND and NOR gates based on logical expressions, resulting in a less simplified circuit structure. Furthermore, although existing ternary gate circuit designs use memristors to replace traditional resistors and diodes for functional implementation, reducing silicon area, the reduction in power consumption is limited. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a balanced ternary NAND gate and NOR gate circuit based on memristors. The structure is clear and simple, easy to implement, has a wide range of applications, and can effectively improve the power consumption, speed, and data density of the circuit.

[0005] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:

[0006] A balanced ternary NAND gate circuit based on memristors is constructed from a first memristor M1, a second memristor M2, a first NMOS transistor T1, a second NMOS transistor T2, a third NMOS transistor T3, and a fourth NMOS transistor T4. The negative terminal of the first memristor M1 is connected to the power supply V. DDThe first memristor M1 is connected to the negative terminal of the second memristor M2 and the drain of the third NMOS transistor T3, serving as the output terminal TNAND of a balanced three-value NAND gate circuit; the positive terminal of the second memristor M2 is connected to the drain of the first NMOS transistor T1 and the second NMOS transistor T2; the source of the third NMOS transistor T3 is connected to the drain of the fourth NMOS transistor T4; the sources of the first NMOS transistor T1, the third NMOS transistor T3, and the fourth NMOS transistor T4 are connected to the power supply -V. DD The input terminals are connected. Input terminal A1 is connected to the gates of the first NMOS transistor T1 and the third NMOS transistor T3; input terminal B1 is connected to the gates of the second NMOS transistor T2 and the fourth NMOS transistor T4.

[0007] This invention also provides a balanced ternary NOR gate circuit based on memristors, comprising a third memristor M3, a fourth memristor M4, a fifth NMOS transistor T5, a sixth NMOS transistor T6, a seventh NMOS transistor T7, an eighth NMOS transistor T8, a ninth NMOS transistor T9, and a tenth NMOS transistor T1. 10 11th NMOS transistor T 11 and the twelfth NMOS transistor T 12 The third memristor M3 is configured such that its negative terminal is connected to the power supply V. DD Connected; the positive terminal of the third memristor M3 is connected to the negative terminal of the fourth memristor M4, the ninth NMOS transistor T9, and the eleventh NMOS transistor T1. 11 The drain of the first NMOS transistor is connected to the drain of the second NMOS transistor, and serves as the output terminal TNOR of the balanced three-value NOR gate circuit; the positive terminal of the fourth memristor M4 is connected to the drain of the fifth NMOS transistor T5, the sixth NMOS transistor T6, and the seventh NMOS transistor T7; the source of the seventh NMOS transistor T7 is connected to the drain of the eighth NMOS transistor T8; the source of the ninth NMOS transistor T9 is connected to the drain of the tenth NMOS transistor T10. 10 The drains of the eleventh NMOS transistor T are connected. 11 The source of the twelfth NMOS transistor T 12 The drains of the transistors are connected; the fifth NMOS transistor T5, the sixth NMOS transistor T6, the eighth NMOS transistor T8, and the tenth NMOS transistor T... 10 and the twelfth NMOS transistor T 12 The source and power supply -V DD The input terminal A2 is connected to the fifth NMOS transistor T5, the seventh NMOS transistor T7, the ninth NMOS transistor T9, and the twelfth NMOS transistor T1. 12 The gate of the transistor is connected; the input terminal B2 is connected to the sixth NMOS transistor T6, the eighth NMOS transistor T8, and the tenth NMOS transistor T1. 10 and the eleventh NMOS transistor T 11 The gate is connected.

[0008] This invention has the following characteristics and beneficial effects:

[0009] By employing the above technical solution, a ternary digital logic gate circuit is directly implemented using a combination of memristors and CMOS transistors. Without using other basic logic gates, the logic functions of ternary NAND and NOR gates are achieved, resulting in a simple structure and significantly reduced circuit area. Furthermore, the average power consumption of the NAND gate circuit under this technical solution is measured to be 90.94 pW, and the average power consumption of the NOR gate circuit is 190.99 pW, demonstrating low power consumption and stable circuit performance. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a diagram of the balanced ternary NAND gate circuit structure based on memristors of the present invention.

[0012] Figure 2 This is a diagram of the balanced ternary OR gate circuit structure based on memristors of the present invention. Detailed Implementation

[0013] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0014] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0015] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0016] Example 1

[0017] This embodiment provides a balanced ternary NAND gate circuit based on memristors, such as... Figure 1 As shown, its logic state is a voltage value, defined as voltage V. DD 1V corresponds to logic "1"; GND is 0V, corresponding to logic "0"; -V DD The value is -1V, corresponding to logic "-1". The truth table of the balanced ternary NAND gate designed in this invention is shown below, where A1 and B1 represent two input signals, and TNAND represents the output of the NAND gate.

[0018]

[0019]

[0020] For a balanced three-valued NAND gate circuit, the threshold values ​​of the first NMOS transistor T1 and the second NMOS transistor T2 are 0.8V, and the threshold values ​​of the third NMOS transistor T3 and the fourth NMOS transistor T4 are 1.5V.

[0021] When both input signals A1 and B1 are logic "-1", that is, both input terminals A1 and B1 are connected to -V DD The first NMOS transistor T1, the second NMOS transistor T2, the third NMOS transistor T3, and the fourth NMOS transistor T4 are all off. The output terminal TNAND is connected to the power supply V through the first memristor M1. DD Connected, the output is logic "1".

[0022] When input signals A1 and B1 are logic "-1" and "0" respectively, that is, when input terminals A1 and B1 are connected to -V DD With GND connected, the second NMOS transistor T2 is turned on, while the first NMOS transistor T1, the third NMOS transistor T3, and the fourth NMOS transistor T4 are turned off. Current will flow from the power supply V through the first memristor M1 and the second memristor M2. DD Flow to power supply -V DD Based on the resistance change pattern of the memristors, both the first memristor M1 and the second memristor M2 switch to R at this time. OFFIn the current state, the output terminal TNAND is 0V after being divided by the first memristor M1 and the second memristor M2, and the output is logic "0". The analysis is similar when the input signals A1 and B1 are logic "0" and -1 respectively.

[0023] When input signals A1 and B1 are logic "-1" and "1" respectively, that is, input terminals A1 and B1 are connected to -V respectively. DD V DD The second NMOS transistor T2 and the fourth NMOS transistor T4 are turned on, while the first NMOS transistor T1 and the third NMOS transistor T3 are turned off. Current flows from the power supply V through the first memristor M1 and the second memristor M2. DD Flow to power supply -V DD Both the first memristor M1 and the second memristor M2 are switched to R OFF In the current state, the output terminal TNAND is 0V after being divided by the first memristor M1 and the second memristor M2, and the output is logic "0". When the input signals A1 and B1 are logic "1" and -1 respectively, the analysis is similar to the above process.

[0024] When both input signals A1 and B1 are logic "0", that is, when both input terminals A1 and B1 are connected to GND, the first NMOS transistor T1 and the second NMOS transistor T2 are turned on, while the third NMOS transistor T3 and the fourth NMOS transistor T4 are turned off. The output terminal TNAND is still 0V after being divided by the first memristor M1 and the second memristor M2, and the output is logic "0".

[0025] When input signals A1 and B1 are logic "0" and "1" respectively, that is, input terminals A1 and B1 are connected to GND and V respectively. DD The first NMOS transistor T1, the second NMOS transistor T2, and the fourth NMOS transistor T4 are turned on, while the third NMOS transistor T3 is turned off. Similarly, a current path exists in the circuit flowing through the first memristor M1, the second memristor M2, and the second NMOS transistor T2. The output terminal TNAND, after being divided by the first memristor M1 and the second memristor M2, is 0V, resulting in a logic "0". The analysis is similar when the input signals A1 and B1 are logic "1" and "0" respectively.

[0026] When both input signals A1 and B1 are logic "1", that is, both input terminals A1 and B1 are connected to V. DD The first NMOS transistor T1, the second NMOS transistor T2, the third NMOS transistor T3, and the fourth NMOS transistor T4 are all turned on. The output terminal TNAND is connected to -V through the third NMOS transistor T3 and the fourth NMOS transistor T4. DD The output is a logical "-1".

[0027] Example 2

[0028] This embodiment provides a balanced ternary NOR gate circuit based on a memristor, such as Figure 2 As shown, its logic state is a voltage value, defined as voltage V. DD 1V corresponds to logic "1"; GND is 0V, corresponding to logic "0"; -V DD The value is -1V, corresponding to logic "-1". The truth table of the balanced three-valued NOR gate designed in this invention is shown below, where A2 and B2 represent two input signals, and TNOR represents the output of the NOR gate.

[0029]

[0030]

[0031] For a balanced three-valued NOR gate circuit, the fifth NMOS transistor T5, the sixth NMOS transistor T6, the ninth NMOS transistor T9, and the eleventh NMOS transistor T... 11 The threshold voltage is 1.5V. The seventh NMOS transistor is T7, the eighth NMOS transistor is T8, and the tenth NMOS transistor is T... 10 and the twelfth NMOS transistor T 12 The threshold is 0.8V.

[0032] When both input signals A2 and B2 are logic "-1", that is, both input terminals A2 and B2 are connected to -V DD All NMOS

[0033] All are cut off. The output terminal TNOR is connected to the power supply V through the third memristor M3. DD Connected, the output is logic "1".

[0034] When input signals A2 and B2 are logic "-1" and "0" respectively, that is, input terminals A2 and B2 are connected to -V respectively. DD GND, the eighth NMOS transistor T8 and the tenth NMOS transistor T 10 When the TNOR transistor is turned on, the other NMOS transistors are turned off. No current loop is formed in the circuit; the output TNOR is still connected to the power supply V through the third memristor M3. DD When connected, the output is logic "1". The analysis is similar when input signals A2 and B2 are logic "0" and -1 respectively.

[0035] When input signals A2 and B2 are logic "-1" and "1" respectively, that is, input terminals A2 and B2 are connected to -V respectively. DD V DD The sixth NMOS transistor T6, the eighth NMOS transistor T8, and the tenth NMOS transistor T 10 and the eleventh NMOS transistor T 11The fifth NMOS transistor T5, the seventh NMOS transistor T7, the ninth NMOS transistor T9, and the twelfth NMOS transistor T1 are turned on. 12 Cut off. Current flows from power supply V through the first memristor M1, the second memristor M2, and the sixth NMOS transistor T6. DD Flow to power supply -V DD Both the first memristor M1 and the second memristor M2 are switched to R OFF In the current state, the output terminal TNAND is 0V after being divided by the first memristor M1 and the second memristor M2, and the output is logic "0". When the input signals A2 and B2 are logic "1" and -1 respectively, the analysis is similar to the above process.

[0036] When input signals A2 and B2 are both logic "0", that is, when input terminals A2 and B2 are both connected to GND, the seventh NMOS transistor T7, the eighth NMOS transistor T8, and the tenth NMOS transistor T... 10 and the twelfth NMOS transistor T 12 The fifth NMOS transistor T5, the sixth NMOS transistor T6, the ninth NMOS transistor T9, and the eleventh NMOS transistor T1 are turned on. 11 Cut-off. There is a current path in the circuit that flows through the first memristor M1, the second memristor M2, the seventh NMOS transistor T7, and the eighth NMOS transistor T8. The output terminal TNAND is still 0V after being divided by the first memristor M1 and the second memristor M2, and the output is logic "0".

[0037] When input signals A2 and B2 are logic "0" and "1" respectively, that is, input terminals A2 and B2 are connected to GND and V respectively. DD The fifth NMOS transistor T5 and the ninth NMOS transistor T9 are cut off, while the remaining NMOS transistors are turned on. The output terminal TNAND is connected to the eleventh NMOS transistor T1. 11 and the twelfth NMOS transistor T 12 With power supply -V DD When connected, the output is logic "-1". The analysis is similar when input signals A2 and B2 are logic "1" and "0" respectively.

[0038] When both input signals A2 and B2 are logic "1", that is, both input terminals A2 and B2 are connected to V. DD All NMOS transistors are turned on. The output terminal TNAND is connected to the power supply -VDD through the eleventh NMOS transistor T11 and the twelfth NMOS transistor T12, and the output is logic "-1".

[0039] In this embodiment, the following data comparison is given in conjunction with Embodiment 1, Embodiment 2, and the comparative example, as shown in Table 1:

[0040]

[0041] Table 1

[0042] As can be seen from Table 1, the average power consumption of the NAND gate circuit in this embodiment is 90.94pW, and the average power consumption of the NOR gate circuit is 190.99pW. In contrast, the average power consumption of the NAND gate circuit in the comparative scheme is 16.2uW, and the average power consumption of the NOR gate circuit is 39.77uW. Compared with the comparative example, this embodiment has lower power consumption and more stable circuit performance, showing a significant improvement.

[0043] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations can be made to these embodiments, including components, without departing from the principles and spirit of the present invention, and these variations still fall within the protection scope of the present invention.

Claims

1. A balanced ternary NAND gate circuit based on memristors, characterized in that, It includes a first memristor M1, a second memristor M2, a first NMOS transistor T1, a second NMOS transistor T2, a third NMOS transistor T3, and a fourth NMOS transistor T4. The negative terminal of the first memristor M1 is connected to the power supply V. DD The first memristor M1 is connected to the negative terminal of the second memristor M2 and the drain of the third NMOS transistor T3. The positive terminal of the first memristor M1 serves as the output terminal TNAND of a balanced NAND gate. The positive terminal of the second memristor M2 is connected to the drain of the first NMOS transistor T1 and the second NMOS transistor T2. The source of the third NMOS transistor T3 is connected to the drain of the fourth NMOS transistor T4. The sources of the first NMOS transistor T1, the second NMOS transistor T2, and the fourth NMOS transistor T4 are connected to the power supply -V. DD The gates of the first NMOS transistor T1 and the third NMOS transistor T3 are connected to the input terminal A1 of the balanced NAND gate circuit; the gates of the second NMOS transistor T2 and the fourth NMOS transistor T4 are connected to the input terminal B1 of the balanced NAND gate circuit.

2. The balanced ternary NAND gate circuit based on memristor according to claim 1, characterized in that, The first NMOS transistor T The threshold voltage of the first and second NMOS transistors T1 and T2 is 0.8V.

3. The balanced ternary NAND gate circuit based on memristor according to claim 1, characterized in that, The threshold voltage of the third NMOS transistor T3 and the fourth NMOS transistor T4 is 1.5V.

4. A balanced ternary NOR gate circuit based on a memristor, characterized in that, Including the third memristor M3, the fourth memristor M4, the fifth NMOS transistor T5, the sixth NMOS transistor T6, the seventh NMOS transistor T7, the eighth NMOS transistor T8, the ninth NMOS transistor T9, and the tenth NMOS transistor T1. 10 11th NMOS transistor T 11 and the twelfth NMOS transistor T 12 The negative terminal of the third memristor M3 is connected to the power supply V. DD The positive terminal of the third memristor M3 is connected to the negative terminal of the fourth memristor M4, the ninth NMOS transistor T9, and the eleventh NMOS transistor T1, respectively. 11 The drain of the third memristor M3 is connected to the drain of the fourth memristor M4, which is connected to the drain of the fifth NMOS transistor T5, the sixth NMOS transistor T6, and the seventh NMOS transistor T7. The source of the seventh NMOS transistor T7 is connected to the drain of the eighth NMOS transistor T8. The source of the ninth NMOS transistor T9 is connected to the drain of the tenth NMOS transistor T10. 10 The drain of the eleventh NMOS transistor T is connected. 11 The source of the twelfth NMOS transistor T 12 The drains of the five NMOS transistors T5, T6, T8, and T10 are connected; 10 and the twelfth NMOS transistor T 12 The source and power supply -V DD Connected; the fifth NMOS transistor T5, the seventh NMOS transistor T7, the ninth NMOS transistor T9, and the twelfth NMOS transistor T 12 The gates of all are connected to the input terminal A2 of the balanced ternary NOR gate circuit; and to the sixth NMOS transistor T6, the eighth NMOS transistor T8, and the tenth NMOS transistor T... 10 and the eleventh NMOS transistor T 11 The gates of all are connected to the input terminal B2 of the balanced ternary NOR gate circuit.

5. A balanced ternary NOR gate circuit based on a memristor according to claim 4, characterized in that, The fifth NMOS transistor T5, the sixth NMOS transistor T6, the ninth NMOS transistor T9, and the eleventh NMOS transistor T 11 The threshold is 1.5V.

6. A balanced ternary NOR gate circuit based on a memristor according to claim 4, characterized in that, The seventh NMOS transistor T7, the eighth NMOS transistor T8, and the tenth NMOS transistor T 10 and the twelfth NMOS transistor T 12 The threshold is 0.8V.

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