Apparatus for synchronizing an ethernet network

Abstract

An apparatus for synchronizing an Ethernet network includes a processor, a programmable logic gate array, a synchronizer, a physical layer implementer, and a media access controller. The processor transmits control data through a first transmission interface. The programmable logic gate array receives the control data and generates control instructions according to the control data and transmits the control instructions through a second transmission interface. The synchronizer receives the control instructions and generates a synchronization clock according to the control instructions. The physical layer implementer receives the synchronization clock and receives network data from or transmits network data to the Ethernet network according to the synchronization clock. The media access controller receives the synchronization clock from the synchronizer and receives the network data from or transmits prepared data to the physical layer implementer according to the synchronization clock and a media access control protocol.

Description

Technical Field

[0001] This invention relates to a network device, and more particularly to a device for synchronizing Ethernet networks. Background Technology

[0002] Traditional Ethernet transmits data asynchronously. However, with the advent of 5G networks, synchronization must be incorporated to ensure compatibility between traditional Ethernet and 5G networks. Currently, Synchronous Ethernet (SyncE) and the IEEE 1588v2 standard are the only methods to achieve synchronization. Synchronous Ethernet is the result of migrating synchronous networks (PDH, SDH / SONET) to Ethernet-based packet-switched networks (PSNs), while the IEEE 1588v2 standard defines a Precision Time Protocol (PTP) to ensure a synchronized clock across the entire packet-switched network.

[0003] Currently, the most common product on the market for implementing synchronization technology integrates the synchronization-related technologies into an integrated circuit chip. This chip interfaces with a processor and is directly used to handle Ethernet network clock synchronization. While this approach is convenient for users, it also reduces its compatibility with other technologies. For the further development of Ethernet synchronization, engineers need a more flexible product that can achieve Ethernet network clock synchronization. Summary of the Invention

[0004] In view of this, the present invention discloses an apparatus for synchronizing Ethernet networks using the following description and figures, which provides another technical approach to achieve clock synchronization of Ethernet networks.

[0005] In one aspect, the present invention proposes an apparatus for synchronizing an Ethernet network, adapted to connect to an Ethernet network for transmitting and receiving network data over the Ethernet network. This apparatus includes a processor, a programmable gate array (PGA), a synchronizer, a physical layer actuator, and a media access controller. The processor transmits control data externally via a first transmission interface. The PGA is electrically coupled to the processor via the first transmission interface to receive the control data, generates control commands based on the control data, and transmits the control commands externally via a second transmission interface. The synchronizer is electrically coupled to the aforementioned PGA via the second transmission interface to receive the aforementioned control commands, and further determines the content of a group of parameter values ​​associated with the generated synchronization clock based on the control commands. The physical layer actuator is electrically coupled to the aforementioned synchronizer to receive the synchronization clock it generates, and the physical layer actuator receives network data from or transmits network data to the Ethernet network based on the received synchronization clock. The media access controller is electrically coupled to the aforementioned synchronizer and physical layer actuator. It receives the aforementioned synchronization clock from the synchronizer and receives network data from the physical layer actuator or sends preparatory data to the physical layer actuator according to the synchronization clock and the media access control protocol.

[0006] In one embodiment, the aforementioned first transmission interface is a fast peripheral component interconnect interface.

[0007] In one embodiment, the aforementioned second transmission interface is an internally integrated circuit interface.

[0008] In one embodiment, the programmable gate array (PGA) includes a register set and a timer. The register set is adapted to store the aforementioned control data, while the timer is used for timing and stores at least one count value. When the control data transmitted by the processor is used to control the synchronizer to change the content of the aforementioned parameter value group, the PGA starts the timer according to the received control data and stores the number of times the timer is started as the aforementioned count value. Furthermore, after the processor changes the content of the parameter value group using a parameter changing strategy to meet the Ethernet clock synchronization requirement, it obtains the count value corresponding to this parameter changing strategy and finally selects the parameter changing strategy corresponding to the count value with the smallest average value within a unit time length based on the multiple obtained count values, so as to subsequently use the selected parameter changing strategy to adjust the parameter value group.

[0009] In one embodiment, if no control data for controlling the synchronizer to change parameter value groups is received from the processor within a preset time period after the timer starts, the aforementioned programmable gate array will generate an interrupt to the processor to notify the processor that the previously stored count value can be read.

[0010] By employing the above-described technology, the device for synchronous Ethernet proposed in this invention allows users to adjust the parameters of the synchronizer used to generate the clock signal according to their own design. Compared to existing synchronous Ethernet solutions integrated into a single integrated circuit chip, the technology proposed in this invention obviously offers users in this field greater design flexibility. Attached Figure Description

[0011] Figure 1 This is a circuit block diagram of an apparatus for a synchronous Ethernet network according to an embodiment of the present invention.

[0012] Figure 2 This is an operation flowchart of an apparatus for synchronizing an Ethernet network according to an embodiment of the present invention.

[0013] Figure 3 This is a circuit block diagram of an FPGA according to an embodiment of the present invention.

[0014] The reference numerals in the attached figures are explained as follows:

[0015] 10: Device

[0016] 15: Ethernet

[0017] 32: First transmission interface

[0018] 34: Second transmission interface

[0019] 100: Processor

[0020] 102, 112, 114, 116, 122, 124, 126, 132, 134, 136, 142, 144, 146: Connection ends

[0021] 110: Programmable Gate Array

[0022] 120: Synchronizer

[0023] 130: Media Access Controller

[0024] 140: Entity Layer Actuator

[0025] 300: Register Set

[0026] 300a~300n: Registers

[0027] 330: Execution Unit

[0028] 350: Timer

[0029] S200~S222: Operation steps of an embodiment of the present invention Detailed Implementation

[0030] To ensure that the following content is clearly understood by those skilled in the art, it should be noted that the term "electrically coupled" as used below refers to the ability to transmit electronic signals between two electrically coupled objects. Unless otherwise specified, the transmission of electronic signals may be wired or wireless, and the direction of transmission may be unidirectional or bidirectional.

[0031] Please refer to Figure 1 This is a circuit block diagram of an apparatus for synchronizing an Ethernet network according to an embodiment of the present invention. The apparatus 10 provided in this embodiment can be any device capable of exchanging data with the Ethernet network 15, such as a desktop computer, switch, router, or smartphone. As shown in the figure, the apparatus 10 in this embodiment includes a processor 100, a field-programmable gate array (FPGA) 110, a synchronizer 120, a media access controller 130, and a physical layer actuator 140. The processor 100 is electrically coupled to the FPGA 110, the FPGA 110 is further electrically coupled to the synchronizer 120 and the media access controller 130, the synchronizer 120 is further electrically coupled to the media access controller 130 and the physical layer 140, and the media access controller 130 is also electrically coupled to the physical layer actuator 140.

[0032] In this embodiment, the processor 100 and the FPGA 110 each have a connection terminal 102 and 112 conforming to the same transmission interface (hereinafter referred to as the first transmission interface) specification. Therefore, the processor 100 and the FPGA 110 can send and receive electronic data through connection terminals 102 and 112 using the transmission protocol defined by the first transmission interface. Similarly, the FPGA 110 and the synchronizer 120 each have a connection terminal 114 and 122 conforming to the same transmission interface (hereinafter referred to as the second transmission interface) specification. Therefore, the FPGA 110 and the synchronizer 120 can send and receive electronic data through connection terminals 114 and 122 using the transmission protocol defined by the second transmission interface. The FPGA 110 and the media access controller 130 each have a connection terminal 116 and 132 conforming to the same transmission interface (hereinafter referred to as the third transmission interface) specification. Synchronizer 110 and media access controller 130 can exchange electronic data via connection terminals 116 and 132 through the transmission protocol defined by the third transmission interface; synchronizer 120 and media access controller 130 each have connection terminals 124 and 134 conforming to the same transmission interface (hereinafter referred to as the fourth transmission interface) specification, thus synchronizer 120 and media access controller 130 can exchange electronic data via connection terminals 124 and 134 through the transmission protocol defined by the fourth transmission interface; synchronizer 120 and physical layer actuator 140 each have connection terminals 126 and 142 conforming to the same transmission interface (hereinafter referred to as the fifth transmission interface) specification, thus synchronizer 120 and physical layer actuator 140 can exchange electronic data via connection terminals 116 and 134 through the transmission protocol defined by the fourth transmission interface; The actuators 140 can send and receive electronic data to each other through connection terminals 126 and 142 via the transmission protocol defined by the fifth transmission interface; the media access controller 130 and the physical layer actuator 140 each have a connection terminal 136 and 144 that conform to the same transmission interface (hereinafter referred to as the sixth transmission interface) specification, so the media access controller 130 and the physical layer actuator 140 can send and receive electronic data to each other through connection terminals 136 and 144 via the transmission protocol defined by the sixth transmission interface; the physical layer actuator 140 has a connection terminal 146 that can be connected to the Ethernet network 15, so the physical layer actuator 140 and the Ethernet network 15 can send and receive electronic data to each other through connection terminal 146.

[0033] The aforementioned first to sixth transmission interfaces can use the transmission interfaces available in device 10, such as a Peripheral Component Interconnect Express (PCIe) interface and an internal integrated circuit (I... 2 C, Inter-Integrated Circuit (I-C) interface, etc., but not limited to this.

[0034] In order to make the technical content of this invention clear and easy to understand, the following will also refer to it. Figure 1 and Figure 2 To provide relevant explanations, among which, Figure 2 This is an operation flowchart of an apparatus for synchronizing an Ethernet network according to an embodiment of the present invention.

[0035] As those skilled in the art know, after connecting device 10 to Ethernet network 15, device 10 begins clock synchronization with other devices on Ethernet network 15. In this embodiment, in order to achieve clock synchronization between device 10 and other devices on Ethernet network 15, processor 100 needs to issue control data to cause synchronizer 120 to begin corresponding operations.

[0036] Control data issued by processor 100 to control synchronizer 120 is first transmitted to FPGA 110 via a first transmission interface (e.g., the aforementioned PCIe interface). After device 10 is started, FPGA 110 may clear its internal data to facilitate subsequent operations, but this is not a limitation. During the operation of device 10, after confirming receipt of control data (step S200), FPGA 110 first determines, based on the content of the control data, whether the received control data is intended to adjust various parameters of synchronizer 120 for clock synchronization (step S202). If the received control data is not intended for adjusting the parameters of synchronizer 120, FPGA 110 will directly perform the corresponding operation based on the content of the control data (step S204), such as providing the relevant data to processor 100 or forwarding it to media access controller 130, and continue to wait for the arrival of the next control data; conversely, if the received control data is intended for adjusting the parameters of synchronizer 120, FPGA 110 will start its internal timer (if the timer has not been reset to zero beforehand, it can be reset to zero first and then started), thereby calculating the time length from the receipt of this control data (step S206).

[0037] After starting the timer, FPGA 110 records the number of times the timer is reset and restarted during the timer's operation as a counter value (step S208), and then continuously checks whether another control data is received before the timer reaches a preset time length (e.g., 1 minute) (steps S210, S212). If another control data is received before the timer reaches the preset time length, FPGA 110 determines whether the newly received control data is to be used to adjust various parameters of synchronizer 120 for clock synchronization (step S220). If the determination in step S220 is yes, the process returns to step S206 to reset the timer and start it. Then, after incrementing the count value of the number of times the timer is started (step S208) (or simultaneously), a new round of timing operation continues (steps S210, S212). Conversely, if the determination in step S220 is no, that is, when the newly received control data is not used to adjust the synchronizer 120 for clock synchronization, the FPGA 110 directly performs the corresponding operation according to the content of the control data (step S222), and continues to wait for the arrival of the next control data before the timer has reached the aforementioned preset time length (steps S212, S210).

[0038] In another situation, when the timer has reached the preset time length and no other control data is received to adjust the synchronizer 120 for clock synchronization (the judgment result of step S212 is yes), the FPGA 110 will turn off the timer (step S214) and then issue an interrupt to notify the processor 100 that the count value stored in the FPGA 110 can be read (step S216).

[0039] In order for FPGA 110 to complete Figure 2 The operations mentioned above can be configured in the FPGA 110 by setting a register group and a timer, such as... Figure 3 As shown. Please refer to the following: Figure 1 and Figure 3The FPGA 30 shown in this embodiment includes a register group 300, an execution unit 330, and a timer 350. The register group 300 is electrically coupled to the processor 100 via a first transmission interface 32; the execution unit 330 is electrically coupled to the synchronizer 120 via a second transmission interface 34, and is also electrically coupled to the register group 300 and the timer 350. In this embodiment, the processor 100 can write the aforementioned control data into the register group 300 via the first transmission interface 32; the execution unit 330 can read the contents of the register group 300 and, based on the contents of the register group 300, issue control commands to the synchronizer 120 via the second transmission interface 34. As those skilled in the art will know, FPGA 30 should include other functions, such as data transfer operations with media access controller 130, storing count values ​​using timers, and providing count values ​​to processor 100 as requested by processor 100. However, since such functions can be accomplished using existing technology and are not the focus of this invention, they are not specifically marked or described in detail here.

[0040] Furthermore, since the first transmission interface 32 and the second transmission interface 34 can be any transmission interface suitable for the device 10, there are many different possibilities for the actual design of the FPGA 30. In this embodiment, the first transmission interface 32 is a PCIe interface and the second transmission interface 34 is an I / O interface. 2 Taking the PCIe interface as an example, we can illustrate a possible design for FPGA 30. In this case, FPGA 30 can serve as a PCIe interface to I / O. 2 A relay for the C interface. Those skilled in the art can develop different FPGAs 30 based on the described technical spirit, without being limited to... Figure 3 The details shown.

[0041] like Figure 3 As shown, the register group in this embodiment includes several registers 300a to 300n. These registers 300a to 300n are used to store control data transmitted from the processor 100, and the execution unit 330 can also read data from registers 300a to 300n or write data to registers 300a to 300n. For the processor 100, registers 300a to 300n correspond to different PCIe addresses, so the processor 100 can achieve the result of transmitting and storing control data in registers 300a to 300n by filling control data into each PCIe address. Table 1 below shows an embodiment of the PCIe addresses corresponding to register group 300 and their corresponding functions:

[0042]

[0043]

[0044]

[0045] Table 1

[0046] Specifically, in the register at PCIe address 0x10000, bits 31 to 24, used to express the number of bytes, use 0x00 to indicate processing 1 byte of data, 0x01 to indicate processing 2 bytes of data, and so on up to 0xff to indicate processing 256 bytes of data. Additionally, bits 15 to 8, in the register at PCIe address 0x10000, are used to express write / read instructions, using 0x00 for write and 0x01 for read. Furthermore, bits 7 to 0, in the register at PCIe address 0x10004, are used to express I... 2 The C frequency setting uses 0x04 to indicate a frequency setting of 400 kHz and 0x10 to indicate a frequency setting of 100 kHz. Finally, the values ​​led by 0x represent hexadecimal values, which are well known to those skilled in the art and will not be explained further here.

[0047] The interaction between the processor 100 and the FPGA 30 will be briefly described below based on Table 1 above.

[0048] Assuming synchronizer 120's I 2 The C device identification code is 0x15. When processor 100 wants to write a byte of data to synchronizer 120, 2 When the address offset value (Offset) in the C register is 0x03, the processor 100 first executes step one to fill the relevant data into the register at PCIe address 0x10000. The relevant data filled in includes: filling 0x00 into bits 31 to 24 ([32:24]) to indicate that a byte of data is being processed; filling 0x03 into bits 23 to 16 ([23:16]) to indicate that the address offset value is x03; filling 0x00 into bits 15 to 8 ([15:8]) to indicate that a write operation is being performed; and filling 0x15 into bits 7 to 0 ([7:0]) to indicate that the object to be processed (i.e., synchronizer 120) is I 2 The identification code for device C is 0x15.

[0049] Next, processor 100 executes step two to set I by writing data into the register at PCIe address 0x10004. 2The operating frequency of C. For example, bits 31 to 8 ([31:24], [23:16], [15:8]) are all filled with 0x00, and bits 7 to 0 ([7:0]) are filled with 0x10 to indicate that I is to be operated at a frequency of 100 kHz. 2 C interface.

[0050] Next, processor 100 executes step three to fill the data to be written to synchronizer 120 into the register with PCIe address 0x10100. The filled data includes: bits 31 to 8 ([31:24], [23:16], [15:8]) are all filled with 0x00, and bits 7 to 0 ([7:0]) are filled with 0xAA to indicate that the data to be written to synchronizer 120 is 0xAA.

[0051] Next, processor 100 executes step four to notify that PCIe to I2C should begin by writing data to the register at PCIe address 0x10004. 2 The conversion operation for C. The data to be filled in includes: 0x00 in bits 31 to 8 ([31:24], [23:16], [15:8]), and 0x01 in bits 7 to 0 ([7:0]) to indicate the start of I. 2 Data is transmitted via the C interface.

[0052] Finally, processor 100 executes step five to determine I by reading the contents of the register at PCIe address 0x1000C. 2 Has the operation in C been completed? Specifically, in I... 2 When the C interface is in use, execution unit 330 sets bits 7 to 0 ([7:0]) of the register at PCIe address 0x1000C to 0x01; while in I 2 When the C interface is idle, execution unit 330 sets bits 7 to 0 ([7:0]) of the register at PCIe address 0x1000C to 0x00. Therefore, when the contents of bits 7 to 0 of the register at PCIe address 0x1000C read in step five are 0x00, processor 100 can determine the current I / O... 2 The operation C, namely writing data to synchronizer 120, has been completed.

[0053] Similarly, when processor 100 needs to read data from synchronizer 120, processor 100 can also determine the amount of data to be read, the address offset value of the data to be read at synchronizer 120, the operation type, the device identification code of synchronizer 120, and I... 2 The operation frequency and other data for C are processed through steps one and two above. After completing steps one and two, the next step is to write data to the register at PCIe address 0x10004 to notify that the PCIe-to-I2B transfer should begin. 2 The conversion operation for C (i.e., step four above) should begin after notification. 2 After the C conversion operation, processor 100 must wait for I... 2 Operation C is complete (i.e., step five above). Finally, upon learning that I... 2 After C completes its operation, processor 100 can read the required data from the register at PCIe address 0x10200.

[0054] Using the above techniques, the present invention can easily complete the data transfer between the processor 100 and the synchronizer 120. Please return to... Figure 1 Synchronizer 120 is an electronic component that can generate a corresponding clock signal (hereinafter referred to as the synchronization clock) based on various set parameters (hereinafter collectively referred to as the parameter value group). (Such electronic components are commonly available on the market, so they will not be described in detail here.) The synchronization clock generated by synchronizer 120 is provided to media access controller 130 and physical layer actuator 140 respectively. In this embodiment, media access controller 130 is used to receive network data from physical layer actuator 140 or send pre-processed data to physical layer actuator 140 according to the received synchronization clock and the Media Accessing Control Protocol (MAC protocol); while physical layer actuator 140 is used to receive network data from Ethernet network 15 and forward it to media access controller 130 according to the received synchronization clock, or send data received from media access controller 130 to Ethernet network 15 according to the received synchronization clock. The media access controller 130 and the physical layer actuator 140 perform functions related to existing media access control protocols and physical layers, and should therefore be well known to those skilled in the art, and will not be described further here.

[0055] In this invention, the control data is provided to the FPGA 110 using the above-described technology, and it is confirmed that the FPGA 110 also completes the operation of generating control commands to change the parameter value group of the synchronizer 120 (i.e., I...). 2After the C-interface operation is completed, the processor 100 can use existing technology to perform a polling operation to confirm whether the device 10 has met the requirements of the Precision Time Protocol (PTP), that is, to confirm whether the device 10 has met the requirements of Ethernet clock synchronization. If, after polling, it is found that the device 10 has not yet met the requirements of Ethernet clock synchronization, the processor 100 can provide control instructions with different content according to the user-defined method to adjust the parameter values ​​of the synchronizer 120 and generate a different synchronization clock than before. Conversely, if, after polling, it is found that the device 10 has met the requirements of Ethernet clock synchronization, the processor 10 no longer needs to provide new control data to change the synchronization clock generated by the synchronizer 120.

[0056] Furthermore, since Ethernet clock synchronization may need to be performed every time device 10 is powered on, achieving Ethernet clock synchronization as quickly as possible is a crucial issue. As mentioned above, as processor 100 continuously changes the parameter values ​​of synchronizer 120 and the resulting synchronization clock by sending control data, timer 350 in FPGA 30 is reset and restarted accordingly, and the count value continuously increases. Therefore, in one embodiment, the user can set different parameter change strategies in the software executed by processor 100 to modify the parameter value set, and select different parameter change strategies to adjust the synchronization clock in different ways each time Ethernet clock synchronization is performed. Finally, the parameter change strategy that achieves Ethernet clock synchronization fastest is selected as the parameter change strategy used for subsequent Ethernet clock synchronizations.

[0057] For example, assuming the polling interval is consistent, and the processor 100 needs to issue 30 control data points to enable the device 10 to achieve Ethernet clock synchronization when using the first parameter change strategy to adjust the synchronization clock, while the processor 100 only needs to issue 20 control data points to enable the device 10 to achieve Ethernet clock synchronization when using the second parameter change strategy, then after reading the two count values ​​generated by the different parameter change strategies, the processor 100 can select the second parameter change strategy that results in fewer count values ​​as the parameter change strategy for subsequent Ethernet clock synchronization operations of the device 10.

[0058] As can be seen from the above, the timer 350 and the count value are actually auxiliary tools that help technicians more easily determine which parameter change strategy is more suitable for their needs. If this function is not required, the parts related to the timer 350 and the count value in the aforementioned embodiments can be omitted. Figure 2 The process shown can also be simplified further. Since these changes can be easily made by those skilled in the art based on the above description, they will not be elaborated upon here.

[0059] Furthermore, although the number of timer starts and the timer duration are used as auxiliary means to select the synchronizer parameter adjustment method in the above embodiments, the detailed technical means mentioned in these examples are for illustrative purposes only and are not intended to limit the implementation of the present invention. Those skilled in the art can design appropriate software and firmware for the processor 100 to execute to determine how to adjust the synchronizer parameters based on the hardware architecture of the device 10 disclosed in the above embodiments, without being limited to the above content.

[0060] In summary, the device for synchronous Ethernet proposed in this invention allows users to adjust the parameters of the synchronizer used to generate the clock signal according to their own design, and further utilizes timers and count values ​​to assist in determining the optimal parameter modification strategy. Compared to existing synchronous Ethernet solutions integrated into a single integrated circuit chip, the technology proposed in this invention obviously provides users in this field with greater design flexibility.

Claims

1. An apparatus for synchronizing an Ethernet network, adapted to connect to an Ethernet network for transmitting and receiving network data on the Ethernet network, characterized in that, include: A processor transmits control data to an external device via a first transmission interface; A programmable gate array is electrically coupled to the processor through the first transmission interface to receive the control data, and generates a control command based on the control data and transmits the control command to the outside of the programmable gate array through a second transmission interface. A synchronizer is electrically coupled to the programmable logic gate array via the second transmission interface to receive the control command and determine the content of a parameter value group of a generated synchronization clock according to the control command. A physical layer actuator is electrically coupled to the synchronizer to receive the synchronization clock, and the physical layer actuator receives network data from the Ethernet network or sends network data to the Ethernet network according to the synchronization clock. as well as A media access controller is electrically coupled to the synchronizer and the physical layer actuator. The media access controller receives the synchronization clock from the synchronizer and receives network data from the physical layer actuator or sends pre-processed data to the physical layer actuator according to the synchronization clock and the media access control protocol.

2. The apparatus of claim 1, wherein the first transmission interface is a fast peripheral component interconnect interface.

3. The apparatus of claim 1, wherein the second transmission interface is an internal integrated circuit interface.

4. The apparatus of claim 1, wherein the programmable logic gate array comprises: A register set suitable for storing the control data; as well as A timer, adapted to keep time and store at least one count value; When the control data transmitted by the processor is used to control the synchronizer to change the content of the parameter value group, the programmable gate array starts the timer according to the received control data and stores the number of times the timer is started as the count value. In this process, after the processor changes the parameter value group with a parameter changing strategy to achieve the requirement of Ethernet clock synchronization, it obtains the count value corresponding to the parameter changing strategy, and selects the parameter changing strategy corresponding to the count value with the minimum value based on the multiple obtained count values, so as to adjust the parameter value group thereafter.

5. The apparatus of claim 4, wherein if no control data for controlling the synchronizer to change the parameter value group is received from the processor again within a preset time period after the timer is started, the programmable gate array generates an interrupt to notify the processor that the count value can be read.

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