A method and apparatus for detecting inter-chip congestion

Abstract

The application provides a method and device for detecting inter-chip congestion. The method comprises: setting a congestion detection timer for a special hardware chip; sending a BFD detection packet to a peer by a CMIC port of the special hardware chip according to a BFD period; sending a chip congestion detection packet with a sending serial number and a destination port being the CMIC port when a sending period of the detection packet arrives; sending the chip congestion detection packet back by the CMIC port of the special hardware chip; receiving the chip congestion detection packet back by the CMIC port of the special hardware chip, refreshing a recorded sending serial number of the detection packet; calculating a detection packet delay time; and shielding a BFD fault event interrupt sent to a processor when the detection packet delay time reaches a preset fault shielding time and a maximum congestion detection time is not reached.

Description

Technical Field

[0001] This application relates to communication technology, specifically a method and device for detecting congestion between chips. Background Technology

[0002] Bidirectional Forwarding Detection (BFD) is a general, standardized, media-independent, and protocol-independent fast fault detection mechanism used to detect the connectivity of forwarding paths. It ensures that devices can quickly detect communication faults so that timely measures can be taken to guarantee continuous service operation. BFD can quickly detect faults in bidirectional forwarding paths between two devices for various upper-layer protocols (such as routing protocols). When either end of a BFD session does not receive a BFD control message within the detection time, the link is considered faulty, and the BFD session state is set to DOWN.

[0003] The BFD session between the communication equipment and the peer is implemented through a dedicated hardware chip, such as an FPGA. When the switching chip receives a BFD message from an external device, it determines the UDP port number of the BFD protocol message and then transmits the BFD message to the peer or the received BFD message from the peer through the switching chip's Gigabit Ethernet port (GE port) to the dedicated hardware chip. The physical transmit and receive channel for BFD messages between the switching chip and the dedicated hardware chip is independent of the physical transmit and receive channel between the switching chip and the CPU.

[0004] However, as the high-speed forwarding pressure of communication equipment increases, the hardware design architecture of the switching chip changes. All Ethernet ports of the switching chip are used for external forwarding. The CPU and dedicated hardware chip are connected to the bridge chip via PCIe, and the bridge chip is then connected to the CMIC (CPU Management Interface Controller) port of the switching chip via PCIe. Messages sent from the CPU and dedicated hardware chip to the outside are sent to the CMIC port through the bridge chip. Messages sent from the outside to the CPU or dedicated hardware chip are sent to the bridge chip through the CMIC port. The bridge chip then selects whether to send the message to the dedicated hardware chip or the CPU.

[0005] However, the CPU runs the entire software system of the communication device, and its performance can degrade due to the large number of messages it needs to process. For security reasons, the CPU will instruct the switching chip to reduce the inter-chip message transmission rate. The switching chip will then buffer messages destined for the CPU or dedicated hardware chips in the FIFO queue of the CMIC port. Since the number of messages sent by the switching chip to the CPU for software processing is far greater than the number of BFD messages sent to the dedicated hardware chips, the waiting time for received BFD messages in the FIFO queue of the CMIC port exceeds the BFD detection cycle, leading to false BFD fault alarms and service interruptions. Summary of the Invention

[0006] The purpose of this application is to provide a method and apparatus for detecting congestion between chips, so as to prevent congestion between chips from causing errors in the forwarding status detection between the device and other devices.

[0007] To achieve the above objectives, this application provides a method for detecting congestion between chips. The method includes: setting a congestion detection timer for a dedicated hardware chip; the dedicated hardware chip sending BFD detection messages destined for the peer to a switching chip via a CMIC port according to a bidirectional forwarding detection (BFD) cycle; the dedicated hardware chip sending a chip congestion detection message with a sequence number when the detection message sending cycle arrives; wherein the destination port of the chip congestion detection message is the CMIC port, so that the switching chip sends the chip congestion detection received at the CMIC port back to the dedicated hardware chip; the dedicated hardware chip receiving the returned chip congestion detection message through the CMIC port, refreshing the recorded detection message sending sequence number according to the received chip congestion detection message's sending sequence number; calculating the detection message delay time based on the sent chip congestion detection message's sending sequence number, the recorded detection message sending sequence number, and the detection message sending cycle; and the dedicated hardware chip blocking BFD fault event interruptions sent to the processor when the detection message delay time reaches a preset fault masking time and the congestion detection timer has not reached the maximum congestion detection time.

[0008] To achieve the above objectives, this application also provides a device for detecting congestion between chips, the device including a network interface, a switching chip, a dedicated hardware chip, a processor, and a memory.

[0009] The processor sets a congestion detection timer for a dedicated hardware chip by executing processor-executable instructions stored in the processor.

[0010] The dedicated hardware chip executes electronic instructions to send BFD detection messages destined for the other end to the switching chip through the CMIC port according to the bidirectional forwarding detection (BFD) cycle; when the detection message sending cycle is determined, a chip congestion detection message with a sending sequence number and a destination port of CMIC port is sent.

[0011] A switching chip is used to send the chip congestion detection received by the CMIC port back to a dedicated hardware chip.

[0012] The dedicated hardware chip is also used to receive chip congestion detection messages sent back through the CMIC port, refresh the recorded sequence number of the detection message according to the sequence number of the received chip congestion detection message; calculate the detection message delay time according to the sequence number of the sent chip congestion detection message, the recorded sequence number of the detection message, and the detection message sending period; and determine that the detection message delay time reaches the preset fault masking time and the congestion detection timer has not reached the maximum congestion detection time, and then mask the BFD fault event interrupt sent to the processor.

[0013] The beneficial effect of this application is that the dedicated hardware chip can accurately detect when there is queue congestion at the CMIC port between the switching chip and the dedicated hardware chip that sends and receives BFD messages, thus preventing false alarms of BFD fault events, avoiding BFD session oscillations, and ensuring normal traffic forwarding between devices. Attached Figure Description

[0014] Figure 1 A flowchart of a method for detecting congestion between chips provided in this application;

[0015] Figure 2 A schematic diagram of an embodiment of a dedicated hardware chip for detecting inter-chip congestion for sending and receiving BFD messages provided in this application;

[0016] Figure 3 A schematic diagram of another embodiment of the dedicated hardware chip for detecting inter-chip congestion for transmitting and receiving BFD messages provided in this application;

[0017] Figure 4 This is a schematic diagram of a device for detecting congestion between chips, provided in this application. Detailed Implementation

[0018] The following detailed description will be provided with reference to several examples illustrated in the accompanying figures. In this detailed description, numerous specific details are used to provide a comprehensive understanding of the present application. Known methods, steps, components, and circuits are not described in detail in the examples to avoid obscuring their meaning.

[0019] In the terminology used, the term "including" means including but not limited to; the term "containing" means including but not limited to; the terms "above," "within," and "below" include the number itself; the terms "greater than" and "less than" mean not including the number itself. The term "based on" means based on at least a portion of them.

[0020] Figure 1 A flowchart of a method for detecting inter-chip congestion provided in this application; the method of this embodiment includes,

[0021] Step 101: Set the congestion detection timer for the dedicated hardware chip;

[0022] Step 102: The dedicated hardware chip sends the BFD detection message destined for the other end to the switching chip through the CMIC port according to the bidirectional forwarding detection BFD cycle.

[0023] Step 103: When the dedicated hardware chip determines that the probe message sending period has arrived, it sends a chip congestion probe message with a sending sequence number; wherein, the destination port of the chip congestion probe message is the CMIC port, so that the switching chip sends the chip congestion probe received by the CMIC port back to the dedicated hardware chip.

[0024] Step 104: The dedicated hardware chip receives the chip congestion detection message sent back through the CMIC port, refreshes the recorded detection message sending sequence number according to the received chip congestion detection message sending sequence number, and calculates the detection message delay time according to the sent sequence number of the chip congestion detection message, the recorded detection message sending sequence number, and the detection message sending period.

[0025] Step 105: The dedicated hardware chip determines that the delay time of the probe message has reached the preset fault masking time and the congestion detection timer has not reached the maximum congestion detection time. The dedicated hardware chip then masks the BFD fault event interrupt sent to the processor.

[0026] The beneficial effect of this application is that the dedicated hardware chip can accurately detect when there is queue congestion at the CMIC port between the switching chip and the dedicated hardware chip that sends and receives BFD messages, thus preventing false alarms of BFD fault events, avoiding BFD session oscillations, and ensuring normal traffic forwarding between devices.

[0027] Figure 2 This is a schematic diagram of an embodiment of a dedicated hardware chip for transmitting and receiving BFD messages provided in this application, which detects congestion between chips.

[0028] In this application, the dedicated hardware chip can be implemented by an FPGA chip. The FPGA chip, according to the BFD detection cycle, sends BFD messages destined for the BFD session peer to the switching chip through the CMIC port; and receives BFD messages from the peer through the CMIC port. The CPU and FPGA are connected to the PEX8624 bridge chip via PCIe, and the PEX8624 bridge chip is then connected to the CMIC port of the switching chip via PCIe.

[0029] The congestion detection timer is set by the CPU for the FPGA. In this embodiment, the maximum congestion detection time is 100ms. The detection message sending period of the FPGA sending chip congestion detection message is 1ms.

[0030] The FPGA sets the destination port (destination chip port) of the chip congestion probe message to the CMIC port and sends it to the switching chip through the CMIC port. After receiving the chip congestion probe message, the switching chip finds that the destination port is the CMIC port, and then forwards the chip congestion probe message back to the FPGA through the CMIC port.

[0031] Figure 2 In the process, when the FPGA sends a chip congestion detection message with a sequence number of 60, the FPGA receives a chip congestion detection message with a sequence number of 59 through the CMIC port; the FPGA attribute record shows that the received chip congestion detection message has a sequence number of 59; based on the difference between the sequence number of the sent chip congestion detection message 60 and the sequence number of the received chip congestion detection message, which is 1, and based on the detection message sending period of 1ms, the delay between the currently sent chip congestion detection message and the currently received chip congestion detection message is calculated to be 1ms; this is less than the preset fault masking time of 10ms; therefore, it is confirmed that no chip congestion has occurred.

[0032] Figure 3 A schematic diagram of another embodiment of the dedicated hardware chip for detecting inter-chip congestion for transmitting and receiving BFD messages provided in this application;

[0033] The CPU software processes too many messages, causing the backpressure switching chip to reduce the rate at which messages are sent through the CMIC. The switching chip then buffers the messages sent through the CMIC port in the FIFO queue of the CMIC port, resulting in congestion.

[0034] However, there was no congestion in the direction of the processor CPU and FPGA sending messages to the CMIC port, and the FPGA continued to send BFD detection messages and chip congestion detection messages through the CMIC port.

[0035] Figure 3 In the process, when the FPGA sends a chip congestion detection message with a sequence number of 60, the FPGA receives a chip congestion detection message with a sequence number of 49 through the CMIC port; the FPGA attribute record shows that the received chip congestion detection message has a sequence number of 49; based on the difference between the sequence number of the sent chip congestion detection message 60 and the sequence number of the received chip congestion detection message, which is 11, and based on the detection message sending period of 1ms, the delay between the currently sent chip congestion detection message and the currently received chip congestion detection message is calculated to be 11ms; the preset fault masking time of 10ms has been reached.

[0036] The FPGA determines that the current congestion detection timer has not reached the maximum congestion detection time of 100ms, and the dedicated hardware chip shields the BFD fault event interrupt sent to the processor; it avoids sending interrupt signals to the CPU to notify the BFD fault event and avoids false reports of BFD detection faults.

[0037] If the FIFO queue at the CMIC port towards the FPGA and CPU is cleared, the FPGA will receive the chip congestion detection message again. Figure 3 (Not shown in the image), the BFD fault timeout sent to the processor is released after a predetermined delay (e.g., 5ms). Within the maximum congestion detection time, the FPGA receives the chip congestion detection message again and refreshes the recorded sequence number of the detection message.

[0038] If the FIFO queue from the CMIC port to the FPGA and CPU remains congested, and the FPGA does not receive a chip congestion detection message within the maximum congestion detection time, the recorded sequence number of the detection message does not need to be refreshed.

[0039] Figure 3 In the process, after the FPGA detects congestion at the CMIC port, regardless of whether it receives a chip congestion detection message from the switching chip, it releases the BFD fault event interrupt destined for the processor CPU when the congestion detection timer reaches the maximum congestion detection time; resets the sequence number of the recorded detection message; and sends a BFD fault event interrupt signal to the CPU to notify of the BFD fault.

[0040] Figure 2 and Figure 3 In the process, if the FPGA does not detect chip congestion or detects chip congestion, after the congestion detection timer reaches the maximum congestion detection time, it waits for a period of time (e.g., 30ms) and then restarts the congestion detection timer to continue detecting whether inter-chip congestion has occurred at the CMIC port.

[0041] Figure 4 This application provides a schematic diagram of a device for detecting congestion between chips. The device includes a network interface, a switching chip, a dedicated hardware chip, a processor, and memory. The dedicated hardware chip can be implemented using an FPGA chip.

[0042] The processor sets a congestion detection timer for the dedicated hardware chip by executing processor-executable instructions stored in the processor. The dedicated hardware chip executes electronic instructions to send BFD detection messages destined for the peer to the switching chip through the CMIC port according to the bidirectional forwarding detection (BFD) cycle. When the detection message sending cycle is reached, it sends a chip congestion detection message with a sequence number and a destination port of the CMIC port. The switching chip sends the chip congestion detection received through the CMIC port back to the dedicated hardware chip and sends the BFD messages received through the CMIC port to the peer device. The dedicated hardware chip also receives the returned chip congestion detection messages through the CMIC port, refreshes the recorded detection message sequence number based on the received chip congestion detection message sequence number, calculates the detection message delay time based on the sent chip congestion detection message sequence number, the recorded detection message sequence number, and the detection message sending cycle. When the detection message delay time reaches the preset fault masking time and the congestion detection timer has not reached the maximum congestion detection time, it masks the BFD fault event interrupt sent to the processor.

[0043] The dedicated hardware chip is also used to determine when the congestion detection timer reaches the maximum congestion detection time, release the BFD fault event interrupt destined for the processor, reset the sequence number of the recorded probe packets, and send a BFD fault event interrupt signal to the CPU.

[0044] The dedicated hardware chip receives the chip congestion detection message sent back through the CMIC port and refreshes the recorded sequence number of the detection message. The dedicated hardware chip determines that the congestion detection timer has not reached the maximum congestion detection time, and releases the BFD fault time interrupt sent to the processor after a preset delay.

[0045] The dedicated hardware chip is also used to determine if the congestion detection timer has not reached the maximum congestion detection time, reset the sequence number of the recorded detection packets, and send a BFD fault event interrupt signal to the CPU.

[0046] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for detecting congestion between chips, characterized in that, The method includes, Set up a congestion detection timer for the dedicated hardware chip; The dedicated hardware chip sends the BFD detection message destined for the other end to the switching chip through the CMIC port according to the bidirectional forwarding detection (BFD) cycle. When the dedicated hardware chip determines that the probe message sending period has arrived, it sends a chip congestion probe message with a sending sequence number; wherein, the destination port of the chip congestion probe message is the CMIC port, so that the switching chip sends the chip congestion probe received by the CMIC port back to the dedicated hardware chip. The dedicated hardware chip receives the chip congestion detection message sent back through the CMIC port, refreshes the recorded detection message sending sequence number according to the received chip congestion detection message sending sequence number, and calculates the detection message delay time according to the sent sequence number of the chip congestion detection message, the recorded detection message sending sequence number, and the detection message sending period. The dedicated hardware chip determines that the delay time of the probe message reaches the preset fault masking time and the congestion detection timer has not reached the maximum congestion detection time, and then the dedicated hardware chip masks the BFD fault event interrupt sent to the processor.

2. The method according to claim 1, characterized in that, The method further includes: The dedicated hardware chip determines when the congestion detection timer reaches the maximum congestion detection time that it releases the BFD fault event interrupt destined for the processor. Reset the sequence number of the recorded probe messages; Send a BFD fault event interrupt signal to the CPU.

3. The method according to claim 1, characterized in that, The method further includes: The dedicated hardware chip receives the chip congestion detection message sent back through the CMIC port and refreshes the recorded detection message transmission sequence number. The dedicated hardware chip determines that the congestion detection timer has not reached the maximum congestion detection time, and releases the BFD fault time interrupt destined for the processor after a preset delay.

4. The method according to claim 3, characterized in that, The method further includes: The dedicated hardware chip determines that the congestion detection timer has not reached the maximum congestion detection time, resets the sequence number of the recorded detection packets, and sends a BFD fault event interrupt signal to the CPU.

5. A device for detecting congestion between chips, characterized in that, The device includes a network interface, a switching chip, a dedicated hardware chip, a processor, and a memory. The processor sets a congestion detection timer for the dedicated hardware chip by running processor-executable instructions stored in the processor; The dedicated hardware chip executes electronic instructions to send BFD detection messages destined for the other end to the switching chip through the CMIC port according to the bidirectional forwarding detection (BFD) cycle; when the detection message sending cycle is determined to be reached, a chip congestion detection message with a sending sequence number and the destination port being the CMIC port is sent. The switching chip is used to send the chip congestion detection received by the CMIC port back to the dedicated hardware chip; The dedicated hardware chip is also used to receive the chip congestion detection message sent back through the CMIC port, refresh the recorded detection message sending sequence number according to the received chip congestion detection message sending sequence number, and calculate the detection message delay time according to the sent sequence number of the chip congestion detection message, the recorded detection message sending sequence number and the detection message sending period. If the delay time of the probe message reaches the preset fault masking time and the congestion detection timer has not reached the maximum congestion detection time, the BFD fault event interruption sent to the processor is masked.

6. The device according to claim 5, characterized in that, The dedicated hardware chip is also used to determine when the congestion detection timer reaches the maximum congestion detection time, release the BFD fault event interrupt destined for the processor; reset the sequence number of the recorded detection message; and send a BFD fault event interrupt signal to the CPU.

7. The device according to claim 5, characterized in that, The dedicated hardware chip receives the chip congestion detection message sent back through the CMIC port and refreshes the recorded detection message transmission sequence number. The dedicated hardware chip determines that the congestion detection timer has not reached the maximum congestion detection time, and releases the BFD fault time interrupt destined for the processor after a preset delay.

8. The device according to claim 7, characterized in that, The dedicated hardware chip is also used to determine that the congestion detection timer has not reached the maximum congestion detection time, reset the sequence number of the recorded detection message, and send a BFD fault event interrupt signal to the CPU.

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