Semiconductor structure and method of fabricating the same

Abstract

This disclosure relates to the semiconductor field, providing a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, and an active layer spaced apart on the substrate; multiple bit lines spaced apart along a first direction and extending along a second direction, with a first portion of each bit line covering a side surface of the active layer and a second portion of each bit line located within the active layer; both the first and second directions are parallel to the surface of the substrate and intersect each other. This can improve the reliability of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Memory is a storage component used to store programs and various data information. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor storage device in computers, consisting of many repeating storage cells.

[0003] A memory cell typically includes a capacitor and a transistor. The drain of the transistor is connected to the bit line, and the source is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitance. The word line of the memory cell can control the opening or closing of the transistor's channel region, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0004] However, there are currently position lines that are difficult to connect into a single line. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for fabricating the same, which can at least reduce the difficulty of forming interconnected bit lines.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including a substrate and an active layer spaced apart on the substrate; a plurality of bit lines, the plurality of bit lines being spaced apart along a first direction, the bit lines extending along a second direction, a first portion of each bit line covering a side surface of the active layer, and a second portion of each bit line located within the active layer; both the first direction and the second direction are parallel to the surface of the substrate, and the first direction intersects the second direction.

[0007] In some embodiments, the first portion includes two first conductive structures spaced apart and extending along the second direction, and the second portion includes a plurality of second conductive structures located within the active layer. The plurality of second conductive structures are located at least between two of the first conductive structures, and each second conductive structure is electrically connected to a first conductive structure.

[0008] In some embodiments, a plurality of the second conductive structures are connected as a whole along the extension direction of the bit line and penetrate the active layer.

[0009] In some embodiments, the material of the second conductive structure includes a metal silicide, and the material of the first conductive structure includes a conductive metal.

[0010] In some embodiments, the thickness of the first conductive structure in the first direction is 1 nm-3 nm.

[0011] In some embodiments, on a plane perpendicular to the substrate, the height of the overlapping portion of the projection of the second conductive structure and the projection of the first conductive structure is 0.5 to 1 times the height of the projection of the second conductive structure.

[0012] According to some embodiments of this disclosure, another aspect of this disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate, forming an active layer spaced apart along a first direction in the substrate; forming a plurality of bit lines spaced apart along the first direction, the bit lines extending along a second direction, a first portion of each bit line covering a side surface of the active layer, and a second portion of each bit line located within the active layer; the first direction and the second direction are both parallel to the surface of the substrate, and the first direction intersects the second direction.

[0013] In some embodiments, the method of forming a plurality of bit lines includes: forming a plurality of first conductive structures extending along a second direction, the first conductive structures being located on the active layer spaced apart along the first direction; forming a plurality of second conductive structures, the plurality of second conductive structures being located within the active layer, the second conductive structures being located at least between two first conductive structures and being electrically connected to the first conductive structures in contact.

[0014] In some embodiments, the step of forming the first conductive structure includes: providing the substrate; patterning the substrate to form active layers spaced apart along the first direction; forming a first isolation layer located between adjacent active layers, wherein the top surface of the first isolation layer is lower than the top surface of the active layers; and forming the first conductive structure above the first isolation layer.

[0015] In some embodiments, the step of forming the first isolation layer includes: forming a first mask layer on the surface of the substrate; etching the first mask layer and the substrate to form a plurality of first trenches extending along the second direction, the first trenches being located between adjacent active layers; filling the first trenches with insulating material; and removing a portion of the insulating material to form the first isolation layer in the first trenches.

[0016] In some embodiments, the step of forming the first conductive structure over the first isolation layer includes: forming a second mask layer, the second mask layer being located above the first isolation layer and covering the sidewalls of the active layer; removing a portion of the first isolation layer and a portion of the sidewalls of the active layer located below the second mask layer to form a first groove; depositing a first conductive material in the first groove; patterning the first conductive material to form a first conductive structure arranged at intervals.

[0017] In some embodiments, the step of forming the second conductive structure includes: etching the active layer to form a plurality of second trenches extending along the first direction, the bottom surface of the second trenches being higher than the top surface of the first conductive structure; forming a third mask layer in the second trenches, the third mask layer covering the sidewalls of the second trenches; depositing a second conductive material at the bottom of the second trenches; and rapidly heat-treating to form the second conductive structure.

[0018] In some embodiments, the second conductive material comprises a metallic material that diffuses into the active layer during rapid thermal processing to form a metal silicide, the metal silicide being located at least between two of the first conductive structures to form the second conductive structure.

[0019] In some embodiments, the temperature of the rapid heat treatment is 400°C to 800°C.

[0020] In some embodiments, a plurality of second conductive structures located between two first conductive structures are interconnected and extend through the active layer along the second direction.

[0021] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by setting a first part of the bit line covering the side of the active layer and a second part of the bit line located in the active layer, the bit line can be connected into a line in the second direction, thereby realizing the bit line read and write function and reducing the difficulty of forming the bit line. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is a top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0024] Figure 2 A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure;

[0025] Figures 3 to 17 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0026] As is known from the background technology, it is currently difficult for bit lines formed by metal silicide processes to diffuse and connect into a single line in the second direction, which will affect the reliability of the semiconductor structure. When the bit lines are not connected in the second direction, the function of the formed bit lines may be abnormal, and it will also affect the function of the semiconductor structure.

[0027] This disclosure provides a semiconductor structure in which a first portion of a bit line is provided on the side of an active layer, and a second portion of a bit line is provided inside the active layer, thereby connecting the bit lines into a single line in a second direction. The connection between the first and second portions can improve the reliability of the semiconductor structure and ensure the transmission function of the bit lines.

[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] refer to Figure 1 and Figure 2 , Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 As an embodiment of this disclosure Figure 1 A cross-sectional view along the direction of the dashed line.

[0030] refer to Figure 1 The semiconductor structure includes: a substrate 100, and an active layer 110 spaced apart on the substrate 100; multiple bit lines 120 spaced apart along a first direction X and extending along a second direction Y; multiple word lines 130 extending along the first direction X and spaced apart along the second direction Y; and a dielectric layer 140 located on the sidewall of the active layer 110 to prevent the word lines 130 from directly contacting the active layer 110. The first direction X and the second direction Y are both parallel to the surface of the substrate 100, and the first direction X and the second direction Y intersect.

[0031] In some embodiments, the substrate 100 may be made of silicon, germanium, or silicon germanide, and may also be doped. For example, if the substrate 100 is made of silicon, a trace amount of trivalent element, such as boron, indium, gallium, or aluminum, may be doped into the substrate 100 to form a P-type substrate. Similarly, a trace amount of pentavalent element, such as phosphorus, antimony, or arsenic, may be doped into the substrate 100 to form an N-type substrate. The selection of doping elements for the substrate 100 may be based on actual needs and product performance. This disclosure does not limit the material of the substrate 100 or the doped elements.

[0032] In some embodiments, word line 130 can be a multilayer stacked structure, such as including: a polysilicon layer, a metal layer and a protective layer. By providing a polysilicon layer, abnormalities can be avoided when the electrical signal of the substrate material is directly transmitted to the metal layer of word line 130. By providing a metal layer, the signal transmission speed of word line 130 can be improved. By providing a protective layer, oxidation of the metal layer of word line 130 due to contact with the outside world can be avoided, thus preventing the reduction of the conductivity of word line 130 due to partial oxidation of the metal layer.

[0033] In some embodiments, the dielectric layer 140 may be made of insulating materials such as silicon oxide or silicon nitride, thereby preventing word lines 130 from directly contacting the active layer 110 and causing abnormal semiconductor structures.

[0034] refer to Figure 2 In some embodiments, the first portion of each bit line 120 covers the side of the active layer 110, and the second portion of each bit line 120 is located within the active layer 110. By setting the first portion to cover the side of the active layer 110 and the second portion to be located within the active layer 110, the bit line 120 can be made into a continuous whole, thereby ensuring the continuity of signal transmission of the bit line 120 and improving the reliability of the semiconductor structure.

[0035] In some embodiments, the first part may include two first conductive structures 121 that are spaced apart and extend along the second direction Y, and the second part may include a plurality of second conductive structures 122. The plurality of second conductive structures 122 are located within the active layer 110. The plurality of second conductive structures 122 are located at least between two first conductive structures 121, and each second conductive structure 122 is electrically connected to a first conductive structure 121.

[0036] By setting the first conductive structure 121 and the second conductive structure 122 to be electrically connected, the bit line 120 can be made into a continuous whole. Furthermore, by setting the first conductive structure 121 to be located on the sidewalls of the active layer 110 at intervals along the first direction X, the first conductive structure 121 and the second conductive structure 122 can be connected on the sidewalls of the active layer 110 at intervals along the first direction X, thereby improving the reliability of the bit line 120 conduction.

[0037] In some embodiments, multiple second conductive structures 122 are connected as a whole along the extension direction of bit line 120 and penetrate the active layer 110. It is understood that when the process of forming the second conductive structure 122, such as the metal silicide process, is good enough, the second conductive structure 122 can penetrate the active layer 110 along the extension direction of bit line 120, and the bit line 120 can form a continuous whole through the second conductive structure 122. At this time, the first conductive structure 121 can improve the conductivity of bit line 120 and improve the reliability of bit line 120 connection.

[0038] It should be noted that it is difficult to form a second conductive structure 122 that extends through the active layer 110 along the extension direction of the bit line 120 using metal silicide processes. Therefore, by forming a first conductive structure 121, the second conductive structures 122 arranged at intervals in the second direction are connected to form a continuous bit line 120, thereby improving the reliability of the semiconductor structure.

[0039] In some embodiments, the material of the second conductive structure 122 may include a metal silicide, and the material of the first conductive structure 121 may include a conductive metal, such as titanium nitride, tungsten, or molybdenum. By using a metal silicide as the material of the second conductive structure 122, the contact resistance between the second conductive structure 122 and the active layer 110 can be reduced; by using a metallic material as the material of the first conductive structure 121, the transmission rate of the first conductive structure 121 can be increased.

[0040] In some embodiments, the thickness of the first conductive structure 121 in the first direction X is 1nm-3nm, for example, 1.5nm or 2nm. When the thickness of the first conductive structure 121 is less than 1nm, the resistance of the first conductive structure 121 is relatively large, which may affect the conduction performance of the bit line 120; when the thickness of the first conductive structure 121 is greater than 3nm, it may cause adjacent bit lines 120 to connect or cause adjacent bit lines 120 to interfere with each other. In other embodiments, the thickness of the first conductive structure can also be other dimensions, and the thickness of the first conductive structure can be adjusted according to actual needs.

[0041] In some embodiments, on a plane perpendicular to the substrate 100, the height of the overlapping portion of the projections of the second conductive structure 122 and the first conductive structure 121 is 0.5 to 1 times the height of the projection of the second conductive structure 122. It is understood that when the height of the overlapping portion is less than 0.5 times the height of the projection of the second conductive structure 122, the interfacial contact resistance between the first conductive structure 121 and the second conductive structure 122 is high. By setting the height of the overlapping portion to be 0.5 to 1 times the height of the projection of the second conductive structure 122, the interfacial contact resistance between the first conductive structure 121 and the second conductive structure 122 can be reduced. In other embodiments, the height of the overlapping portion is 0.5 to 1 times the height of the projection of the first conductive structure.

[0042] It is understood that, in the direction perpendicular to the substrate 100, the height of the second conductive structure 122 is less than or equal to the height of the first conductive structure 121. When the projection of the second conductive structure 122 is located within the projection of the first conductive structure 121, the height of the overlapping portion of the projection of the second conductive structure 122 and the projection of the first conductive structure 121 is 1 times the height of the projection of the second conductive structure 122. In the direction perpendicular to the substrate 100, the height of the second conductive structure 122 is greater than or equal to the height of the first conductive structure 121. When the projection of the first conductive structure 121 is located within the projection of the second conductive structure 122, the height of the overlapping portion of the projection of the second conductive structure 122 and the projection of the first conductive structure 121 is 1 times the height of the projection of the first conductive structure 121.

[0043] In some embodiments, the semiconductor structure further includes: a first isolation layer 170, which is located on the surface of the substrate 100 and between the active layers 110; a second isolation layer 200, which is located on the top surface of the first isolation layer 170; a third isolation layer 240, which is located on the top surface of the second conductive structure 122, and the top surface of the third isolation layer 240 is lower than the top surface of the active layer 110 and higher than or flush with the top surface of the first conductive structure 121; and a fourth isolation layer 250, which is located on the top surface of the third isolation layer 240, and is located between adjacent word lines 130, and also on the top surface of the active layer 110 and the word lines 130.

[0044] This disclosure provides a semiconductor structure, including: a first portion of a bit line 120 covering the side of an active layer 110, and a second portion of the bit line 120 located within the active layer 110, wherein the first portion and the second portion are electrically connected, which enables the bit line 120 to form a continuous whole in a second direction, thereby improving the stability of the signal transmitted by the bit line 120 and thus improving the reliability of the semiconductor structure.

[0045] Another embodiment of this disclosure also provides a method for fabricating a semiconductor structure. This method can be used to form the above-mentioned semiconductor structure. The method for fabricating a semiconductor structure provided by another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be repeated below.

[0046] refer to Figure 3 and Figure 4 A substrate 101 is provided, in which active layers 110 are formed at intervals along a first direction X.

[0047] It should be noted that the portion of the substrate 101 located at the bottom of the active layer 110 after the patterned substrate 101 can be referred to as the substrate 100.

[0048] In some embodiments, the step of forming the active layer 110 may include: forming a first mask layer 150 on the surface of a substrate 101; etching the first mask layer 150 and the substrate 101 to form a plurality of first trenches 160 extending along a second direction Y, wherein the first trenches 160 are located between adjacent active layers 110. That is, the first trenches 160 and the active layers 110 are formed in the same step, a portion of the substrate 101 is patterned and removed, and the remaining substrate 101 forms the first trenches 160, with the portion of the substrate 101 serving as the active layer 110. The formation of the first trenches 160 provides a process basis for the subsequent formation of the first conductive structure.

[0049] In some embodiments, the active layer 110 can be formed using a self-aligned double patterning (SADP) process, while in other embodiments, it can be formed using a self-aligned quadruple patterning (SAQP) process. SADP or SAQP techniques can result in a more precise pattern of the formed active layer 110.

[0050] In some embodiments, the first mask layer 150 is retained after the active layer 110 is formed. By retaining the first mask layer 150, the top surface of the formed active layer 110 can be protected, thereby preventing the top surface of the active layer 110 from being contaminated, and thus improving the stability of the semiconductor structure. In other embodiments, the formation of the active layer may further include: removing the first mask layer.

[0051] refer to Figure 5 and Figure 6 A first isolation layer 170 is formed, which is located between adjacent active layers 110, and the top surface of the first isolation layer 170 is lower than the top surface of the active layer 110.

[0052] For details, please refer to Figure 5 The first trench 160 is filled with insulating material to form a first initial isolation layer 171. In some embodiments, the top surface of the first initial isolation layer 171 is also higher than the top surface of the active layer 110. This can be achieved by graphically removing a portion of the first initial isolation layer 171 so that the top surface of the first initial isolation layer 171 is flush with the top surface of the active layer 110. It should be noted that "flush" here can mean that the top surface of the first initial isolation layer 171 is completely flush with the top surface of the active layer 110; or that the height difference between the top surface of the first initial isolation layer 171 and the top surface of the active layer 110 is within an allowable range, which can also be considered as the top surface of the first initial isolation layer 171 being flush with the top surface of the active layer 110.

[0053] In some embodiments, the insulating material may be silicon oxide or silicon nitride, etc. Taking silicon oxide as an example, silicon oxide is relatively soft, easy to fill, and easy to etch. Filling with silicon oxide to form the first initial isolation layer 171 also facilitates the subsequent patterning of the first initial isolation layer 171.

[0054] refer to Figure 6 Part of the insulating material is removed to form a first insulating layer 170 in the first trench 160. The thickness of the first insulating layer 170 can be controlled by filling the first trench 160 first and then removing it, thereby forming a more precise first insulating layer 170.

[0055] In some embodiments, the first initial isolation layer 171 can be etched by wet etching to form the first isolation layer 170, and the thickness of the first initial isolation layer 171 removed by etching can be controlled by controlling the concentration of the etching reagent and the etching time.

[0056] refer to Figures 7 to 16Multiple bit lines 120 are formed, spaced apart along a first direction X. The bit lines 120 extend along a second direction Y. A first portion of each bit line 120 covers the side surface of the active layer 110, and a second portion of each bit line 120 is located within the active layer 110. Both the first direction X and the second direction Y are parallel to the surface of the substrate 101, and the first direction X intersects the second direction Y. By forming bit lines 120 with a first portion covering the side surface of the active layer 110 and a second portion located within the active layer 110, the bit lines 120 can be made into a continuous whole, thereby ensuring the continuity of signal transmission through the bit lines 120 and improving the reliability of the semiconductor structure.

[0057] refer to Figures 7 to 10 Multiple first conductive structures 121 extending along the second direction Y are formed. The first conductive structures 121 are located on the side surfaces of the active layer 110 spaced apart along the first direction. The multiple first conductive structures 121 constitute the first portion of the bit line 120. By forming the first conductive structures 121, a basis can be provided for subsequent connection of the second conductive structures to form a continuous bit line 120, thereby improving the reliability of the semiconductor structure.

[0058] For details, please refer to Figure 7 A second initial mask layer 181 is formed, which is located above the first isolation layer 170 and covers the sidewalls of the active layer 110. In some embodiments, the second initial mask layer 181 can be formed on the sidewalls of the active layer 110, the top surface of the first isolation layer 170, the sidewalls of the first mask layer 150, and the top surface of the first mask layer 150 by atomic layer deposition. The second initial mask layer 181 can be used as a mask layer for subsequent etching of the first isolation layer 170. The second initial mask layer 181 formed by atomic layer deposition is relatively uniform and the thickness of the formed second initial mask layer 181 is easy to control.

[0059] In some embodiments, the material of the second initial mask layer 181 may be carbon or carbon-containing organic materials, which are relatively soft, have a fast etching speed, and can be used as a mask with a more precise pattern, thereby improving the accuracy of the subsequent first conductive structure.

[0060] refer to Figure 8 Graphicalized second initial mask layer 181 (reference) Figure 7 Remove the second initial mask layer 181 located on the top surface of the first mask layer 150 and part of the surface of the first isolation layer 170 (see reference). Figure 7 A second mask layer 180 is formed by spacing it in a first direction. The second mask layer 180 is located above the first isolation layer 170 and covers the sidewalls of the active layer 110. The second mask layer 180 can serve as a mask for the subsequent formation of the spaced first conductive structure.

[0061] refer to Figure 9 A portion of the first isolation layer 170 and a portion of the sidewalls of the active layer 110 located below the second mask layer 180 are removed to form a first groove 190. It should be noted that during the etching of the first isolation layer 170, the etching reagent inevitably comes into contact with the active layer 110, thus etching a portion of the active layer 110. In other embodiments, only a portion of the first isolation layer 170 may be etched. Forming the first groove 190 provides a process basis for the subsequent formation of the first conductive structure. Etching a portion of the active layer 110 provides more space for the subsequently formed first conductive structure, thereby increasing the width of the first conductive structure and reducing its resistance.

[0062] refer to Figure 10 A first conductive material is deposited in the first groove 190 to form a first initial conductive structure. The first conductive material is then patterned to form spaced-apart first conductive structures 121. In some embodiments, the first initial conductive structure can be patterned by filling the first groove 190 with the first conductive material and then using a second mask layer 180 as a mask to form the spaced-apart first conductive structures 121. In other embodiments, the first conductive structures 121 can be formed on the bottom surface of the second mask layer by selective atomic layer deposition. The formation of the first conductive structure 121 provides a basis for the subsequent formation of bit lines connected in the first direction.

[0063] It is understandable that the first conductive structures 121 patterned to form an interval arrangement of a first initial conductive structure are first conductive structures 121 of different bit lines. In other words, the first conductive structures 121 located on both sides of the same active layer 110 are the first part of the same bit line.

[0064] refer to Figures 11 to 15 Multiple second conductive structures 122 are formed within the active layer 110. Each second conductive structure 122 is located between at least two first conductive structures 121 and is electrically connected to the first conductive structures 121. By forming second conductive structures 122 electrically connected to the first conductive structures 121, continuous bit lines 120 can be formed, making the bit lines 120 a single unit, thereby improving the reliability of the semiconductor structure.

[0065] For details, please refer to Figure 11 Remove the first mask layer 150 and the second mask layer 180 to expose the top surface of the active layer 110 and the first isolation layer 170.

[0066] refer to Figure 12A second isolation layer 200 is formed. The second isolation layer 200 is located on the top surface of the first isolation layer 170 and is also located between the active layers 110. By setting the second isolation layer 200, the first conductive structure 121 can be protected, and the word lines formed subsequently can be prevented from contacting the first conductive structure 121.

[0067] In some embodiments, the step of forming the second isolation layer 200 may include: forming a second initial isolation layer, the second initial isolation layer further covering the top surface of the active layer 110, graphically representing the second initial isolation layer until the top surface of the active layer 110 is exposed, and the remaining second initial isolation layer serving as the second isolation layer 200.

[0068] refer to Figure 13 The active layer 110 is etched to form multiple second trenches 210 extending along the first direction X. The bottom surface of the second trenches 210 is higher than the top surface of the first conductive structure 121. The second trenches 210 are used to form the third mask layer in the future. The formation of the second trenches 210 provides a process basis for the subsequent formation of the second conductive structure.

[0069] In some embodiments, it further includes: an etched portion of a second isolation layer 200.

[0070] In some embodiments, a second trench 210 can be formed by forming a fourth mask layer 230 on the top surface of the active layer 110 and by patterning the active layer 110 with the fourth mask layer 230 as a mask. The second trench 210 with a more precise pattern can be formed by forming the fourth mask layer 230. In other embodiments, the second trench can also be formed in other ways.

[0071] In some embodiments, after the second trench 210 is formed, the fourth mask layer 230 is retained. By retaining the fourth mask layer 230, the active layer 110 can be protected from contamination in subsequent process steps, thereby improving the reliability of the semiconductor structure.

[0072] In some embodiments, the material of the fourth mask layer 230 can be the same as that of the first mask layer 150, such as silicon nitride.

[0073] refer to Figure 14 A third mask layer 220 is formed in the second trench 210, and the third mask layer 220 covers the sidewall of the second trench 210. By forming the third mask layer 220, the active layer 110 can be protected when the second conductive structure is formed in the subsequent metal silicide process, thereby avoiding contamination of the inner wall of the second trench 210. The reliability of the semiconductor structure is improved by forming the third mask layer 220.

[0074] In some embodiments, the step of forming the third mask layer 220 may include: forming a third initial mask layer, the third initial mask layer further covering the top surface of the fourth mask layer 230 and the surface of the active layer 110; and patterning the third initial mask layer to form spaced third mask layers 220. During the patterning of the third initial mask layer, the fourth mask layer 230 can serve as an etch stop layer for etching the third initial mask layer, and the fourth mask layer 230 can also prevent the etchant from directly contacting the top surface of the active layer 110, thereby preventing contamination of the top surface of the active layer 110 and improving the reliability of the semiconductor structure.

[0075] In some embodiments, the third mask layer 220 and the second mask layer 180 may be made of the same material, such as carbon or carbon-containing organic materials.

[0076] refer to Figure 15 A second conductive material is deposited at the bottom of the second trench 210, followed by rapid thermal processing to form a second conductive structure 122. In some embodiments, the second conductive material may include a metallic material, which diffuses into the active layer 110 during rapid thermal processing to form a metal silicide. The metal silicide is located at least between the two first conductive structures 121 to form the second conductive structure 122. That is, the second conductive structure 122 is formed using a metal silicide process to reduce the resistance of forming the second conductive structure 122, thereby improving the performance of the semiconductor structure. After forming the second conductive structure 122, the process further includes removing the second conductive material to expose the top surface of the second conductive structure 122.

[0077] In some embodiments, rapid thermal treatment can be rapid thermal annealing (RTA). In some embodiments, two rapid thermal annealing processes can be used to avoid the overgrowth of the second conductive structure 122, which could lead to a short circuit.

[0078] Specifically, the steps for forming the second conductive structure 122 may include: depositing a second conductive material at the bottom of the second trench 210, taking titanium as the second conductive material and single-crystal silicon as the active layer material as an example; after depositing the second conductive material, depositing a titanium nitride film on the surface of the titanium, which can prevent the titanium from flowing during rapid thermal annealing; performing a first rapid thermal annealing process, in which the titanium reacts with the single-crystal silicon of the active layer 110 to generate a high-resistivity metal silicide; removing the titanium and titanium nitride film by selective wet etching; and performing a second rapid thermal annealing process, which can convert the high-resistivity metal silicide into a low-resistivity metal silicide. The low-resistivity metal silicide is the second conductive structure. It is understood that the above-mentioned titanium nitride film, titanium, and single-crystal silicon material are only examples for ease of explanation and do not limit the materials of the second conductive material, the film on the second conductive material, and the active layer 110, which can be adjusted according to the actual situation.

[0079] In some embodiments, the rapid thermal processing temperature can be 400°C to 800°C. When the rapid thermal processing temperature is less than 400°C, the formation rate of the second conductive structure 122 is slow, and the morphology of the formed second conductive structure 122 is poor. When the rapid thermal processing temperature is greater than 800°C, the formation of the second conductive structure 122 may affect the first conductive structure 121, which may cause the first conductive structure 121 to malfunction. Therefore, by setting the rapid thermal processing temperature to 400°C to 800°C, the formation rate and morphology of the second conductive structure 122 can be guaranteed while avoiding the impact on other structures of the semiconductor structure.

[0080] In some embodiments, the rapid heat treatment is performed twice, and the temperature of the later rapid heat treatment can be higher than the temperature of the earlier rapid heat treatment.

[0081] In some embodiments, a plurality of second conductive structures 122 located between two first conductive structures 121 are interconnected and penetrate the active layer 110 along the second direction Y. By forming a plurality of interconnected second conductive structures 122, the formed bit line 120 can be a continuous whole, thereby improving the stability of the signal transmitted by the bit line 120 and thus improving the reliability of the semiconductor structure.

[0082] It should be noted that it is difficult to guarantee that the metal ions diffuse into a continuous whole within the active layer 110 through the metal silicide process. Therefore, by forming the first conductive structure 121 first and then performing the metal silicide process, even if the metal silicide process does not form a continuous whole within the active layer 110, the bit line 120 can still be made into a continuous whole by connecting the first conductive structure 121 and the second conductive structure 122. This can ensure the stability of the signal transmitted by the bit line 120 and improve the reliability of the semiconductor structure.

[0083] refer to Figure 16 Remove the third mask layer 220 and the fourth mask layer 230 to expose the top surface of the active layer 110 and the second conductive structure 122.

[0084] refer to Figure 17 In some embodiments, the step of forming word lines 130 may include: forming a third isolation layer 240 in the second trench 210, the top surface of the third isolation layer 240 being lower than the top surface of the active layer 110 and higher than the top surface of the first conductive structure or flush with the top surface of the first conductive structure 121; forming a dielectric layer 140 located on the sidewall of the active layer 110; forming word lines 130 located on the sidewall of the dielectric layer 140, with adjacent word lines 130 spaced apart in the second direction Y; and forming a fourth isolation layer 250 filling the second trench 210 and also covering the word lines 130 and the top surface of the active layer 110.

[0085] In some embodiments, the step of forming the third isolation layer 240 may include: forming a third initial isolation layer, the top surface of which is flush with the top surface of the active layer 110; patterning the third initial isolation layer, with the remaining portion of the third initial isolation layer serving as the third isolation layer 240. The height of the formed third isolation layer 240 in the direction perpendicular to the substrate 100 can be controlled by controlling the concentration of the etching reagent and the etching time of the etching third initial isolation layer. By forming the third isolation layer 240, contact between the word line 130 and the first conductive structure 121 can be avoided, preventing abnormalities in the semiconductor structure and improving the reliability of the semiconductor structure.

[0086] In some embodiments, the step of forming the dielectric layer 140 may include: forming the dielectric layer 140 by thermal oxidation, wherein the dielectric layer 140 formed by thermal oxidation has a higher density and better performance; in other embodiments, the dielectric layer 140 may also be formed by a deposition-then-mask etching method, which allows for better control of the width of the formed dielectric layer 140. By forming the dielectric layer 140, direct contact between the active layer 110 and the word line 130 is avoided, which could lead to semiconductor structure abnormalities and improve the reliability of the semiconductor structure.

[0087] In some embodiments, the step of forming the fourth isolation layer 250 may include: depositing an insulating material over the entire surface of the semiconductor structure, and then removing surface irregularities by chemical mechanical polishing to form the fourth isolation layer 250. In some embodiments, the third isolation layer 240 and the fourth isolation layer 250 may be made of the same material as the first isolation layer 170, which may be silicon oxide or silicon nitride. By forming the fourth isolation layer 250, adjacent word lines 130 can be separated, thereby avoiding signal interference between adjacent word lines 130, and it can also serve as a protective layer for the word lines 130, preventing the word lines 130 from directly contacting the outside world.

[0088] In this embodiment, the first conductive structure 121 is formed first and the second conductive structure 122 is formed when the bit line 120 is formed. Even if the second conductive structure 122 is not connected into a continuous structure during the formation process, it can still be electrically connected to the first conductive structure 121 and the second conductive structure 122, so that the bit line 120 is a continuous whole, thereby improving the stability of the signal transmitted by the bit line 120 and thus improving the reliability of the semiconductor structure.

[0089] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: include: A substrate is provided in which active layers are spaced apart along a first direction; Multiple bit lines are formed and spaced apart along the first direction. The bit lines extend along the second direction. The first part of each bit line covers the side of the active layer, and the second part of each bit line is located inside the active layer. Both the first direction and the second direction are parallel to the surface of the substrate, and the first direction and the second direction intersect each other; The method for forming multiple bit lines includes: First, a plurality of first conductive structures extending along the second direction are formed, wherein the first conductive structures are located on the side surfaces of the active layer spaced apart along the first direction. Multiple second conductive structures are then formed, with each second conductive structure located within the active layer. Each second conductive structure is located between at least two first conductive structures and is electrically connected to the first conductive structure.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The steps for forming the first conductive structure include: Provide the substrate; The substrate is graphically represented to form the active layers spaced apart along the first direction; A first isolation layer is formed, which is located between adjacent active layers, and the top surface of the first isolation layer is lower than the top surface of the active layer; The first conductive structure is formed above the first isolation layer.

3. The method of fabricating a semiconductor structure of claim 2, wherein, The step of forming the first isolation layer includes: forming a first mask layer on the surface of the substrate, etching the first mask layer and the substrate to form a plurality of first trenches extending along the second direction, wherein the first trenches are located between adjacent active layers; The first trench is filled with insulating material, and a portion of the insulating material is removed to form the first insulating layer in the first trench.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The step of forming the first conductive structure over the first insulating layer includes: A second mask layer is formed, which is located above the first isolation layer and covers the sidewall of the active layer; A portion of the first isolation layer and a portion of the sidewalls of the active layer located below the second mask layer are removed to form a first groove; A first conductive material is deposited in the first groove, and the first conductive material is patterned to form a first conductive structure with spaced intervals.

5. The method of fabricating a semiconductor structure of claim 4, wherein, The steps for forming the second conductive structure include: The active layer is etched to form multiple second trenches extending along the first direction, wherein the bottom surface of the second trenches is higher than the top surface of the first conductive structure. A third mask layer is formed in the second trench, the third mask layer covering the sidewall of the second trench; A second conductive material is deposited at the bottom of the second trench and rapidly heat-treated to form the second conductive structure.

6. The method of fabricating a semiconductor structure of claim 5, wherein, The second conductive material includes a metallic material, which diffuses into the active layer during rapid thermal processing to form a metal silicide. The metal silicide is located between at least two of the first conductive structures to form the second conductive structure.

7. The method of fabricating a semiconductor structure of claim 5, wherein, The rapid heat treatment temperature is 400℃~800℃.

8. The method of fabricating a semiconductor structure of claim 1, wherein, A plurality of second conductive structures located between two first conductive structures are interconnected and penetrate the active layer along the second direction.

9. A semiconductor structure, characterized by The semiconductor structure is manufactured using the method according to any one of claims 1-8, and comprises: A substrate, and an active layer spaced apart on the substrate; Multiple bit lines are arranged at intervals along a first direction and extend along a second direction. A first portion of each bit line covers the side of the active layer, and a second portion of each bit line is located within the active layer. Both the first direction and the second direction are parallel to the surface of the substrate, and the first direction and the second direction intersect.

10. The semiconductor structure of claim 9, wherein, The first part includes two first conductive structures that are spaced apart and extend along the second direction. The second part includes a plurality of second conductive structures located within the active layer. The plurality of second conductive structures are located between at least two of the first conductive structures, and each second conductive structure is electrically connected to a first conductive structure.

11. The semiconductor structure of claim 10, wherein, Multiple second conductive structures are connected as a whole along the extension direction of the bit line, penetrating the active layer.

12. The semiconductor structure according to claim 10 or 11, characterized in that, The material of the second conductive structure includes metal silicide, and the material of the first conductive structure includes conductive metal.

13. The semiconductor structure according to claim 10, characterized in that, In the first direction, the thickness of the first conductive structure is 1nm-3nm.

14. The semiconductor structure of claim 10, wherein, On a plane perpendicular to the substrate, the height of the overlapping portion of the projection of the second conductive structure and the projection of the first conductive structure is 0.5 to 1 times the height of the projection of the second conductive structure.

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