Semiconductor structure and method of making the same, memory
Patent Information
- Application Number
- CN202210708797.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-21
- Publication Date
- 2026-09-04
- Estimated Expiration
- 2042-06-21
Smart Images
Figure CN117320435B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory. Background Technology
[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
[0003] As the size of dynamic random access memory (DRAM) continues to shrink, the manufacturing process of DRAM involves numerous steps. How to simplify the process while ensuring the performance of DRAM has become an urgent problem to be solved.
[0004] Public content
[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a memory.
[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:
[0007] A substrate, a plurality of first semiconductor pillars, a memory structure, a plurality of transistors, and a first protective layer located above the substrate; wherein,
[0008] The plurality of first semiconductor pillars are arranged in an array along a first direction and a second direction; each first semiconductor pillar includes a first portion and a second portion located on the first portion, the second portion including a bottom, a middle and a top portion arranged in sequence; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;
[0009] The storage structure surrounds the sidewall of the first part;
[0010] The first protective layer surrounds the top sidewall of the second portion;
[0011] The channel structure of the transistor is located in the middle of the second part, and the extension direction of the channel structure is the same as the extension direction of the second part.
[0012] In the above scheme, the first protective layer includes a plurality of first protective pillars and a plurality of second protective pillars;
[0013] The plurality of first protective pillars are arranged in an array along a first direction and a second direction. Each first protective pillar is located between the tops of two adjacent first semiconductor pillars in the first direction and covers the two opposite sidewalls of the two adjacent first semiconductor pillars.
[0014] Each of the second protective posts extends along the first direction, covering the sidewall of the second portion that is not covered by the first protective post, and also covering the sidewall of the first protective post.
[0015] In the above scheme, each transistor includes: a gate oxide layer disposed around the middle of the second portion, a gate disposed around the gate oxide layer, and a source and a drain disposed at the bottom and top of the second portion, respectively; wherein, the surface of the gate away from the gate oxide layer is flush with the bottom edge of the second guard pillar away from the second portion.
[0016] In the above scheme, the diameter of the middle part of the second part is smaller than the diameter of the top part of the second part, and smaller than the diameter of the bottom part of the second part.
[0017] In the above scheme, the semiconductor structure further includes multiple oxide pillars and a first oxide layer;
[0018] Each of the first semiconductor pillars is located on the top surface of one of the oxide pillars, and the first oxide layer is located between adjacent oxide pillars.
[0019] In the above scheme, the storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer;
[0020] The first electrode layer covers the sidewall of the first portion;
[0021] The dielectric layer at least covers the surface of the first electrode layer;
[0022] The second electrode layer covers the surface of the dielectric layer, and the storage structure covers the surface of the first oxide layer.
[0023] In the above scheme, the semiconductor structure further includes:
[0024] Multiple bit lines are located on the transistor and are electrically contacted at the top of the second portion.
[0025] According to another aspect of this disclosure, a memory is provided, comprising: at least one semiconductor structure as described in any of the above embodiments of this disclosure.
[0026] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:
[0027] A substrate is provided on which a plurality of first semiconductor pillars are formed in an array along a first direction and a second direction; each first semiconductor pillar includes a first portion and a second portion located on the first portion, the second portion including a bottom, a middle and a top portion arranged in sequence; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;
[0028] A storage structure is formed around the sidewalls of the first part;
[0029] A first protective layer is formed around the top sidewall of the second part;
[0030] A transistor is formed, wherein the channel structure of the transistor is located in the middle of the second portion, and the extension direction of the channel structure is the same as the extension direction of the second portion.
[0031] In the above scheme, forming the first protective layer includes:
[0032] A first insulating layer is formed between the second portions;
[0033] A portion of the first insulating layer at the top of the second part is removed to form a plurality of first grooves, each of the first grooves exposing two opposing sidewalls at the top of two adjacent first semiconductor pillars in a first direction;
[0034] The first groove is filled to form a plurality of first protective pillars;
[0035] Remove the remaining first insulating layer at the top of the second portion to form a plurality of second grooves extending along the first direction, each second groove exposing two opposing sidewalls at the top of two adjacent first semiconductor pillars in the second direction;
[0036] Multiple second protective pillars are formed on the sidewall of the second groove, and the first protective pillar and the second protective pillar together constitute the first protective layer.
[0037] In the above scheme, forming a transistor includes:
[0038] After the first protective layer is formed, the first insulating layer in the middle of the second part is removed to expose the sidewall in the middle of the second part;
[0039] A gate oxide layer is formed covering the sidewall of the middle portion of the second part;
[0040] A gate is formed covering the gate oxide layer;
[0041] The source and drain are formed at the bottom and top of the second part, respectively;
[0042] A second insulating layer is formed between the second protective pillars and between the gate.
[0043] In the above scheme, the gate forming the gate oxide layer includes:
[0044] The gaps in the gate oxide layer are filled with gate conductive material;
[0045] Using the first protective layer as a mask layer, a portion of the gate conductive material is removed, and the remaining gate conductive material forms the gate.
[0046] In the above scheme, forming the first semiconductor pillar includes:
[0047] Provide semiconductor substrates;
[0048] A plurality of first trenches are formed in the semiconductor substrate at intervals along a first direction, and a third insulating layer is formed in the first trenches and on the surface of the semiconductor substrate.
[0049] The semiconductor substrate and the third insulating layer are etched to form a plurality of second trenches spaced apart along a second direction, wherein the bottom surface of the first trench is lower than the bottom surface of the second trench; the first trench and the second trench divide the semiconductor substrate into a plurality of first semiconductor pillars.
[0050] In the above scheme, the method further includes: forming a second protective layer on the sidewall of each of the second trenches;
[0051] The semiconductor substrate at the bottom of the second trench is etched to form an enlarged third trench, the bottom surface of the third trench being flush with the bottom surface of the first trench.
[0052] A plurality of second semiconductor pillars are formed between adjacent third trenches, each of the first semiconductor pillars is located on a corresponding second semiconductor pillar, and the maximum diameter of the second semiconductor pillar along the second direction is smaller than the minimum diameter of the first semiconductor pillar.
[0053] The second semiconductor pillar is subjected to an oxidation treatment so that the second semiconductor pillar is completely oxidized into an oxide pillar.
[0054] In the above scheme, the method further includes: after forming the second protective layer, filling the second trench with sacrificial material;
[0055] Remove the third insulating layer, the second protective layer, and the sacrificial material located above the first semiconductor pillar;
[0056] A plurality of first support material layers are formed on the top surface of the first semiconductor pillar, which are spaced apart along a first direction and extend along a second direction.
[0057] Remove the remaining sacrificial material and etch the semiconductor substrate along the bottom of the second trench.
[0058] In the above scheme, the method further includes: filling the spaces between the first support material layers, the spaces between the second protective layers, and the spaces between the oxide pillars with a first oxide layer;
[0059] A portion of the first support material layer and a portion of the first oxide layer on the top surface of the first semiconductor pillar are removed to form a plurality of third grooves extending along the first direction, and the remaining first support material layer constitutes the first support layer.
[0060] A second support layer is formed in the third groove, and the first support layer and the second support layer together form a grid-like top support layer.
[0061] In the above scheme, forming the storage structure includes:
[0062] Remove part of the first oxide layer and the second protective layer;
[0063] A first conductive material, a dielectric layer material, and a second conductive material are sequentially filled between the first semiconductor pillars;
[0064] Remove the top support layer, and then etch back the first conductive material, dielectric layer material, and second conductive material between the second parts. The remaining first conductive material, dielectric layer material, and second conductive material located between the first parts together constitute the storage structure.
[0065] The method in the above scheme further includes:
[0066] Multiple bit lines are formed on the second portion; the bit lines are in electrical contact with the top of the second portion.
[0067] This disclosure provides a semiconductor structure and its fabrication method, as well as a memory. The semiconductor structure fabrication method includes: providing a substrate, forming a plurality of first semiconductor pillars arranged in an array along a first direction and a second direction on the substrate; each first semiconductor pillar includes a first portion and a second portion located on the first portion, the second portion including a bottom, a middle, and a top portion arranged in sequence; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; forming a memory structure surrounding the sidewalls of the first portion; forming a first protective layer surrounding the top sidewall of the second portion; forming a transistor, the channel structure of the transistor being located within the middle portion of the second portion, the extension direction of the channel structure being the same as the extension direction of the second portion. In this embodiment, on the one hand, by forming a first protective layer around the top sidewall of the second part, the top sidewall of the second part is protected, so that when forming a transistor with a channel structure located in the middle of the second part, it is not necessary to first form the transistor material covering the top sidewall and the middle sidewall of the second part, and then remove the transistor material from the top sidewall of the second part, thereby saving process steps and saving transistor material; on the other hand, the first protective layer formed around the top sidewall of the second part can also serve as a mask when forming the gate, thereby saving process steps and reducing manufacturing costs. Attached Figure Description
[0068] Figure 1 This is a circuit connection diagram of a DRAM transistor provided in an embodiment of this disclosure;
[0069] Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;
[0070] Figures 3-26 This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation
[0071] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.
[0072] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0073] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0074] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.
[0075] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0076] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.
[0077] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0078] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.
[0079] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.
[0080] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.
[0081] In some embodiments of this disclosure, regardless of whether it is a planar transistor, a recessed gate array transistor, a buried transistor, or a vertical gate transistor, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.
[0082] Figure 1 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), and the source of transistor T is electrically connected to one of the electrode plates of capacitor C. The other electrode plate of capacitor C can be connected to a reference voltage, which can be ground or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.
[0083] However, with the development of memory, the size of dynamic random access memory is constantly shrinking, and the manufacturing process of memory involves many steps and has high manufacturing costs.
[0084] In view of this, in order to solve one or more of the above problems, this disclosure provides a method for fabricating a semiconductor structure, which can simplify the process steps. Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 2 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:
[0085] S100: A substrate is provided, on which a plurality of first semiconductor pillars are formed in an array along a first direction and a second direction; the first semiconductor pillars include a first portion and a second portion located on the first portion, the second portion including a bottom, a middle and a top portion arranged in sequence; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;
[0086] S200: Form a storage structure around the sidewalls of the first portion;
[0087] S300: Form a first protective layer around the top sidewall of the second part;
[0088] S400: Forming a transistor, wherein the channel structure of the transistor is located in the middle of the second portion, and the extension direction of the channel structure is the same as the extension direction of the second portion.
[0089] It should be understood that Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs. Figures 3 to 26 This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 3 to 26 This is a schematic diagram illustrating the complete manufacturing process of a semiconductor structure. Unmarked parts in some of the accompanying drawings can be shared. The following section combines... Figure 2 , Figures 3 to 26 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.
[0090] In step S100, the main task is to provide a substrate and form a plurality of first semiconductor pillars on the substrate.
[0091] In some embodiments, forming the first semiconductor pillar includes:
[0092] Provide semiconductor substrates;
[0093] A plurality of first trenches are formed in the semiconductor substrate at intervals along a first direction, and a third insulating layer is formed in the first trenches and on the surface of the semiconductor substrate.
[0094] The semiconductor substrate and the third insulating layer are etched to form a plurality of second trenches spaced apart along a second direction, wherein the bottom surface of the first trench is lower than the bottom surface of the second trench; the first trench and the second trench divide the semiconductor substrate into a plurality of first semiconductor pillars.
[0095] In some embodiments, the method further includes: forming a second protective layer on each of the second trench sidewalls;
[0096] The semiconductor substrate at the bottom of the second trench is etched to form an enlarged third trench, the bottom surface of the third trench being flush with the bottom surface of the first trench.
[0097] A plurality of second semiconductor pillars are formed between adjacent third trenches, each of the first semiconductor pillars is located on a corresponding second semiconductor pillar, and the maximum diameter of the second semiconductor pillar along the second direction is smaller than the minimum diameter of the first semiconductor pillar.
[0098] The second semiconductor pillar is subjected to an oxidation treatment so that the second semiconductor pillar is completely oxidized into an oxide pillar.
[0099] In some embodiments, the method further includes: filling the second trench with sacrificial material after forming the second protective layer;
[0100] Remove the third insulating layer, the second protective layer, and the sacrificial material located above the first semiconductor pillar;
[0101] A plurality of first support material layers are formed on the top surface of the first semiconductor pillar, which are spaced apart along a first direction and extend along a second direction.
[0102] Remove the remaining sacrificial material and etch the semiconductor substrate along the bottom of the second trench.
[0103] In some embodiments, the method further includes filling a first oxide layer between the first support material layers, between the second protective layers, and between the oxide pillars;
[0104] A portion of the first support material layer and a portion of the first oxide layer on the top surface of the first semiconductor pillar are removed to form a plurality of third grooves extending along the first direction, and the remaining first support material layer constitutes the first support layer.
[0105] A second support layer is formed in the third groove, and the first support layer and the second support layer together form a grid-like top support layer.
[0106] The following is combined Figures 3-14 The formation process of the first semiconductor pillar is described in detail.
[0107] like Figure 3 As shown, a semiconductor substrate 111 is provided, and a plurality of first trenches 112 are formed in the semiconductor substrate 111.
[0108] In some specific examples, the semiconductor substrate 111 includes a substrate, which may include a substrate of elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.
[0109] In some specific examples, the surface of the semiconductor substrate 111 is etched to form a plurality of first trenches 112 spaced apart along a first direction in the semiconductor substrate 111. Here, each of the first trenches 112 extends along a second direction.
[0110] Here, the first direction is parallel to the surface of the substrate; the second direction intersects the first direction and is parallel to the surface of the substrate.
[0111] Here, the first direction intersects with the second direction, which can be understood as the angle between the first direction and the second direction being 0-90 degrees.
[0112] To clearly describe this disclosure, the following embodiments are illustrated using the example of a first direction being perpendicular to a second direction. For example, the first direction is... Figure 3 The X-axis direction shown in the figure; the second direction is Figure 3 The Y-axis direction shown in the figure is described in the following embodiments only for illustrative purposes and is not intended to limit the scope of the disclosure.
[0113] In some specific examples, the first trench 112 includes, but is not limited to, a shallow trench isolation (STI) structure.
[0114] In some specific examples, the method for forming the first trench 112 includes, but is not limited to, dry plasma etching processes.
[0115] like Figure 4 As shown, a third insulating layer 113 is formed in the first trench 112 and on the surface of the semiconductor substrate 111.
[0116] It is understandable that forming a third insulating layer 113 on the surface of the semiconductor substrate 111 can avoid certain consumption of the top surface of the semiconductor substrate 111 in subsequent processes.
[0117] Here, the third insulating layer 113 formed in the first trench 112 can be used to provide support.
[0118] In some specific examples, the constituent materials of the third insulating layer 113 include, but are not limited to, silicon oxide (SiO2).
[0119] In some specific examples, the methods for forming the third insulating layer 113 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.
[0120] In some specific examples, after forming the third insulating layer 113, a planarization process is further performed on the third insulating layer 113 to make its surface flat. Exemplarily, the planarization process includes, but is not limited to, chemical mechanical polishing (CMP).
[0121] Next, as Figure 5 As shown, etching the semiconductor substrate 111 and the third insulating layer 113 forms a plurality of second trenches 114 spaced apart along the second direction, the bottom surface of the first trench 112 is lower than the bottom surface of the second trench 114; the first trench 112 and the second trench 114 divide the semiconductor substrate 111 into a plurality of first semiconductor pillars 102.
[0122] Here, each of the second grooves 114 extends along a first direction; that is, the first groove 112 and the second groove 114 intersect.
[0123] In some specific examples, when the first direction is perpendicular to the second direction, the first groove 112 and the second groove 114 are perpendicular to each other.
[0124] In some specific examples, a plurality of first grooves 112 are spaced apart along the X-axis; and each first groove 112 extends along the Y-axis; a plurality of second grooves 114 are spaced apart along the Y-axis; and each second groove 114 extends along the X-axis.
[0125] In some specific examples, the methods for forming the second trench 114 include, but are not limited to, dry plasma etching processes.
[0126] In some specific examples, the second trench 114 includes, but is not limited to, shallow trench isolation (STI) structures.
[0127] Here, the first trench 112 and the second trench 114 divide the semiconductor substrate 111 into a plurality of first semiconductor pillars 102 arranged in an array along the first direction and the second direction.
[0128] In some specific examples, the methods for etching the semiconductor substrate 111 and the third insulating layer 113 include, but are not limited to, dry etching processes.
[0129] Here, when etching the semiconductor substrate 111 and the third insulating layer 113 to form the first semiconductor pillar 102, the third insulating layer 113 on the top surface of the first semiconductor pillar 102 is retained.
[0130] It is understandable that the third insulating layer 113 on the top surface of the first semiconductor pillar 102 is used to protect the top surface of the first semiconductor pillar 102 and avoid damage to the top surface of the first semiconductor pillar 102 in subsequent processes.
[0131] Next, as Figure 6 As shown, a second protective layer 115 is formed on the sidewall of each of the second trenches 114.
[0132] In this embodiment, the following two schemes are given for how to form the second protective layer 115 on the sidewall of the second trench 114.
[0133] Option 1: A second protective layer 115 is formed on the sidewall of each of the second trenches 114, comprising:
[0134] A second protective material layer is formed on the sidewalls and bottom wall of each of the second trenches 114 using a selective atomic layer deposition process.
[0135] Remove the second protective material layer from the bottom wall of the second trench 114 to form the second protective layer 115.
[0136] In some specific examples, the method for removing the second protective material layer from the bottom wall of the second trench 114 includes, but is not limited to, removal with diluted hydrofluoric acid.
[0137] Option 2 involves forming a second protective layer 115 on the sidewall of each of the second trenches 114, which includes: first filling the second protective material layer into the second trench 114, then etching back a portion of the second protective material layer, retaining the second protective material layer on the sidewall of the second trench 114, thereby forming the second protective layer 115.
[0138] In some specific examples, the method of filling the second trench 114 with the second protective material layer includes, but is not limited to, PVD and CVD.
[0139] In some specific examples, the material of the second protective layer 115 includes, but is not limited to, silicon nitride.
[0140] Understandably, the second protective layer 115 formed on the sidewall of the second trench 114 serves to protect the first semiconductor pillar 102, preventing the first semiconductor pillar 102 from being oxidized during the oxidation process of the second semiconductor pillar 117 in subsequent processes.
[0141] Next, as Figure 7 As shown, the second trench 114 is filled with sacrificial material 119, specifically the second trench 114 in which the second protective layer 115 is formed.
[0142] Here, the selection of the material of the sacrificial material 119 needs to take into account a certain selection ratio with the materials of the second protective layer 115, the third insulating layer 113, and the top support layer 120, so that the impact on the second protective layer 115, the third insulating layer 113, and the top support layer 120 is small when the sacrificial material 119 is removed in the subsequent process.
[0143] In some specific examples, the material of the sacrificial material 119 includes, but is not limited to, carbon.
[0144] Next, as Figure 8 As shown, the third insulating layer 113, the second protective layer 115 and the sacrificial material 119 located above the first semiconductor pillar 102 are removed; and a plurality of first support material layers 120-11 are formed on the top surface of the first semiconductor pillar 102, which are spaced apart along the first direction and extend along the second direction.
[0145] Here, the first support material layer 120-11 can serve as part of the top support layer 120 formed in subsequent processes, providing support for the first semiconductor pillar 102.
[0146] Next, as Figure 9 As shown, the remaining sacrificial material 119 is removed, exposing the sidewalls of the second protective layer 115 and the surface of the semiconductor substrate 111 in the second trench 114.
[0147] In some specific examples, the methods for removing the remaining sacrificial material 119 include, but are not limited to, dry etching processes and wet etching processes.
[0148] Next, as Figure 10 As shown, the semiconductor substrate 111 is etched along the bottom of the second trench 114 to form an enlarged third trench 116 (as shown). Figure 10 (As shown in the dashed box in the middle), the bottom surface of the third groove 116 is flush with the bottom surface of the first groove 112.
[0149] It should be noted that the term "basic flush" in this disclosure can be understood as "approximately flush"; it is also understood that misalignment or non-flushness caused by process errors during the manufacturing process of memory is also included within the scope of "basic flush".
[0150] Here, etching the semiconductor substrate 111 along the bottom of the second trench 114 can be understood as etching the bottom of the second trench 114 along the second direction, so that the diameter of the formed third trench 116 along the second direction is greater than the diameter of the second trench 114 along the second direction.
[0151] In some specific examples, the etching process used may include wet etching, dry etching, etc.
[0152] For example, in the wet etching process, an etchant is introduced into the bottom of the second trench 114, and the diameter of the bottom of the second trench 114 along the Y-axis is increased by the anisotropic etching of the etchant, thereby forming the third trench 116.
[0153] For example, in the dry etching process, lateral etching is performed by controlling plasma to form a third trench 116 with an increased diameter at the bottom of the second trench 114.
[0154] Here, the cross-sectional shape of the formed third trench 116 includes, but is not limited to, as shown in the figure. Figure 10 The bowl shape shown.
[0155] While forming the third trench 116, a plurality of second semiconductor pillars 117 are formed between adjacent third trenches 116. Each first semiconductor pillar 102 is located on a corresponding second semiconductor pillar 117. The maximum diameter of the second semiconductor pillar 117 along the second direction is smaller than the minimum diameter of the first semiconductor pillar 102.
[0156] For example, the maximum diameter of the second semiconductor pillar 117 along the second direction can be understood as Figure 10 The diameter along the second direction at the contact position between the second semiconductor pillar 117 and the first semiconductor pillar 102; the minimum diameter of the first semiconductor pillar 102 can be understood as the region with the smallest size along the second direction in the first semiconductor pillar 102; Reference Figure 10 The upper and lower portions of the first semiconductor pillar 102 have the same dimensions along the second direction, that is, the minimum and maximum diameters of the first semiconductor pillar 102 are the same.
[0157] Next, as Figure 11As shown, the second semiconductor pillar 117 is subjected to an oxidation treatment so that the second semiconductor pillar 117 is completely oxidized into an oxide pillar 118 (e.g., Figure 11 (As shown in the dashed box).
[0158] Here, each first semiconductor pillar 102 is located on the top surface of an oxide pillar 118.
[0159] It should be noted that when the second semiconductor pillar 117 is oxidized, the semiconductor substrate 111 between adjacent second semiconductor pillars 117 will also be oxidized by the second oxide layer 123 (e.g., Figure 11 (As shown in the dashed box). The second oxide layer 123 here, together with the first oxide layer 121 filled between the oxide pillars 118 in subsequent processes, serves to isolate the memory structure formed in subsequent processes from the substrate, thereby improving the leakage problem of the memory structure.
[0160] After the second semiconductor pillar 117 is oxidized, the remaining semiconductor substrate 111 located under the oxide pillar 118 and the second oxide layer 123 constitutes the substrate 101 (e.g., Figure 11 (As shown in the dashed box).
[0161] Next, as Figure 12 As shown, the first oxide layer 121 is filled between the first support material layers 120-11, between the second protective layers 115, and between the oxide pillars 118.
[0162] In some specific examples, the material of the first oxide layer 121 includes, but is not limited to, silicon oxide.
[0163] In some specific examples, the methods for filling the first oxide layer 121 include, but are not limited to, PVD, CVD, and ALD.
[0164] Next, as Figure 13 As shown, a portion of the first support material layer 120-11 and a portion of the first oxide layer 121 on the top surface of the first semiconductor pillar 102 are removed to form a plurality of third grooves 122 extending along the first direction, and the remaining first support material layer 120-11 constitutes the first support layer 120-1.
[0165] In some specific examples, the methods for removing part of the first support material layer 120-11 and part of the first oxide layer 121 include, but are not limited to, dry etching process and wet etching process.
[0166] Next, as Figure 14 As shown, a second support layer 120-2 is formed in the third groove 122 (e.g. Figure 14(As shown in the dashed box in the middle), the first support layer 120-1 and the second support layer 120-2 together form a grid-like top support layer 120.
[0167] Here, the top support layer 120 at least covers a portion of the top surface of the first semiconductor pillar 102. It is understood that the top support layer 120 serves to support the first semiconductor pillar 102, mitigating the problem of the first semiconductor pillar 102 easily collapsing after the removal of the first oxide layer 121 and the second protective layer 115 between the first semiconductor pillars 102 in subsequent processes.
[0168] Regarding the selection of materials for the first support layer 120-1 and the second support layer 120-2, firstly, it is necessary to consider that the materials of the first support layer 120-1 and the second support layer 120-2 have a certain etching selectivity ratio with the material of the second protective layer 115, so as to reduce the impact on the first support layer 120-1 and the second support layer 120-2 when removing the second protective layer 115; secondly, it is necessary to consider that the materials of the first support layer 120-1 and the second support layer 120-2 have a certain etching selectivity ratio with the material of the first oxide layer 121, so as to reduce the impact on the first support layer 120-1 and the second support layer 120-2 when removing the first oxide layer 121; thirdly, it is necessary to consider that the material of the first support layer 120-1 has a certain etching selectivity ratio with the sacrificial material 119, so as to reduce the impact on the material of the first support layer 120-1 when removing the sacrificial material 119.
[0169] In some specific examples, the materials of the first support layer 120-1 and the second support layer 120-2 include, but are not limited to, polycrystalline silicon.
[0170] Here, the materials of the first support layer 120-1 and the second support layer 120-2 can be the same or different.
[0171] In step S200, the main task is to form a storage structure around the sidewalls of the first part.
[0172] In some embodiments, forming the storage structure includes:
[0173] Remove part of the first oxide layer and the second protective layer;
[0174] A first conductive material, a dielectric layer material, and a second conductive material are sequentially filled between the first semiconductor pillars;
[0175] Remove the top support layer, and then etch back the first conductive material, dielectric layer material, and second conductive material between the second parts. The remaining first conductive material, dielectric layer material, and second conductive material located between the first parts together constitute the storage structure.
[0176] The following is combined Figures 15-18 The formation process of the storage structure is explained in detail.
[0177] First, such as Figure 15 As shown, a portion of the first oxide layer 121 and the second protective layer 115 are removed;
[0178] In some specific examples, the methods for removing part of the first oxide layer 121 and the second protective layer 115 include, but are not limited to, dry etching process and wet etching process.
[0179] Here, the first oxide layer 121 removed is the first oxide layer 121 between the first semiconductor pillars 102 and between the top support layer 120, while the first oxide layer 121 between the oxide pillars 118 is retained.
[0180] Understandably, the oxide pillars 118 and the first oxide layer 121 between the oxide pillars 118 isolate the memory structure formed in subsequent processes from the substrate, thereby improving the leakage problem of the memory structure.
[0181] Next, as Figure 16 As shown, a first conductive material 103-11 is filled between the first semiconductor pillars 102.
[0182] In some specific examples, the methods for filling the first conductive material 103-11 include, but are not limited to, processes such as PVD and CVD.
[0183] It should be noted that the methods of filling the first conductive material 103-11 and filling the second conductive material 103-33 in the subsequent processes in the above embodiments can also be understood as forming conductive layer-to-conductive layer (CoC) using selective deposition processes; here, selective deposition processes include, but are not limited to, ALD processes.
[0184] In some specific examples, the constituent materials of the first conductive material 103-11 may include, but are not limited to, ruthenium (Ru), ruthenium oxide (RuO), and titanium nitride (TiN).
[0185] Next, as Figure 17 As shown, dielectric layer material 103-22 and second conductive material 103-33 are sequentially filled between the first conductive material 103-11.
[0186] In some specific examples, the methods for filling the first conductive material 103-11 include, but are not limited to, processes such as PVD, CVD, and ALD.
[0187] Here, the constituent materials of the dielectric layer material 103-22 include high-k dielectric materials. High-k dielectric materials generally refer to materials with a dielectric constant higher than 3.9, and are usually significantly higher than this value. In some specific examples, the materials of the dielectric layer material 103-22 may include, but are not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), strontium titanate (SrTiO3), etc.
[0188] In some specific embodiments, the constituent materials of the second conductive material 103-33 may include, but are not limited to, ruthenium, ruthenium oxide, and titanium nitride.
[0189] It should be noted that when the first conductive material 103-11, dielectric layer material 103-22, and second conductive material 103-33 are filled between the first semiconductor pillars 102, the first conductive material 103-11, dielectric layer material 103-22, and second conductive material 103-33 are not filled between the top support layers 120.
[0190] Next, as Figure 18 As shown, the top support layer 120 is removed, and the first conductive material 103-11, dielectric layer material 103-22, and second conductive material 103-33 between the second parts are etched back. The remaining first conductive material 103-11, dielectric layer material 103-22, and second conductive material 103-33 located between the first parts together constitute the storage structure 103.
[0191] In some specific examples, the methods for removing the top support layer 120 include, but are not limited to, dry etching and wet etching processes.
[0192] In some specific examples, the methods for removing the first conductive material 103-11, the dielectric layer material 103-22, and the second conductive material 103-33 between the second parts include, but are not limited to, dry etching processes and wet etching processes.
[0193] Here, the remaining first conductive material 103-11, dielectric layer material 103-22, and second conductive material 103-33 located between the first parts respectively constitute the first electrode layer 103-1, dielectric layer 103-2, and second electrode layer 103-3 of the storage structure 103.
[0194] Here, the first electrode layer 103-1 is used as the lower electrode of the capacitor; the dielectric layer 103-2 is used as the dielectric of the capacitor; and the second electrode layer 103-3 is used as the upper electrode of the capacitor.
[0195] In step S300, the main task is to form a first protective layer around the top sidewall of the second part.
[0196] In some embodiments, forming the first protective layer includes:
[0197] A first insulating layer is formed between the second portions;
[0198] A portion of the first insulating layer at the top of the second part is removed to form a plurality of first grooves, each of the first grooves exposing two opposing sidewalls at the top of two adjacent first semiconductor pillars in a first direction;
[0199] The first groove is filled to form a plurality of first protective pillars;
[0200] Remove the remaining first insulating layer at the top of the second portion to form a plurality of second grooves extending along the first direction, each second groove exposing two opposing sidewalls at the top of two adjacent first semiconductor pillars in the second direction;
[0201] Multiple second protective pillars are formed on the sidewall of the second groove, and the first protective pillar and the second protective pillar together constitute the first protective layer.
[0202] The following is combined Figures 19-23 The formation process of the first protective layer is explained in detail.
[0203] First, such as Figure 19 As shown, a first insulating layer 105 is formed between the second parts.
[0204] In some specific examples, the methods for forming the first insulating layer 105 include, but are not limited to, PVD, CVD, and ALD.
[0205] In some specific examples, the material of the first insulating layer 105 includes, but is not limited to, silicon oxide.
[0206] Next, as Figure 20 As shown, a portion of the first insulating layer 105 at the top of the second part is removed to form a plurality of first grooves 106.
[0207] In some specific examples, a mask layer may be formed on the first insulating layer 105 and the first semiconductor pillar 102, and a predefined pattern may be formed in the mask layer. The first insulating layer 105 may be etched through the mask layer to remove a portion of the first insulating layer 105 between the top of the second part, thereby obtaining the first groove 106.
[0208] In some specific examples, the methods for removing a portion of the first insulating layer 105 at the top of the second part include, but are not limited to, dry etching processes and wet etching processes.
[0209] Here, each first groove 106 exposes two opposing sidewalls on the tops of two adjacent first semiconductor pillars 102 in the first direction, such that the first protective pillar 104-1 formed in the first groove 106 in a subsequent process is located between the tops of two adjacent first semiconductor pillars 102 in the first direction and covers the two opposing sidewalls of the two adjacent first semiconductor pillars 102.
[0210] Next, as Figure 21 As shown, a first protective post 104-1 is formed in the first groove 106.
[0211] In some specific examples, the methods for forming the first protective pillar 104-1 include, but are not limited to, PVD, CVD, and ALD.
[0212] In some specific examples, the material of the first protective pillar 104-1 includes, but is not limited to, silicon nitride.
[0213] Next, as Figure 22 As shown, the remaining first insulating layer 105 at the top of the second portion is removed to form a plurality of second grooves 107 extending along the first direction. Each second groove 107 exposes two opposing sidewalls at the top of two adjacent first semiconductor pillars 102 in the second direction.
[0214] In some specific examples, the methods for removing the remaining first insulating layer 105 at the top of the second part include, but are not limited to, dry etching processes and wet etching processes.
[0215] Here, the first groove 106 extends along the first direction, and each second groove 107 exposes two opposing sidewalls at the top of two adjacent first semiconductor pillars 102 in the second direction, such that the second protective pillar 104-2 formed in the sidewalls of the second groove 107 in a subsequent process extends along the first direction, covers the sidewalls of the second portion not covered by the first protective pillar 104-1, and covers the sidewalls of the first protective pillar 104-1.
[0216] Next, as Figure 23 As shown, a plurality of second protective posts 104-2 are formed on the sidewall of the second groove 107.
[0217] Here, the first protective pillar 104-1 and the second protective pillar 104-2 together constitute the first protective layer 104. The first protective layer 104 covers the top sidewall of the second part of the first semiconductor pillar 102.
[0218] In some specific examples, the material of the second protective pillar 104-2 includes, but is not limited to, silicon nitride.
[0219] Here, the materials of the first protective post 104-1 and the second protective post 104-2 can be the same or different.
[0220] In some specific examples, the methods for forming the second protective pillar 104-2 include, but are not limited to, PVD, CVD, and ALD.
[0221] In some specific examples, the specific process of forming the second protective pillar 104-2 may be as follows: a second protective material layer is formed in the sidewall and bottom wall of the second groove 107 using an ALD process; the second protective material layer at the bottom of the second groove 107 is removed using an etching process, and the remaining second protective material layer on the sidewall of the second groove 107 constitutes the second protective pillar 104-2.
[0222] It should be noted that when the second protective material layer at the bottom of the second groove 107 is removed using an etching process, the second protective material layer on the sidewall of the second groove 107 is also partially removed, thus forming a layer as shown in the figure. Figure 23 The second protective post 104-2 shown has a diameter that gradually decreases from bottom to top along the second direction. However, the shape of the second protective post 104-2 includes, but is not limited to, the shape shown below. Figure 23 The shape shown is a slope.
[0223] In step S400, the main task is to form a transistor, wherein the channel structure of the transistor is located in the middle of the second part, and the extension direction of the channel structure is the same as the extension direction of the second part.
[0224] In some embodiments, forming a transistor includes:
[0225] After the first protective layer is formed, the first insulating layer in the middle of the second part is removed to expose the sidewall in the middle of the second part;
[0226] A gate oxide layer is formed covering the sidewall of the middle portion of the second part;
[0227] A gate is formed covering the gate oxide layer;
[0228] The source and drain are formed at the bottom and top of the second part, respectively;
[0229] A second insulating layer is formed between the second protective pillars and between the gate.
[0230] The following is combined Figures 24-26 The process of transistor formation is explained in detail.
[0231] First, the first insulating layer 105 in the middle of the second part is removed, exposing the sidewall in the middle of the second part.
[0232] In some specific examples, the methods for removing the first insulating layer 105 in the middle of the second part include, but are not limited to, dry etching processes and wet etching processes.
[0233] Next, as Figure 24 As shown, a gate oxide layer 108 is formed covering the sidewall of the middle part of the second portion.
[0234] Here, the gate oxide layer 108 is located between the gate 109 formed in a subsequent process and the channel structure, and is used to electrically isolate the channel structure and the gate 109 to reduce the hot carrier effect of the transistor.
[0235] In some specific examples, the methods for forming the gate oxide layer 108 include, but are not limited to, thermal oxidation and ALD.
[0236] For example, after the gate oxide layer 108 is formed by thermal oxidation, the diameter of the middle part of the second portion is smaller than the diameter of the top part of the second portion and smaller than the diameter of the bottom part of the second portion.
[0237] In some specific examples, the gate oxide layer 108 includes, but is not limited to, silicon oxide.
[0238] Next, as Figure 25 As shown, a gate 109 is formed covering the gate oxide layer 108.
[0239] In some embodiments, forming the gate 109 covering the gate oxide layer 108 includes:
[0240] Gate conductive material is filled into the gaps of the gate oxide layer 108;
[0241] Using the first protective layer 104 as a mask layer, a portion of the gate conductive material is removed, and the remaining gate conductive material forms the gate 109.
[0242] In some specific examples, the methods for filling the gate conductive material include, but are not limited to, PVD, CVD, and ALD.
[0243] In some specific examples, the gate conductive material may include metals or polysilicon, etc.
[0244] It is understandable that the first protective layer 104 is used as a mask layer to remove part of the gate conductive material, thereby forming the gate 109, and forming a filling region between the gates 109, so that the second insulating layer 110 is filled in the filling region in the subsequent process to isolate the two adjacent gates 109. In other words, the first protective layer 104 not only protects the top sidewall of the second part, but also acts as a mask, which can save process steps and reduce process costs.
[0245] Here, the shape of the gate 109 varies in different types of transistors; for example, in a pillar gate transistor, the gate 109 is formed in a pillar shape on one side of the channel structure; in a semi-around gate transistor, the gate 109 partially surrounds the channel structure; and in a gate all around (GAA) gate transistor, the gate 109 fully surrounds the channel structure.
[0246] The transistor types in this disclosure may include, but are not limited to, the types described above. Preferably, the transistor type is a full-around gate transistor.
[0247] Next, the source and drain are formed at the bottom and top of the second part, respectively. The methods for forming the source and drain include, but are not limited to, doping and diffusion processes.
[0248] The first semiconductor pillar 102 between the source and drain forms the channel structure of the transistor. In this embodiment of the present disclosure, the channel structure is located in the middle of the second part, and the extension direction of the channel structure is the same as the extension direction of the second part.
[0249] It should be noted that the positions of the source and drain at the bottom and top of the second part can be interchanged; in practice, the selection and setting can be made according to actual needs.
[0250] Next, as Figure 26 As shown, a second insulating layer 110 is formed between the second protective pillars 104-2 and between the gate 109 (e.g., Figure 26 (As shown in the dashed box).
[0251] In some specific examples, the methods for forming the second insulating layer 110 include, but are not limited to, PVD, CVD, and ALD.
[0252] In some specific examples, the material of the second insulating layer 110 includes, but is not limited to, silicon oxide.
[0253] Here, the second insulating layer 110 serves to isolate adjacent gates 109, thereby improving the mutual interference problem between adjacent gates 109.
[0254] In some embodiments, the method further includes:
[0255] Multiple bit lines are formed on the second portion; the bit lines are in electrical contact with the top of the second portion.
[0256] It is understood that the memory in the above embodiment is a transistor-capacitor (TOC) structure, which further includes multiple bit lines located on the transistor and electrically contacting the top of the first semiconductor pillar 102.
[0257] It is understood that the bit line BL is used to perform read or write operations on the transistor when the transistor is turned on.
[0258] Here, placing the bit line BL above the transistor and treating the bit line BL as a metal bit line can reduce resistance and simplify the manufacturing process; it is also more compatible with the circuit design of the memory.
[0259] It is understood that in this embodiment of the present disclosure, the first protective layer 104 formed around the top sidewall of the first semiconductor pillar 102 serves to protect the top sidewall of the second part of the first semiconductor pillar 102, allowing the gate 109 and gate oxide layer 108 of the transistor to surround the middle sidewall of the second part of the first semiconductor pillar 102. Compared with the prior art, which first forms the gate conductive material and gate oxide layer material around the top and middle sidewalls of the second part of the first semiconductor pillar 102, and then removes the gate conductive material and gate oxide layer material around the top sidewall to form the gate 109 and gate oxide layer 108, the solution provided by this embodiment of the present disclosure can save gate conductive material. On the other hand, the solution provided by this embodiment of the present disclosure does not require re-etching the gate conductive material and gate oxide layer material around the top sidewall to form the gate 109 and gate oxide layer 108, thereby simplifying the process steps and saving process costs.
[0260] This disclosure provides a semiconductor structure and its fabrication method, as well as a memory. The semiconductor structure fabrication method includes: providing a substrate, forming a plurality of first semiconductor pillars 102 arranged in an array along a first direction and a second direction on the substrate; each first semiconductor pillar 102 includes a first portion and a second portion located on the first portion, the second portion including a bottom, a middle, and a top portion arranged in sequence; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; forming a memory structure 103 surrounding the sidewalls of the first portion; forming a first protective layer 104 surrounding the top sidewall of the second portion; forming a transistor, the channel structure of the transistor being located within the middle portion of the second portion, the extension direction of the channel structure being the same as the extension direction of the second portion. In this embodiment, on the one hand, by forming a first protective layer 104 around the top sidewall of the second part, the top sidewall of the second part is protected, so that when forming a transistor with a channel structure located in the middle of the second part, it is not necessary to first form the transistor material covering the top sidewall and the middle sidewall of the second part, and then remove the transistor material from the top sidewall of the second part, thereby saving process steps and saving transistor material; on the other hand, the first protective layer 104 formed around the top sidewall of the second part can also serve as a mask when forming the gate 109, thereby saving process steps and reducing manufacturing costs.
[0261] According to another aspect of this disclosure, embodiments of this disclosure further provide a semiconductor structure, including:
[0262] A substrate, a plurality of first semiconductor pillars, a memory structure, a plurality of transistors, and a first protective layer located above the substrate; wherein,
[0263] The plurality of first semiconductor pillars are arranged in an array along a first direction and a second direction; each first semiconductor pillar includes a first portion and a second portion located on the first portion, the second portion including a bottom, a middle and a top portion arranged in sequence; the first direction and the second direction intersect and are both parallel to the top surface of the substrate;
[0264] The storage structure surrounds the sidewall of the first part;
[0265] The first protective layer surrounds the top sidewall of the second portion;
[0266] The channel structure of the transistor is located in the middle of the second part, and the extension direction of the channel structure is the same as the extension direction of the second part.
[0267] In some embodiments, the first protective layer includes a plurality of first protective pillars and a plurality of second protective pillars;
[0268] The plurality of first protective pillars are arranged in an array along a first direction and a second direction. Each first protective pillar is located between the tops of two adjacent first semiconductor pillars in the first direction and covers the two opposite sidewalls of the two adjacent first semiconductor pillars.
[0269] Each of the second protective posts extends along the first direction, covering the sidewall of the second portion that is not covered by the first protective post, and also covering the sidewall of the first protective post.
[0270] In some embodiments, each transistor includes: a gate oxide layer disposed around the middle portion of the second portion, a gate disposed around the gate oxide layer, and a source and a drain disposed at the bottom and top of the second portion, respectively; wherein the surface of the gate away from the gate oxide layer is flush with the bottom edge of the second guard pillar away from the second portion.
[0271] In some embodiments, the diameter of the middle portion of the second portion is smaller than the diameter of the top portion of the second portion and smaller than the diameter of the bottom portion of the second portion.
[0272] In some embodiments, the semiconductor structure further includes a plurality of oxide pillars and a first oxide layer;
[0273] Each of the first semiconductor pillars is located on the top surface of one of the oxide pillars, and the first oxide layer is located between adjacent oxide pillars.
[0274] In some embodiments, the storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer;
[0275] The first electrode layer covers the sidewall of the first portion;
[0276] The dielectric layer at least covers the surface of the first electrode layer;
[0277] The second electrode layer covers the surface of the dielectric layer, and the storage structure covers the surface of the first oxide layer.
[0278] In some embodiments, the semiconductor structure further includes:
[0279] Multiple bit lines are located on the transistor and are electrically contacted at the top of the second portion.
[0280] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory comprising: at least one semiconductor structure as described in any of the embodiments described above in this disclosure.
[0281] The semiconductor structure and memory provided in the above embodiments have been described in detail in the method section, and will not be repeated here.
[0282] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.
[0283] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.
[0284] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor structure, characterized in that, include: A substrate, a plurality of first semiconductor pillars, a memory structure, a plurality of transistors, and a first protective layer located above the substrate; wherein, The plurality of first semiconductor pillars are arranged in an array along a first direction and a second direction; each first semiconductor pillar includes a first portion and a second portion located on the first portion, the second portion including a bottom, a middle and a top portion arranged in sequence; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; The storage structure surrounds the sidewall of the first part; The first protective layer surrounds the top sidewall of the second portion; The channel structure of the transistor is located in the middle of the second part, and the extension direction of the channel structure is the same as the extension direction of the second part. The semiconductor structure further includes a plurality of oxide pillars and a first oxide layer, wherein the plurality of oxide pillars are formed prior to the first oxide layer; Each of the first semiconductor pillars is located on the top surface of one of the oxide pillars, and the first oxide layer is located between adjacent oxide pillars.
2. The semiconductor structure according to claim 1, characterized in that, The first protective layer includes a plurality of first protective pillars and a plurality of second protective pillars; The plurality of first protective pillars are arranged in an array along a first direction and a second direction. Each first protective pillar is located between the tops of two adjacent first semiconductor pillars in the first direction and covers the two opposite sidewalls of the two adjacent first semiconductor pillars. Each of the second protective posts extends along the first direction, covering the sidewall of the second portion that is not covered by the first protective post, and also covering the sidewall of the first protective post.
3. The semiconductor structure according to claim 2, characterized in that, Each of the transistors includes: a gate oxide layer disposed around the middle of the second portion, a gate disposed around the gate oxide layer, and a source and a drain disposed at the bottom and top of the second portion, respectively; wherein the surface of the gate away from the gate oxide layer is flush with the bottom edge of the second guard pillar away from the second portion.
4. The semiconductor structure according to claim 1, characterized in that, The diameter of the middle part of the second part is smaller than the diameter of the top part of the second part, and smaller than the diameter of the bottom part of the second part.
5. The semiconductor structure according to claim 1, characterized in that, The storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer; The first electrode layer covers the sidewall of the first portion; The dielectric layer at least covers the surface of the first electrode layer; The second electrode layer covers the surface of the dielectric layer, and the storage structure covers the surface of the first oxide layer.
6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: Multiple bit lines are located on the transistor and are electrically contacted at the top of the second portion.
7. A memory, characterized in that, include: At least one semiconductor structure as described in any one of claims 1 to 6.
8. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided on which a plurality of first semiconductor pillars are formed in an array along a first direction and a second direction; each first semiconductor pillar includes a first portion and a second portion located on the first portion, the second portion including a bottom, a middle and a top portion arranged in sequence; the first direction and the second direction intersect and are both parallel to the top surface of the substrate; A storage structure is formed around the sidewalls of the first part; A first protective layer is formed around the top sidewall of the second part; A transistor is formed, wherein the channel structure of the transistor is located in the middle of the second portion, and the extension direction of the channel structure is the same as the extension direction of the second portion; The formation of the first protective layer includes: A first insulating layer is formed between the second portions; A portion of the first insulating layer at the top of the second part is removed to form a plurality of first grooves, each of the first grooves exposing two opposing sidewalls at the top of two adjacent first semiconductor pillars in a first direction; The first groove is filled to form a plurality of first protective pillars; Remove the remaining first insulating layer at the top of the second portion to form a plurality of second grooves extending along the first direction, each second groove exposing two opposing sidewalls at the top of two adjacent first semiconductor pillars in the second direction; Multiple second protective pillars are formed on the sidewall of the second groove, and the first protective pillar and the second protective pillar together constitute the first protective layer.
9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The formation of the transistor includes: After the first protective layer is formed, the first insulating layer in the middle of the second part is removed to expose the sidewall in the middle of the second part; A gate oxide layer is formed covering the sidewall of the middle portion of the second part; A gate is formed covering the gate oxide layer; The source and drain are formed at the bottom and top of the second part, respectively; A second insulating layer is formed between the second protective pillars and between the gate.
10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The gate forming the gate oxide layer includes: The gaps in the gate oxide layer are filled with gate conductive material; Using the first protective layer as a mask layer, a portion of the gate conductive material is removed, and the remaining gate conductive material forms the gate.
11. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The formation of the first semiconductor pillar includes: Provide semiconductor substrates; A plurality of first trenches are formed in the semiconductor substrate at intervals along a first direction, and a third insulating layer is formed in the first trenches and on the surface of the semiconductor substrate. The semiconductor substrate and the third insulating layer are etched to form a plurality of second trenches spaced apart along a second direction, wherein the bottom surface of the first trench is lower than the bottom surface of the second trench; the first trench and the second trench divide the semiconductor substrate into a plurality of first semiconductor pillars.
12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The method further includes: forming a second protective layer on the sidewall of each of the second trenches; The semiconductor substrate at the bottom of the second trench is etched to form an enlarged third trench, the bottom surface of the third trench being flush with the bottom surface of the first trench. A plurality of second semiconductor pillars are formed between adjacent third trenches, each of the first semiconductor pillars is located on a corresponding second semiconductor pillar, and the maximum diameter of the second semiconductor pillar along the second direction is smaller than the minimum diameter of the first semiconductor pillar. The second semiconductor pillar is subjected to an oxidation treatment so that the second semiconductor pillar is completely oxidized into an oxide pillar.
13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, The method further includes: after forming the second protective layer, filling the second trench with sacrificial material; Remove the third insulating layer, the second protective layer, and the sacrificial material located above the first semiconductor pillar; A plurality of first support material layers are formed on the top surface of the first semiconductor pillar, which are spaced apart along a first direction and extend along a second direction. Remove the remaining sacrificial material and etch the semiconductor substrate along the bottom of the second trench.
14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The method further includes filling a first oxide layer between the first support material layers, between the second protective layers, and between the oxide pillars; A portion of the first support material layer and a portion of the first oxide layer on the top surface of the first semiconductor pillar are removed to form a plurality of third grooves extending along the first direction, and the remaining first support material layer constitutes the first support layer. A second support layer is formed in the third groove, and the first support layer and the second support layer together form a grid-like top support layer.
15. The method for fabricating a semiconductor structure according to claim 14, characterized in that, The formation of the storage structure includes: Remove part of the first oxide layer and the second protective layer; A first conductive material, a dielectric layer material, and a second conductive material are sequentially filled between the first semiconductor pillars; Remove the top support layer, and then etch back the first conductive material, dielectric layer material, and second conductive material between the second parts. The remaining first conductive material, dielectric layer material, and second conductive material located between the first parts together constitute the storage structure.
16. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The method further includes: Multiple bit lines are formed on the second portion; the bit lines are in electrical contact with the top of the second portion.
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