Semiconductor structure and method of making the same, memory

Abstract

The embodiment of the present disclosure discloses a semiconductor structure, a manufacturing method thereof and a memory, wherein the semiconductor structure comprises a substrate, a plurality of oxide columns, a plurality of active columns, a first insulating layer and a storage structure; the plurality of oxide columns are located on the substrate and arranged in an array along a first direction and a second direction; the first direction and the second direction are both parallel to the surface of the substrate, and the first direction and the second direction intersect; the first insulating layer is located in the gap between the plurality of oxide columns; each active column is located on the top surface of a corresponding oxide column; and the storage structure covers at least part of the sidewall of the active column.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of transistors and capacitors (i.e., 1T1C memory cells) that serve as memory cells. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, the size of capacitors also shrinks. Ensuring the performance of capacitors in DRAM has become a pressing issue.

[0004] Public content

[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a memory.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0007] Substrate, multiple oxide pillars, multiple active pillars, first insulating layer, memory structure;

[0008] The plurality of oxide pillars are located on the substrate and are arranged in an array along a first direction and a second direction; both the first direction and the second direction are parallel to the surface of the substrate and intersect each other;

[0009] The first insulating layer is located in the gaps between the plurality of oxide pillars;

[0010] Each of the active columns is located on the top surface of a corresponding oxide column;

[0011] The storage structure at least covers a portion of the sidewall of the active column.

[0012] In the above scheme, the material of the oxide column may be the same as or different from the material of the first insulating layer.

[0013] In the above scheme, each active pillar includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; the orthographic projection of the first sub-active pillar on the substrate is located within the orthographic projection of the second sub-active pillar on the substrate.

[0014] In the above scheme, the storage structure includes:

[0015] A first conductive layer covers the sidewall of the first sub-active pillar;

[0016] A dielectric layer that covers the surface of the first conductive layer and the top surface of the first insulating layer;

[0017] The second conductive layer is located within the dielectric layer.

[0018] In the above scheme, the semiconductor structure further includes: a plurality of transistors, wherein the channel structure of each transistor is located within the second sub-active pillar, and the extension direction of the channel structure is perpendicular to the surface of the substrate.

[0019] In the above scheme, the transistor includes:

[0020] The gate structure surrounding the second sub-active pillar, and

[0021] The source and drain are respectively set at the two opposite ends of the second sub-active pillar.

[0022] In the above scheme, the semiconductor structure further includes:

[0023] Multiple bit lines are located on the transistor and are electrically contacted at the top of the second sub-active pillar.

[0024] According to another aspect of this disclosure, a memory is provided, comprising: one or more semiconductor structures as described in any of the embodiments of this disclosure above.

[0025] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0026] A plurality of semiconductor pillars are formed on a substrate in an array along a first direction and a second direction; each semiconductor pillar includes a first portion and a second portion located on the first portion; wherein the maximum diameter of the first portion is smaller than the minimum diameter of the second portion; both the first direction and the second direction are parallel to the surface of the substrate, and the first direction and the second direction intersect.

[0027] A support layer is formed on top of the semiconductor pillar, and the support layer covers the top sidewall of the second part;

[0028] The semiconductor pillar is subjected to an oxidation treatment so that the first portion is completely oxidized into an oxide pillar and the exposed surface of the second portion is oxidized into an oxide layer;

[0029] A first insulating material is filled into the gaps between the plurality of oxide pillars to form a first insulating layer on the substrate surface;

[0030] Remove the oxide layer to obtain the first sub-active column;

[0031] A storage structure is formed at least on the sidewall of the first active column.

[0032] In the above scheme, forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction on the substrate includes:

[0033] Provide semiconductor substrates;

[0034] Multiple first grooves spaced apart along a first direction and multiple second grooves spaced apart along a second direction are formed in the substrate;

[0035] The bottom of each of the first trenches and / or the second trenches is enlarged to form the plurality of semiconductor pillars.

[0036] In the above scheme, forming the support layer includes: filling the space between the plurality of semiconductor pillars with the first insulating material, etching away a portion of the first insulating material to expose the top of the semiconductor pillars, thereby obtaining a second sub-active pillar;

[0037] A second insulating material is deposited, which covers the surface of the second sub-active pillar, forming a second insulating layer on top of the semiconductor pillar.

[0038] In the above scheme, a portion of the second insulating layer is removed along the second direction to form a first shallow trench. The bottom surface of the first shallow trench is flush with the bottom surface of the second sub-active post, and the first insulating material is filled in the first shallow trench.

[0039] A portion of the second insulating layer is removed along the first direction to form a second shallow trench. The bottom surface of the second shallow trench is flush with the top surface of the second sub-active post. The second insulating material is then filled into the second shallow trench.

[0040] Remove all the first insulating material filling the spaces between the semiconductor pillars and form a mesh-like support layer on top of the semiconductor pillars.

[0041] In the above scheme, after the support layer is formed, the semiconductor pillar is oxidized, the first part of the semiconductor pillar is completely oxidized into an oxide pillar, and the surface of the exposed second part of the semiconductor pillar is oxidized into an oxide layer.

[0042] A first insulating material is then filled between the semiconductor pillars, and a portion of the first insulating material and the oxide layer are etched away. The remaining first insulating material and the oxide pillars form a first insulating layer on the surface of the substrate.

[0043] In the above scheme, forming a storage structure at least on the sidewall of the first sub-active column includes:

[0044] A first conductive layer is formed covering the sidewall of the first sub-active pillar;

[0045] A dielectric layer is formed covering the surface of the first conductive layer and the top surface of the first insulating layer;

[0046] A second conductive layer is formed in the dielectric layer.

[0047] In the above scheme, forming a first conductive layer covering the sidewall of the first sub-active pillar includes:

[0048] A first conductive layer is formed covering the sidewall of the first active post by a selective deposition process.

[0049] The method in the above scheme further includes:

[0050] Remove the support layer to expose the second sub-active pillar;

[0051] A gate structure is formed covering at least one side of the second sub-active pillar;

[0052] The source and drain are formed at opposite ends of the second active post.

[0053] In the above scheme, the maximum diameter of the first part along the first direction is smaller than the minimum diameter of the second part along the first direction;

[0054] And / or,

[0055] The maximum diameter of the first portion along the second direction is less than the minimum diameter of the second portion along the second direction.

[0056] In this embodiment of the present disclosure, a plurality of semiconductor pillars are formed on a substrate, each semiconductor pillar comprising a first portion and a second portion located on the first portion, such that the maximum diameter of the first portion is smaller than the minimum diameter of the second portion; then, through an oxidation process, the first portions of the plurality of semiconductor pillars are all oxidized into oxide pillars, and a first insulating material is filled between the plurality of oxide pillars; finally, a corresponding active pillar is formed on the top surface of each oxide pillar, such that the active pillar is insulated from the substrate; thereby, the memory structure formed on a portion of the sidewall of the active pillar is insulated from the substrate, thereby improving the leakage problem of the memory structure and thus improving the reliability of the memory. Attached Figure Description

[0057] Figure 1a This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;

[0058] Figure 1b This is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure;

[0059] Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0060] Figures 3a-3q This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure.

[0061] Explanation of reference numerals in the attached figures:

[0062] 300 - Semiconductor substrate; 301 - First trench; 302 - First insulating material; 303 - Second trench; 304 - Substrate; 305 - Semiconductor pillar; 3051 - First portion of semiconductor pillar; 3052 - Second portion of semiconductor pillar; 3052a - First sub-active pillar; 3052b - Second sub-active pillar; 306 - First gap; 308 - Second insulating layer; 309 - First shallow trench; 310 - Second shallow trench; 311 - Support layer; 312 - Oxide pillar; 313 - Oxide layer; 314 - First insulating layer; 315 - Storage structure; 3151 - First conductive layer; 3152 - Dielectric layer; 3153 - Second conductive layer.

[0063] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0064] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0065] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0066] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0067] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0068] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0069] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0070] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0071] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.

[0072] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0073] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0074] In some embodiments of this disclosure, regardless of whether it is a planar array transistor or a vertical channel array transistor, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0075] Figure 1a This is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of this disclosure. Figure 1b This is a schematic diagram of a DRAM memory array formed by transistors using a 1T1C architecture, provided in an embodiment of this disclosure; as shown... Figure 1a , Figure 1b As shown, the drain of transistor T is electrically connected to the bit line (BL), the source region of transistor T is electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C can be connected to a reference voltage, which can be ground voltage or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0076] However, in order to achieve the miniaturization of memory, the size of dynamic random access memory is constantly shrinking, and the size of capacitors is also shrinking. This makes the process of forming capacitors increasingly difficult, resulting in leakage problems in the capacitors during use.

[0077] In view of this, in order to solve one or more of the above problems, this disclosure provides a method for fabricating a semiconductor structure, which can increase the capacitor height, improve the storage capacity of the memory, and at the same time reduce the difficulty of the process. Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 2 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0078] S100: A plurality of semiconductor pillars are formed on a substrate in an array along a first direction and a second direction; each semiconductor pillar includes a first portion and a second portion located on the first portion; wherein the maximum diameter of the first portion is smaller than the minimum diameter of the second portion; the first direction and the second direction are both parallel to the surface of the substrate, and the first direction and the second direction intersect.

[0079] S200: A support layer is formed on top of the semiconductor pillar, the support layer covering the top sidewall of the second part;

[0080] S300: The semiconductor pillar is oxidized so that the first part is completely oxidized into an oxide pillar and the exposed surface of the second part is oxidized into an oxide layer;

[0081] S400: Fill the gaps between the plurality of oxide pillars with a first insulating material to form a first insulating layer on the surface of the substrate;

[0082] S500: Remove the oxide layer to obtain the first sub-active column;

[0083] S600: A storage structure is formed at least on the sidewall of the first sub-active column.

[0084] It should be understood that Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs. Figures 3a to 3q This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. The following is in conjunction with... Figure 2 , Figures 3a to 3q The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0085] In step S100, refer to Figure 3a , Figure 3b , Figure 3c , Figure 3d This forms multiple semiconductor pillars.

[0086] The plurality of semiconductor pillars are located on the substrate and are arranged in an array along the first and second directions.

[0087] In some embodiments, forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction on a substrate includes:

[0088] Provide semiconductor substrates;

[0089] Multiple first grooves spaced apart along a first direction and multiple second grooves spaced apart along a second direction are formed in the substrate;

[0090] The bottom of each of the first trenches and / or the second trenches is enlarged to form the plurality of semiconductor pillars.

[0091] Here, as Figure 3a As shown, the material of the semiconductor substrate 300 may include silicon (Si), germanium (Ge), silicon germanide (SiGe), etc.

[0092] refer to Figure 3a The surface of the semiconductor substrate 300 is first etched to form a plurality of first trenches 301 arranged at intervals along a first direction in the semiconductor substrate; here, each of the first trenches 301 extends along a second direction.

[0093] It should be noted that the first trench 301 is located in the semiconductor substrate, that is, the depth of the first trench 301 along the third direction is less than the thickness of the semiconductor substrate 300 along the third direction.

[0094] The first direction is parallel to the surface of the semiconductor substrate 300; the second direction intersects the first direction and is parallel to the surface of the semiconductor substrate 300. The third direction is perpendicular to the surface of the semiconductor substrate 300; this third direction can also be understood as the extension direction of the semiconductor substrate 300.

[0095] In other words, the first direction intersects the second direction, meaning the angle between the first direction and the second direction is any angle between 0 and 90 degrees. Here, both the first direction and the second direction are perpendicular to the third direction.

[0096] To clearly describe this disclosure, the following embodiments are illustrated using the example of a first direction being perpendicular to a second direction. For example, the first direction is... Figure 3a The X-axis direction is shown in the figure; the second direction is Figure 3a The Y-axis direction is shown in the figure; the third direction is Figure 3a The Z-axis direction is shown in the figure. However, it should be noted that the description of the direction in the following embodiments is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0097] In some embodiments, the first trench 301 includes, but is not limited to, a shallow trench isolation (STI) structure.

[0098] The first etching includes, but is not limited to, dry plasma etching processes.

[0099] refer to Figure 3b A first insulating material 302 is formed in the first trench 301; wherein the top surface of the first insulating material 302 is substantially flush with the top surface of the semiconductor substrate 300; here, the first insulating material 302 serves as a support.

[0100] In some embodiments, the constituent materials of the first insulating material 302 include, but are not limited to, silicon oxide (SiO2).

[0101] The methods for forming the first insulating material 302 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and other processes.

[0102] refer to Figure 3c The semiconductor substrate 300 on which the first insulating material 302 is formed is subjected to a second etching to form a plurality of second trenches 303 in the semiconductor substrate 300; wherein the plurality of second trenches 303 are arranged at intervals along a second direction, and each second trench 303 extends along a first direction; that is, the first trench 301 and the second trench 303 intersect.

[0103] For example, when the first direction is perpendicular to the second direction, the first groove 301 and the second groove 303 are perpendicular to each other.

[0104] Here, the second trench 303 is located in the semiconductor substrate 300, that is, the depth of the second trench 303 in the third direction is less than the thickness of the semiconductor substrate 300 in the third direction.

[0105] For example, a plurality of second trenches 303 are spaced apart along the Y-axis direction; and each second trench 303 extends along the X-axis direction, and the depth of each second trench 303 in the Z-axis direction is less than the thickness of the semiconductor layer in the Z-axis direction.

[0106] Here, the second etching includes, but is not limited to, dry plasma etching processes.

[0107] In some embodiments, the second trench 303 includes, but is not limited to, a shallow trench isolation (STI) structure.

[0108] In some embodiments, the depth of the first trench 301 along the third direction and the depth of the second trench 303 along the third direction may be the same or different.

[0109] Preferably, the depth of the first groove 301 along the third direction is the same as the depth of the second groove 303 along the third direction. This can reduce the need to adjust process parameters during manufacturing and reduce the difficulty of the process.

[0110] Here, the first trench 301 and the second trench 303 divide the semiconductor substrate into a plurality of cubic pillars arranged in an array along the first direction and the second direction; and a substrate 304 is formed under the plurality of cubic pillars.

[0111] In other embodiments, a grid-like mask layer can be formed on the surface of the semiconductor substrate, and the grid-like mask layer can be used as a mask to etch the semiconductor substrate to form a plurality of cubic pillars arranged in an array along the first and second directions in the semiconductor substrate.

[0112] Next, refer to Figure 3c The bottom of each of the first trench 301 and / or the second trench 303 is enlarged; here, the enlargement process can be understood as etching the bottom of the first trench 301 along a first direction; and / or etching the bottom of the second trench 303 along a second direction, such that the diameter of the bottom of the first trench 301 and / or the second trench 303 along the first direction is greater than the diameter of the top of the corresponding trench along the first direction.

[0113] And / or,

[0114] The bottom diameter of the first groove 301 and / or the second groove 303 along the second direction is greater than the top diameter of the corresponding groove along the second direction.

[0115] The etching process used here may include wet etching process, dry etching process, etc.

[0116] For example, in the wet etching process, an etchant is introduced into the bottom of the first trench 301 and / or the second trench 303, and the anisotropic etching of the etchant increases the diameter of the bottom of the first trench 301 and / or the second trench 303 along the X-axis direction; and / or increases the diameter of the bottom of the first trench 301 and / or the second trench 303 along the Y-axis direction.

[0117] For example, in the dry etching process, lateral etching is performed by controlling plasma to form a trench structure with an enlarged diameter at the bottom of the first trench 301 and / or the second trench 303.

[0118] In this embodiment of the disclosure, after the process of enlarging the bottom of each of the first trench 301 and / or the second trench 303, the etching process etches the bottom regions of a plurality of cubic pillars located on the substrate, reducing the size of the bottom regions of the cubic pillars, thereby forming the semiconductor pillars 305. (Refer to...) Figure 3c .

[0119] In other words, the semiconductor pillar 305 includes a first portion 3051 (reference 3051). Figure 3c (See the diagram within the dashed box) and the second portion 3052 located on the first portion 3051; here, the first portion 3051 of the semiconductor pillar is located between the second portion 3052 of the semiconductor pillar and the substrate 304.

[0120] In some embodiments, the maximum diameter of the first portion along the first direction is smaller than the minimum diameter of the second portion along the first direction;

[0121] And / or,

[0122] The maximum diameter of the first portion along the second direction is less than the minimum diameter of the second portion along the second direction.

[0123] For example, when only the first trench 301 is enlarged, the maximum diameter of the first portion 3051 of the semiconductor pillar along the X-axis is smaller than the minimum diameter of the second portion 3052 of the semiconductor pillar along the X-axis.

[0124] For example, when only the second trench 303 is enlarged, the maximum diameter of the first portion 3051 of the semiconductor pillar along the Y-axis is smaller than the minimum diameter of the second portion 3052 of the semiconductor pillar along the Y-axis.

[0125] For example, when both the first trench 301 and the second trench 303 are enlarged, the maximum diameter of the first portion 3051 of the semiconductor pillar along the X-axis is smaller than the minimum diameter of the second portion 3052 of the semiconductor pillar along the X-axis; and the maximum diameter of the first portion 3051 of the semiconductor pillar along the Y-axis is smaller than the minimum diameter of the second portion 3052 of the semiconductor pillar along the Y-axis.

[0126] Preferably, both the first trench 301 and the second trench 303 are enlarged to reduce the size of the first portion of the semiconductor pillar.

[0127] For example, the maximum diameter of the first part can be understood as Figure 3c The diameter at the contact point between the first portion 3051 and the second portion 3052 of the semiconductor pillar; the minimum diameter of the second portion can be understood as the smallest region within the second portion 3052 of the semiconductor pillar; Reference Figure 3c The upper and lower portions of the second part 3052 of the semiconductor pillar have the same dimensions, that is, the minimum and maximum diameters of the second part of the semiconductor pillar are the same.

[0128] refer to Figure 3d A first insulating material 302 is formed in the second trench 303; the top surface of the first insulating material 302 is substantially flush with the top surface of the semiconductor pillar 305. The first insulating material serves as a support.

[0129] For example, the constituent materials of the first insulating material 302 include, but are not limited to, silicon oxide.

[0130] Here, the methods for forming the first insulating material 302 include, but are not limited to, processes such as PVD and CVD.

[0131] It should be noted that the order in which the first trench 301 and the second trench 303 are formed, and the first insulating material 302 is filled into the first trench 301 and the second trench 303, can be selected according to the actual situation. In some other specific embodiments, the first trench 301 and the second trench 303 can be formed first, and then the first insulating material 302 can be filled into the first trench 301 and the second trench 303; here, the first insulating material is substantially flush with the top surface of the plurality of semiconductor pillars.

[0132] In step S200, refer to Figures 3e to 3k This forms a supporting layer.

[0133] In some embodiments, forming the support layer includes: etching away a portion of the first insulating material to expose the top of the semiconductor pillar, thereby obtaining a second sub-active pillar;

[0134] A second insulating material is deposited, which covers the surface of the second sub-active pillar, forming a second insulating layer on top of the semiconductor pillar.

[0135] refer to Figure 3e A portion of the first insulating material 302 located in the first trench 301 and the second trench 303 is etched to form a first gap 306, exposing the top of the semiconductor pillar, namely the second sub-active pillar 3052b. Here, the second sub-active pillar 3052b is the end portion of the second part of the semiconductor pillar that is away from the first part 3051.

[0136] refer to Figure 3f A second insulating material is formed in the first gap through a deposition process; then the second insulating material is planarized to form a second insulating layer 308 on the top of the semiconductor pillar; wherein the second insulating layer 308 covers the surface of the second sub-active pillar, and the top surface of the second insulating layer 308 is higher than the top surface of the semiconductor pillar.

[0137] Here, the deposition process includes, but is not limited to, PVD, CVD and other processes.

[0138] The planarization process includes, but is not limited to, chemical mechanical polishing (CMP).

[0139] The constituent materials of the second insulating layer 308 include, but are not limited to, nitrides, carbides, etc.

[0140] In some embodiments, reference Figure 3g A portion of the second insulating layer 308 is removed along the second direction to form a first shallow trench 309. The bottom surface of the first shallow trench 309 is flush with the bottom surface of the second sub-active post. The first insulating material 302 is filled into the first shallow trench 309.

[0141] A portion of the second insulating layer 308 is removed along the first direction to form a second shallow trench 310. The bottom surface of the second shallow trench 310 is flush with the top surface of the second sub-active post. The second shallow trench 310 is located directly above the second sub-active post and exposes the top surface of the second sub-active post. The second insulating material is filled into the second shallow trench 310.

[0142] Remove all the first insulating material 302 filling the space between the semiconductor pillars and form a mesh-like support layer 311 on top of the semiconductor pillars.

[0143] For example, refer to Figure 3g The second insulating layer 308 is etched by an etching process to remove part of the second insulating layer 308, exposing part of the top of the first insulating material 302, and forming a plurality of first shallow trenches 309 on the top of the semiconductor pillar; the plurality of first shallow trenches 309 are arranged at intervals along the X-axis direction, and each first shallow trench 309 extends along the Y-axis direction.

[0144] Here, the bottom surface of the first shallow trench 309 is basically flush with the bottom surface of the second active post 3052b.

[0145] refer to Figure 3hThe first shallow trench 309 is filled with a first insulating material 302, such that the top surface of the first insulating material 302 in the first shallow trench 309 is higher than the top surface of the semiconductor pillar. Here, the top surface of the first insulating material 302 in the first shallow trench 309 is substantially flush with the top surface of the remaining second insulating layer 308.

[0146] refer to Figure 3i The second insulating layer 308 and the first insulating material 302 located in the first shallow trench 309 are etched by an etching process to remove part of the second insulating layer 308 and part of the first insulating material 302, exposing part of the top surface of the semiconductor pillar, and forming a plurality of second shallow trenches 310 on the top surface of the semiconductor pillar; the plurality of second shallow trenches 310 are arranged at intervals along the Y-axis direction, and each second shallow trench 310 extends along the X-axis direction.

[0147] Here, the bottom surface of the second shallow trench 310 is basically flush with the top surface of the second sub-active post 3052b. The second shallow trench 310 is located directly above the second sub-active post and exposes the top surface of the second sub-active post.

[0148] It should be noted that the term "basic flush" in the embodiments of this disclosure can be understood as "approximately flush"; it is also understood that misalignment or non-flushness caused by process errors during the manufacturing process of the memory is also included within the scope of "basic flush".

[0149] refer to Figure 3j The second insulating material is filled into the second shallow trench 310; here, the top surface of the second insulating material in the second shallow trench 310 is substantially flush with the top surface of the second insulating layer 308.

[0150] refer to Figure 3k Remove the first insulating material 302 located between the semiconductor pillars and form a mesh-like support layer 311 on top of the semiconductor pillars.

[0151] Here, the supporting layer 311 is composed of materials including but not limited to nitrides, carbon, etc.

[0152] Preferably, the supporting layer 311 is composed of silicon nitride.

[0153] In step S300, refer to Figure 3l , Figure 3m The semiconductor pillar 305 is subjected to oxidation treatment.

[0154] In some embodiments, reference Figure 3l After the support layer 311 is formed, the semiconductor pillar is oxidized. The first part of the semiconductor pillar is completely oxidized into an oxide pillar 312, and the surface of the exposed second part of the semiconductor pillar is oxidized into an oxide layer 313.

[0155] refer to Figure 3m Then, a first insulating material 302 is filled between the semiconductor pillars, and a portion of the first insulating material 302 and the oxide layer 313 are etched away. The remaining first insulating material 302 and the oxide pillars 312 form a first insulating layer 314 on the surface of the substrate.

[0156] For example, refer to Figure 3l The semiconductor pillar is oxidized by an oxidation process, so that the first part 3051 of the semiconductor pillar is completely oxidized into an oxide pillar 312, and the surface of the exposed second part of the semiconductor pillar is oxidized into an oxide layer 313. At the same time, the surface of the substrate 304 is also oxidized to form an oxide layer.

[0157] Here, the oxide pillar 312 and the oxide layer 313 are made of the same material.

[0158] For example, the constituent materials of the oxide pillar 312 and the oxide layer 313 include, but are not limited to, silicon oxide.

[0159] In some embodiments, the material of the oxide pillar 312 may be the same as or different from the material of the first insulating layer 314.

[0160] For example, the constituent materials of the first insulating layer 314 include, but are not limited to, silicon oxide.

[0161] It should be noted that, in the foregoing embodiments, after enlarging the first trench 301 and / or the second trench 303, the first portion of the semiconductor pillar is smaller in size and easier to be completely oxidized. Furthermore, when the first portion of the semiconductor pillar is completely oxidized, only the surface of the second portion of the semiconductor pillar is oxidized.

[0162] It should also be noted that, since the second sub-active column in the second part of the semiconductor column is surrounded by the support layer 311, the support layer 311 can be used to protect the top of the semiconductor column (i.e. the second sub-active column) from oxidation or damage when the first part and the second part of the semiconductor column are oxidized.

[0163] refer to Figure 3m , Figure 3n In step S400, a first insulating layer 314 is formed; in step S500, a first sub-active post is obtained.

[0164] refer to Figure 3m A first insulating material 302 is filled between the plurality of semiconductor pillars on which the oxide layer 313 is formed, such that the first insulating material 302 is substantially flush with the top surface of the support layer 311.

[0165] Here, the methods for filling the first insulating material 302 include, but are not limited to, processes such as PVD and CVD.

[0166] refer to Figure 3n The first insulating material 302 located between the plurality of semiconductor pillars and the oxide layer 313 located on the second part of the surface of the semiconductor pillars are removed by etching process to obtain the first sub-active pillar 3052a.

[0167] It should be noted that the first sub-active pillar 3052a and the second sub-active pillar 3052b constitute the second part 3052 of the semiconductor pillar, and the second sub-active pillar 3052b is located on the first sub-active pillar 3052a.

[0168] Here, the remaining first insulating material 302 and the oxide pillar 312 constitute a first insulating layer 314; wherein, the first insulating layer 314 is located between the first sub-active pillar 3052a and the substrate 304.

[0169] The etching process includes, but is not limited to, dry plasma etching.

[0170] In some embodiments, the orthographic projection of the first sub-active post 3052a on the substrate lies within the orthographic projection of the second sub-active post 3052b on the substrate.

[0171] In step S600, refer to Figure 3o , Figure 3p , Figure 3q This forms a storage structure 315.

[0172] Here, the storage structure 315 is used to store data. For example, the storage structure 315 includes a capacitor.

[0173] In some embodiments, forming a storage structure at least on the sidewall of the first sub-active column 3052a includes:

[0174] A first conductive layer 3151 is formed covering the sidewall of the first sub-active pillar 3052a;

[0175] A dielectric layer 3152 is formed covering the surface of the first conductive layer and the top surface of the first insulating layer 314;

[0176] A second conductive layer 3153 is formed in the dielectric layer 3152.

[0177] Here, the first conductive layer is used as the lower electrode of the capacitor; the dielectric layer is used as the dielectric of the capacitor; and the second conductive layer is used as the upper electrode of the capacitor.

[0178] In some specific embodiments, the constituent materials of the first conductive layer 3151 may include, but are not limited to, ruthenium (Ru), ruthenium oxide (RuO), and titanium nitride (TiN).

[0179] In this embodiment of the disclosure, a first conductive layer can be formed on the sidewall of the first sub-active pillar by a selective deposition process, or by other deposition processes.

[0180] The selective deposition process refers to the selective deposition of the first conductive layer on the sidewall of the first active pillar. Here, other deposition processes include, but are not limited to, PVD, CVD, and atomic layer deposition (ALD).

[0181] In some specific embodiments, forming a first conductive layer covering the sidewall of the first sub-active pillar 3052a includes:

[0182] A first conductive layer is formed covering the sidewall of the first active post 3052a using a selective deposition process.

[0183] It should be noted that, in the embodiments of this disclosure, during the selective deposition process to form the first conductive layer, the material used to form the first conductive layer can be formed only on the sidewall of the first active pillar 3052a, or on other selected materials, and not on the top surface of the first insulating layer 314. (Refer to...) Figure 3o This avoids forming the first conductive layer in gaps with high aspect ratios, reducing process difficulty and increasing the process window; on the other hand, it also avoids the void problem that occurs when forming the first conductive layer using other processes, thereby improving the reliability of the semiconductor structure.

[0184] refer to Figure 3o A dielectric layer 3152 is formed on the surface of the first conductive layer and the dielectric layer on the top surface of the first insulating layer 314 by a deposition process.

[0185] The dielectric layer is composed of high-k dielectric materials, which generally refer to materials with a dielectric constant higher than 3.9, and are usually significantly higher than this value. In some specific examples, the dielectric layer material may include, but is not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), strontium titanate (SrTiO3), etc.

[0186] refer to Figure 3o A second conductive layer 3153 is formed in the dielectric layer.

[0187] In some specific embodiments, the constituent materials of the second conductive layer may include, but are not limited to, ruthenium, ruthenium oxide, and titanium nitride.

[0188] Here, the methods for forming the second conductive layer include, but are not limited to, processes such as PVD and CVD.

[0189] It should be noted that the method for forming the first conductive layer and the second conductive layer in the above embodiments can also be understood as forming a conductive layer-to-conductive layer (CoC) using a selective deposition process; here, the selective deposition process includes, but is not limited to, ALD process, etc.

[0190] In some embodiments, the method further includes:

[0191] Remove the support layer 311 to expose the second sub-active pillar 3052b;

[0192] A gate structure is formed covering at least one side of the second sub-active pillar;

[0193] The source and drain are formed at opposite ends of the second active post.

[0194] For example, refer to Figure 3p , Figure 3q The support layer 311 is removed by etching to expose the second sub-active pillar 3052b.

[0195] It should be noted that, in some other specific embodiments, when the dielectric layer is also formed at the bottom of the support layer 311, the removal of the support layer 311 further includes: removing the dielectric layer located at the bottom of the support layer 311.

[0196] Here, the bottom of the support layer 311 is parallel to the bottom surface of the second sub-active column 3052b.

[0197] The etching process includes, but is not limited to, dry plasma etching.

[0198] Next, refer to Figure 3q Through a process, a gate structure is formed on at least one side of the second sub-active pillar. Figure 3q (Not shown in the image).

[0199] Here, the shape of the gate differs in different types of transistors; for example, in a pillar gate transistor, the gate is formed in a pillar shape on one side of the channel region; in a semi-around gate transistor, the gate partially surrounds the channel region; and in a gate all around (GAA) transistor, the gate completely surrounds the channel region.

[0200] The transistor types in this disclosure may include, but are not limited to, the types described above. Preferably, the transistor type is a full-around gate transistor.

[0201] It should be noted that the gate structure here includes the gate (G) and the gate oxide layer; the gate oxide layer is located between the gate and the channel region, and is used to electrically isolate the channel region and the gate, thereby reducing the hot carrier effect of the transistor.

[0202] Here, the gate material can include metal or polysilicon, etc. The gate oxide material can include, but is not limited to, silicon oxide.

[0203] In some embodiments, the gate formation method includes, but is not limited to, PVD, CVD, ALD, etc. The gate oxide layer formation method includes, but is not limited to, in-situ oxidation.

[0204] The source and drain are formed at opposite ends of the second active pillar, respectively. Figure 3q (Not shown in the image).

[0205] In some specific embodiments, the methods for forming the source and drain include, but are not limited to, doping and diffusion processes.

[0206] It should be noted that the positions of the source and drain at opposite ends of the second active post can be interchanged; in practice, the selection and setting can be made according to actual needs.

[0207] It is understood that the memory in the above embodiment is a transistor-capacitor (TOC) structure, which further includes multiple bit lines located on the transistor and electrically contacting the top of the second sub-active pillar.

[0208] Therefore, in some embodiments, the method further includes forming a bit line BL on the transistor.

[0209] It is understood that the bit line BL is used to perform read or write operations on the transistor when the transistor is turned on.

[0210] Here, placing the bit line BL above the transistor and treating the bit line BL as a metal bit line can reduce resistance and simplify the manufacturing process; it is also more compatible with the circuit design of the memory.

[0211] Based on this, in this embodiment of the present disclosure, a plurality of semiconductor pillars are formed on a substrate, each semiconductor pillar including a first portion and a second portion located on the first portion, such that the maximum diameter of the first portion is smaller than the minimum diameter of the second portion; then, through an oxidation process, the first portions of the plurality of semiconductor pillars are all oxidized into oxide pillars, and a first insulating material is filled between the plurality of oxide pillars; finally, a corresponding active pillar is formed on the top surface of each oxide pillar, so that the active pillar is insulated from the substrate; thereby, the memory structure formed on a portion of the sidewall of the active pillar is insulated from the substrate, thereby improving the leakage problem of the memory structure and thus improving the reliability of the memory.

[0212] According to another aspect of this disclosure, embodiments of this disclosure further provide a semiconductor structure, including:

[0213] Substrate, multiple oxide pillars, multiple active pillars, first insulating layer, memory structure;

[0214] The plurality of oxide pillars are located on the substrate and are arranged in an array along a first direction and a second direction; both the first direction and the second direction are parallel to the surface of the substrate and intersect each other;

[0215] The first insulating layer is located in the gaps between the plurality of oxide pillars;

[0216] Each of the active columns is located on the top surface of a corresponding oxide column;

[0217] The storage structure at least covers a portion of the sidewall of the active column.

[0218] In some embodiments, the material of the oxide pillar may be the same as or different from the material of the first insulating layer.

[0219] In some embodiments, each of the active pillars includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; the orthographic projection of the first sub-active pillar on the substrate lies within the orthographic projection of the second sub-active pillar on the substrate.

[0220] In some embodiments, the storage structure includes:

[0221] A first conductive layer covers the sidewall of the first sub-active pillar;

[0222] A dielectric layer that covers the surface of the first conductive layer and the top surface of the first insulating layer;

[0223] The second conductive layer is located within the dielectric layer.

[0224] In some embodiments, the semiconductor structure further includes: a plurality of transistors, each transistor having a channel structure located within the second sub-active pillar, the channel structure extending perpendicularly to the surface of the substrate.

[0225] In some embodiments, the transistor includes:

[0226] The gate structure surrounding the second sub-active pillar, and

[0227] The source and drain are respectively set at the two opposite ends of the second sub-active pillar.

[0228] In some embodiments, the semiconductor structure further includes:

[0229] Multiple bit lines are located on the transistor and are electrically contacted at the top of the second sub-active pillar.

[0230] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory comprising: one or more semiconductor structures as described in any of the above embodiments of this disclosure.

[0231] Based on this, in the embodiments of this disclosure, by providing a corresponding oxide pillar between each active pillar and the substrate, the storage structure (e.g., capacitor) formed on a portion of the sidewall of the active pillar can be isolated, thereby reducing the leakage problem of the storage structure (e.g., capacitor) during use.

[0232] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0233] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, multiple oxide pillars, multiple active pillars, first insulating layer, memory structure; The plurality of oxide pillars are located on the substrate and are arranged in an array along a first direction and a second direction; both the first direction and the second direction are parallel to the surface of the substrate and intersect each other; The first insulating layer is located in the gaps between the plurality of oxide pillars; Each of the active columns is located on the top surface of a corresponding oxide column; The storage structure at least covers a portion of the sidewall of the active column; Each of the active pillars includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar; the orthographic projection of the first sub-active pillar on the substrate is located within the orthographic projection of the second sub-active pillar on the substrate; The storage structure includes: A first conductive layer covers the sidewall of the first sub-active pillar; A dielectric layer that covers the surface of the first conductive layer and the top surface of the first insulating layer; The second conductive layer is located within the dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, The material of the oxide column may be the same as or different from the material of the first insulating layer.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a plurality of transistors, each of which has a channel structure located within the second sub-active pillar, the channel structure extending perpendicularly to the surface of the substrate.

4. The semiconductor structure according to claim 3, characterized in that, The transistor includes: The gate structure surrounding the second sub-active pillar, and The source and drain are respectively set at the two opposite ends of the second sub-active pillar.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: Multiple bit lines are located on the transistor and are electrically contacted at the top of the second sub-active pillar.

6. A memory, characterized in that, include: One or more semiconductor structures as described in any one of claims 1 to 5.

7. A method for fabricating a semiconductor structure, characterized in that, The method includes: A plurality of semiconductor pillars are formed on a substrate in an array along a first direction and a second direction; each semiconductor pillar includes a first portion and a second portion located on the first portion; wherein the maximum diameter of the first portion is smaller than the minimum diameter of the second portion; both the first direction and the second direction are parallel to the surface of the substrate, and the first direction and the second direction intersect. A support layer is formed on top of the semiconductor pillar, and the support layer covers the top sidewall of the second part; The semiconductor pillar is subjected to an oxidation treatment so that the first portion is completely oxidized into an oxide pillar and the exposed surface of the second portion is oxidized into an oxide layer; A first insulating material is filled into the gaps between the plurality of oxide pillars to form a first insulating layer on the substrate surface; Remove the oxide layer to obtain the first sub-active column; A storage structure is formed at least on the sidewall of the first active column.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The formation of a plurality of semiconductor pillars arranged in an array along a first direction and a second direction on the substrate includes: Provide semiconductor substrates; Multiple first grooves spaced apart along a first direction and multiple second grooves spaced apart along a second direction are formed in the substrate; The bottom of each of the first trenches and / or the second trenches is enlarged to form the plurality of semiconductor pillars.

9. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The formation of the support layer includes: filling the space between the plurality of semiconductor pillars with the first insulating material, etching away a portion of the first insulating material to expose the top of the semiconductor pillars, thereby obtaining a second sub-active pillar; A second insulating material is deposited, which covers the surface of the second sub-active pillar, forming a second insulating layer on top of the semiconductor pillar.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, A portion of the second insulating layer is removed along the second direction to form a first shallow trench. The bottom surface of the first shallow trench is flush with the bottom surface of the second sub-active post. The first insulating material is then filled into the first shallow trench. A portion of the second insulating layer is removed along the first direction to form a second shallow trench. The bottom surface of the second shallow trench is flush with the top surface of the second sub-active post. The second insulating material is then filled into the second shallow trench. Remove all the first insulating material filling the spaces between the semiconductor pillars and form a mesh-like support layer on top of the semiconductor pillars.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, After the support layer is formed, the semiconductor pillar is oxidized, the first portion of the semiconductor pillar is completely oxidized into an oxide pillar, and the surface of the exposed second portion of the semiconductor pillar is oxidized into an oxide layer. A first insulating material is then filled between the semiconductor pillars, and a portion of the first insulating material and the oxide layer are etched away. The remaining first insulating material and the oxide pillars form a first insulating layer on the surface of the substrate.

12. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The formation of a storage structure at least on the sidewall of the first sub-active column includes: A first conductive layer is formed covering the sidewall of the first sub-active pillar; A dielectric layer is formed covering the surface of the first conductive layer and the top surface of the first insulating layer; A second conductive layer is formed in the dielectric layer.

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, The formation of the first conductive layer covering the sidewall of the first sub-active pillar includes: A first conductive layer is formed covering the sidewall of the first active post by a selective deposition process.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The method further includes: Remove the support layer to expose the second sub-active pillar; A gate structure is formed covering at least one side of the second sub-active pillar; The source and drain are formed at opposite ends of the second active post.

15. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The maximum diameter of the first part along the first direction is smaller than the minimum diameter of the second part along the first direction; And / or, The maximum diameter of the first portion along the second direction is less than the minimum diameter of the second portion along the second direction.

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