Semiconductor element and method for producing the same

Abstract

A semiconductor element includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first bottom electrode layer and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor element also includes a plurality of insulating portions laterally separating the first bottom electrode layer and the second bottom electrode layer. The semiconductor element further includes a top electrode disposed over and surrounded by the bottom electrode structure. The top electrode has a ring shape from a top view. In addition, the semiconductor element includes an insulating layer separating the top electrode from the bottom electrode structure.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 17 / 849,768 (i.e., priority date "June 27, 2022"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, it relates to a semiconductor device having a ring electrode and a method for fabricating the same. Background Technology

[0003] Semiconductor components are crucial for many modern applications. With advancements in electronics, semiconductor components are becoming increasingly smaller while offering more functionality and incorporating a greater number of integrated circuits. Due to the miniaturization of semiconductor components, various types and sizes of semiconductor components providing different functions are integrated and packaged into a single module. Furthermore, multiple manufacturing processes are employed to integrate various types of semiconductor components together.

[0004] However, the manufacturing and integration of semiconductor devices involves many complex steps and operations. Integration within semiconductor devices is becoming increasingly complex. This increased complexity in the manufacturing and integration of semiconductor devices can introduce defects. Therefore, continuous improvement of semiconductor device manufacturing processes is necessary to address these defects.

[0005] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] In one embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a bottom electrode structure disposed on a semiconductor substrate. The bottom electrode structure includes a first bottom electrode layer and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor device also includes a plurality of insulating portions laterally separating the first bottom electrode layer and the second bottom electrode layer. The semiconductor device further includes a top electrode disposed on and surrounded by the bottom electrode structure. From a top view, the top electrode has an annular shape. Furthermore, the semiconductor device includes an insulating layer that separates the top electrode from the bottom electrode structure.

[0007] In one embodiment, the first bottom electrode layer and the second bottom electrode layer comprise different materials. In one embodiment, the first bottom electrode layer extends over a top surface of the second bottom electrode layer. In one embodiment, the insulating layer extends over a top surface of the second bottom electrode layer. In one embodiment, the insulating portions include an inner insulating portion and an outer insulating portion spaced apart from the inner insulating portion, and the top electrode is disposed between the inner insulating portion and the outer insulating portion. In one embodiment, the inner insulating portion and the outer insulating portion are annular. In one embodiment, the semiconductor element further includes a dielectric layer disposed between the bottom electrode structure and the semiconductor substrate, wherein the first bottom electrode layer and the second bottom electrode layer are in direct contact with the dielectric layer.

[0008] In another embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a top electrode disposed on a semiconductor substrate. From a top view, the top electrode has an annular shape. The semiconductor device also includes an insulating layer disposed along an inner sidewall, a bottom surface, and an outer sidewall of the top electrode, and a bottom electrode structure surrounding the insulating layer. The bottom electrode structure includes a first bottom electrode layer in direct contact with the insulating layer, and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor device further includes a plurality of insulating portions disposed between the first bottom electrode layer and the second bottom electrode layer.

[0009] In one embodiment, the first bottom electrode layer extends between the insulating layer and the semiconductor substrate. In one embodiment, the first bottom electrode layer comprises titanium nitride (TiN), and the second bottom electrode layer comprises polycrystalline silicon, silicon germanium (SiGe), or a combination thereof. In one embodiment, the first bottom electrode layer extends over and directly contacts a top surface of the second bottom electrode layer and the top surfaces of the insulating portions. In one embodiment, the insulating layer comprises a first insulating material, and the insulating portions comprise a second insulating material, wherein the first insulating material is different from the second insulating material. In one embodiment, the semiconductor element further includes a dielectric layer disposed between the bottom electrode structure and the semiconductor substrate, wherein the first bottom electrode layer, the second bottom electrode layer, and the insulating portions are in direct contact with the dielectric layer.

[0010] In another embodiment of this disclosure, a method for fabricating a semiconductor device is provided. The method includes forming a dielectric layer on a semiconductor substrate and forming an energy-removable layer on the dielectric layer. The method also includes etching the energy-removable layer to form an annular opening exposing the dielectric layer, and depositing a first bottom electrode layer along an inner sidewall, a bottom surface, and an outer sidewall of the annular opening. The method further includes depositing an insulating layer on the first bottom electrode layer and forming a top electrode in a remaining portion of the annular opening. Additionally, the method includes removing the energy-removable layer after forming the top electrode.

[0011] In one embodiment, the first bottom electrode layer extends over a top surface of the energy-removable layer. In one embodiment, the insulating layer extends over a top surface of the energy-removable layer. In one embodiment, forming the top electrode includes depositing a top electrode material over the insulating layer and performing a planarization process on the top electrode material to expose a portion of the insulating layer located over a top surface of the energy-removable layer. In one embodiment, the method further includes, after removing the energy-removable layer, depositing an insulating material covering a top surface of the dielectric layer, the sidewalls of the first bottom electrode layer, and a top surface of the top electrode, and performing an etch process on the insulating material such that an inner insulating portion and an outer insulating portion remain on the sidewalls of the first bottom electrode layer. In one embodiment, the inner insulating portion and the outer insulating portion are annular, and the top electrode is located between the inner insulating portion and the outer insulating portion. In one embodiment, the method further includes depositing a second bottom electrode layer between the first bottom electrode layer and the dielectric layer after forming the inner insulating portion and the outer insulating portion, wherein the second bottom insulating layer includes an interior surrounded by the inner insulating portion and an exterior surrounding the outer insulating portion.

[0012] This invention provides an embodiment of a semiconductor device and a method for fabricating the same. In some embodiments, the semiconductor device includes a bottom electrode structure, a top electrode disposed on the bottom electrode structure, and an insulating layer separating the top electrode from the bottom electrode structure. In some embodiments, the bottom electrode structure includes a first bottom electrode layer and a second bottom electrode layer surrounding the first bottom electrode layer. The top electrode has an annular shape and is surrounded by the first bottom electrode layer. Before forming the second bottom electrode layer, the top electrode, the insulating layer, and the first bottom electrode layer together form a columnar structure to enhance structural strength and make the structure less likely to collapse. Furthermore, the first bottom electrode layer and the second bottom electrode layer are laterally separated by multiple insulating portions, thereby increasing the surface area of ​​the electrode plate and thus obtaining effective capacitance. As a result, the overall device performance can be improved, and the yield of the semiconductor device can be increased.

[0013] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0014] This disclosure can be read in conjunction with the following figures and detailed description for better understanding. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of each feature may be arbitrarily enlarged or reduced.

[0015] Figure 1 A cross-sectional view of a semiconductor device is shown according to some embodiments.

[0016] Figure 2 According to some embodiments, along Figure 1 The cross-sectional view drawn by line A-A' in the diagram.

[0017] Figure 3 A flowchart of a method for fabricating a semiconductor device is shown according to some embodiments.

[0018] Figure 4 A cross-sectional view showing an intermediate stage in the formation of a semiconductor substrate during the formation of a semiconductor element, according to some embodiments.

[0019] Figure 5 According to some embodiments, a cross-sectional view of an intermediate stage during the formation of a dielectric layer on a semiconductor substrate is shown.

[0020] Figure 6 According to some embodiments, a cross-sectional view of an intermediate stage during the formation of a semiconductor device is shown, in which an energy-removable layer is formed on top of the dielectric layer.

[0021] Figure 7 According to some embodiments, a cross-sectional view of an intermediate stage is shown in which a patterned hard mask with an annular opening is formed on the energy-removable layer during the formation of a semiconductor device.

[0022] Figure 8 According to some embodiments, along Figure 7 The cross-sectional view drawn by line B-B' in the diagram.

[0023] Figure 9According to some embodiments, a cross-sectional view of an intermediate stage is shown, which is etched during the formation of a semiconductor device to form an annular opening that exposes the dielectric layer.

[0024] Figure 10 A cross-sectional view of an intermediate stage during the formation of a semiconductor device, as shown in some embodiments, is displayed.

[0025] Figure 11 According to some embodiments, along Figure 10 The cross-sectional view drawn by line A-A' in the diagram.

[0026] Figure 12 According to some embodiments, a cross-sectional view of an intermediate stage during the deposition of a first bottom electrode layer along an inner sidewall, a bottom surface, and an outer sidewall of the annular opening is shown.

[0027] Figure 13 According to some embodiments, a cross-sectional view of an intermediate stage during the formation of a semiconductor device is shown, in which an insulating layer is deposited on the first bottom electrode layer.

[0028] Figure 14 According to some embodiments, a cross-sectional view of an intermediate stage during the deposition of a top electrode material on an insulating layer during the formation of a semiconductor device is shown.

[0029] Figure 15 According to some embodiments, a cross-sectional view of an intermediate stage of a planarization process is shown on the top electrode material during the formation of a semiconductor device to form a top electrode.

[0030] Figure 16 According to some embodiments, along Figure 15 The cross-sectional view drawn by line A-A' in the diagram.

[0031] Figure 17 A cross-sectional view of an intermediate stage during the formation of a semiconductor device, as shown in some embodiments.

[0032] Figure 18 According to some embodiments, along Figure 17 The cross-sectional view drawn by line A-A' in the diagram.

[0033] Figure 19 A cross-sectional view showing an intermediate stage of conformal deposition of an insulating material during the formation of a semiconductor device, according to some embodiments.

[0034] Figure 20 According to some embodiments, a cross-sectional view of an intermediate stage is shown where an etching process is performed on the insulating material during the formation of a semiconductor device to form multiple insulating portions.

[0035] Figure 21According to some embodiments, along Figure 20 The cross-sectional view drawn by line A-A' in the diagram.

[0036] The reference numerals in the attached figures are explained as follows:

[0037] 10: Method

[0038] 100: Semiconductor components

[0039] 101: Semiconductor substrate

[0040] 103a: Conductive contact

[0041] 103b: Conductive contact

[0042] 105: Dielectric layer

[0043] 107: Energy-Removable Layer

[0044] 109: Patterned Hard Mask

[0045] 112: Annular opening

[0046] 114: Annular opening

[0047] 117: First bottom electrode layer

[0048] 119: Insulation layer

[0049] 121: Top electrode material

[0050] 123: Top electrode

[0051] 125: Insulating materials

[0052] 127a: Insulation part

[0053] 127b: Insulation section

[0054] 129: Second bottom electrode layer

[0055] 129a: Internal

[0056] 129b: External

[0057] 131: Bottom Electrode Structure

[0058] A-A': line

[0059] B-B': Line

[0060] BS1: Bottom surface

[0061] BS2: Bottom surface

[0062] S11: Steps

[0063] S13: Steps

[0064] S15: Steps

[0065] S17: Steps

[0066] S19: Steps

[0067] S21: Steps

[0068] S23: Steps

[0069] S25: Steps

[0070] S27: Steps

[0071] SW1: Inner wall

[0072] SW2: Lateral wall

[0073] SW3: Inner wall

[0074] SW4: Lateral wall

[0075] SW5: Sidewall

[0076] SW6: Sidewall

[0077] TS1: Top surface

[0078] TS2: Top surface

[0079] TS3: Top surface

[0080] TS4: Top surface

[0081] TS5: Top surface

[0082] TS6: Top surface Detailed Implementation

[0083] The following discloses various embodiments or examples of different components for implementing the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as limiting the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to limit the relationship between the different embodiments and / or structures discussed.

[0084] Furthermore, this text uses spatially related terms such as "below," "below," "lower," "above," "higher," and similar terms to facilitate the description of the relationship between one element or component shown in the diagram and another. These spatial relation terms are used to cover different orientations of elements in use or operation, beyond those depicted in the diagram. The device may be rotated to different orientations (90 degrees or other orientations), and the spatially related adjectives used therein can be interpreted similarly.

[0085] According to some embodiments, Figure 1 A cross-sectional view of a semiconductor device 100 is shown, and Figure 2 Show along Figure 1 The cross-sectional view is drawn along line A-A'. In some embodiments, the semiconductor element 100 includes a semiconductor substrate 101, a plurality of conductive contacts 103a and 103b disposed in the semiconductor substrate 101, and a dielectric layer 105 disposed on the semiconductor substrate 101. In some embodiments, the semiconductor element 100 includes a capacitor disposed on the dielectric layer 105.

[0086] In some embodiments, the capacitor of the semiconductor element 100 includes a bottom electrode structure 131, a plurality of insulating portions 127a and 127b disposed in the bottom electrode structure 131, a top electrode 123 disposed on and surrounded by the bottom electrode structure 131, and an insulating layer 119 separating the top electrode 123 and the bottom electrode structure 131. In some embodiments, the bottom electrode structure 131 includes a first bottom electrode layer 117 and a second bottom electrode layer 129 surrounding the first bottom electrode layer 117, and the second bottom electrode layer 129 includes an inner 129a and an outer 129b. In some embodiments, the second bottom electrode layer 129 is laterally separated from the first bottom electrode layer 117 by the insulating portions 127a and 127b.

[0087] In some embodiments, the top electrode 123 has an annular shape, such as Figure 2 As shown in the cross-sectional view. In some embodiments, the top electrode 123 has an annular shape when viewed from the top view. In some embodiments, the insulating portion 127a (also referred to as the inner insulating portion) and the insulating portion 127b (also referred to as the outer insulating portion) are separated (i.e., there is no physical connection). In some embodiments, the insulating portions 127a and 127b are annular, as... Figure 2 As shown in the cross-sectional view. In some embodiments, from the top view, the insulating portions 127a and 127b have an annular shape.

[0088] Furthermore, in some embodiments, the top electrode 123 is disposed between the inner insulating portion 127a and the outer insulating portion 127b. In some embodiments, the interior 129a of the second bottom electrode layer 129 is surrounded by and in direct contact with the inner insulating portion 127a. In some embodiments, the outer insulating portion 127b is surrounded by and in direct contact with the exterior 129b of the second bottom electrode layer 129.

[0089] In some embodiments, the first bottom electrode layer 117 and the second bottom electrode layer 129 comprise different materials. For example, according to some embodiments, the first bottom electrode layer 117 comprises titanium nitride (TiN), and the second bottom electrode layer 129 comprises polycrystalline silicon, silicon germanium (SiGe), or a combination thereof. Furthermore, in some embodiments, the insulating layer 119 comprises a first insulating material, and the insulating portions 127a and 127b comprise a second insulating material, and the first insulating material is different from the second insulating material.

[0090] In some embodiments, a first bottom electrode layer 117 extends over a top surface TS1 of a second bottom electrode layer 129. In some embodiments, an insulating layer 119 extends over the top surface TS1 of the second bottom electrode layer 129, and the portion of the first bottom electrode layer 117 extending over the top surface TS1 of the second bottom electrode layer 129 is covered by the insulating layer 119. In some embodiments, the first bottom electrode layer 117 directly contacts the top surface TS1 of the second bottom electrode layer 129 and the top surfaces TS2 and TS3 of the insulating portions 127a and 127b.

[0091] In some embodiments, the top electrode 123 has an inner sidewall SW1 (i.e., an inner periphery or inner edge) and an outer sidewall SW2 (i.e., an outer periphery or outer edge), and an insulating layer 119 is disposed along (or covering) the inner sidewall SW1, the outer sidewall SW2, and the bottom surface BS1 of the top electrode 123. In some embodiments, the first bottom electrode layer 117 and the second bottom electrode layer 129 are in direct contact with the dielectric layer. In some embodiments, the inner insulating portion 127a and the outer insulating portion 127b are in direct contact with the dielectric layer 105.

[0092] In some embodiments, the semiconductor element 100 is part of a dynamic random access memory (DRAM), and the top electrode 123, insulating layer 119, bottom electrode structure 129, and insulating portions 127a and 127b form a capacitor in the DRAM. In some embodiments, the capacitor is a metal-insulator-metal (MIM) capacitor. In some embodiments, the capacitor is electrically connected to conductive contacts 103a and 103b disposed in the semiconductor substrate 101.

[0093] Because the first bottom electrode layer 117 and the second bottom electrode layer 129 of the bottom electrode structure 131 are laterally separated by insulating portions 127a and 127b, the surface area of ​​the electrode plate is increased, and effective capacitance can be obtained. As a result, the overall component performance can be improved.

[0094] Figure 3 A flowchart of a method 10 for fabricating a semiconductor device (e.g., semiconductor device 100) is shown according to some embodiments, and method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, and S27. The following figures illustrate... Figure 3 Steps S11 to S27 will be explained in detail.

[0095] According to some embodiments, Figure 4-6 , Figure 8-10 , Figure 12-15 , Figure 17 and Figures 19-20 A cross-sectional view showing an intermediate stage in the formation of semiconductor element 100. Figure 7 yes Figure 8 The top view, and Figure 8 It is along Figure 7 The cross-sectional view drawn by line B-B' in the diagram. Figure 11 , Figure 16 , Figure 18 and Figure 21 Along respectively Figure 10 , Figure 15 , Figure 17 and Figure 20 The cross-sectional view drawn by line A-A' in the diagram. For example... Figure 4 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer.

[0096] Optionally or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0097] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SIO) substrate, which may include a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SIO substrate can be fabricated using separation by implantation oxygen (SIMOX), wafer bonding, and / or another suitable method. Furthermore, in some embodiments, multiple source / drain regions (not shown) are formed in the semiconductor substrate 101.

[0098] like Figure 4 As shown, according to some embodiments, a plurality of conductive contacts 103a and 103b are formed in the semiconductor substrate 101. In some embodiments, the conductive contacts 103a and 103b include copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), combinations thereof, or another suitable conductive material. In some embodiments, the fabrication techniques for the conductive contacts 103a and 103b include etching processes, deposition processes, and planarization processes.

[0099] For example, the fabrication techniques for conductive contacts 103a and 103b may include etching the semiconductor substrate 101 to form a plurality of openings (not shown), depositing a conductive material (not shown) in the openings and on the top surface of the semiconductor substrate 101, and performing a planarization process on the conductive material to remove excess portions of the conductive material on the top surface of the semiconductor substrate 101. The etching process may include a wet etching process, a dry etching process, or a combination thereof. The deposition process may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating process, or another suitable method. The planarization process may include chemical mechanical polishing (CMP).

[0100] Next, as Figure 5 As shown, according to some embodiments, a dielectric layer 105 is formed on a semiconductor substrate 101, and the dielectric layer 105 covers conductive contacts 103a and 103b. The corresponding steps are as follows: Figure 3 Step S11 is shown in method 10. In some embodiments, the dielectric layer 105 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or another suitable dielectric material. In some embodiments, the dielectric layer 105 is fabricated using a deposition process, such as CVD, PVD, ALD, spin coating, or another suitable method.

[0101] Subsequently, as Figure 6 As shown, according to some embodiments, an energy-removable layer 107 is formed on the dielectric layer 105. The corresponding steps are as follows: Figure 3 The method 10 shown is step S13. In some embodiments, the energy-removable layer 107 comprises a crosslinked compound having crosslinking functional groups. In some embodiments, the crosslinking functional groups comprise double bonds. In some embodiments, the crosslinked compound has hydrogen-bonded groups, polymerizable diacetylene groups, or combinations thereof. In some embodiments, the fabrication technique of the energy-removable layer 107 includes deposition processes, such as CVD, PVD, ALD, spin coating, or combinations thereof.

[0102] Then, as Figure 7 and Figure 8 As shown, according to some embodiments, a patterned hard mask 109 with an annular opening 112 is formed on an energy-removable layer 107. In some embodiments, the fabrication techniques of the patterned hard mask 109 include deposition processes, such as CVD, PVD, ALD, spin coating, or combinations thereof. In some embodiments, the patterned hard mask 109 and the energy-removable layer 107 comprise different materials, allowing for different etch selectivity in subsequent etch processes.

[0103] Next, as Figure 9 As shown, according to some embodiments, a patterned hard mask 109 is used as a mask to perform an etching process on the energy-removable layer 107 to form an annular opening 114 in the energy-removable layer 107. In some embodiments, the annular opening 114 extends through the energy-removable layer 107, such that the annular opening 114 partially exposes the dielectric layer 105. The corresponding steps are described in... Figure 3 Step S15 is shown in method 10. The etching process can be a wet etching process, a dry etching process, or a combination thereof.

[0104] like Figure 10 and Figure 11 As shown, according to some embodiments, the patterned hard mask 109 can be removed after the annular opening 114 is formed. In some embodiments, the patterned hard mask 109 is removed by a stripping process, an ashing process, an etching process, or another suitable process.

[0105] Subsequently, as Figure 12 As shown, according to some embodiments, a first bottom electrode layer 117 is conformally deposited on Figure 10 The structure is above. In some embodiments, a first bottom electrode layer 117 is formed as a liner within the annular opening 114 and located above the top surface TS4 of the energy-removable layer 107. In some embodiments, the first bottom electrode layer 117 is formed along the inner sidewall SW3, bottom surface BS2, and outer sidewall SW4 of the annular opening 114. The corresponding steps are in Figure 3 This is shown as step S17 in method 10.

[0106] In some embodiments, the first bottom electrode layer 117 comprises titanium nitride (TiN). In some embodiments, the fabrication techniques for the first bottom electrode layer 117 include deposition processes, such as CVD, PVD, ALD, sputtering, another suitable method, or a combination thereof.

[0107] Then, as Figure 13 As shown, according to some embodiments, the insulating layer 119 is conformally deposited on... Figure 12 The structure is above. In some embodiments, the insulating layer 119 covers the first bottom electrode layer 117. The corresponding steps are as follows: Figure 3 The method shown in the diagram is step S19.

[0108] In some embodiments, the insulating layer 119 comprises a dielectric material, such as silicon dioxide (SiO2), hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), or a combination thereof. In some embodiments, the fabrication technique of the insulating layer 119 includes a deposition process, such as CVD, PVD, ALD, spin coating, another suitable method, or a combination thereof. After the insulating layer 119 is formed, a portion of the annular opening 114 remains unfilled.

[0109] Next, as Figure 14As shown, according to some embodiments, a top electrode material 121 is deposited on the insulating layer 119. In some embodiments, the remaining portion of the annular opening 114 is filled with the top electrode material 121, and a portion of the top electrode material 121 extends over the top surface TS4 of the energy-removable layer 107. In some embodiments, the top electrode material 121 comprises titanium nitride (TiN), silicon germanium (SiGe), or a combination thereof. In some embodiments, the fabrication technique of the top electrode material 121 includes deposition processes such as CVD, PVD, ALD, sputtering, another suitable method, or a combination thereof.

[0110] Subsequently, as Figure 15 and Figure 16 As shown, according to some embodiments, a planarization process is performed on the top electrode material 121 to remove excess portions of the top electrode material 121 located above the top surface TS4 of the energy-removable layer 107. In some embodiments, the planarization process is performed until the insulating layer 119 is exposed. The planarization process may include a CMP process.

[0111] After the planarization process, a top electrode 123 is obtained. Since the remaining portion of the annular opening 114 is filled by the top electrode 123, the top electrode 123 has an annular shape when viewed from the top view. The corresponding steps are as follows: Figure 3 The method shown in the diagram is step S21.

[0112] Then, as Figure 17 and Figure 18 As shown, according to some embodiments, the energy-removable layer 107 is removed. The corresponding steps are as follows: Figure 3 Step S23 is shown in method 10. In some embodiments, the energy-removable layer 107 is removed by a heat treatment process. In some embodiments, the temperature used in the heat treatment process may be high enough to effectively burn off the energy-removable layer 107.

[0113] In some embodiments, after the energy-removable layer 107 is removed, the top electrode 123, the insulating layer 119, and the first bottom electrode layer 117 together form a columnar structure, and the structural strength of the columnar structure is high enough to prevent structural collapse. As a result, the yield of semiconductor devices can be increased.

[0114] Next, as Figure 19 As shown, according to some embodiments, an insulating material 125 is conformally formed as a wrapping. Figure 17The surface of the structure. In some embodiments, insulating material 125 covers the exposed surfaces of dielectric layer 105, first bottom electrode layer 117, insulating layer 119, and top electrode 123. In some embodiments, insulating material 125 covers the top surface TS5 of dielectric layer 105, sidewalls SW5 and SW6 of first bottom electrode layer 117, and top surface TS6 of top electrode 123.

[0115] In some embodiments, the insulating material 125 includes a dielectric material, such as silicon dioxide (SiO2), hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), or a combination thereof. In some embodiments, the insulating material 125 and the insulating layer 119 include different materials, such that the etching selectivity can differ in subsequent etching processes.

[0116] Subsequently, as Figure 20 and Figure 21 As shown, according to some embodiments, an etch-back process is performed on the insulating material 125, such that multiple insulating portions 127a and 127b remain on the sidewalls SW5 and SW6 of the first bottom electrode layer 117. The corresponding steps are described in... Figure 3 The method 10 shown is step S25. In some embodiments, the inner insulating portion 127a remains on and in direct contact with the sidewall SW5 of the first bottom electrode layer 117, and the outer insulating portion 127b remains on and in direct contact with the sidewall SW6 of the first bottom electrode layer 117. The etching process may include a wet etching process, a dry etching process, or a combination thereof.

[0117] like Figure 1 and Figure 2 As shown, according to some embodiments, after forming insulating portions 127a and 127b, a second bottom electrode layer 129 is formed, which surrounds the first bottom electrode layer 117 and covers the insulating portions 127a and 127b. The corresponding steps are as follows: Figure 3 The method 10 shown is step S27. In some embodiments, the second bottom electrode layer 129 includes an inner 129a and an outer 129b.

[0118] In some embodiments, the second bottom electrode layer 129 comprises silicon germanium (SiGe). In some embodiments, the fabrication technology of the second bottom electrode layer 129 includes deposition processes such as CVD, PVD, ALD, sputtering, another suitable method, or a combination thereof. In some embodiments, the interior 129a of the second bottom electrode layer 129 is surrounded by and in direct contact with an inner insulating portion 127a, and the outer insulating portion 127b is surrounded by and in direct contact with the exterior 129b of the second bottom electrode layer 129.

[0119] In some embodiments, a second bottom electrode layer 129 is disposed between the dielectric layer 105 and the first bottom electrode layer 117. In some embodiments, the first bottom electrode layer 117 and the second bottom electrode layer 129 together form a bottom electrode structure 131. After forming the second bottom electrode layer 129, a semiconductor device 100 is obtained.

[0120] In some embodiments, the first bottom electrode layer 117 and the second bottom electrode layer 129 are laterally separated by an inner insulating portion 127a and an outer insulating portion 127b, thereby increasing the surface area of ​​the electrode plate and thus achieving effective capacitance. As a result, overall device performance can be improved, and the yield of semiconductor devices can be increased.

[0121] This invention provides an embodiment of a semiconductor device and a method for fabricating the same. In some embodiments, the semiconductor device includes a bottom electrode structure (e.g., bottom electrode structure 131), a top electrode (e.g., top electrode 123) disposed on the bottom electrode structure, and an insulating layer (e.g., insulating layer 119) separating the top electrode from the bottom electrode structure. In some embodiments, the bottom electrode structure includes a first bottom electrode layer (e.g., first bottom electrode layer 117) and a second bottom electrode layer (e.g., second bottom electrode layer 129) surrounding the first bottom electrode layer. The top electrode has an annular shape and is surrounded by the first bottom electrode layer.

[0122] Before the second bottom electrode layer is formed, the top electrode, the insulating layer, and the first bottom electrode layer together form a columnar structure (e.g., Figure 17 The structure shown above dielectric layer 105 is used to enhance structural strength, making the structure less likely to collapse. Furthermore, the first and second bottom electrode layers are laterally separated by multiple insulating portions (e.g., inner insulating portion 127a and outer insulating portion 127b), thereby increasing the surface area of ​​the electrode plates and thus achieving effective capacitance. As a result, overall device performance can be improved, and the yield of semiconductor devices can be increased.

[0123] In one embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a bottom electrode structure disposed on a semiconductor substrate. The bottom electrode structure includes a first bottom electrode layer and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor device also includes a plurality of insulating portions laterally separating the first bottom electrode layer and the second bottom electrode layer. The semiconductor device further includes a top electrode disposed on and surrounded by the bottom electrode structure. From a top view, the top electrode has an annular shape. Furthermore, the semiconductor device includes an insulating layer that separates the top electrode from the bottom electrode structure.

[0124] In another embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a top electrode disposed on a semiconductor substrate. From a top view, the top electrode has an annular shape. The semiconductor device also includes an insulating layer disposed along an inner sidewall, a bottom surface, and an outer sidewall of the top electrode, and a bottom electrode structure surrounding the insulating layer. The bottom electrode structure includes a first bottom electrode layer in direct contact with the insulating layer, and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor device further includes a plurality of insulating portions disposed between the first bottom electrode layer and the second bottom electrode layer.

[0125] In another embodiment of this disclosure, a method for fabricating a semiconductor device is provided. The method includes forming a dielectric layer on a semiconductor substrate and forming an energy-removable layer on the dielectric layer. The method also includes etching the energy-removable layer to form an annular opening exposing the dielectric layer, and depositing a first bottom electrode layer along an inner sidewall, a bottom surface, and an outer sidewall of the annular opening. The method further includes depositing an insulating layer on the first bottom electrode layer and forming a top electrode in a remaining portion of the annular opening. Additionally, the method includes removing the energy-removable layer after forming the top electrode.

[0126] The embodiments of this disclosure have several advantageous features. In some embodiments, the semiconductor device includes a ring-shaped top electrode. Because the top electrode, insulating layer, and first bottom electrode layer together form a columnar structure before the second bottom electrode layer is formed, the increased structural strength makes the structure less prone to collapse. As a result, overall device performance can be improved, and the yield of the semiconductor device can be increased.

[0127] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by combinations of other processes.

[0128] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A bottom electrode structure is disposed on a semiconductor substrate, wherein the bottom electrode structure includes: A first bottom electrode layer; and A second bottom electrode layer surrounds the first bottom electrode layer; Multiple insulating portions laterally separate the first bottom electrode layer and the second bottom electrode layer; A top electrode is disposed on top of and surrounded by the bottom electrode structure, wherein, from a top view, the top electrode has a ring shape; An insulating layer separates the top electrode from the bottom electrode structure; and A dielectric layer is disposed between the bottom electrode structure and the semiconductor substrate, wherein the first bottom electrode layer and the second bottom electrode layer are in direct contact with the dielectric layer.

2. The semiconductor device of claim 1, wherein the first bottom electrode layer and the second bottom electrode layer comprise different materials.

3. The semiconductor device of claim 1, wherein the first bottom electrode layer extends over a top surface of the second bottom electrode layer.

4. The semiconductor device of claim 1, wherein the insulating layer extends over a top surface of the second bottom electrode layer.

5. The semiconductor element of claim 1, wherein the insulating portions include an inner insulating portion and an outer insulating portion spaced apart from the inner insulating portion, and the top electrode is disposed between the inner insulating portion and the outer insulating portion.

6. The semiconductor element of claim 5, wherein the inner insulating portion and the outer insulating portion are annular.

7. A semiconductor element, comprising: A top electrode is disposed on a semiconductor substrate, wherein, from a top view, the top electrode has a ring shape; An insulating layer is provided along an inner sidewall, a bottom surface, and an outer sidewall of the top electrode; A bottom electrode structure surrounding the insulating layer, wherein the bottom electrode structure includes: A first bottom electrode layer directly contacts the insulating layer; A second bottom electrode layer surrounds the first bottom electrode layer; Multiple insulating portions are disposed between the first bottom electrode layer and the second bottom electrode layer; and A dielectric layer is disposed between the bottom electrode structure and the semiconductor substrate, wherein the first bottom electrode layer, the second bottom electrode layer and the insulating portions are in direct contact with the dielectric layer.

8. The semiconductor device of claim 7, wherein the first bottom electrode layer extends between the insulating layer and the semiconductor substrate.

9. The semiconductor device of claim 7, wherein the first bottom electrode layer comprises titanium nitride (TiN), and the second bottom electrode layer comprises polycrystalline silicon, silicon germanium (SiGe), or a combination thereof.

10. The semiconductor device of claim 7, wherein the first bottom electrode layer extends over and is in direct contact with a top surface of the second bottom electrode layer and the top surfaces of the insulating portions.

11. The semiconductor device of claim 7, wherein the insulating layer comprises a first insulating material, and the insulating portions comprise a second insulating material, and The first insulating material is different from the second insulating material.

12. A method for fabricating a semiconductor device, comprising: A dielectric layer is formed on a semiconductor substrate; An energy-removable layer is formed on the dielectric layer; The energy-removable layer is etched to form an annular opening that exposes the dielectric layer; A first bottom electrode layer is deposited along an inner sidewall, a bottom surface, and an outer sidewall of the annular opening; An insulating layer is deposited on the first bottom electrode layer; A top electrode is formed in the remaining portion of the annular opening; After the top electrode is formed, the energy-removable layer is removed. After the energy-removable layer is removed, an insulating material is deposited to cover a top surface of the dielectric layer, the sidewalls of the first bottom electrode layer, and a top surface of the top electrode. An etching process is performed on the insulating material to leave an inner insulating portion and an outer insulating portion on the sidewall of the first bottom electrode layer; as well as After the inner insulating portion and the outer insulating portion are formed, a second bottom electrode layer is deposited between the first bottom electrode layer and the dielectric layer. The first bottom electrode layer and the second bottom electrode layer are in direct contact with the dielectric layer.

13. The method of fabricating a semiconductor device as claimed in claim 12, wherein the first bottom electrode layer extends over a top surface of the energy-removable layer.

14. The method of fabricating a semiconductor element as claimed in claim 12, wherein the insulating layer extends over a top surface of the energy-removable layer.

15. The method for fabricating a semiconductor device as claimed in claim 12, wherein forming the top electrode comprises: A top electrode material is deposited on the insulating layer; as well as A planarization process is performed on the top electrode material to expose a portion of the insulating layer located above a top surface of the energy-removable layer.

16. The method for fabricating a semiconductor element as claimed in claim 12, wherein the inner insulating portion and the outer insulating portion are annular, and the top electrode is located between the inner insulating portion and the outer insulating portion.

17. The method of fabricating a semiconductor element as claimed in claim 12, wherein the second bottom electrode layer comprises an interior surrounded by the inner insulating portion and an exterior surrounding the outer insulating portion.

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