A preparation method of a memory chip and the memory chip

Abstract

The application discloses a preparation method of a storage chip and the storage chip and is applied to the technical field of storage chips, and the bottom electrode material is arranged on the array area and the logic area on the surface of the bottom circuit layer at the same time, the bottom electrode is etched, and the storage unit and the logic via hole are all on the surface of the bottom electrode. The height difference between the logic area and the array area can be effectively reduced through the bottom electrode, the height of the logic via hole is reduced, the requirement for the interconnection metal filling is reduced, the filling effect is better, and the product reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of memory chip technology, and in particular to a method for fabricating a memory chip and a memory chip itself. Background Technology

[0002] For memory chips, their internal structure can typically be divided into a memory array area for implementing storage functions and a logic area for implementing logic functions and other functions. For some memory chips, the array area structure is characterized by placing / fabricating storage functional structures between two metal layers, such as MRAM (Magnetoresistive Random Access Memory) and RRAM (Resistive Random Access Memory).

[0003] For this type of memory chip, due to the existence of the memory function structure and the interconnection structure, the top via of the logic area is generally quite deep. Due to the limitations of the metal filling process for the top via, it is not only difficult to reduce the size of the logic area interconnection, but also limits the possibility of increasing the height of the bottom contact structure.

[0004] On the other hand, the presence of the storage functional structure and the interconnected structure inevitably leads to a significant difference in the depth of the top vias between the array area and the logic area. If the top vias of the array area and the logic area are fabricated on the same photomask, it means that the top via etching step will be performed simultaneously in both areas, resulting in a large load effect, increasing the difficulty of process control, affecting process stability, and even impacting chip yield. Therefore, how to provide a method that can effectively reduce the height difference between the logic area and the array area and reduce the filling requirements of the logic vias is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating a memory chip that can effectively reduce the height difference between the logic region and the array region, and reduce the filling requirements of logic vias; another purpose of this invention is to provide a memory chip that can effectively reduce the height difference between the logic region and the array region, and reduce the filling requirements of logic vias.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a memory chip, comprising:

[0007] Bottom electrode material is provided in both the array region and the logic region on the surface of the bottom circuit layer to form bottom electrodes that are in contact with the bottom circuit in the bottom circuit layer;

[0008] A storage unit is disposed on the bottom electrode surface located in the array region;

[0009] A top electrode is disposed on the surface of the memory cell, and the array area and the logic area are etched to form a separate memory cell;

[0010] A top circuit trace electrically connected to the discrete memory cell is provided in the array area, and a logic via is provided in the logic area to contact the bottom electrode.

[0011] Optionally, the bottom electrode material is disposed on both the array region and the logic region on the surface of the bottom circuit layer to form a bottom electrode that contacts the bottom circuit in the bottom circuit layer, including:

[0012] Bottom electrode material is provided in both the array region and the logic region on the surface of the bottom circuit layer;

[0013] The bottom electrode material is etched to form a protrusion corresponding to the bottom circuit on the surface of the bottom electrode material, thereby forming the bottom electrode; the depth of etching the bottom electrode material is less than the thickness of the bottom electrode material.

[0014] Optionally, the size of the protrusion in the logic area is larger than the size of the bottom circuit in the logic area.

[0015] Optionally, the provision of bottom electrode material in both the array region and the logic region on the surface of the bottom circuit layer includes:

[0016] A single layer of bottom electrode material is provided in both the array region and the logic region on the surface of the bottom circuit layer;

[0017] The etching of the bottom electrode material to form a protrusion corresponding to the bottom circuit on the surface of the bottom electrode material, forming the bottom electrode includes:

[0018] Using time as a control condition, the monolayer bottom electrode material is etched to form a protrusion corresponding to the bottom circuit on the surface of the monolayer bottom electrode material, thereby forming the bottom electrode.

[0019] Optionally, the provision of bottom electrode material in both the array region and the logic region on the surface of the bottom circuit layer includes:

[0020] Composite bottom electrode materials are provided in both the array region and the logic region on the surface of the bottom circuit layer; the composite bottom electrode materials include a first electrode material in contact with the bottom circuit, a first electrode material etching barrier layer located on the first electrode material facing away from the bottom circuit, and a second electrode material located on the first electrode material etching barrier layer facing away from the bottom circuit; the first electrode material and the second electrode material can be the same material or different materials.

[0021] The etching of the bottom electrode material to form a protrusion corresponding to the bottom circuit on the surface of the bottom electrode material, forming the bottom electrode includes:

[0022] Using the detection of the etching endpoint signal as a control condition, the composite bottom electrode material is etched to form a protrusion corresponding to the bottom circuit on the surface of the composite bottom electrode material, thereby forming the bottom electrode.

[0023] Optionally, the step of setting the storage unit on the bottom electrode surface located in the array region includes:

[0024] A storage unit material is disposed on the surface of the bottom electrode;

[0025] The memory cell material is etched to form a memory cell on the bottom electrode surface located in the array region.

[0026] Optionally, etching the memory cell material to form a memory cell on the bottom electrode surface located in the array region includes:

[0027] The memory cell material is etched using reactive ion etching, ion beam etching, or a combination of both, to form a memory cell on the bottom electrode surface of the array region.

[0028] Optionally, after etching the memory cell material to form memory cells on the bottom electrode surface located in the array region, the method further includes:

[0029] A protective layer is provided to cover the storage unit.

[0030] Optionally, the size of the top electrode is larger than the size of the corresponding bottom circuit.

[0031] The present invention also provides a memory chip, comprising a memory chip prepared by the method for preparing a memory chip as described in any of the preceding claims.

[0032] The present invention provides a method for fabricating a memory chip, comprising: setting bottom electrode material in both the array region and the logic region on the surface of the bottom circuit layer to form a bottom electrode in contact with the bottom circuit in the bottom circuit layer; setting memory cells on the surface of the bottom electrode located in the array region; setting top electrodes on the surface of the memory cells, and etching the array region and the logic region to form discrete memory cells; setting top circuit traces electrically connected to the discrete memory cells in the array region, and setting logic vias in the logic region in contact with the bottom electrodes.

[0033] By simultaneously setting bottom electrode material on the array area and logic area on the surface of the bottom circuit layer, and etching out the bottom electrode, the memory cells and logic vias fall on the surface of the bottom electrode. This bottom electrode can effectively reduce the height difference between the logic area and the array area, and at the same time reduce the height of the logic vias, thereby reducing the requirements for interconnect metal filling, resulting in better filling effect and increased product reliability.

[0034] The present invention also provides a memory chip, which has the same beneficial effects as described above, and will not be described in detail here. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of a memory chip in the prior art;

[0037] Figures 2 to 6 This is a process flow diagram of a method for fabricating a memory chip according to an embodiment of the present invention;

[0038] Figures 7 to 14 This is a process flow diagram of a specific memory chip fabrication method provided in an embodiment of the present invention.

[0039] In the diagram: 1. Bottom circuit layer, 2. Bottom electrode, 21. Bottom electrode material, 3. Memory cell, 31. Memory cell material, 4. Top electrode, 5. Top circuit trace, 6. Logic via, 7. Protective layer. Detailed Implementation

[0040] The core of this invention is to provide a method for fabricating a memory chip. See also... Figure 1 , Figure 1This is a schematic diagram of the structure of a memory chip in the prior art. For memory chips in the prior art, the array region typically contains bottom vias (BV), bottom contact structures (BC), memory functional structures (SS), top contact structures (TC), and top vias (TV) between the bottom metal layer Mx-1 and the top metal layer Mx. Correspondingly, the logic region only has top vias (TV) between the bottom metal layer Mx-1 and the top metal layer Mx. Due to the presence of the memory functional structure (SS) and the interconnecting structures (BV, BC, TC), the logic region (TV) is generally quite deep. Limited by the TV metal filling process capabilities, not only is it difficult to reduce the interconnect size of the logic region, but it also limits the possibility of increasing the height of BC. Furthermore, the presence of the memory functional structure (SS) and the interconnecting structures (BV, BC, TC) inevitably leads to a significant difference in the depth of TV between the array region and the logic region. If a photomask process is used to fabricate both the array region (TV) and the logic region (TV), it means that the TV etching step will be performed simultaneously in both the array region and the logic region, resulting in a large load effect, increasing the difficulty of process control, affecting process stability, and even impacting chip yield.

[0041] The present invention provides a method for fabricating a memory chip, comprising: setting bottom electrode material in both the array region and the logic region on the surface of the bottom circuit layer to form a bottom electrode in contact with the bottom circuit in the bottom circuit layer; setting memory cells on the surface of the bottom electrode in the array region; setting top electrodes on the surface of the memory cells and etching the array region and the logic region to form discrete memory cells; setting top circuit traces in the array region that are electrically connected to the discrete memory cells; and setting logic vias in the logic region that are in contact with the bottom electrodes.

[0042] By simultaneously setting bottom electrode material on the array area and logic area on the surface of the bottom circuit layer, and etching out the bottom electrode, the memory cells and logic vias fall on the surface of the bottom electrode. This bottom electrode can effectively reduce the height difference between the logic area and the array area, and at the same time reduce the height of the logic vias, thereby reducing the requirements for interconnect metal filling, resulting in better filling effect and increased product reliability.

[0043] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Please refer to Figures 2 to 6 , Figures 2 to 6 This is a process flow diagram of a method for fabricating a memory chip according to an embodiment of the present invention.

[0045] See Figure 2 In this embodiment of the invention, the method for fabricating a memory chip includes:

[0046] S101: Bottom electrode material is provided in both the array area and the logic area on the surface of the bottom circuit layer to form a bottom electrode that contacts the bottom circuit in the bottom circuit layer.

[0047] See Figure 3 Before this step, a substrate with a bottom circuit layer 1 needs to be prepared. This bottom circuit layer 1 is the corresponding bottom circuit structure in the memory chip. The specific content of this bottom circuit can be set according to the actual situation and is not specifically limited here. Specifically, the bottom circuit layer 1 is divided into an array area and a logic area. In subsequent steps, memory cells 3 need to be set in the array area, and logic vias 6 need to be set in the logic area.

[0048] In this step, a bottom electrode material 21 of a certain thickness is first deposited on the surface of the bottom circuit layer 1, including both the array region and the logic region. Typically, the bottom electrode material 21 can be deposited on both the array region surface and the logic region surface simultaneously. This bottom electrode material 21 directly contacts the bottom circuit in the bottom circuit layer 1 to achieve electrical connection, forming a bottom electrode 2 in contact with the bottom circuit in the bottom circuit layer 1. In this step, the bottom electrode material 21 can typically be further etched to obtain the desired bottom electrode 2 morphology. The specific details will be described in detail in the following embodiments of the invention, and will not be repeated here. Typically, after this step, the heights of the logic region and the array region remain approximately equal.

[0049] It should be noted that after this step and subsequent steps, media backfilling is usually required, followed by surface smoothing processes such as chemical mechanical polishing (CMP) to facilitate the installation of subsequent structures. For details regarding the media used for backfilling and the specifics of CMP, please refer to existing technologies; they will not be elaborated upon here.

[0050] S102: A storage unit is disposed on the bottom electrode surface located in the array region.

[0051] See Figure 4 In this step, a storage unit 3 is separately disposed on the surface of the bottom electrode 2 of the array region. This storage unit 3 mainly performs the storage function in the memory chip. The storage unit 3 needs to be in contact with the upper surface of the corresponding bottom electrode 2 in the array region to achieve electrical connection. The specific structure of the storage unit 3 itself can be referred to the prior art, and will not be described in detail here. After this step and before the dielectric backfilling, there is a difference in height between the array region and the logic region, and their thickness is roughly equal to the thickness of the storage unit 3.

[0052] S103: A top electrode is set on the surface of the memory cell, and the array area and logic area are etched to form a separate memory cell.

[0053] See Figure 5 In this step, a top electrode 4 needs to be set on the surface of the memory cell 3. That is, only in the array region, a top electrode 4 is set on the surface of the memory cell 3 to contact the corresponding memory cell 3. Afterwards, the top electrode 4 usually needs to be etched to form a top electrode 4 that meets the preset morphology requirements. Simultaneously, while etching the top electrode 4, the structures in the array region and logic region will continue to be etched. At this time, it is necessary to ensure that the uncut portions of the bottom electrode 2 are cut off, so that the memory cells 3 are separated from each other and there is no short-circuit path. That is, this step requires specifically etching the array region and the logic region to form separate memory cells. It should be noted that in this step, it is not only necessary to achieve the mechanical separation of the memory cells 3 described in S102, but also to ensure that the memory cells 3 are separated from each other in the electrical structure to form separate memory cells. That is, it is necessary to etch off the interconnected bottom electrodes 2 to avoid short circuits between the memory cells 3.

[0054] After this step and before media backfilling, there is a difference in height between the array area and the logic area, and its thickness is roughly equal to the sum of the thickness of the memory cell 3 and the thickness of the top electrode 4.

[0055] S104: A top circuit trace electrically connected to the discrete memory cell is provided in the array area, and a logic via is provided in the logic area to contact the bottom electrode.

[0056] See Figure 6 In this step, top circuit traces 5, electrically connected to the individual memory cells 3, are typically provided on the upper surface of the top electrode 4, and logic vias 6, contacting the bottom electrode 2, are provided in the logic area, thus forming the top circuit of the entire memory chip. The specific structure of the top circuit traces 5 needs to be determined according to the actual situation, while the steps for setting the logic vias 6 can refer to existing technologies, typically requiring interconnect metal filling processes. It should be noted that, since the depth required for the logic vias 6 when setting the top circuit is only approximately equal to the sum of the thickness of the memory cell 3 and the thickness of the top electrode 4, its height difference is lower than in existing technologies. Therefore, the height of the logic vias 6 can be effectively reduced, thereby effectively reducing the requirements for interconnect metal filling, resulting in better filling and increased product reliability.

[0057] The present invention provides a method for fabricating a memory chip by first setting a bottom electrode material 21 on both the array region and the logic region on the surface of the bottom circuit layer 1, and etching out a bottom electrode 2. The memory cell 3 and the logic via 6 are both located on the surface of the bottom electrode 2. The bottom electrode 2 can effectively reduce the height difference between the logic region and the array region, and at the same time reduce the height of the logic via 6, thereby reducing the requirements for interconnect metal filling, resulting in better filling effect and increased product reliability.

[0058] The specific details of the method for fabricating a memory chip provided by this invention will be described in detail in the following embodiments.

[0059] Please refer to Figures 7 to 14 , Figures 7 to 14 This is a process flow diagram of a specific memory chip fabrication method provided in an embodiment of the present invention.

[0060] See Figure 7 In this embodiment of the invention, the method for fabricating a memory chip includes:

[0061] S201: Bottom electrode material is provided in both the array area and the logic area on the surface of the bottom circuit layer.

[0062] See Figure 8 In this step, a bottom electrode material 21 in contact with the bottom circuit is deposited on the upper surface of the bottom circuit layer 1. This bottom electrode material 21 can be a single material; specifically, this step can involve depositing a single layer of bottom electrode material 21 on both the array region and the logic region on the surface of the bottom circuit layer 1. Alternatively, the bottom electrode material 21 can be a composite bottom electrode material 21, which may include a three-layer structure from bottom to top: a first electrode material, a first electrode material etching barrier layer, and a second electrode material. Specifically, this step can involve depositing a composite bottom electrode material 21 on both the array region and the logic region on the surface of the bottom circuit layer 1. The composite bottom electrode material 21 includes a first electrode material in contact with the bottom circuit, a first electrode material etching barrier layer located opposite to the bottom circuit, and a second electrode material located opposite to the bottom circuit within the first electrode material etching barrier layer. The first electrode material and the second electrode material can be the same material or different materials. The etching barrier layer specifically corresponds to the first electrode material and is used to slow down the etching rate of the first electrode material.

[0063] Specifically, the bottom electrode material 21, including the first electrode material and the second electrode material, can be Ti, Ta, or their metal nitrides, and the etching barrier layer of the first electrode material can be Ru. Furthermore, to ensure the subsequent etching effect, a dielectric hard mask material can be deposited on the surface of the bottom electrode material 21, on the side facing away from the bottom circuit layer 1. The specific materials of the bottom electrode material 21, the first electrode material etching barrier layer, and the dielectric hard mask material can be set according to the actual situation and are not specifically limited here.

[0064] In this step, it is usually necessary to perform photolithographic patterning on the bottom electrode material, that is, to set a photoresist with a corresponding pattern distribution so that the bottom electrode 2 with the desired morphology can be etched in subsequent steps. For details on photolithographic patterning, please refer to the prior art, which will not be elaborated here.

[0065] S202: Etch the bottom electrode material to form a protrusion corresponding to the bottom circuit on the surface of the bottom electrode material, thus forming the bottom electrode.

[0066] See Figure 9 In this step, the etching depth of the bottom electrode material 21 is less than the thickness of the bottom electrode material 21. That is, in this step, a portion of the bottom electrode material 21 is pre-reduced, thereby reducing the etching time when the memory cells 3 are separated from each other, and ensuring the morphology of the memory cells 3 and related structures when the memory cells 3 are separated from each other. Specifically, in this step, the structure after photolithography patterning is etched. During the etching process, it is necessary to ensure that the etching depth of the bottom electrode material 21 is less than the thickness of the bottom electrode material 21, thereby forming a protrusion corresponding to the bottom circuit on the surface of the bottom electrode material 21, forming the bottom electrode 2. At this time, except for the above-mentioned protrusion structure, the entire bottom electrode material 21 is still connected as a whole, that is, the bottom electrode 2 structure is electrically connected. This structure can significantly reduce the plasma damage to the bottom transistor in subsequent processes, that is, reduce the plasma damage to the bottom circuit layer 1, including the bottom circuit, and reduce the plasma-induced damage (PID) effect.

[0067] Firstly, regarding the above etching process, when the bottom electrode material 21 is a single-layer bottom electrode material 21, this step can specifically include: using time as a control condition, etching the single-layer bottom electrode material 21 to form protrusions corresponding to the bottom circuit on the surface of the single-layer bottom electrode material 21, thus forming the bottom electrode 2. Because the single-layer bottom electrode material 21 cannot distinguish the etching endpoint signal, the etching specifically selected in this step is time-controlled etching, that is, the etching time is monitored in real time during etching, thereby ensuring etching accuracy.

[0068] When the bottom electrode material 21 is the aforementioned composite bottom electrode material 21, this step may specifically include: using the detection of the etching endpoint signal as a control condition, etching the composite bottom electrode material 21 to form a protrusion corresponding to the bottom circuit on the surface of the composite bottom electrode material 21, thus forming the bottom electrode 2. Because the composite bottom electrode material 21 has a first electrode material etching barrier layer, the etching signal changes. Therefore, the etching specifically selected in this step is etching endpoint control, that is, monitoring the etching endpoint signal in real time during etching to ensure etching accuracy. It should be noted that, regardless of whether it is time control or etching endpoint control, this etching step must ensure that the bottom electrode material 21 is not etched through.

[0069] Secondly, regarding the aforementioned protrusion structure, the size of the protrusion in the logic region typically needs to be larger than the size of the corresponding bottom circuit in the logic region. That is, in the logic region, the area corresponding to a circuit unit of the bottom circuit layer 1 needs to be smaller than the area of ​​its corresponding bottom electrode 2 protrusion in the logic region, so that the protrusion in the logic region can shield its corresponding bottom circuit layer 1 circuit unit. In this case, when the bottom electrode 2 is subsequently etched to form separate memory cells, there will be no risk of contamination due to copper exposure. Correspondingly, in this embodiment of the invention, the size of the protrusion in the array region is typically smaller than the size of the memory cell. This structure helps prevent etching backsplashing caused by bottom electrode exposure during subsequent memory cell etching, thus avoiding device performance degradation.

[0070] Following this step, the structure needs to be cleaned after removing the photoresist to facilitate subsequent structure fabrication. Specifically, the patterned structure in S202 also needs to be backfilled with dielectric material and subjected to chemical mechanical polishing to ensure that the top of the bottom electrode 2 is exposed for contact with the conductive agent of the subsequent memory cell 3, thereby achieving a good electrical connection.

[0071] S203: Set storage cell material on the surface of the bottom electrode.

[0072] See Figure 10 In this step, memory cell material 31 is typically deposited simultaneously on the surface of the bottom electrode 2 in both the array region and the logic region. Since the memory cell 3 is usually composed of a multi-layer structure, the memory cell material 31 is typically deposited sequentially on the surface of the bottom electrode 2 and then patterned using photolithography.

[0073] S204: Etching memory cell material to form memory cells on the bottom electrode surface located in the array region.

[0074] See Figure 11In this step, the photolithographic patterned structure in S203 can be etched based on the photolithography process. Usually, all the memory cell material 31 in the logic area is etched away to form the memory cell 3 located on the surface of the bottom electrode 2 of the array area.

[0075] Specifically, this step may include: etching the memory cell material 31 using reactive ion etching, ion beam etching, or a combination of both, to form the memory cell 3 on the surface of the bottom electrode 2 located in the array region. The specific details of each etching process can be found in existing technologies and will not be elaborated upon here.

[0076] Following this step, the process may further include: setting a protective layer 7 covering the storage cell 3. This protective layer 7 protects the storage cell 3 from water and oxygen corrosion. When setting the protective layer 7, it must at least cover the upper surface and sides of the storage cell 3. After subsequent dielectric backfilling and surface polishing, since the upper surface of the storage cell 3 needs to be exposed to contact the top electrode 4, the protective layer 7 must ultimately cover at least the sides of the storage cell 3. The protective layer 7 can be made of silicon nitride (SiN) or other insulating materials, depending on the specific circumstances, and is not specifically limited here.

[0077] See Figure 12 After setting up the storage unit 3, including the aforementioned protective layer 7, in this step, the patterned structure in S203 needs to be backfilled with media and subjected to chemical mechanical polishing to flatten its surface.

[0078] S205: A top electrode is provided on the surface of the memory cell, and the column area and logic area are etched to form a separate memory cell.

[0079] See Figure 13 Prior to this step, chemical mechanical polishing or overall etching is typically used to remove the dielectric and protective layer 7 covering the storage cell 3, so that it can form a conductive contact with the subsequently deposited top electrode material.

[0080] In this step, a top electrode material is first deposited on the surface of the exposed memory cell 3. Then, the top electrode material is patterned by photolithography. Afterward, a top electrode 4 is formed on the surface of the memory cell 3 by photolithography. Preferably, in this embodiment of the invention, the size of the etched top electrode 4 needs to be larger than the size of the corresponding bottom circuit. That is, the top electrode 4 needs to cover the corresponding circuit unit in the bottom circuit, so that when the bottom electrode 2 is subsequently etched open to form a separate memory cell, there will be no risk of contamination due to copper exposure.

[0081] In this step, after the top electrode material is patterned by photolithography, the top electrode material is first etched to form the top electrode 4, and then the etching continues downward until the interconnected bottom electrodes 2 are etched apart, ensuring that the uncut parts of the bottom electrodes 2 are cut off, so that the memory cells 3 are separated from each other, forming separate memory cells, so that there is no short circuit between the separate memory cells.

[0082] See Figure 14 Following this step, the etched patterned structure formed in S205 also needs to be backfilled with dielectric material and chemically and mechanically planarized to provide a filling area and a flat interface for the subsequent top circuit.

[0083] S206: A top circuit trace electrically connected to the discrete memory cell is provided in the array area, and a logic via is provided in the logic area to contact the bottom electrode.

[0084] This step is basically the same as S104 in the above-described embodiment of the invention. For details, please refer to the above-described embodiment of the invention, and it will not be repeated here. Before this step, the top electrode 4 needs to be exposed so that the top circuit trace 5 can be set on the surface of the top electrode 4.

[0085] The present invention provides a method for fabricating a memory chip by simultaneously depositing bottom electrode material 21 on both the array region and the logic region on the surface of the bottom circuit layer 1, and etching out the bottom electrode 2. The memory cell 3 and the logic via 6 both fall on the surface of the bottom electrode 2. This bottom electrode 2 effectively reduces the height difference between the logic region and the array region, and also reduces the height of the logic via 6, thereby reducing the requirements for interconnect metal filling, resulting in better filling performance and increased product reliability. Furthermore, because the bottom electrode structure is electrically connected during memory chip fabrication, it significantly reduces plasma damage to the bottom transistors caused by intermediate processes, i.e., the plasma-induced damage (PID) effect.

[0086] The present invention also provides a memory chip, specifically a memory chip fabricated using the memory chip fabrication method provided in any of the above embodiments. For details regarding the memory chip fabrication method, please refer to the above embodiments. Other structures of the memory chip can be found in the prior art and will not be described further here.

[0087] Because the memory chip provided in this embodiment of the invention has a bottom electrode 2, and the memory cell 3 and logic via 6 both fall on the surface of the bottom electrode 2, the bottom electrode 2 can effectively reduce the height difference between the logic region and the array region, and at the same time reduce the height of the logic via 6, thereby reducing the requirements for interconnect metal filling, resulting in better filling effect and increased product reliability. Furthermore, because the bottom electrode structure is electrically connected during memory chip fabrication, it can significantly reduce plasma damage to the bottom transistor caused by intermediate processes, i.e., the plasma-induced damage (PID) effect.

[0088] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0089] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0090] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0091] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0092] The foregoing has provided a detailed description of a method for fabricating a memory chip and a memory chip itself. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are merely illustrative of the method and its core concepts. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A method for fabricating a memory chip, characterized in that, include: Bottom electrode material is disposed in both the array region and the logic region on the surface of the bottom circuit layer to form bottom electrodes that are in contact with the bottom circuit in the bottom circuit layer; wherein, the bottom electrode material is etched to form protrusions corresponding to the bottom circuit on the surface of the bottom electrode material to form the bottom electrodes; the depth of etching the bottom electrode material is less than the thickness of the bottom electrode material; except for the protrusions, the bottom electrode material is connected as a whole, and the bottom electrodes are in an electrically connected state; A storage unit is disposed on the bottom electrode surface located in the array region; A top electrode is disposed on the surface of the memory cell, and the array area and the logic area are etched. The un-etched portion of the bottom electrode is etched off to form a separate memory cell. A top circuit trace electrically connected to the discrete memory cell is provided in the array area, and a logic via is provided in the logic area to contact the bottom electrode.

2. The method according to claim 1, characterized in that, The size of the protrusion in the logic area is larger than the size of the bottom circuit in the logic area.

3. The method according to claim 1, characterized in that, The bottom electrode material disposed in both the array region and the logic region on the surface of the bottom circuit layer includes: A single layer of bottom electrode material is provided in both the array region and the logic region on the surface of the bottom circuit layer; The etching of the bottom electrode material to form a protrusion corresponding to the bottom circuit on the surface of the bottom electrode material, forming the bottom electrode includes: Using time as a control condition, the monolayer bottom electrode material is etched to form a protrusion corresponding to the bottom circuit on the surface of the monolayer bottom electrode material, thereby forming the bottom electrode.

4. The method according to claim 1, characterized in that, The bottom electrode material disposed in both the array region and the logic region on the surface of the bottom circuit layer includes: Composite bottom electrode materials are provided in both the array region and the logic region on the surface of the bottom circuit layer; the composite bottom electrode material includes a first electrode material in contact with the bottom circuit, a first electrode material etching barrier layer located on the first electrode material facing away from the bottom circuit, and a second electrode material located on the first electrode material etching barrier layer facing away from the bottom circuit; The etching of the bottom electrode material to form a protrusion corresponding to the bottom circuit on the surface of the bottom electrode material, forming the bottom electrode includes: Using the detection of the etching endpoint signal as a control condition, the composite bottom electrode material is etched to form a protrusion corresponding to the bottom circuit on the surface of the composite bottom electrode material, thereby forming the bottom electrode.

5. The method according to claim 1, characterized in that, The step of setting a storage unit on the bottom electrode surface located in the array region includes: A storage unit material is disposed on the surface of the bottom electrode; The memory cell material is etched to form a memory cell on the bottom electrode surface located in the array region.

6. The method according to claim 5, characterized in that, The etching of the memory cell material to form a memory cell on the bottom electrode surface located in the array region includes: The memory cell material is etched using reactive ion etching, ion beam etching, or a combination of both, to form a memory cell on the bottom electrode surface of the array region.

7. The method according to claim 5, characterized in that, After etching the memory cell material to form memory cells on the bottom electrode surface located in the array region, the method further includes: A protective layer is provided to cover the storage unit.

8. The method according to claim 1, characterized in that, The size of the top electrode is larger than the size of the corresponding bottom circuit.

9. A memory chip, characterized in that, This includes memory chips manufactured by the method for manufacturing memory chips as described in any one of claims 1 to 8.

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