Semiconductor element and method for manufacturing the same

Abstract

A method for fabricating a semiconductor device is disclosed. A substrate is provided, which includes a logic region and a magnetoresistive random access memory (MRAM) region. A magnetic tunneling junction (MTJ) is formed on the MRAM region. A metal interconnect is formed on the MTJ. A dielectric layer is formed on the metal interconnect. The dielectric layer is patterned to form a plurality of openings. A barrier layer is formed on the patterned dielectric layer and the metal interconnect and fills the openings.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 202010235266.X, application date: March 30, 2020, invention title: semiconductor element and method of manufacturing thereof). Technical Field

[0002] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Background Technology

[0003] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0004] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, the existing technologies typically suffer from drawbacks including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0005] One embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a substrate is provided, the substrate including a logic region and a magnetoresistive random access memory (MRAM) region. Then, a magnetic tunneling junction (MTJ) is formed on the MRAM region, a metal interconnect is formed on the MTJ, a dielectric layer is formed on the metal interconnect, the dielectric layer is patterned to form a plurality of openings, and finally, a barrier layer is formed on the patterned dielectric layer and the metal interconnect to fill the openings.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes: a substrate containing a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunnel junction (MTJ) disposed on the MRAM region, a metal interconnect disposed on the MTJ, and a barrier layer disposed on the metal interconnect. Attached Figure Description

[0007] Figure 1 A top view of an MRAM cell for one embodiment of the present invention;

[0008] Figure 2 A top view of an MRAM cell for one embodiment of the present invention;

[0009] Figure 3 A top view of an MRAM cell for one embodiment of the present invention;

[0010] Figure 4 for Figure 2 and Figure 3 A cross-sectional view of a semiconductor device fabricated along tangent AA'.

[0011] Figure 5 for Figure 1 A cross-sectional view of a semiconductor device fabricated along tangent BB'.

[0012] Figure 6 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention.

[0013] Explanation of main component symbols

[0014] 12: Base

[0015] 14: MRAM region

[0016] 16: Logical Area

[0017] 18: Interlayer dielectric layer

[0018] 20: Contact plug

[0019] 22: Metal interconnect structure

[0020] 24: Intermetallic dielectric layer

[0021] 26: Metal interconnects

[0022] 28: Metal interconnect structure

[0023] 30: Intermetallic dielectric layer

[0024] 32: Metal interconnects

[0025] 34:MTJ

[0026] 36: Fixed layer

[0027] 38: Barrier Layer

[0028] 40: Free Layer

[0029] 42: Lower electrode

[0030] 44: Upper electrode

[0031] 46: Intermetallic dielectric layer

[0032] 48: Metal interconnects

[0033] 50: Stop Layer

[0034] 52: Intermetallic dielectric layer

[0035] 54: Metal interconnects

[0036] 56: Stop Layer

[0037] 58: Material layer

[0038] 60: Barrier layer

[0039] 62: Contact pad

[0040] 64: Dielectric layer

[0041] 66: Dielectric layer

[0042] 68: Dielectric layer

[0043] 70: Opening Detailed Implementation

[0044] Please refer to Figures 1 to 5 , Figures 1 to 3 A top view of a semiconductor element, or more specifically, an MRAM cell, fabricated according to different embodiments of the present invention. Figure 4 for Figure 2 and Figure 3 A cross-sectional view of a semiconductor device is shown along tangent AA'. Figure 5 Then it is Figure 1A cross-sectional view of a semiconductor device is shown along the tangent line BB'. (See diagram below.) Figures 1 to 5 As shown, a substrate 12 is first provided, for example, a substrate 12 made of semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0045] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs 20 electrically connecting the gate structure and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layer 18 are well known in the art, they will not be described in detail here.

[0046] Then, metal interconnect structures 22 and 28 are sequentially formed on the interlayer dielectric layer 18 of the MRAM region 14 and the logic region 16 to electrically connect the aforementioned contact plug 26. The metal interconnect structure 22 includes a stop layer (not shown) disposed on the interlayer dielectric layer 18, an intermetallic dielectric layer 24 and metal interconnects 26 embedded in the intermetallic dielectric layer 24. The metal interconnect structure 28 includes a stop layer (not shown), an intermetallic dielectric layer 30 and a plurality of metal interconnects 32 embedded in the stop layer and the intermetallic dielectric layer 30.

[0047] In this embodiment, each metal interconnect 26 in the metal interconnect structure 22 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 28 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 22 and 28 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. In addition, in this example, the metal interconnect 26 preferably contains copper, the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide, and the stop layer contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited to these.

[0048] Next, an MTJ stack structure (not shown) is formed on the metal interconnect structure 28. Then, one or more etching processes are performed to remove part of the MTJ stack structure to form multiple MTJs, such as MTJ 34, in the MRAM region 14. It is worth noting that the etching process performed on the patterned MTJ stack structure in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the upper surface of the remaining intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface.

[0049] In this embodiment, each MTJ 34 preferably includes a fixed layer 36, a barrier layer 38, and a free layer 40, wherein each MTJ 34 has a lower electrode 42 below and an upper electrode 44 above. In this embodiment, the lower electrode 42 and the upper electrode 44 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or titanium nitride (TiN). The fixed layer 36 may be made of an antiferromagnetic (AFM) material, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 38 may be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The magnetization direction of the free layer 40 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these.

[0050] First, a masking layer (not shown) and an intermetallic dielectric layer 46 are sequentially formed on the MTJ 34, covering the surface of the intermetallic dielectric layer 30. Then, a planarization process is performed, for example, using chemical mechanical polishing (CMP) to remove part of the intermetallic dielectric layer 46, so that the remaining masking layer is approximately flush with the top of the upper electrode 44. Next, a photolithography and etching process is performed to remove part of the intermetallic dielectric layer 46 in the logic region 16, forming contact holes (not shown). Conductive material is then filled into each contact hole, and a planarization process is used to form metal interconnects 48 that electrically connect to the underlying metal interconnects 26. In this embodiment, the masking layer preferably comprises silicon nitride, but other dielectric materials can be selected according to the fabrication process requirements, such as silicon oxide, silicon oxynitride, or silicon carbide. The intermetallic dielectric layer 46 preferably comprises an ultra-low dielectric constant dielectric layer, which may comprise a porous dielectric material such as, but not limited to, silicon oxycarbide (SiOC).

[0051] Subsequently, a stop layer 50 and another intermetallic dielectric layer 52 are sequentially formed on the MTJ 34, covering the masking layer and the surface of the intermetallic dielectric layer 46. Then, one or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 52 and part of the stop layer 50 in the MRAM region 14 and logic region 16 to form contact holes (not shown). Then, a barrier layer and a metal layer are sequentially formed in each contact hole to fill the contact hole. The barrier layer may contain materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof, while the metal layer may contain low-resistivity materials such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Next, a planarization process is performed, for example, CMP is used to remove part of the metal layer and part of the barrier layer to form metal interconnect 54 connecting the upper electrode 44 in the MRAM region 14 and the metal interconnect 48 in the logic region 16.

[0052] Subsequently, another stop layer 56 is formed on the intermetallic dielectric layer 52 and covers the metal interconnects 54. Then, a portion of the stop layer 56 in the logic region 16 is removed using a photolithography and etching process to form an opening (not shown) exposing the underlying metal interconnects 54. A material layer 58 is formed on the stop layer 56 and fills the opening. Another photolithography and etching process is then performed to pattern the material layer 58, simultaneously forming patterned material layers 58 in both the MRAM region 14 and the logic region 16. Preferably, the material layer 58 in the MRAM region 14 serves as a barrier layer 60, while the material layer 58 in the logic region 16 serves as a contact pad 62. In this embodiment, the material layer 58 or the barrier layer 60 preferably comprises a conductive material or a metallic material, wherein if the barrier layer 60 is made of a metallic material, it preferably comprises aluminum. Since the barrier layer 60 of MRAM region 14 is separated from the metal interconnect 54 below by the stop layer 56, and the material layer 58 of logic region 16 is in direct contact with the metal interconnect 54 below, the barrier layer 60 of MRAM region 14 is preferably not electrically connected to the MTJ 34 directly below.

[0053] It should be noted that the barrier layer 60 disclosed in this invention, viewed from above, can have different shapes or forms covering the underlying MTJ 34 depending on the manufacturing process requirements. For example, it can be as follows: Figure 1 As shown, it completely covers MRAM region 14, as Figure 2 As shown, it is placed above MTJ in a line pattern, or as... Figure 3 The pattern shown is roughly chessboard-like or fence-like. Furthermore, the cross-sectional structure of the barrier layer 60 can be varied depending on the angle and direction of the sampled area. Figure 4 As shown, they are respectively positioned directly above each MTJ 34 or as... Figure 5As shown, multiple MTJ 34s overlap simultaneously, wherein the barrier layer 60 is preferably not electrically connected to the metal interconnect 54 directly below and / or the MTJ 34, and these variations are all within the scope of this invention.

[0054] Subsequently, multiple dielectric layers, such as dielectric layers 64, 66, and 68, are sequentially formed on the stop layer 56 of the MRAM region 14 and the logic region 16, and a barrier layer 60 is covered. A portion of the dielectric layers 66 and 68 in the logic region 16 is removed using photolithography and etching processes to form an opening 70. A selective high-voltage annealing process is then performed, using hydrogen gas at approximately 400 degrees Celsius to adjust the entire structure. Finally, wire bonding connections to external circuits are formed within the opening 70 as required by the process or product. In this embodiment, dielectric layer 64 may comprise materials such as silicon oxide, silicon nitride, silicon oxynitride, or an ultra-low dielectric constant dielectric layer; dielectric layer 66 preferably comprises silicon oxide; and dielectric layer 68 preferably comprises silicon nitride. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0055] Please continue to refer to Figure 6 , Figure 6 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 6 As shown, compared to the previous embodiment where a barrier layer 60 made of metal is formed in the MRAM region 14 to shield the MTJ 34 below, the present invention can optionally omit the step of forming a metal barrier layer 60 in the MRAM region 14 and instead use a barrier layer 60 made of dielectric material to shield the MTJ 34 below. For example, it can first be based on the aforementioned... Figure 4 The fabrication process involves forming a material layer 58 on the stop layer 56 after the stop layer 56 is formed. Then, a photolithography and etching process is performed to pattern the material layer 58, and the patterned material layer 58 is formed only in the logic region 16 as a contact pad 62, but no patterned material layer 58 is formed in the MRAM region 14. Then, dielectric layers 64, 66, and 68 are formed on the stop layer 56 of the MRAM region 14 and the logic region 16, covering the material layer 58 of the logic region 16. A photolithography and etching process is used to remove part of the dielectric layers 66 and 68 of the logic region 16 to form an opening 70. Another photolithography and etching process is performed to remove all the dielectric layers 68 of the logic region 16. Finally, the process or product requires wire bonding to connect to external circuits within the opening 70.

[0056] It should be noted that, compared to the previous embodiment where the top dielectric layer 68 was made of silicon nitride, in this embodiment, the barrier layer 60 or dielectric layer 68 is preferably made of a dielectric material capable of isolating hydrogen, such as, but not limited to, silicon carbide (SiC), silicon carbide nitride (SiCN), and / or silicon carbide oxide nitride (SiCON). Furthermore, compared to the previous embodiment where the top dielectric layer 68 was retained when the opening 70 was formed in the logic region 16, in this embodiment, all dielectric layers 68 in the logic region 16 can be removed using another photolithography and etching process after the opening 70 is formed in the logic region 16. All such variations are within the scope of this invention.

[0057] Generally, current MRAM cells typically undergo a high-pressure annealing process during the back-end-of-the-line (BEOL) fabrication, such as the fabrication of metal interconnects, to adjust the overall structure. The reactive gases, such as hydrogen, produced during this annealing process, can directly affect the magnetic properties of the metal interconnect (MTJ) below the metal interconnect without obstruction, potentially even causing component damage. To address this issue, this invention preferably places a barrier layer made of metal or dielectric material above the MTJ in the MRAM region to prevent hydrogen penetration. Preferably, the barrier layer does not directly contact the metal interconnect directly above the MTJ, and the barrier layer can be customized according to product requirements. Figure 1 The embodiment typically fully covers the MRAM region 14, such as Figure 2 As shown, lines are used to define the MRAM area, or as... Figure 3 The MRAM area is typically covered with a rough checkerboard or fence-like pattern.

[0058] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Include: The substrate includes a magnetoresistive random access memory region and a logic region. A magnetic tunnel junction is disposed on the region of the magnetoresistive random access memory. Metal interconnects are provided on the magnetic tunnel junction; A stop layer is provided on the internal interconnect of the metal; as well as A barrier layer is disposed on the stop layer, wherein the stop layer separates the metal interconnect and the barrier layer, and the barrier layer includes a linear pattern according to an upward viewing angle.

2. The semiconductor device of claim 1, further comprising: A first dielectric layer is disposed on the barrier layer; and The second dielectric layer is disposed on the first dielectric layer.

3. The semiconductor device of claim 2, wherein the first dielectric layer comprises silicon oxide.

4. The semiconductor device of claim 1, wherein the barrier layer comprises metal.

5. The semiconductor device of claim 4, wherein the barrier layer comprises aluminum.

6. The semiconductor device of claim 1, further comprising: A first dielectric layer is disposed on the metal interconnect; and The barrier layer is disposed on the first dielectric layer.

7. The semiconductor device of claim 6, wherein the first dielectric layer comprises silicon oxide.

8. The semiconductor device of claim 6, wherein the barrier layer comprises a second dielectric layer.

9. The semiconductor device of claim 8, wherein the barrier layer comprises silicon carbide, silicon nitride, or silicon oxynitride.

10. A semiconductor element, characterized in that, Include: The substrate includes a magnetoresistive random access memory region and a logic region. A magnetic tunnel junction is disposed on the region of the magnetoresistive random access memory. Metal interconnects are disposed on the magnetic tunnel junction; and A barrier layer is disposed on the inner metal line, wherein the barrier layer includes a fence-like pattern according to an upward viewing angle.

11. The semiconductor device of claim 10, further comprising: A first dielectric layer is disposed on the barrier layer; and The second dielectric layer is disposed on the first dielectric layer.

12. The semiconductor device of claim 11, wherein the first dielectric layer comprises silicon oxide.

13. The semiconductor device of claim 10, wherein the barrier layer comprises metal.

14. The semiconductor device of claim 13, wherein the barrier layer comprises aluminum.

15. The semiconductor device of claim 10, further comprising: A first dielectric layer is disposed on the metal interconnect; and The barrier layer is disposed on the first dielectric layer.

16. The semiconductor device of claim 15, wherein the first dielectric layer comprises silicon oxide.

17. The semiconductor device of claim 15, wherein the barrier layer comprises a second dielectric layer.

18. The semiconductor device of claim 17, wherein the barrier layer comprises silicon carbide, silicon carbide nitride, or silicon carbide nitride.

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