Switching device and front-end circuit

Abstract

A switching device (10) includes: a common terminal (Pan); a switching circuit (1) that switches conduction of a pair of terminals (Ps10 and Ps101); a switching circuit (2) that switches conduction of a pair of terminals (Ps20 and Ps201); and a switching circuit (3) that switches conduction of at least one of a pair of terminals (Ps301 and Ps302) and a terminal (Ps30). Switching elements (E111, E121, E131, and E132) are respectively provided in paths that connect the terminals (Ps10 and Ps101), paths that connect the terminals (Ps20 and Ps201), and a plurality of paths that connect the terminal (Ps30) and the pair of terminals (Ps301 and Ps302). The switching elements are each composed of one or more semiconductor elements stacked together, and the number of stacked semiconductor elements of a switching element (E121) is less than the number of stacked semiconductor elements of a switching element (E111).

Description

Technical Field

[0001] The present invention relates to a switching device, and more specifically, to a switching device that can be used in a high-frequency front-end circuit for communication of high-frequency signals in multiple communication bands. Background Technology

[0002] In recent years, mobile communication devices and other communication terminals have been required to be miniaturized and to support multiple communication frequency bands with a single communication terminal.

[0003] To achieve this, for example, the high-frequency module described in Patent Document 1 includes a switching element and various filters. The switching element has an antenna-side connection terminal connected to an antenna and multiple filter-side terminals connected to the filter side. By selectively connecting the multiple filter-side terminals to the antenna-side connection terminals at the switching element, the high-frequency module can selectively communicate in multiple communication frequency bands.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2014-050098 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] In the high-frequency module described in Patent Document 1, as the number of communication frequency bands increases, the number of terminals that the switching circuit (switching element) can switch also increases. Along with this, the parasitic capacitance generated between the common terminal of the switching circuit and ground increases, thus raising concerns about increased mismatch losses when the number of communication frequency bands increases.

[0009] To reduce this mismatch loss, a structure was conceived of connecting multiple stages of the switching circuit (cascaded connection). However, this structure introduces another problem: as the number of switching stages increases, the signal loss due to on-resistance increases.

[0010] Therefore, the object of the present invention is to provide a switching device and front-end circuit that can reduce signal loss caused by on-resistance while reducing mismatch loss.

[0011] Solution for solving the problem

[0012] The switching device of the present invention includes: a common terminal; a first switching circuit having a first terminal and a second terminal, for switching between the conduction and non-conduction of the first terminal and the second terminal; a second switching circuit having a third terminal and a fourth terminal, for switching between the conduction and non-conduction of the third terminal and the fourth terminal; and a third switching circuit having a fifth terminal and a plurality of sixth terminals, for switching between the conduction and non-conduction of at least one of the plurality of sixth terminals and the fifth terminal. The first terminal and the third terminal are connected to the common terminal, and the fifth terminal is connected to the fourth terminal. The first switching circuit, the second switching circuit, and the third switching circuit include a first switching element, which is respectively disposed in a first path connecting the first terminal and the second terminal, a second path connecting the third terminal and the fourth terminal, and a plurality of third paths connecting the fifth terminal and the plurality of sixth terminals. The first switching element is composed of one or more stacked semiconductor elements, and the number of stacked semiconductor elements in the first switching element of the second switching circuit is less than the number of stacked semiconductor elements in the first switching element of the first switching circuit.

[0013] The effects of the invention

[0014] According to the present invention, it is possible to reduce mismatch loss while suppressing signal loss caused by on-resistance. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of the high-frequency front-end circuit involved in the first embodiment.

[0016] Figure 2 This is a circuit diagram of the switching device according to the first embodiment.

[0017] Figure 3 This is a circuit diagram illustrating the switching device according to the first embodiment, using semiconductor elements.

[0018] Figure 4 This is a circuit diagram of the switching device involved in Comparative Example 1.

[0019] Figure 5A This is a first Smith chart showing the impedance in the first embodiment.

[0020] Figure 5B This is a second Smith chart illustrating the impedance in the first embodiment.

[0021] Figure 5C This is a third Smith chart showing the impedance in the first embodiment.

[0022] Figure 5D This is a first graph showing the insertion loss of the switching device in the first embodiment.

[0023] Figure 5EThis is a second graph showing the insertion loss of the switching device in the first embodiment.

[0024] Figure 5F This is a third graph showing the insertion loss of the switching device in the first embodiment.

[0025] Figure 6 This is the circuit diagram of the switching device involved in Comparative Example 2.

[0026] Figure 7 The circuit diagram of the switching device involved in Comparative Example 2 is shown using semiconductor components.

[0027] Figure 8 This is a graph showing the insertion loss of the switching circuit according to the first embodiment and the switching circuit according to Comparative Example 2.

[0028] Figure 9A This is a first diagram showing in detail the semiconductor element involved in the first embodiment.

[0029] Figure 9B This is a second figure that shows in detail the semiconductor element involved in the first embodiment.

[0030] Figure 9C The third figure shows in detail the semiconductor element involved in the first embodiment.

[0031] Figure 10 This is a circuit diagram of a high-frequency front-end circuit with a switching device involved in the variation example.

[0032] Figure 11A This is a first graph showing the insertion loss of the high-frequency front-end circuit involved in the modified example.

[0033] Figure 11B This is a second graph showing the insertion loss of the high-frequency front-end circuit involved in the modified example.

[0034] Figure 11C This is the third graph showing the insertion loss of the high-frequency front-end circuit involved in the modified example.

[0035] Figure 12A This is the fourth graph showing the insertion loss of the high-frequency front-end circuit involved in the modified example.

[0036] Figure 12B This is the fifth graph showing the insertion loss of the high-frequency front-end circuit involved in the modified example.

[0037] Figure 13A The sixth graph shows the insertion loss of the high-frequency front-end circuit involved in the modified example.

[0038] Figure 13BThis is the seventh graph showing the insertion loss of the high-frequency front-end circuit involved in the modified example.

[0039] Figure 14A This is the eighth graph showing the insertion loss of the high-frequency front-end circuit involved in the modified example.

[0040] Figure 14B This is the ninth graph showing the insertion loss of the high-frequency front-end circuit involved in the modified example.

[0041] Figure 15 This is a circuit diagram of the high-frequency front-end circuit with a switching device involved in Comparative Example 3.

[0042] Figure 16 This is a circuit diagram of the high-frequency front-end circuit involved in the second embodiment.

[0043] Figure 17A This is the first Smith chart used to illustrate the relationship between parasitic capacitance and loss.

[0044] Figure 17B This is the second Smith chart used to illustrate the relationship between parasitic capacitance and loss.

[0045] Figure 17C This is the third Smith chart used to illustrate the relationship between parasitic capacitance and losses.

[0046] Figure 17D It is the first graph used to illustrate the relationship between parasitic capacitance and loss.

[0047] Figure 17E This is the second chart used to illustrate the relationship between parasitic capacitance and loss.

[0048] Figure 17F This is the third chart used to illustrate the relationship between parasitic capacitance and loss.

[0049] Figure 18A This is the first circuit diagram used to illustrate the effect of the matching circuit.

[0050] Figure 18B This is the second circuit diagram used to illustrate the effect of the matching circuit.

[0051] Figure 18C This is the third circuit diagram used to illustrate the effect of the matching circuit.

[0052] Figure 18D This is the fourth circuit diagram used to illustrate the effect of the matching circuit.

[0053] Figure 18E This is the first Smith chart used to illustrate the effect of the matching circuit.

[0054] Figure 18FThis is the second Smith chart used to illustrate the effect of the matching circuit.

[0055] Figure 18G This is the third Smith chart used to illustrate the effect of the matching circuit.

[0056] Figure 18H This is the fourth Smith chart used to illustrate the effect of the matching circuit. Detailed Implementation

[0057] The following describes an example of how the present invention is implemented. However, the following embodiments are merely illustrative, and the present invention is not limited to the following embodiments at all.

[0058] Furthermore, in the accompanying drawings referenced in the embodiments, etc., components having substantially the same function are referred to using the same reference numerals. The drawings referenced in the embodiments, etc., are schematic illustrations, and the scales of the objects depicted in the drawings may sometimes differ from the scales of actual objects. In addition, the scales of objects may sometimes differ between the drawings themselves. The specific scales of the objects should be determined by referring to the following description.

[0059] (First Implementation)

[0060] The high-frequency front-end circuit with a switching device according to the first embodiment will be described with reference to the accompanying drawings.

[0061] [1. Structure]

[0062] [1.1. Overall Structure]

[0063] Figure 1 This is a circuit diagram of the high-frequency front-end circuit 5 with switching device 10 according to the first embodiment. Furthermore, Figure 1 The diagram also illustrates an example of an antenna ANT used as a device to connect to the high-frequency front-end circuit 5. The device connecting to the high-frequency front-end circuit 5 is not limited to an antenna; it can also be an amplifier such as a PA (Power Amplifier) ​​or an LNA (Low Noise Amplifier).

[0064] The high-frequency front-end circuit 5 is configured between the RFIC (Radio Frequency Integrated Circuit, not shown) and the antenna ANT, transmitting high-frequency signals of the supported communication frequency bands between the RFIC and the antenna ANT. In this embodiment, the high-frequency front-end circuit 5 supports LTE (Long Term Evolution) Band3 (Tx: 1710MHz~1785MHz, Rx: 1805MHz~1880MHz), Band1 (Tx: 1920MHz~1980MHz, Rx: 2110MHz~2170MHz), Band40 (TRx: 2300MHz~2400MHz), Band41 (TRx: 2496MHz~2690MHz), and Band7 (Tx: 2500MHz~2570MHz, Rx: 2620MHz~2690MHz). In addition, "Tx" refers to the uplink frequency of the FDD (Frequency Division Duplex) communication band, "Rx" refers to the downlink frequency of the FDD communication band, and "TRx" refers to both the uplink and downlink frequencies of the TDD (Time Division Duplex) communication band.

[0065] like Figure 1 As shown, the high-frequency front-end circuit 5 includes a multiplexer 21 supporting Band 3 and Band 1, a multiplexer 22 supporting Band 7, a filter 31 (first filter) supporting Band 40 (first frequency band), and a filter 32 (second filter) supporting Band 41 (second frequency band).

[0066] The multiple filters included in multiplexers 21 and 22, as well as the filters in filters 31 and 32, are, for example, elastic wave filters using SAW (Surface Acoustic Wave). Furthermore, these filters are not particularly limited and can also be elastic wave filters using BAW (Bulk Acoustic Wave), LC resonant filters, and dielectric filters.

[0067] [1.2. Overview of the Switching Device]

[0068] The switching device 10 includes switching circuits 1 to 3, which switch the multiplexer 21, multiplexer 22, filter 31 and filter 32 for devices that are to be connected to the antenna ANT.

[0069] Specifically, the switching device 10 includes: a common terminal Pan, which is connected to the antenna ANT via the external terminal Pe of the high-frequency front-end circuit 5; a terminal Pc21, which is connected to terminals Pb1 to Pb4 of the high-frequency front-end circuit 5 via a multiplexer 21; a terminal Pc22, which is connected to terminals Pb7 and Pb8 of the high-frequency front-end circuit 5 via a multiplexer 22; a terminal Pc31, which is connected to terminal Pb5 of the high-frequency front-end circuit 5 via a filter 31; and a terminal Pc32, which is connected to terminal Pb6 of the high-frequency front-end circuit 5 via a filter 32.

[0070] Switching circuit 1 is an example of a first switching circuit, and is a so-called SPnT (n=2 in this embodiment) type switch having multiple switching elements, including terminals Ps10 (first terminal), Ps101 (second terminal), and Ps102. Terminals Ps10, Ps101, and Ps102 are respectively connected to the common terminal Pan, terminal Pc21, and terminal Pc31 of switching device 10. Switching circuit 1 selectively connects at least one of terminals Ps101 and Ps102 to terminal Ps10. Alternatively, switching circuit 1 de-connects both terminals Ps101 and Ps102 to terminal Ps10.

[0071] Switching circuit 2 is an example of a second switching circuit. It is a so-called SPST type switch with more than one switching element, having terminal Ps20 (third terminal) and terminal Ps201 (fourth terminal). Terminals Ps20 and Ps201 are respectively connected to the common terminal Pan of switching device 10 and terminal Ps30 of switching circuit 3 (described later). Switching circuit 2 enables or de-energizes terminal Ps201 and terminal Ps20.

[0072] Switching circuit 3 is an example of a third switching circuit. It is a so-called SPnT (n=2 in this embodiment) type switch with multiple switching elements, having terminals Ps30 (fifth terminal), Ps301 (sixth terminal), and Ps302 (sixth terminal). Terminals Ps30, Ps301, and Ps302 are respectively connected to terminal Ps201 of switching circuit 2, terminal Pc32 of switching device 10, and terminal Pc22 of switching device 10. Switching circuit 3 selectively connects at least one of terminals Ps301 and Ps302 to terminal Ps30. Alternatively, switching circuit 3 prevents both terminals Ps301 and Ps302 from connecting to terminal Ps30.

[0073] Here, the switching circuit 3 is connected to the common terminal Pan via the switching circuit 2. That is, the switching device 10 has a structure in which the switching circuits 2 and 3 are cascaded in multiple stages. As a result, the switching device 10 can reduce the parasitic capacitance generated between the common terminal Pan and ground, and thus reduce mismatch losses. This will be described later using Comparative Example 1.

[0074] Furthermore, each of the switching circuits 1 to 3 includes one or more stacked semiconductor elements, as detailed later. In the switching device 10, the number of semiconductor elements stacked between terminals Ps20 and Ps201 in the switching circuit 2 is less than the number of semiconductor elements stacked between terminals Ps10 and Ps101 in the switching circuit 1. Therefore, the switching device 10 can reduce mismatch losses while suppressing signal loss caused by on-resistance. This will be described later using Comparative Example 2.

[0075] The switching device 10 configured in this way switches the conduction and non-conduction of the common terminal Pan and terminals Pc21, Pc22, Pc31 and Pc32 according to the control signal from the internal or external control unit (not shown) of the high-frequency front-end circuit 5, thereby switching the device to be connected to the antenna ANT.

[0076] [1.3. Detailed Structure of the Switching Device]

[0077] The detailed structure of the switching device 10 will now be described with a focus on the structure of the switching elements in the switching circuits 1 to 3. Figure 2 This is a detailed circuit diagram of the switching device 10 according to the first embodiment.

[0078] The switching circuit 1 includes a switching element E111 connected between terminals Ps10 and Ps101, and a switching element E112 connected between terminals Ps10 and Ps102. By switching the on and off states of switching elements E111 and E112 according to a control signal, at least one of terminals Ps101 and Ps102 is selectively connected to terminal Ps10. Switching element E111 is disposed in path 1a (first path) connecting terminals Ps10 and Ps101. Switching element E112 is disposed in path 1b connecting terminals Ps10 and Ps102. The switching circuit 1 also includes a switching element E211 connected between path 1a and ground, and a switching element E212 connected between path 1b and ground. Switching element E211 is disposed between switching element E111 and terminal Ps101, and switching element E212 is disposed between switching element E112 and terminal Ps102.

[0079] The switching circuit 2 has a switching element E121 connected between terminals Ps20 and Ps201. The conduction and non-conduction of terminals Ps201 and Ps30 are switched by turning the switching element E121 on and off according to a control signal. The switching element E121 is positioned in the second path connecting terminals Ps20 and Ps201.

[0080] The switching circuit 3 includes a switching element E131 connected between terminals Ps30 and Ps301, and a switching element E132 connected between terminals Ps30 and Ps302. By switching the on and off states of switching elements E131 and E132 according to a control signal, at least one of terminals Ps301 and Ps302 is selectively connected to terminal Ps30. Switching element E131 is disposed in path 3a (third path) connecting terminals Ps30 and Ps301. Switching element E132 is disposed in path 3b (third path) connecting terminals Ps30 and Ps302. The switching circuit 3 also includes a switching element E231 connected between path 3a and ground, and a switching element E232 connected between path 3b and ground. Switching element E231 is disposed between switching element E131 and terminal Ps301, and switching element E232 is disposed between switching element E132 and terminal Ps302.

[0081] Switching elements E211, E212, E231, and E232 are examples of second semiconductor elements.

[0082] Thus, in switching circuits 1 and 3, there are not only switching elements E111, E112, E131, and E132 configured on the path connecting the common terminal Pan to terminals Pc21, Pc22, Pc31, and Pc32, which is used for communication, but also switching elements E211, E212, E231, and E232 configured on the path connecting this path to ground. Switching elements E211, E212, E231, and E232 become non-conducting when switching elements E111, E112, E131, and E132 are in the ON state, and become ON when switching elements E111, E112, E131, and E132 are in the non-conducting state. In other words, switching elements E211, E212, E231, and E232 operate exclusively with switching elements E111, E112, E131, and E132, respectively. Furthermore, in this embodiment, to ensure the withstand voltage of switching element E121, when switching element E121 is in a non-conducting state, switching elements E131 and E132 in the switching circuit 3 are also in a non-conducting state.

[0083] Figure 3This diagram illustrates the circuit of the switching device 10 using semiconductor elements. As shown, each of the switching elements E111, E211, E112, E212, E121, E131, E231, E132, and E232 comprises one or more stacked semiconductor elements. In this embodiment, the semiconductor element is a FET (Field Effect Transistor), but it is not limited to this; for example, it could also be a diode switch or a MEMS switch. Furthermore, in this embodiment, only switching element E121 comprises one FET, while the other switching elements comprise multiple FETs (e.g., eight FETs).

[0084] In switching elements E111, E211, E112, E212, E121, E131, E231, E132, and E232, the gates of FETs are connected to the corresponding control terminals Vc1a(s), Vc1a(g), Vc2(s), Vc3a(s), Vc3a(g), Vc3b(s), and Vc3b(g), respectively. Furthermore, in switching elements E111, E211, E112, E212, E131, E231, E132, and E232, which include multiple FETs, the source of one of two adjacent FETs is connected to the drain of the other FET.

[0085] Here, the number of semiconductor elements stacked in the switching element is determined by the withstand voltage of the semiconductor elements and the voltage applied to the switching element. For example, when the withstand voltage of the semiconductor elements is set to 2.5V and the voltage applied to the switching element is set to 20V, the number of semiconductor elements stacked needs to be 8 or more. Specific examples are given below to illustrate this.

[0086] Assume that when transmitting a high-frequency signal through the switching device 10, a voltage of 20V is applied between the common terminal Pan of the switching device 10 and ground. At this time, although the switching elements E111 and E112 of the switching circuit 1 are required to withstand a voltage of 20V, the switching element E121 of the switching circuit 2 is only required to withstand a lower voltage.

[0087] Specifically, switching element E121 becomes non-conducting when at least one of the switching elements E111 and E112 in switching circuit 1 is in a conducting state, and therefore the applied voltage is at its maximum. In this embodiment, when switching element E121 is in a non-conducting state, switching elements E131 and E132 in switching circuit 3 are also in a non-conducting state. Therefore, the 20V voltage applied between the common terminal Pan of switching device 10 and ground is not applied only to switching element E121, but is divided by switching elements E121 and switching elements E131 and E132.

[0088] Therefore, even if the number of FETs stacked in the switching element E121 of the switching circuit 2 is less than the number of FETs stacked in the switching elements E111 and E112 of the switching circuit 1, the withstand voltage of the switching element E121 can be ensured, and as a result, damage to the switching device 10 can be suppressed.

[0089] [2. Comparison with Comparative Examples 1 and 2]

[0090] The structure of the switching device 10 according to this embodiment has been described above. The main effects of this switching device 10 will now be explained using Comparative Examples 1 and 2.

[0091] First, using Comparative Example 1, we can illustrate the following: The switching device 10 according to the first embodiment can reduce mismatch losses by making the parasitic capacitance small.

[0092] Figure 4 This is a circuit diagram of the high-frequency front-end circuit 2000 with switching device 1000 involved in Comparative Example 1. For example... Figure 4 As shown, the high-frequency front-end circuit 2000 differs from the high-frequency front-end circuit 5 of the first embodiment in the following aspects: it is equipped with an SP4T type switching device 1000 instead of the switching device 10. Specifically, in the path connecting the common terminal Pan to the terminals Pc22 and Pc32, the switching device 10 in the first embodiment is equipped with two switching elements, but in Comparative Example 1, only one switching element is provided.

[0093] Typically, in SPnT type switching devices, due to the influence of the turn-off capacitance of the switching elements included in the switching device, the parasitic capacitance generated between the common terminal and ground increases as the number of selected terminals increases. Furthermore, the selected terminal refers to the terminal selectively connected to the common terminal in the switching circuit. Additionally, the turn-off capacitance of the switching element is the capacitance when the switching element is not conducting.

[0094] In high-frequency front-end circuits with switching devices, the parasitic capacitance of the switching devices can affect mismatch losses. Figures 5A to 5C as well as Figures 5D to 5F This is a graph used to illustrate the relationship between parasitic capacitance and losses. Specifically, Figures 5A to 5C This is a Smith chart showing the impedance of the common terminal of the switching device, with the impedances shown for parasitic capacitance Cp1 of 0.5, 1.0, and 2.0 [pF], respectively. Figures 5D to 5F This is a graph showing the insertion loss of the switching device, with the insertion loss shown for the parasitic capacitance Cp1 of the switching device being 0.5, 1.0, and 2.0 [pF].

[0095] like Figures 5A to 5C as well as Figures 5D to 5F As shown, as the parasitic capacitance Cp1 increases, the impedance deviation in the frequency band increases, resulting in a greater insertion loss, or mismatch loss, caused by impedance mismatch.

[0096] Therefore, in the switching device 10 according to the first embodiment, in order to reduce mismatch losses, the switching circuits 2 and 3 are cascaded to suppress parasitic capacitance.

[0097] Typically, the switching elements in a switching device generate a parasitic capacitance known as the turn-off capacitance when not conducting. Therefore, if only one of the selected terminals is connected to the common terminal, and the switching circuit is not cascaded, the sum of the turn-off capacitances of the individual switching elements connected between the remaining selected terminals and the common terminal will affect the parasitic capacitance. Conversely, if the switching circuit is cascaded, the switching elements are connected in series, and thus, a combined capacitance smaller than the sum of the turn-off capacitances of the individual switching elements will affect the parasitic capacitance.

[0098] Therefore, in the switching device 10 according to the first embodiment, parasitic capacitance can be reduced compared to the switching device 1000 according to Comparative Example 1.

[0099] Next, using Comparative Example 2, we will illustrate the following aspects: The switching device 10 according to the first embodiment can reduce signal loss caused by on-resistance while reducing mismatch loss.

[0100] One factor contributing to signal loss in switching devices is the on-resistance of the semiconductor elements along the signal's path. On-resistance is the resistive component of a signal flowing through a switching element in a conducting state. In this specification, it refers to the resistive component of the signal passing through a semiconductor element; in the case of a FET (Field-FET), it refers to the resistance between the drain and source of that FET. In other words, in a switching device, the more semiconductor elements the signal passes through, the greater the resistive component of the semiconductor elements, and therefore the greater the signal loss.

[0101] Figure 6 This is a detailed circuit diagram of the switching device 10A involved in Comparative Example 2. Figure 7 This is a circuit diagram showing the switching device 10A using semiconductor components. For example... Figure 6 and Figure 7 As shown, the switching device 10A involved in Comparative Example 2 includes a switching circuit 2A instead of the switching circuit 2 in the first embodiment.

[0102] Figure 6 and Figure 7 The switch circuit 2A shown in the figure and Figure 2 and Figure 3 The switching circuit 2 shown differs from the previous one in the following aspects: it has a switching element E121A with eight stacked FETs instead of a switching element E121 including one FET, and it has a switching element E222A connected between the terminal Ps201A and ground. Here, the switching elements E121A and E222A operate exclusively.

[0103] Although the switching device 10A involved in Comparative Example 2 can reduce mismatch losses by cascading the switching circuits 2A and 3, the following second problem arises: compared with the signal path through the uncascaded switching circuit 1, the signal loss caused by the on-resistance of the switching elements is greater on the signal path through the cascaded switching circuits 2A and 3.

[0104] Specifically, in the signal path through the uncascaded switching circuit 1, signal loss occurs due to the on-resistance of the eight FETs included in the switching circuit 1. On the other hand, in Comparative Example 2, in the signal path through the cascaded switching circuits 2A and 3, loss occurs due to the on-resistance of a total of 16 FETs, including the eight FETs in the switching element E121A of the switching circuit 2A and the eight FETs in the switching element E131 or E132 of the switching circuit 3.

[0105] In contrast, in the first embodiment, the number of FETs included in the switching element E121 of the switching circuit 2 is one, thereby reducing the losses generated in the signal path through the cascaded switching circuits 2 and 3.

[0106] Figure 8 The simulation results show the insertion loss of the switching device 10A according to Comparative Example 2 and the switching device 10 according to the first embodiment. Specifically, Figure 8The solid lines in the diagram show the insertion loss in the first embodiment relative to the frequency of the high-frequency signal flowing when the common terminal Pan is connected to terminal Ps101 or terminal Ps102. The dashed lines show the insertion loss in the first embodiment relative to the frequency of the high-frequency signal flowing when the common terminal Pan is connected to terminal Ps301 or terminal Ps302. The dotted lines show the insertion loss in Comparative Example 2 relative to the frequency of the high-frequency signal flowing when the common terminal Pan is connected to terminal Ps301 or terminal Ps302.

[0107] First, let's explain the relationship between the solid and dashed lines. When comparing the solid line (the path between the common terminal Pan and the terminal Ps101) with the dashed line (the path between the common terminal Pan and the terminal Ps301), the cascaded path has more FETs, resulting in greater insertion loss.

[0108] Next, the relationship between the dashed lines and the dotted lines will be explained. When the dashed lines represent the cascading paths involved in the first embodiment (…),… Figure 2 The path between the common terminal Pan and terminal Ps301 in the above example is compared with the cascading connection path involved in Comparative Example 2, as shown by the dashed line. Figure 6 When comparing the path between the common terminal Pan and the terminal Ps301 in the first embodiment, it is shown that the insertion loss can be reduced compared to Comparative Example 2.

[0109] In other words, for cascaded paths, insertion loss can be reduced by using the structure of the first embodiment. Specifically, it is shown that the insertion loss suppression effect increases with increasing frequency, and is effective in the high-frequency region.

[0110] Here, the withstand voltage of the switching device 10 according to the first embodiment and the switching device 10A according to the comparative example 2 will be compared to illustrate the first embodiment. Figure 2 and Figure 6 When making comparisons, in Figure 6 Comparative Example 2 shown includes a switching element E222A; in contrast, in Figure 2 In the first embodiment shown, the switching element E222A is not provided. In other words, the switching device 10 according to the first embodiment does not have a path for connecting the path for connecting terminals Ps20 and Ps201 to ground, nor a switching element disposed on that path. Therefore, in terms of withstand voltage, switching circuits 2 and 3 function as a single switch, and voltage from other paths is not applied only to switching circuit 2, but rather to both switching circuits 2 and 3.

[0111] On the other hand, the switching device 10A involved in Comparative Example 2 is provided with a switching element E222A. Therefore, regardless of whether the switching circuit 3 is in a conducting or non-conducting state, when the switching element E121A is in a non-conducting state in the switching circuit 2A, voltages from other paths will be applied to the switching element E121A. Therefore, in order to ensure the withstand voltage, the number of stacked switching elements E121A needs to be large, resulting in a larger signal.

[0112] In other words, in the switching device 10 according to the first embodiment, there is no path for connecting the path for connecting the terminal Ps20 and the terminal Ps201 to ground, and no switching element disposed on the path. Therefore, the applied voltage is divided by the switching element E121 of the switching circuit 2 and the switching element E131 of the switching circuit 3.

[0113] More specifically, in the switching device 10 according to the first embodiment, the switching circuit 2 does not have a switching element on the path connecting terminals Ps20 and Ps30 to ground. Therefore, switching elements E121 and E131 are connected in series, and switching elements E121 and E132 are also connected in series. Furthermore, switching elements E121 and E131 are directly connected, and a switching element E231 is disposed between switching element E131 and terminal Ps301 and ground. Additionally, switching elements E121 and E132 are directly connected, and a switching element E232 is disposed between switching element E132 and terminal Ps302 and ground.

[0114] Through this connection, the switching device 10 performs an operation similar to a so-called SP2T type switch, selectively connecting one of terminals Ps301 and Ps302 to terminal Ps20. Therefore, voltages from other paths are not applied only to the switching circuit 2. In other words, compared to the switching element E121A in Comparative Example 2, the switching element E121 in the first embodiment can ensure withstand voltage with fewer stacking elements.

[0115] [3. Construction]

[0116] Here, the structure of the FET included in each switching element according to the first embodiment will be described. When the switching element is a FET switch, that is, when the semiconductor element included in the switching element is a FET, the on-resistance of the FET included in the switching element can be defined by the gate width of the FET.

[0117] Reference Figures 9A to 9C This will illustrate the relationship between gate width and gate width. Figure 9A The diagram shows in detail Qs11, one of the FETs included in the switching element E111 of the switching circuit 1. Figure 9BThe diagram shows in detail Qs21, one of the FETs included in the switching element E121 of the switching circuit 2. Figure 9C The diagram shows in detail Qs31, one of the FETs included in the switching element E131 of the switching circuit 3.

[0118] Here, the gate width is represented by the product of the gate electrode width (width) W1 and the number of gate electrodes (index). In a FET, the gate electrode width specifically refers to the length of the gate electrode facing the drain or source electrode. Figures 9A to 9C When comparing, the finger width W1 of FET elements Qs11, Qs21, and Qs31 is equal. On the other hand, the index of FET element Qs21 is more than that of FET element Qs11 and FET element Qs31. For example, the index of FET element Qs21 is 21, while the index of FET element Qs11 and FET element Qs31 is 14.

[0119] In other words, such as Figure 9A and Figure 9B As shown, the gate width of FET element Qs21 in switching circuit 2 is larger than the gate width of FET element Qs11 in switching circuit 1. Additionally, as... Figure 9B and Figure 9C As shown, the gate width of the FET element Qs21 in the switching circuit 2 is larger than the gate width of the FET element Qs31 in the switching circuit 3.

[0120] Generally, the larger the gate width of a switching element, the smaller its on-resistance. Therefore, the on-resistance of FET element Qs21 in switching circuit 2 is smaller than that of FET element Qs11 in switching circuit 1. Furthermore, the on-resistance of FET element Qs21 in switching circuit 2 is smaller than that of FET element Qs31 in switching circuit 3.

[0121] Furthermore, the finger widths of FET elements Qs11, Qs21, and Qs31 can be unequal. For example, in FET elements Qs21 and Qs11, with equal exponents, the finger width of FET element Qs21 can be wider than that of FET element Qs11. In this case, the gate width of FET element Qs21 is also wider than the gate width of FET element Qs11. However, the finger width or exponent does not need to be fixed among the FET elements.

[0122] Furthermore, when the gate widths of two FET elements are equal, the on-resistance of a FET element with more gate electrodes is smaller than that of a FET element with fewer gate electrodes.

[0123] [4. Summary]

[0124] As described above, the switching device 10 according to this embodiment includes cascaded switching circuits 2 and 3, which suppresses parasitic capacitance and thus reduces mismatch losses. Furthermore, the number of semiconductor elements stacked in the switching element E121 in switching circuit 2 is less than the number of semiconductor elements stacked in the switching element E111 in switching circuit 1. Therefore, the number of semiconductor elements stacked along the path from the cascaded switching circuits 2 and 3 to the common terminal Pan can be suppressed. As a result, signal loss due to on-resistance when high-frequency signals pass through semiconductor elements can be reduced. In other words, the switching device 10 according to this embodiment reduces both mismatch losses and signal loss due to on-resistance.

[0125] Furthermore, according to this embodiment, the switching circuit 1 and the switching circuit 3 include not only switching elements E111, E112, E131, and E132 disposed on the path connecting the common terminal Pan to terminals Pc21, Pc31, Pc32, and Pc22, but also switching elements E211, E212, E231, and E232 disposed on the path connecting this path to ground. Here, switching elements E211, E212, E231, and E232 operate exclusively with switching elements E111, E112, E131, and E132, respectively.

[0126] Accordingly, the isolation between the paths that connect the common terminal Pan to terminals Pc21, Pc31, Pc32, and Pc22 can be improved.

[0127] Furthermore, according to this embodiment, the number of semiconductor elements stacked in the switching element E121 in the switching circuit 2 is less than the number of semiconductor elements stacked in the switching element E131 in the switching circuit 3.

[0128] Accordingly, the number of semiconductor elements stacked on the path including the cascaded switching circuits 2 and 3 can be suppressed, thus further suppressing signal loss on the path.

[0129] Furthermore, by minimizing the parasitic capacitance of the switching device 10 when the switching element E121 is in the non-conducting state, signal loss due to mismatch loss can be further suppressed. Specifically, as long as the sum of the number of semiconductor elements stacked in the switching circuit 2 (e.g., the semiconductor elements stacked in the switching element E121) and the switching circuit 3 (e.g., the semiconductor elements stacked in the switching element E131) remains constant, the signal loss due to on-resistance is equal regardless of the number of semiconductor elements stacked in the switching element E121. However, when the switching element E121 is in the non-conducting state, the number of semiconductor elements stacked in the switching device 10 (e.g., the semiconductor elements stacked in the switching element E121) has a more dominant effect on the parasitic capacitance generated between the common terminal Pan of the switching device 10 and ground compared to the number of semiconductor elements stacked in the switching element E131 of the switching circuit 3. Therefore, by making the number of semiconductor elements stacked in the switching element E121 less than the number of semiconductor elements stacked in the switching element E131, insertion loss due to impedance mismatch can be reduced.

[0130] The relationship between the number of semiconductor elements stacked as illustrated by switching elements E121 and E131, and the resulting effect, also apply to switching elements E121 and E132.

[0131] Furthermore, according to this embodiment, the number of stacked semiconductor elements of the switching element E121 in the switching circuit 2 is 1.

[0132] Accordingly, the number of semiconductor elements stacked along the path from switching circuits 2 and 3 to the common terminal Pan can be further suppressed. As a result, signal loss caused by on-resistance when high-frequency signals pass through semiconductor elements can be further suppressed. In addition, the parasitic capacitance (turn-off capacitor) of the switching element E121 in switching circuit 2 when it is in the non-conducting state can be reduced, and as a result, signal loss caused by impedance mismatch loss can also be further suppressed.

[0133] In addition, the number of semiconductor elements stacked in the switching element E121 can be more than two.

[0134] Furthermore, according to this embodiment, when there is no connection between terminal Ps20 and terminal Ps201 in the switching circuit 2, there is no connection between terminal Ps30 and multiple terminals Ps301 and Ps302 in the switching circuit 3.

[0135] In this case, the voltage applied to the switching circuit 2 is the voltage divided by the switching circuits 2 and 3. Therefore, the required withstand voltage for the switching circuit 2 can be reduced, thus reducing the number of semiconductor elements stacked in the switching element E121 of the switching circuit 2.

[0136] Furthermore, depending on the device (filter) connected to switch circuit 3, there are sometimes frequencies where the impedance appears to be short-circuited. In this case, when switch circuit 3 is in the on state and switch circuit 2 is in the off state, the voltage applied to switch circuit 2 is prone to increase. Therefore, by making switch circuit 3 also in the off state when switch circuit 2 is in the off state, damage to switch circuit 2 caused by applying a voltage exceeding its withstand voltage can be avoided.

[0137] Furthermore, in this specification, a switch circuit is defined as a non-conductive switch when all selected terminals are in a non-conductive state with the common terminal, and a switch circuit is defined as a conductive switch when at least one selected terminal is in a conductive state with the common terminal.

[0138] In addition, in this embodiment, the switching circuit 2 is composed only of the switching element E121.

[0139] Accordingly, the switching circuit 2 can be miniaturized. Furthermore, from a voltage withstand perspective, switching circuit 2 and switching circuit 3 function as a single switch, meaning that voltage from other paths is applied to both switching circuits, not just switching circuit 2. As a result, the parasitic capacitance observed at the common terminal Pan is reduced, further suppressing signal loss.

[0140] In addition, the switching circuit 2 can also have, for example Figure 6 The switch element E222A is shown.

[0141] Furthermore, according to the high-frequency front-end circuit 5 with such a switching device 10, while reducing mismatch loss, signal loss caused by on-resistance can be suppressed, thus enabling support for multiple frequency bands while reducing losses.

[0142] (A variation of the first embodiment)

[0143] Next, the high-frequency front-end circuit 5B with a switching device according to a modification of the first embodiment will be described with reference to the accompanying drawings.

[0144] Figure 10This is a circuit diagram of the high-frequency front-end circuit 5B with switching device 10B according to the modified example. The switching device 10B according to this modified example differs from the switching device 10 according to the first embodiment in the following aspects: it also has a terminal Pc31B as a selected terminal, and it includes an SP3T type switching circuit 1B instead of an SPDT type switching circuit 1. Compared with the switching circuit 1, the switching circuit 1B also has a terminal Ps102B connected to the terminal Pc31B, a switching element E112B connected between the terminal Ps10 and the terminal Ps102B, and a switching element E212B connected between the terminal Ps102B and ground.

[0145] In this modified example, the high-frequency front-end circuit 5B, in addition to the switching device 10B, also includes a multiplexer 21B supporting Band 32, Band 3 and Band 1, a multiplexer 22 supporting Band 7, a filter 31 supporting Band 40, a multiplexer 31B supporting Band 34 and Band 39, and a filter 32 supporting Band 41.

[0146] The characteristics of the high-frequency front-end circuit 5B constructed in this way will be explained below.

[0147] Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A as well as Figure 14B This represents the simulation results of the insertion loss in the high-frequency front-end circuit 5B involved in this variation, relative to the frequency of the high-frequency signal flowing through each path.

[0148] Figures 11A to 11C , Figure 12A as well as Figure 12B This is a simulation result for the state where only one device is connected to the common terminal Pan. Specifically, Figure 11A This is a simulation result of the state where only the multiplexer 21B supporting Band32, Band3 and Band1 is connected to the common terminal Pan. Figure 11B This is a simulation result showing the state where only the multiplexer 31B supporting Band34 and Band39 is connected to the common terminal Pan. Figure 11C This is a simulation result of the state where only the filter 32 supporting Band7 is connected to the common terminal Pan. Figure 12A This is a simulation result of the state where only the filter 31 supporting Band40 is connected to the common terminal Pan. Figure 12B This is a simulation result of the state where only the filter 32 supporting Band41 is connected to the common terminal Pan.

[0149] Figure 13A , Figure 13B , Figure 14A as well as Figure 14B This is a simulation result of the state of two devices connected to the common terminal Pan. Figure 13A The simulation results show the state of connecting the multiplexer 21B supporting Band32, Band3 and Band1 and the filter 31 supporting Band40 to the common terminal Pan. Figure 13B The simulation results show the state of connecting the multiplexer 21B supporting Band32, Band3 and Band1 and the filter 32 supporting Band41 to the common terminal Pan. Figure 14A The simulation results show the state of connecting the multiplexer 21B supporting Band32, Band3 and Band1 and the filter 32 supporting Band7 to the common terminal Pan. Figure 14B The simulation results show the state of connecting the multiplexer 31B supporting Band 34 and Band 39 and the filter 32 supporting Band 41 to the common terminal Pan.

[0150] The following comparative example 3 will be used to illustrate the effect of this modified example. Figure 15 This is a circuit diagram of the high-frequency front-end circuit 5D with switching device 10D involved in Comparative Example 3. The switching device 10D involved in Comparative Example 3 differs from the switching device 10B involved in the modified example of the first embodiment in the following aspects: it is equipped with the switching circuit 2A described in Comparative Example 2 instead of the switching circuit 2. Table 1 shows the insertion loss of the high-frequency signal flowing through each path in the modified example and Comparative Example 3. Table 1 records the maximum value of the insertion loss in the passband of the frequency band recorded in the uppermost layer when the filter or multiplexer supporting the frequency bands recorded in the leftmost column is connected to the common terminal Pan. In addition, in this specification, in the figures or tables, Band is referred to as "B", the transmit frequency band is referred to as "Tx", the receive frequency band is referred to as "Rx", and the transmit and receive frequency band is referred to as "TRx". For example, the transmit and receive frequency band of Band 41 is referred to as "B41TRx".

[0151] [Table 1]

[0152] Table 1

[0153]

[0154] As shown in Table 1, in all cases, compared to Comparative Example 3, the maximum value of insertion loss within the frequency band is smaller in the modified example of the first embodiment. Specifically, similar to the first embodiment, in the modified example of the first embodiment, by reducing the number of semiconductor elements in the path that cascades the switching circuits 2A and 3, the insertion loss of high-frequency signals passing through Band 41 and Band 7 via that path can be reduced. Furthermore, for high-frequency signals passing through a frequency band different from the path that cascades the switching circuits 2A and 3, similar to the first embodiment, in the modified example of the first embodiment, the parasitic capacitance of the switching circuit 1B can be reduced, thus reducing the insertion loss caused by impedance mismatch.

[0155] Alternatively, for example, the transmit filter supporting the frequency band of PC2 (power level 2) can be connected to a different switch circuit 1 than the cascaded switch circuits 2A and 3.

[0156] Therefore, for frequency bands requiring higher transmission power, the signal can be propagated to the common terminal Pan while maintaining power with reduced signal loss.

[0157] Alternatively, for example, a transmit filter supporting the PC3 (power level 3) band could be connected to cascaded switch circuits 2A and 3. In other words, a transmit filter with a lower maximum transmit power could be connected to cascaded switch circuit 3.

[0158] Furthermore, power class is a classification of the UE's output power defined by maximum output power, etc. A smaller power class value indicates a higher permissible output power. For example, in 3GPP (registered trademark), the maximum permissible output power for power class 1 is 31 dBm, for power class 1.5 it is 29 dBm, for power class 2 it is 26 dBm, and for power class 3 it is 23 dBm.

[0159] (Second Implementation)

[0160] With the increasing prevalence of multi-band switching in recent years, the number of devices (filters) connected to switching devices has increased, leading to a rise in the parasitic capacitance of these switching devices. Therefore, even using the switching device described in the first embodiment sometimes fails to sufficiently reduce mismatch losses. Thus, in the second embodiment, a matching circuit that effectively suppresses mismatch losses in the switching device will be described.

[0161] Figure 16This is a circuit diagram of the high-frequency front-end circuit 200 according to the second embodiment. Compared with the high-frequency front-end circuit 5 described in the first embodiment, the high-frequency front-end circuit 200 includes a matching circuit 100 disposed between the common terminal Pan of the switching device 10 and the external terminal Pe of the high-frequency front-end circuit 200.

[0162] Matching circuit 100 is a π-type matching circuit having two inductors L1 and L2 and one capacitor C. Specifically, inductor L1 (the first inductor) is positioned on the path connecting the common terminal Pan to the external terminal Pe. Inductor L2 (the second inductor) is positioned on the path connecting the common terminal Pan to inductor L1 to ground. Regarding capacitor C, capacitor C is positioned on the path connecting the external terminal Pe to inductor L1 to ground.

[0163] By providing this matching circuit 100, according to the second embodiment, even when the parasitic capacitance of the switching device 10 increases, the increase in mismatch loss can be suppressed.

[0164] Figures 17A-17C as well as Figures 17D to 17F This is a graph used to illustrate the relationship between parasitic capacitance and losses. Specifically, Figures 17A-17C This is a Smith chart showing the impedance when the matching circuit 100 of the second embodiment is added to the switching device 10, and the impedances are shown when the parasitic capacitance Cp1 of the switching device 10 is 0.5, 1.0, and 2.0 [pF]. Figures 17D to 17F This is a graph showing the insertion loss when the matching circuit 100 of the second embodiment is added to the switching device 10, showing the insertion loss when the parasitic capacitance Cp1 of the switching device 10 is 0.5, 1.0, and 2.0 [pF]. In the second embodiment, the first to third simulation results showing the impedance observed from the external terminal Pe are shown using a Smith chart.

[0165] The impedance when the matching circuit 100 in the additional second embodiment is shown is... Figures 17A-17C The impedance shown is without the matching circuit 100 in the second embodiment. Figures 5A to 5C A comparison reveals that although the parasitic capacitance Cp1 is the same, in Figures 17A-17C The impedance trajectory is concentrated near the center of the Smith chart. As a result, the insertion loss is shown when the matching circuit 100 in the additional second embodiment is illustrated. Figures 17D to 17F The diagram shows the insertion loss without the matching circuit 100 in the second embodiment. Figures 5D to 5FIn comparison, although the parasitic capacitance Cp1 is the same, the insertion loss at the end of the frequency band can be reduced. That is, according to the matching circuit 100 in the second embodiment, the following effect is achieved: the impedance deviation within the frequency band is reduced, thereby reducing the mismatch loss at the end of the frequency band.

[0166] Next, use Figures 18A to 18D as well as Figures 18E to 18H To explain the mechanism by which this effect is achieved. Figures 18E to 18H It means Figures 18A to 18D Simulation results of the impedance observed from the external terminal Pe in each structure. Figures 18E to 18H In the diagram, the solid line represents the impedance trajectory at the low-frequency end, and the dashed line represents the impedance trajectory at the high-frequency end.

[0167] Figure 18A This is a circuit diagram showing the parasitic capacitance of the switching device 10 as parasitic capacitance Cp1. Figure 18B , Figure 18C , Figure 18D These are circuit diagrams showing the inductors L1, L2, and C, which are connected to the switching device 10 in sequence by the matching circuit 100.

[0168] like Figures 18E to 18H As shown, although the impedance offset differs at the low-frequency and high-frequency ends when components are added, by sequentially adding inductor L1, inductor L2, and capacitor C of the matching circuit 100, the impedance at the low-frequency end (shown by the solid line) and the impedance at the high-frequency end (shown by the dashed line) gradually approach the center of the Smith chart. As a result, mismatch losses at both the low-frequency and high-frequency ends can be reduced.

[0169] Here, the inductance of the series-connected inductor L1 is greater than the inductance of the parallel-connected inductor L2. Therefore, as... Figure 18F and Figure 18G As shown, the impedance shift when adding inductor L1 is greater than the impedance shift when adding inductor L2. Consequently, when adding capacitor C, the impedance at both the low-frequency and high-frequency ends can be brought closer to the center of the Smith chart, thus facilitating the reduction of mismatch losses.

[0170] Alternatively, when the parasitic capacitance of switch circuit 1 is set as C1, the turn-off capacitance of the switching element in switch circuit 2 is set as C2, and the parasitic capacitance of switch circuit 3 is set as C3, the capacitance value C4 of capacitor C satisfies the relationship of equation (1) when switch circuit 2 is not conducting, and the capacitance value C4 of capacitor C satisfies the relationship of equation (2) when switch circuit 2 is conducting.

[0171] [Formula 1]

[0172] (C1·C2) / (C1+C2)+C3≥C4…(1)

[0173] [Equation 2]

[0174] C1 + C3 ≥ C4…(2)

[0175] In other words, when the parasitic capacitance of the switching device 10 is set to Cp1, the relationship of equation (3) can also be satisfied.

[0176] [Formula 3]

[0177] Cp1≥C4…(3)

[0178] like Figure 18E and Figure 18H As shown, Figure 18E and Figure 18H Compared to the large offset, the capacitance value C4 of capacitor C can also be less than or equal to the parasitic capacitance Cp1 of switching device 10 in order to further suppress impedance mismatch.

[0179] Based on the above, in the second embodiment, in addition to the structure of the first embodiment, a matching circuit 100 is also provided, thereby suppressing impedance mismatch. As a result, it is shown that insertion loss can be further reduced. That is, as a method to reduce insertion loss, a structure having a cascaded connection and a matching circuit is shown. Therefore, insertion loss can also be reduced by having a matching circuit without a cascaded connection. Specifically, for example, the following structure may also be used: Figure 4 The high-frequency front-end circuit 2000 involved in Comparative Example 1 shown has the following features: Figure 16 The matching circuit 100 shown can also reduce insertion loss in this case.

[0180] (Other variations)

[0181] The first and second embodiments have been described above to illustrate the front-end circuit involved in the embodiments of the present invention, but the present invention is not limited to the above embodiments. Other embodiments implemented by combining any structural elements in the above embodiments, as well as various modifications that can be conceived by those skilled in the art without departing from the spirit of the present invention, are also included in the present invention.

[0182] For example, in the above description, in each of the switching circuits of switching circuit 1 and switching circuit 3, not only is a first switching element arranged on the path connecting the common terminal of the switching circuit to the selected terminal, but a second switching element is also arranged on the path connecting the path to ground. However, the second switching element may not be arranged.

[0183] Alternatively, the first and second switching elements may operate non-exclusively. For example, when the switching device is not operated, both the first and second switching elements may be in a conducting state for ESD protection.

[0184] Alternatively, for example, the number of stacked semiconductor elements in the first switching element of switching circuit 1 may be different from the number of stacked semiconductor elements in the first switching element of switching circuit 3. For example, if the device connected to switching circuit 1 supports PC2 and the device connected to switching circuit 3 supports PC3, in order to meet the required transmission power, the number of stacked semiconductor elements in switching circuit 1 may be less than the number of stacked semiconductor elements in switching circuit 3, thereby meeting the required transmission power.

[0185] Furthermore, for example, the number of stacked semiconductor elements of the first switching element in the switching circuit 2 is not limited to one, as long as it is less than the number of stacked semiconductor elements of the first switching element in the switching circuit 1. For example, if the device connected to the switching circuit 2 via the switching circuit 3 supports the PC2, the number of stacked semiconductor elements of the first switching element in the switching circuit 2 may be two or more.

[0186] Alternatively, for example, the number of stacked semiconductor elements of the first switching element in switching circuit 1 may be greater than the sum of the number of stacked semiconductor elements of the first switching element in switching circuit 2 and the number of stacked semiconductor elements of the first switching element in switching circuit 3.

[0187] Alternatively, for example, when the first switching element in switching circuit 3 is in a non-conducting state, the first switching element in switching circuit 2 is not in a non-conducting state. That is, it is also possible that when the first switching element in switching circuit 3 is in a non-conducting state, the first switching element in switching circuit 2 is in a conducting state.

[0188] Alternatively, for example, switch circuit 2 could not be an SPST type switch. For example, switch circuit 2 could be an SP2T or SP3T type switch.

[0189] Explanation of reference numerals in the attached figures

[0190] 1, 1B, 2, 2A, 3: Switching circuits; 1a, 1b, 3a, 3b: Paths; 5, 5B, 5D, 200, 2000: High-frequency front-end circuits; 10, 10A, 10B, 10D, 1000: Switching devices; 21, 21B, 22, 31B: Multiplexers; 31, 32, 211, 212, 213, 214, 221, 222: Filters; 00: Matching circuit; B1, B3, B32, B34, B39, B40, B41, B7: Communication frequency band; C2: Shutdown capacitor; C4: Capacitance value; Cp1: Parasitic capacitance; E111, E112, E112B, E121, E121A, E131, E132, E200, E211, E212, E212B, E222A, E231 E232: Switching element; L1, L2: Inductors; Pan: Common terminal; Pb1, Pb1B, Pb2, Pb3, Pb4, Pb5, Pb5B, Pb5C, Pb6, Pb7, Pb8, Pc21, Pc22, Pc31, Pc31B, Pc32, Ps10, Ps101, Ps102, Ps102B, Ps20, Ps2 01, Ps30, Ps301, Ps302: Terminals; Pe: External terminal; Q11, Q21, Q31, Qs1, Qs11, Qs2, Qs21, Qs3, Qs31, Qs4, Qs5, Qs6, Qs7, Qs8: FETs; Vc1a, Vc1b, Vc2, Vc3a, Vc3b: Control terminals; W1: Finger width; n: Stack number.

Claims

1. A switching device comprising: Common terminal; A first switching circuit has a first terminal and a second terminal, which switches the first terminal and the second terminal between being on and off. The second switching circuit has a third terminal and a fourth terminal, and switches the conduction and non-conduction of the third terminal and the fourth terminal; as well as A third switching circuit has a fifth terminal and multiple sixth terminals, which switches at least one of the sixth terminals between the fifth terminal and the circuit being open or closed. The first terminal and the third terminal are connected to the common terminal. The fifth terminal is connected to the fourth terminal. The first switching circuit, the second switching circuit, and the third switching circuit each include a first switching element, which is respectively disposed in a first path connecting the first terminal to the second terminal, a second path connecting the third terminal to the fourth terminal, and a plurality of third paths connecting the fifth terminal to the plurality of sixth terminals. The first switching element comprises one or more stacked semiconductor elements. The number of stacked semiconductor elements in the first switching element of the second switching circuit is less than the number of stacked semiconductor elements in the first switching element of the first switching circuit. The first switching circuit and the third switching circuit further include a second switching element, which is respectively configured on the path connecting the first path to ground and the path connecting the plurality of third paths to ground. The number of stacked semiconductor elements of the first switching element in the first switching circuit is equal to the number of stacked semiconductor elements of the second switching element in the first switching circuit, and the number of stacked semiconductor elements of the first switching element in the third switching circuit is equal to the number of stacked semiconductor elements of the second switching element in the third switching circuit.

2. The switching device according to claim 1, wherein, The second switching element of the first switching circuit is disposed between the first switching element and the second terminal of the first switching circuit. The second switching element of the third switching circuit is disposed between the first switching element of the third switching circuit and one of the plurality of sixth terminals. The first switching element and the second switching element operate independently.

3. The switching device according to claim 1 or 2, wherein, The number of stacked semiconductor elements of the first switching element in the second switching circuit is less than the number of stacked semiconductor elements of the first switching element in the third switching circuit.

4. The switching device according to claim 1 or 2, wherein, The number of stacked semiconductor elements of the first switching element in the first switching circuit is equal to the number of stacked semiconductor elements of the first switching element in the third switching circuit.

5. The switching device according to claim 1 or 2, wherein, The number of stacked semiconductor elements of the first switching element in the second switching circuit is one.

6. The switching device according to claim 1 or 2, wherein, The number of stacked semiconductor elements of the first switching element in the first switching circuit is smaller than the sum of the number of stacked semiconductor elements of the first switching element in the second switching circuit and the number of stacked semiconductor elements of the first switching element in the third switching circuit.

7. The switching device according to claim 1 or 2, wherein, When the third terminal and the fourth terminal in the second switching circuit are not connected, the fifth terminal and the plurality of sixth terminals in the third switching circuit are not connected.

8. The switching device according to claim 1 or 2, wherein, The first switching element is a field-effect transistor switch, i.e., a FET switch.

9. The switching device according to claim 8, wherein, The gate width of the semiconductor element of the first switching element in the second switching circuit is larger than at least one of the gate widths of the semiconductor element of the first switching element in the first switching circuit and the gate width of the semiconductor element of the first switching element in the third switching circuit.

10. The switching device according to claim 1 or 2, wherein, The second switching circuit consists only of the first switching element.

11. The switching device according to claim 1 or 2, wherein, The number of stacked semiconductor elements of the first switching element in the first switching circuit and the number of stacked semiconductor elements of the first switching element in the third switching circuit are eight or more.

12. A front-end circuit, comprising: The switching device according to any one of claims 1 to 11; and Multiple filters are respectively connected to the second terminal and the plurality of sixth terminals.

13. The front-end circuit according to claim 12, wherein, The plurality of filters includes: A first filter, having a first frequency band as its passband, and connected to the second terminal; and The second filter has a second frequency band as its passband and is connected to any one of the plurality of sixth terminals. The high-frequency signal of the first frequency band and the high-frequency signal of the second frequency band are sent or received simultaneously.

14. The front-end circuit according to claim 13, wherein, The first frequency band supports power level 2, i.e., PC2.

15. The front-end circuit according to claim 13, wherein, The second frequency band supports power level 3, namely PC3.

16. The front-end circuit according to any one of claims 12 to 15, wherein, It also has: External terminals; and A matching circuit is disposed between the common terminal and the external terminal. The matching circuit has: A first inductor is disposed in the path connecting the common terminal to the external terminal; A second inductor is configured on the path that connects the common terminal and the first inductor to ground. as well as A capacitor is disposed on a path that connects the external terminal and the first inductor to ground.

17. The front-end circuit according to claim 16, wherein, The inductance value of the first inductor is greater than the inductance value of the second inductor.

18. A front-end circuit, comprising: The switching device according to any one of claims 1 to 11; and Multiple filters connected to the second terminal and the plurality of sixth terminals respectively. The front-end circuit also includes: External terminals; and A matching circuit is disposed between the common terminal and the external terminal. The matching circuit has: A first inductor is disposed in the path connecting the common terminal to the external terminal; A second inductor is configured on the path that connects the common terminal and the first inductor to ground. as well as A capacitor, configured to connect the path for connecting the external terminals and the first inductor to ground. The parasitic capacitance of the first switching circuit is set to C1. Set the turn-off capacitor of the first switching element in the second switching circuit to C2. When the parasitic capacitance of the third switching circuit is set to C3, When the second switching circuit is not conducting, the capacitance C4 of the capacitor satisfies the relationship of equation (1), and when the second switching circuit is conducting, the capacitance C4 of the capacitor satisfies the relationship of equation (2). [Formula 1] [Equation 2] 。 19. The front-end circuit according to claim 18, wherein, The inductance value of the first inductor is greater than the inductance value of the second inductor.

20. The front-end circuit according to claim 18, wherein, The plurality of filters includes: A first filter, having a first frequency band as its passband, and connected to the second terminal; and The second filter has a second frequency band as its passband and is connected to any one of the plurality of sixth terminals. The high-frequency signal of the first frequency band and the high-frequency signal of the second frequency band are sent or received simultaneously.

21. The front-end circuit according to claim 20, wherein, The first frequency band supports power level 2, i.e., PC2.

22. The front-end circuit according to claim 20, wherein, The second frequency band supports power level 3, namely PC3.

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