Display panel and manufacturing method, display device

Abstract

A display panel, a manufacturing method thereof and a display device, the display panel comprising: a driving back plate (BM), a transfer layer (TR), a second planarization layer (PLN2) and a light emitting layer (EE); the pixel circuit layer (DR) of the driving back plate (BM) comprises a plurality of data transfer lines (DL3), one end of one data transfer line (DL3) is connected with one data wire (DL), and the other end extends to a binding area (B1); both ends of the first transfer line (TR1) of the transfer layer (TR) are connected with the first via hole (PLN11) and the second via hole (PLN21) corresponding to the first pixel circuit (PDCA1) respectively. In the embodiment of the present disclosure, the setting of the data transfer line (DL3) can avoid the problem of increasing the frame of the display device; the setting of the first transfer line (TR1) can ensure the planarization of the first light emitting unit (EL1).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and its manufacturing method, and a display device. Background Technology

[0002] With the rapid development of display technology, display devices have entered the era of full-screen and narrow-bezel designs. To provide users with a better experience, full-screen and narrow-bezel designs will inevitably become important future development directions. In the research process of full-screen and narrow-bezel designs, the idea of ​​placing data traces located near the bezel (bottom bezel) within the display area has been widely proposed. If the data traces of the bottom bezel are placed within the display area, the width of the bottom bezel can be significantly reduced, thereby further realizing the full-screen and narrow-bezel designs of display devices.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display panel, a manufacturing method thereof, and a display device.

[0005] According to one aspect of this disclosure, a display panel is provided, the display panel including a display area and a peripheral area located outside the display area, the peripheral area including a binding area located on one side of the display area along a column direction, the display panel comprising:

[0006] The driving backplane includes a substrate, a pixel circuit layer and a first planarization layer stacked sequentially.

[0007] The pixel circuit layer includes multiple pixel circuits, multiple data traces, and multiple data adapters. A column of pixel circuits is connected to a data trace. At least a portion of the pixel circuits located in the display area form multiple pixel circuit islands distributed in an array. The multiple data adapters are located in the display area and do not overlap with the pixel circuit islands. One end of a data adapter is connected to a data trace in the display area, and the other end extends to the bonding area.

[0008] The first planarization layer is provided with a plurality of first vias that are connected one-to-one with the plurality of pixel circuits;

[0009] An adapter layer is located on the side of the first planarization layer opposite to the substrate, and includes a first adapter line;

[0010] The second planarization layer is located on the side of the transition layer away from the substrate, and is provided with a plurality of second vias corresponding one-to-one with the plurality of first vias. The plurality of pixel circuit islands include a first pixel circuit, and the two ends of the first transition line are respectively connected to the first via and the second via corresponding to the first pixel circuit.

[0011] The light-emitting layer is located on the side of the second planarization layer opposite to the substrate, and includes a plurality of light-emitting units that are connected to a plurality of second vias in a one-to-one correspondence. The light-emitting area of ​​the light-emitting unit does not overlap with the second via. The plurality of light-emitting units includes a first light-emitting unit, and the light-emitting area of ​​the first light-emitting unit overlaps with the first via corresponding to the first pixel circuit.

[0012] According to any of the display panels described in this disclosure, the plurality of pixel circuit islands includes a second pixel circuit;

[0013] The light-emitting areas of the multiple light-emitting units do not overlap with the first vias corresponding to the second pixel circuit, but the first vias corresponding to the second pixel circuit overlap with the corresponding second vias.

[0014] According to any of the display panels described in this disclosure, the plurality of pixel circuit islands include a second pixel circuit, and the transition layer further includes a second transition wire;

[0015] The light-emitting areas of the multiple light-emitting units do not overlap with the first vias corresponding to the second pixel circuit, the first vias corresponding to the second pixel circuit do not overlap with the corresponding second vias, and the two ends of the second adapter wire are respectively connected to the first via and the second via corresponding to the second pixel circuit.

[0016] According to any of the display panels described in this disclosure, the transition layer includes multiple sub-transition layers and an interlayer insulating layer located between any two adjacent sub-transition layers;

[0017] Each of the multiple sub-transition layers has a first sub-transition line, and each of the interlayer insulating layers has a via. The vias are respectively connected to the first sub-transition lines on both sides of the sub-transition layers. Multiple first sub-transition lines are connected in sequence to form the first transition line.

[0018] According to any of the display panels described in this disclosure, the pixel circuit layer includes a transistor layer, a first source / drain metal layer, a third planarization layer, and a second source / drain metal layer stacked sequentially in a direction away from the substrate.

[0019] The second source / drain metal layer includes multiple pairs of power traces distributed along the row direction and extending along the column direction. Each pair of power traces encloses multiple clearance areas. The second source / drain metal layer also includes a pair of transition electrodes located in the clearance areas and extending along the column direction. Among the multiple transition electrodes, there is a first transition electrode corresponding to the first pixel circuit. The first transition electrode is connected to the first source / drain metal layer and the first end of the first transition line, respectively.

[0020] The light-emitting layer further includes a pixel definition layer disposed on the surface of the first planarization layer away from the substrate. The pixel definition layer has pixel openings corresponding to the plurality of light-emitting units. The light-emitting unit includes a first electrode, an organic light-emitting layer, and a second electrode stacked sequentially along one side away from the second planarization layer. The first electrode includes an exposed area exposed at the corresponding pixel opening and a covered area covered by the pixel definition layer. The exposed area of ​​the first electrode forms the light-emitting area of ​​the corresponding light-emitting unit. The second end of the first adapter cable is connected to the covered area of ​​a light-emitting unit.

[0021] According to any of the display panels described in this disclosure, the first adapter cable extends along the row direction, and the first end of the first adapter cable overlaps with at least a portion of the first adapter electrode, the first via corresponding to the first pixel circuit, and the exposed area of ​​the first light-emitting unit. The second end of the first adapter cable overlaps with the second via corresponding to the first pixel circuit and the covered area of ​​the first light-emitting unit.

[0022] According to any of the display panels described in this disclosure, the first adapter cable extends along the row direction, and the first end of the first adapter cable overlaps with at least a portion of the first adapter electrode, the first via corresponding to the first pixel circuit, and the exposed area of ​​the first light-emitting unit. The second end of the first adapter cable overlaps with the second via corresponding to the first pixel circuit and the covered area of ​​the second light-emitting unit among the plurality of light-emitting units. The second light-emitting unit is adjacent to the first light-emitting unit.

[0023] According to any of the display panels described in this disclosure, the transition layer further includes a second transition wire, and the plurality of transition electrodes includes a second transition electrode corresponding to the second pixel circuit;

[0024] At least a portion of the second transfer electrode overlaps with the first via corresponding to the second pixel circuit, but does not overlap with the exposed areas of the plurality of light-emitting units;

[0025] The second adapter line extends along the row direction. The first end of the second adapter line overlaps with at least a portion of the second adapter electrode. The second end of the second adapter line overlaps with the second via corresponding to the second pixel circuit and the coverage area of ​​the third light-emitting unit among the plurality of light-emitting units.

[0026] According to any of the display panels described in this disclosure, the data transfer cable includes a first section of trace and a second section of trace;

[0027] The first segment of the trace extends along the row direction, the second segment of the trace extends along the column direction, one end of the first segment of the trace is connected to a data trace, the other end is connected to one end of the second segment of the trace, and the other end of the second segment of the trace extends to the binding area.

[0028] The first segment of the data adapter cable and part of the second segment of the data adapter cable are located in the first source-drain metal layer, and the remaining second segment of the data adapter cable is located in the second source-drain metal layer.

[0029] According to any of the display panels described in this disclosure, the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a storage capacitor;

[0030] The control electrode of the first transistor is used to load a capacitor reset control signal, the first electrode of the first transistor is used to load an initial voltage signal, and the second electrode of the first transistor is connected to the first electrode of the second transistor, the control electrode of the third transistor, and one end of the storage capacitor.

[0031] The control electrode of the second transistor is used to load the first scan signal, and the second electrode of the second transistor is connected to the first electrode of the third transistor and the first electrode of the sixth transistor;

[0032] The second terminal of the third transistor is connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor. The control terminal of the fourth transistor is used to load the second scan signal, the second terminal of the fourth transistor is used to load the drive data signal, the control terminal of the fifth transistor is used to load the enable signal, and the second terminal of the fifth transistor is connected to the other end of the storage capacitor and is used to load the power supply voltage signal.

[0033] The control electrode of the sixth transistor is used to load an enable signal. The second electrode of the sixth transistor is connected to the first electrode of the seventh transistor and is used to connect to the corresponding light-emitting unit. The control electrode of the seventh transistor is used to load an electrode reset control signal, and the second electrode of the seventh transistor is used to load an initial voltage signal.

[0034] According to any of the display panels described in this disclosure, the pixel circuit layer includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and a source / drain metal layer;

[0035] The first semiconductor layer includes the active layers of each of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second semiconductor layer is provided with the active layers of the first transistor and the second transistor.

[0036] The first gate metal layer is provided with a first scan trace and an enable signal line extending along the row direction and arranged sequentially along the column direction, and a first electrode plate located between the first scan trace and the enable signal line and spaced apart along the row direction. The first scan trace is used to load the first scan signal, and the enable signal line is used to load the enable signal.

[0037] The second gate metal layer is provided with an initial voltage trace, a first reset control line and a second scan trace extending along the row direction and arranged sequentially along the column direction, and a second electrode plate located on the side of the second scan trace away from the first reset control line and spaced apart along the row direction. The initial voltage trace is used to load the initial voltage signal, the first reset control line is used to load the capacitor reset control signal, and the second scan trace is used to load the second scan signal.

[0038] The third gate metal layer is provided with a second reset control line and a third scan line extending along the row direction and arranged sequentially along the column direction. The second reset control line is used to load the electrode reset control signal, and the third scan line is used to load the second scan signal.

[0039] The initial voltage trace and the first reset control line are located on the side of the first scan trace away from the enable signal line. The second scan trace and the second electrode are located between the first scan trace and the enable signal line, and the second electrode overlaps with the first electrode. The second reset control line is located between the initial voltage trace and the first scan trace, and overlaps with the first reset control line. The third scan line is located between the first scan trace and the second electrode, and overlaps with the second scan trace.

[0040] The transition layer includes transition lines extending along the row direction. In the pixel circuit island, the transition line corresponding to the upper row of pixel circuits in two adjacent rows is located on the side of the enable signal line closer to the second electrode plate and overlaps with the second electrode plate. The transition line corresponding to the lower row of pixel circuits is located on the side of the enable signal line away from the second electrode plate.

[0041] According to any of the display panels described in this disclosure, the display area includes a transparent display area and a normal display area located around the transparent display area;

[0042] The pixel circuit distribution density of the transparent display area is less than that of the pixel circuit distribution density of the normal display area. The plurality of pixel circuits include a third pixel circuit located in the normal display area. The adapter layer also includes a third adapter wire, the two ends of which are respectively connected to the third pixel circuit and a light-emitting unit of the transparent display area.

[0043] According to any of the display panels described in this disclosure, the display area includes a main display area and a secondary display area located on one or both sides of the main display area along the row direction;

[0044] Multiple pixel circuit islands and multiple data adapter cables are located in the main display area, and one end of one of the data adapter cables extends into the sub-display area and connects to a data trace, while the other end extends into the bonding area.

[0045] According to any of the display panels described in this disclosure, the material of the first adapter cable is a transparent conductive material.

[0046] According to a second aspect of this disclosure, a method for manufacturing a display panel is provided, comprising:

[0047] Fabricate a driving backplane, the driving backplane comprising a substrate, a pixel circuit layer, and a first planarization layer stacked sequentially.

[0048] The display panel includes a display area and a peripheral area located outside the display area. The peripheral area includes a bonding area located on one side of the display area along the column direction. The pixel circuit layer includes multiple pixel circuits, multiple data traces, and multiple data adapter lines. A column of the pixel circuits is connected to a data trace. At least a portion of the pixel circuits located in the display area form multiple pixel circuit islands distributed in an array. The multiple data adapter lines are located in the display area and do not overlap with the pixel circuit islands. One end of a data adapter line is connected to a data trace in the display area, and the other end extends to the bonding area. The first planarization layer is provided with multiple first vias that are connected to the multiple pixel circuits one by one.

[0049] An adapter layer is formed on the side of the first planarization layer opposite to the substrate, the adapter layer including a first adapter line;

[0050] A second planarization layer is formed on the side of the transition layer away from the substrate. The second planarization layer has a plurality of second vias that correspond one-to-one with the plurality of first vias. The plurality of pixel circuit islands include a first pixel circuit. The two ends of the first transition line are respectively connected to the first via and the second via corresponding to the first pixel circuit.

[0051] A light-emitting layer is formed on the side of the second planarization layer away from the substrate. The light-emitting layer includes a plurality of light-emitting units that are connected one-to-one with a plurality of second vias. The light-emitting area of ​​the light-emitting unit does not overlap with the second via. The plurality of light-emitting units include a first light-emitting unit. The light-emitting area of ​​the first light-emitting unit overlaps with the first via corresponding to the first pixel circuit.

[0052] According to a third aspect of this disclosure, a display device is provided, comprising the display panel described in the first aspect above.

[0053] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0055] Figure 1 This is a cross-sectional structural diagram of a display panel provided for an embodiment of the present disclosure.

[0056] Figure 2 This is a schematic diagram of the structure of a display panel provided for an embodiment of this disclosure.

[0057] Figure 3 This is a schematic diagram of the arrangement of a data transfer cabling provided for an embodiment of the present disclosure.

[0058] Figure 4 This is a schematic diagram of the routing of a first source / drain metal layer provided for an embodiment of this disclosure.

[0059] Figure 5 This is a schematic diagram of the routing of a second source / drain metal layer provided for an embodiment of this disclosure.

[0060] Figure 6 This is a schematic diagram of a stacked structure of a pixel circuit and a light-emitting unit provided for an embodiment of this disclosure.

[0061] Figure 7This is a cross-sectional structural diagram of another display panel provided in an embodiment of the present disclosure.

[0062] Figure 8 This is a cross-sectional structural diagram of another display panel provided in this embodiment of the present disclosure.

[0063] Figure 9 This is a schematic diagram of the wiring of another second source / drain metal layer provided in an embodiment of this disclosure.

[0064] Figure 10 This is a schematic diagram of the routing of another second source / drain metal layer provided in an embodiment of this disclosure.

[0065] Figure 11 This is a schematic diagram of a structure in which a second source / drain metal layer and a light-emitting unit are stacked, as provided in an embodiment of this disclosure.

[0066] Figure 12 This is a schematic diagram of another structure of a second source / drain metal layer and a light-emitting unit stacked together, provided for an embodiment of this disclosure.

[0067] Figure 13 This is a schematic diagram of a pixel circuit provided for an embodiment of the present disclosure.

[0068] Figure 14 This is a perspective structural diagram of a display panel provided for an embodiment of the present disclosure.

[0069] Figure 15 This is a partial structural diagram of a first semiconductor layer provided for an embodiment of the present disclosure.

[0070] Figure 16 This is a schematic diagram of the structure of a first semiconductor layer in a pixel circuit region, provided for an embodiment of this disclosure.

[0071] Figure 17 This is a partial structural diagram of a first gate metal layer provided for an embodiment of the present disclosure.

[0072] Figure 18 This is a partial structural diagram of a second gate metal layer provided for an embodiment of the present disclosure.

[0073] Figure 19 This is a partial structural diagram of a second semiconductor layer provided for an embodiment of the present disclosure.

[0074] Figure 20 This is a schematic diagram of the structure of a second semiconductor layer in the pixel circuit region, provided for an embodiment of this disclosure.

[0075] Figure 21 This is a partial structural diagram of a third gate metal layer provided for an embodiment of the present disclosure.

[0076] Figure 22 This is a schematic diagram of a pixel circuit layer and a transition layer stacked structure provided for an embodiment of this disclosure.

[0077] Figure 23 This is a partial structural diagram of a transition layer provided in an embodiment of the present disclosure.

[0078] Figure 24 This is a schematic diagram of another display panel provided in an embodiment of the present disclosure.

[0079] Figure 25 This is a schematic flowchart of a display panel manufacturing method provided for an embodiment of the present disclosure. Detailed Implementation

[0080] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0081] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0082] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0083] This disclosure provides a display device including a display panel. The display panel enables a full-screen display and narrow bezel design while ensuring the flatness of the light-emitting area of ​​the light-emitting unit, thereby avoiding color shift issues when displaying images. Thus, a display device including this display panel can achieve a full-screen display and narrow bezel design while maintaining good image display quality.

[0084] The display panel will now be explained in detail through the following implementation method.

[0085] This disclosure provides a display panel. For example... Figure 1 As shown, the display panel includes a driving backplane BM and an emissive layer EE. The driving backplane BM includes a substrate BP, a pixel circuit layer DR, and a first planarization layer PLN1 stacked sequentially.

[0086] The pixel circuit layer DR includes multiple pixel circuits PDCA, the first planarization layer PLN1 is provided with multiple first vias PLN11, and the light-emitting layer EE includes multiple light-emitting units EL distributed in an array. The multiple pixel circuits PDCA, multiple first vias PLN11, and multiple light-emitting units EL correspond one-to-one. Each first via PLN11 is connected to the corresponding pixel circuit PDCA and the light-emitting unit EL, so that the corresponding light-emitting unit EL can be controlled to emit light under the drive of the pixel circuit PDCA.

[0087] In this disclosure, the substrate BP can be an inorganic material substrate or an organic light-emitting substrate. For example, in some embodiments, the substrate BP can be made of glass materials such as soda-lime glass, quartz glass, and sapphire glass, or metal materials such as stainless steel, aluminum, and nickel. In other embodiments, the substrate BP can be made of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyethersulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or combinations thereof.

[0088] Optionally, the substrate BP can be a single-layer material or a composite of multiple materials. For example, in some embodiments, the substrate BP includes a base film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked sequentially.

[0089] In this embodiment of the disclosure, any pixel circuit PDCA may include multiple transistors and storage capacitors. Further, the transistors may be thin-film transistors, selected from top-gate, bottom-gate, or dual-gate thin-film transistors; the active layer of the thin-film transistor may be made of amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal-oxide semiconductor material, organic semiconductor material, or other types of semiconductor material; the thin-film transistor may be an N-type or P-type thin-film transistor.

[0090] It is understood that among the multiple transistors included in a pixel circuit PDCA, any two transistors may be of the same or different types. For example, in some embodiments, some transistors in a pixel circuit PDCA may be N-type transistors and some may be P-type transistors. Further exemplarily, in other embodiments, the active layer material of some transistors in a pixel circuit PDCA may be low-temperature polycrystalline silicon semiconductor material, and the active layer material of some transistors may be metal-oxide-semiconductor material.

[0091] In this embodiment of the disclosure, the pixel circuit layer DR includes a transistor layer, an interlayer electrolyte layer ILD, and a source / drain metal layer sequentially stacked on the substrate BP.

[0092] Optionally, the transistor layer may include a semiconductor layer, a gate insulating layer, and a gate metal layer stacked between the substrate (BP) and the interlayer electrolyte layer (ILD). The positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor.

[0093] In some embodiments, the transistor layer may include a semiconductor layer, a gate insulating layer, and a gate metal layer stacked sequentially, thus forming a top-gate thin-film transistor. In other embodiments, the transistor layer may include a gate metal layer, a gate insulating layer, and a semiconductor layer stacked sequentially, thus forming a bottom-gate thin-film transistor.

[0094] In some embodiments, the semiconductor layer can be used to form the active layer of a transistor. The active layer includes a channel region and source and drain electrodes located on both sides of the channel region. The channel region can maintain semiconductor characteristics, and the semiconductor materials of the source and drain electrodes are partially or completely conductive. The gate metal layer can be used to form gate metal layer traces such as scan lines, enable signal lines (EML), and reset control lines, and can also be used to form part or all of the electrode plates of a storage capacitor. The source and drain metal layers can be used to form source and drain metal layer traces such as data lines (DL), power lines (VDDL), and conductive structures.

[0095] In some embodiments, the semiconductor layer can be a single semiconductor layer or two semiconductor layers. For example, in some embodiments, the semiconductor layer may include a low-temperature polysilicon semiconductor layer and a metal-oxide-semiconductor layer. The gate metal layer can be a single gate metal layer, or two or three gate metal layers. For example, in some embodiments, the gate metal layer may include a first gate metal layer LG1, a second gate metal layer LG2, and a third gate metal layer LG3.

[0096] It is understood that when the gate metal layer or semiconductor layer has a multilayer structure, the insulating layer in the transistor layer can be adaptively added or removed. For example, in some embodiments, such as... Figure 1 As shown, the pixel circuit layer DR includes transistor layers that may be sequentially stacked on the substrate BP, such as a first semiconductor layer LPoly (low-temperature polysilicon semiconductor layer), a first gate insulating layer GI1, a first gate metal layer LG1, a second gate insulating layer GI2 (e.g., an inorganic layer such as silicon nitride or silicon oxide), a second gate metal layer LG2, a third gate insulating layer GI3, a second semiconductor layer LOxide (metal oxide semiconductor layer), a fourth gate insulating layer GI4, and a third gate metal layer LG3.

[0097] Optionally, the source / drain metal layer can be a single layer, or it can be two or three layers. For example, in some embodiments, such as... Figure 1 As shown, the pixel circuit layer DR includes source / drain metal layers, which may include a first source / drain metal layer LSD1 and a second source / drain metal layer LSD2. A third planarization layer PLN3 may be disposed between the first source / drain metal layer LSD1 and the second source / drain metal layer LSD2, or a passivation layer PVX and a third planarization layer PLN3 may be disposed. The first source / drain metal layer LSD1 can be used to set conductive structures, and the second source / drain metal layer LSD2 can be used to set power traces VDDL and data traces DL.

[0098] Optionally, such as Figure 1As shown, the pixel circuit layer DR may further include an insulating buffer layer Buff disposed between the substrate BP and the semiconductor layer, with the semiconductor layer, gate metal layer, etc., located on the side of the insulating buffer layer Buff away from the substrate BP. The material of the insulating buffer layer Buff can be an inorganic insulating material such as silicon oxide or silicon nitride. The insulating buffer layer Buff can be a single inorganic material layer or multiple stacked inorganic material layers.

[0099] Optionally, a light-shielding layer may be provided between the insulating buffer layer Buff and the substrate BP. The light-shielding layer may overlap with at least part of the channel region of the transistor to block the light shining on the transistor, thereby stabilizing the electrical characteristics of the transistor.

[0100] In this disclosure, the light-emitting unit EL can be an organic light-emitting diode, a micro light-emitting diode, a quantum dot-organic light-emitting diode, a quantum dot light-emitting diode, or other types of light-emitting unit EL. Exemplarily, in some embodiments, the light-emitting unit EL is an organic light-emitting diode, and the display panel is an OLED display panel. Below, taking an organic light-emitting diode as an example, a feasible structure of the light-emitting layer EE is described exemplarily.

[0101] Optionally, such as Figure 1 As shown, the light-emitting layer EE also includes a pixel definition layer PDL disposed on the surface of the first planarization layer PLN1 away from the substrate BP. The pixel definition layer PDL has pixel openings corresponding to a plurality of light-emitting units EL. The light-emitting unit EL includes a first electrode LAn1, an organic light-emitting layer LEL, and a second electrode LCOM1 stacked sequentially along one side away from the second planarization layer PLN2. The first electrode LAn1 includes an exposed area LAn2 exposed at the corresponding pixel opening and a covered area LAn3 covered by the pixel definition layer PDL. The exposed area LAn2 of the first electrode LAn1 forms the light-emitting area of ​​the corresponding light-emitting unit EL.

[0102] The organic light-emitting layer (LEL) may include an organic electroluminescent material layer, and may include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0103] In some implementations, such as Figure 1 As shown, the display panel may also include a thin-film encapsulation layer (TEF). The TEF is disposed on the surface of the light-emitting layer (EE) away from the substrate (BP), and may include alternately stacked inorganic and organic encapsulation layers. The inorganic encapsulation layer effectively blocks external moisture and oxygen, preventing water and oxygen from intruding into the organic light-emitting functional layer and causing material degradation. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers.

[0104] The edge of the inorganic encapsulation layer can be located in the peripheral region BB. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the light-emitting layer EE away from the substrate BP.

[0105] In some embodiments, the display panel may further include a touch function layer disposed on the side of the thin film encapsulation layer away from the substrate BP, for realizing touch operation of the display panel.

[0106] In some embodiments, the display panel may further include an anti-reflection layer, which may be disposed on the side of the thin-film encapsulation layer away from the light-emitting layer EE. Further, the anti-reflection layer may be disposed on the side of the touch functional layer away from the substrate BP. The anti-reflection layer is used to reduce the reflection of ambient light by the display panel, thereby reducing the impact of ambient light on the display effect.

[0107] Optionally, the anti-reflection layer may include a color filter layer and a black matrix layer stacked together, thus reducing ambient light interference while avoiding reducing the light transmittance of the display panel. Alternatively, the anti-reflection layer may be a polarizer, such as a patterned coated circular polarizer.

[0108] This disclosure provides a display panel. For example... Figure 2 As shown, the display panel includes a display area AA and an outer peripheral area BB located outside the display area AA. The outer peripheral area BB includes a binding area B1 located on one side of the display area AA along the column direction H2.

[0109] The pixel circuit layer DR also includes multiple data traces DL, and multiple pixel circuits PDCA form multiple columns. Each column of pixel circuits PDCA is connected to a data trace DL.

[0110] like Figure 2 As shown, the display area AA includes a main display area AA1 and a secondary display area AA2 located on one or both sides of the main display area AA1 along the row direction H1. Multiple data traces DL include a first data trace DL1 located in the main display area AA1 and a second data trace DL2 located in the secondary display area AA2. The first data trace DL1 in the main display area AA1 extends directly to the bonding area B1 to bond with the external circuit. If the second data trace DL2 in the secondary display area AA2 were to extend directly to the bonding area B1, it would inevitably increase the bezel width of the display device. To achieve a full-screen display with a narrow bezel, a data adapter cable DL3 is needed to connect the second data trace DL2 in the secondary display area AA2, allowing it to extend from the main display area AA1 to the bonding area B1.

[0111] Thus, the pixel circuit layer DR also includes multiple data transfer lines DL3, which are located in the display area AA. One end of each data transfer line DL3 is connected to a data trace DL within the display area AA, and the other end extends to the bonding area B1. Considering the aforementioned case where the display area AA includes a main display area AA1 and a sub-display area AA2, as... Figure 2 As shown, multiple data adapter cables DL3 are located in the main display area AA1, and one end of each data adapter cable DL3 is connected to a second data trace DL2 (that is, one end of each data adapter cable DL3 is connected to a data trace DL within the sub-display area AA2), while the other end extends to the bonding area B1. Thus, through the conversion function of the data adapter cables DL3, the second data trace DL2 (the data trace DL in the sub-display area AA2) is adjusted to extend from the main display area AA1 to the bonding area B1, thereby avoiding the technical problem of increasing the bezel of the display device due to the second data trace DL2 directly extending to the bonding area B1.

[0112] To facilitate the placement of multiple data transfer cables DL3 in the display panel while avoiding positional conflicts with pixel circuits PDCA, the pixel circuits PDCA can be compressed (i.e., the line width and spacing of the pixel circuits PDCA can be compressed) to create gaps between two pixel circuits PDCA for arranging the data transfer cables DL3. In other words, at least a portion of the pixel circuits PDCA in the display area AA is compressed to obtain multiple pixel circuit islands PDCC distributed in an array.

[0113] Based on the distribution of the multiple data adapter cables DL3 described above (located in the main display area AA1), as follows: Figure 3 As shown, at least a portion of the pixel circuits PDCA located in the main display area AA1 form multiple pixel circuit islands PDCC distributed in an array, where multiple data transfer lines DL3 do not overlap with the pixel circuit islands PDCC. For example, the data transfer lines DL3 are located in the gaps between adjacent pixel circuit islands PDCC. Of course, since multiple data transfer lines DL3 need to be connected to multiple second data traces DL, at least a portion of the pixel circuits PDCA in the sub-display area AA2 can also be compressed to obtain multiple pixel circuit islands PDCC.

[0114] In this method, compression can be performed grouped by one pixel circuit PDCA to obtain a pixel circuit island PDCC containing one pixel circuit PDCA, or it can be performed grouped by four pixel circuit PDCA to obtain a pixel circuit island PDCC containing four pixel circuit PDCA, or as follows. Figure 3As shown, compression is performed by grouping eight pixel circuits (PDCA) together to obtain a pixel circuit island (PDCC) comprising eight pixel circuits (PDCA). Of course, compression can also be performed by grouping other numbers of pixel circuits (PDCA), and this embodiment of the present disclosure is not limited to this.

[0115] In some implementations, such as Figure 2 or Figure 3 As shown, the data adapter cable DL3 includes a first segment DL31 extending along the row direction H1 and a second segment DL32 extending along the column direction H2. One end of the first segment DL31 is connected to a data line DL (a second data line DL2 in the sub-display area AA2), and the other end is connected to one end of the second segment DL32. The other end of the second segment DL32 extends to the binding area B1.

[0116] In summary, as described above, Figure 3 As shown, the gaps in the pixel circuit island PDCC include row gaps along the row direction H1 and column gaps along the column direction H2. The first trace DL31 is located in the row gap of the pixel circuit island PDCC, and the second trace DL32 is located in the column gap of the pixel circuit island PDCC. In conjunction with the above, when the source / drain metal layers include a first source / drain metal layer LSD1 and a second source / drain metal layer LSD2, as... Figure 4 and Figure 5 As shown, the multiple data transfer lines DL3 include multiple first traces DL31 located in the first source-drain metal layer LSD1. A portion of the second traces DL32 in the multiple data transfer lines DL3 are located in the first source-drain metal layer LSD1, and the remaining portion of the second traces DL32 are located in the second source-drain metal layer LSD2. The second traces DL32 in the second source-drain metal layer LSD2 are connected to the corresponding first traces DL31 in the first source-drain metal layer LSD1 via vias penetrating the third planarization layer PLN3, or vias penetrating the passivation layer PVX and the third planarization layer PLN3.

[0117] Among them, such as Figure 4 As shown, the first source / drain metal layer LSD1 also includes a compensation metal trace LDummy, which is located in the gap between two adjacent pixel circuit islands PDCC. The LDummy's placement avoids uneven metal trace distribution in the first source / drain metal layer LSD1. The LDummy can be connected to the power trace VDDL of the second source / drain metal layer LSD2 via a via.

[0118] In this embodiment of the disclosure, when compressing the pixel circuit PDCA, the first via PLN11 corresponding to a portion of the pixel circuit PDCA will shift to directly below the light-emitting area (exposed area LAn2 of the first electrode LAn1) of the light-emitting unit EL, that is, as shown in the figure. Figure 6 As shown, the multiple pixel circuit islands PDCC include a first pixel circuit PDCA1, and the multiple light-emitting units EL include a first light-emitting unit EL1. The light-emitting area of ​​the first light-emitting unit EL1 overlaps with the first via PLN11 corresponding to the first pixel circuit PDCA1. Therefore, if the light-emitting layer EE is fabricated directly on the side of the first planarization layer PLN1 facing away from the substrate BP, the light-emitting area of ​​the first light-emitting unit EL1 will exhibit unevenness at the first via PLN11 corresponding to the first pixel circuit PDCA1, resulting in color shift when the display panel shows the image.

[0119] Thus, in order to ensure the planarization of the first light-emitting unit EL1, such as Figure 1 As shown, the display panel also includes a transition layer TR and a second flattening layer PLN2 located between the first flattening layer PLN1 and the light-emitting layer EE, with the transition layer TR located on the side closer to the first flattening layer PLN1.

[0120] The overlapping portion mentioned in this disclosure refers to the fact that the orthographic projections of the two on the substrate BP at least partially overlap. For example, if the light-emitting area of ​​the first light-emitting unit EL1 and the first via PLN11 corresponding to the first pixel circuit PDCA1 have an overlapping portion, it means that the orthographic projection of the light-emitting area of ​​the first light-emitting unit EL1 on the substrate BP at least partially overlaps with the orthographic projection of the first via PLN11 corresponding to the first pixel circuit PDCA1 on the substrate BP.

[0121] The second planarization layer PLN2 has multiple second vias PLN21 corresponding to the multiple first vias PLN11. Each of the multiple second vias PLN21 is connected to a multiple light-emitting unit EL, and the light-emitting area of ​​the light-emitting unit EL does not overlap with the second via PLN21. Figure 1 and Figure 6 As shown, the adapter layer TR includes a first adapter line TR1. One end of the first adapter line TR1 is connected to the first via PLN11 corresponding to the first pixel circuit PDCA1, and the other end of the first adapter line TR1 is connected to the second via PLN21 corresponding to the first pixel circuit PDCA1, so as to realize the connection between the first pixel circuit PDCA1 and the corresponding light-emitting unit EL.

[0122] The first adapter line TR1 can be made of a transparent conductive material, or it can be made of a non-transparent conductive material. This disclosure does not limit the specific material used.

[0123] The term "non-overlapping" as used in this disclosure refers to the fact that the orthographic projection of one element on the substrate BP is outside the orthographic projection of the other element on the substrate BP. For example, the non-overlapping of the light-emitting area of ​​the light-emitting unit EL and the second via PLN21 means that the orthographic projection of the light-emitting area of ​​the light-emitting unit EL on the substrate BP is outside the orthographic projection of the second via PLN21 on the substrate BP.

[0124] Thus, by setting the first adapter cable TR1, the connection point of the first light-emitting unit EL1 is moved from the first via PLN11 to the position of the second via PLN21. This ensures the planarization of the first light-emitting unit EL1 during the subsequent fabrication of the light-emitting layer EE, thereby preventing color shift issues in the displayed image of the resulting display panel. Combining the aforementioned structures of the light-emitting layer EE and the light-emitting unit EL, the first adapter cable TR1 ensures the planarization of the subsequently fabricated first electrode LAn1, further preventing color shift issues in the displayed image of the resulting display panel.

[0125] The first light-emitting unit EL1 can be a light-emitting unit EL connected to the first pixel circuit PDCA1, or it can be a light-emitting unit EL that is not connected to the first pixel circuit PDCA1. For details, please refer to the explanation of the relative position of the first adapter line TR1 and the first light-emitting unit EL1 below.

[0126] Of course, when the pixel circuit PDCA is compressed, the first via PLN11 corresponding to the other part of the pixel circuit PDCA in the multiple pixel circuit islands PDCC will not be shifted to the direct under the light-emitting unit EL. That is, the multiple pixel circuit islands PDCC include the second pixel circuit PDCA2, and the light-emitting area of ​​the multiple light-emitting units EL and the first via PLN11 corresponding to the second pixel circuit PDCA2 do not overlap.

[0127] Thus, when connecting the second pixel circuit PDCA2 to the corresponding light-emitting unit EL, the first via PLN11 and the second via PLN21 corresponding to the second pixel circuit PDCA2 can be directly connected, or they can be connected through the second adapter cable TR2.

[0128] For example, the first via PLN11 and the corresponding second via PLN21 of the second pixel circuit PDCA2 overlap. Thus, the first via PLN11 and the corresponding second via PLN21 of the second pixel circuit PDCA2 are directly connected, thereby connecting the second pixel circuit PDCA2 to the corresponding light-emitting unit EL. Alternatively, the first via PLN11 and the corresponding second via PLN21 of the second pixel circuit PDCA2 do not overlap, that is, the first via PLN11 and the corresponding second via PLN21 of the second pixel circuit PDCA2 are misaligned. In this case, ... Figure 6 and Figure 7As shown, the adapter layer TR includes a second adapter line TR2. The two ends of the second adapter line TR2 are connected to the first via PLN11 and the second via PLN21 corresponding to the second pixel circuit PDCA2, respectively, so as to realize the connection between the second pixel circuit PDCA2 and the corresponding light-emitting unit EL.

[0129] The second adapter wire TR2 can be made of a transparent conductive material, or it can be made of a non-transparent conductive material. This disclosure does not limit the type of material used.

[0130] It should be noted that, compared to the direct connection method, the connection method using the second adapter cable TR2 avoids the increased manufacturing difficulty caused by ensuring accurate alignment between the second via PLN21 corresponding to the second pixel circuit PDCA2 and the corresponding first via PLN11 when setting the second via PLN21 on the second planarization layer PLN2.

[0131] In this embodiment of the disclosure, the transition layer TR can be a single-layer structure, that is, the transition layer TR is a single-layer routing layer including a first transition line TR1 and a second transition line TR2. Of course, the transition layer TR can also be a multi-layer structure, that is, the transition layer TR can include multiple sub-transition layers TR and interlayer insulation layers located between any two adjacent sub-transition layers TR. Since the thickness of the interlayer insulation layer is relatively thin, stacking multiple routing layers can increase the thickness of the routing layer, thereby reducing the transmission resistance. For example, such as... Figure 8 As shown, the transition layer TR includes three sub-transition layers TRa and two interlayer insulating layers, which are stacked alternately.

[0132] Each of the multiple sub-transition layers TRa has a first sub-transition line, and each interlayer insulating layer has a via. These vias connect to the first sub-transition lines on the sub-transition layers TRa located on either side of the corresponding interlayer insulating layer. Multiple such first sub-transition lines connect to form a first transition line TR1, thereby connecting the first via PLN11 and the corresponding second via PLN21 of the first pixel circuit PDCA1. Similarly, each of the multiple sub-transition layers TRa has a second sub-transition line. Multiple second sub-transition lines connect through vias in the interlayer insulating layers to form a second transition line TR2, thereby connecting the first via PLN11 and the corresponding second via PLN21 of the second pixel circuit PDCA2.

[0133] In this embodiment, the orthographic projections of the multiple first sub-adapter lines on the substrate BP can completely overlap or partially overlap, as long as it can be ensured that the multiple first sub-adapter lines are connected through vias on the interlayer insulating layer. This disclosure does not limit this aspect.

[0134] In this disclosure, considering the case where the source / drain metal layer includes a second source / drain metal layer LSD2, and the case where the first electrode LAn1 of the light-emitting unit EL includes an exposed area LAn2 and a covered area LAn3, as follows: Figure 5 , Figure 9 or Figure 10 As shown, the second source / drain metal layer LSD2 includes multiple pairs of power traces VDDL distributed along the row direction H1 and extending along the column direction H2, with each pair of power traces VDDL enclosing multiple clearance areas; the second source / drain metal layer LSD2 also includes a pair of transition electrodes PA located in the clearance areas.

[0135] Among them, the two power traces VDDL included in each pair of power traces VDDL can overlap with each other (e.g., Figure 9 (as shown), or integrated settings (such as...) Figure 10 (As shown). Of course, there can also be a certain gap between the two power supply lines VDDL, and this disclosure does not limit this. Among the multiple transition electrodes PA, there is a first transition electrode PA corresponding to the first pixel circuit PDCA1. The first transition electrode PA1 is connected to the first source / drain metal layer LSD1 and the first end of the first transition line TR1, respectively. The second end of the first transition line TR1 is connected to the coverage area LAn3 of a light-emitting unit EL. The transition electrode PA can extend along the column direction H2 or along the row direction H1, and this disclosure does not limit this.

[0136] In some implementations, such as Figure 11 As shown, the first adapter line TR1 extends along the row direction H1. The first end of the first adapter line TR1 overlaps with at least a portion of the first adapter electrode PA1, the first via PLN11 corresponding to the first pixel circuit PDCA1, and the exposed area LAn2 of the first light-emitting unit EL1. The second end of the first adapter line TR1 overlaps with the second via PLN21 corresponding to the first pixel circuit PDCA1 and the covered area LAn3 of the first light-emitting unit EL1.

[0137] Here, the first light-emitting unit EL1 refers to the light-emitting unit EL that is connected to the first pixel circuit PDCA1 among multiple light-emitting units EL. In order to realize the connection between the first pixel circuit PDCA1 and the first light-emitting unit EL1, and at the same time ensure the flattening of the exposed area LAn2 of the first light-emitting unit EL1, the via (second via PLN21) connected to the first light-emitting unit EL1 can be transferred to the covered area LAn3 of the first light-emitting unit EL1 through the first adapter wire TR1. That is, the second end of the first adapter wire TR1 overlaps with the covered area LAn3 of the first light-emitting unit EL1.

[0138] In some implementations, such as Figure 12As shown, the first adapter line TR1 extends along the row direction H1. The first end of the first adapter line TR1 overlaps with at least a portion of the first adapter electrode PA1, the first via PLN11 corresponding to the first pixel circuit PDCA1, and the exposed area LAn2 of the first light-emitting unit EL1. The second end of the first adapter line TR1 overlaps with the second via PLN21 corresponding to the first pixel circuit PDCA1 and the covered area LAn3 of the second light-emitting unit EL2 among the multiple light-emitting units EL. The second light-emitting unit EL2 is adjacent to the first light-emitting unit EL1.

[0139] Here, the second light-emitting unit EL2 refers to the light-emitting unit EL among multiple light-emitting units EL that is connected to the first pixel circuit PDCA1. The first light-emitting unit EL1 and the second light-emitting unit EL2 are adjacent. In order to realize the connection between the first pixel circuit PDCA1 and the second light-emitting unit EL2, while ensuring the flattening of the exposed area LAn2 of the first light-emitting unit EL1, the via (first via PLN11) directly below the first light-emitting unit EL1 can be transferred to the covered area LAn3 of the second light-emitting unit EL2 through the first adapter wire TR1. That is, the second end of the first adapter wire TR1 overlaps with the covered area LAn3 of the second light-emitting unit EL2.

[0140] In some implementations, such as Figure 11 As shown, the transition layer TR also includes a second transition line TR2, and among the multiple transition electrodes PA, there is a second transition electrode PA2 corresponding to the second pixel circuit PDCA2; at least a portion of the second transition electrode PA2 overlaps with the first via PLN11 corresponding to the second pixel circuit PDCA2, and does not overlap with the exposed areas LAn2 of the multiple light-emitting units EL; the second transition line TR2 extends along the row direction H1, the first end of the second transition line TR2 overlaps with at least a portion of the second transition electrode PA2, and the second end of the second transition line TR2 overlaps with the second via PLN21 corresponding to the second pixel circuit PDCA2 and the coverage area LAn3 of the third light-emitting unit EL3 among the multiple light-emitting units EL.

[0141] In this design, there are no light-emitting units (ELs) directly above the first via PLN11 corresponding to the second pixel circuit PDCA2, thus not affecting the setting of the light-emitting units (ELs). However, to avoid the increased technical difficulty caused by needing to ensure accurate alignment of the first via PLN11 and the corresponding second via PLN21 of the second pixel circuit PDCA2, the technical difficulty can be reduced by setting the second adapter cable TR2, thereby facilitating the manufacturing of the display panel.

[0142] In this embodiment, the pixel circuit PDCA included in the pixel circuit layer DR can be a 6T1C, 7T1C, or other circuits, as long as it can drive the light-emitting device to emit light. The structure of the pixel circuit layer DR will be explained in detail below using 7T1C as an example.

[0143] like Figure 13 As shown, the pixel circuit PDCA includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C.

[0144] Optionally, the first transistor T1 and the second transistor T2 are N-type thin-film transistors, such as metal-oxide-semiconductor thin-film transistors; the remaining transistors are P-type thin-film transistors, such as low-temperature polycrystalline silicon thin-film transistors.

[0145] like Figure 13 As shown, the control electrode of the first transistor T1 is used to load the capacitor reset control signal Re1, and the first electrode of the first transistor T1 is used to load the initial voltage signal Vinit. The second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2, the control electrode of the third transistor T3, and one end of the storage capacitor C. The control electrode of the second transistor T2 is used to load the first scan signal G1, and the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The second electrode of the third transistor T3 is connected to the first electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5. The control electrode of the fourth transistor T4... The second terminal of the fourth transistor T4 is used to load the second scan signal G2. The second terminal of the fifth transistor T5 is used to load the drive data signal Da. The control terminal of the fifth transistor T5 is used to load the enable signal EM. The second terminal of the fifth transistor T5 is connected to the other end of the storage capacitor C and is used to load the power supply voltage signal VDD. The control terminal of the sixth transistor T6 is used to load the enable signal EM. The second terminal of the sixth transistor T6 is connected to the first terminal of the seventh transistor T7 and is used to connect to the corresponding light-emitting unit EL. The control terminal of the seventh transistor T7 is used to load the electrode reset control signal Re2. The second terminal of the seventh transistor T7 is used to load the initial voltage signal Vinit.

[0146] In this transistor, the first terminal can be either the source or the drain, and the second terminal can be either the source or the drain. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0147] like Figure 1As shown, the pixel circuit layer DR in this example includes a stacked first semiconductor layer LPoly, a first gate metal layer LG1, a second gate metal layer LG2, a second semiconductor layer LOxide, a third gate metal layer LG3, a first source / drain metal layer LSD1, and a second source / drain metal layer LSD2. The first semiconductor layer LPoly is a low-temperature polycrystalline silicon semiconductor layer, and the second semiconductor layer LOxide is a metal-oxide-semiconductor layer.

[0148] The structure of each film layer will be explained in detail next, taking the region corresponding to at least one pixel circuit PDCA and at least one pixel circuit island PDCC as an example.

[0149] like Figures 14-23 As shown, a pixel circuit island PDCC includes eight pixel circuits PDCA arranged in two rows and four columns. The eight pixel circuits PDCA are arranged into multiple pixel circuit groups. Each pixel circuit group includes two pixel circuits PDCA that are adjacent in the first direction, and the two pixel circuits PDCA are mirrored.

[0150] like Figure 14 , Figure 15 and Figure 16 As shown, the first semiconductor layer LPoly includes the active layer of each of the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The active layer includes the control electrode (channel region), the first electrode (one of the source and drain), and the second electrode (the other of the source and drain) of each transistor.

[0151] In this configuration, the channel regions of the fourth transistor T4 and the fifth transistor T5 are arranged along the column direction H2, and the channel regions of the fifth transistor T5 and the sixth transistor T6 are arranged along the row direction H1. Along the row direction H1, the channel regions of the third transistor T3 and the seventh transistor T7 are located between the channel regions of the fifth transistor T5 and the sixth transistor T6; along the column direction H2, the channel regions of the seventh transistor T7 and the third transistor T3 are located on either side of the channel region of the fifth transistor T5. The first terminals of the fourth transistor T4, the fifth transistor T5, and the third transistor T3 are connected; the first terminals of the third transistor T3 and the sixth transistor T6 are connected; and the first terminals of the seventh transistor T7 and the sixth transistor T6 are connected. In the PDCA of two adjacent rows of pixel circuits, the channel region of the seventh transistor T7 in the previous row of pixel circuits is adjacent to the channel region of the fourth transistor T4 in the next row of pixel circuits.

[0152] like Figure 14 and Figure 17As shown, the first gate metal layer LG1 is provided with a first scan trace GL1 extending along the row direction H1 and an enable signal line EML arranged sequentially along the column direction H2, and a first electrode plate CP1 located between the first scan trace GL1 and the enable signal line EML and spaced apart along the row direction H1.

[0153] The first scan trace GL1 can be used to load the first scan signal G1. The first scan trace GL1 can overlap with the channel region of the fourth transistor T4, and the overlapping portion is multiplexed as the control electrode of the fourth transistor T4. The first scan trace GL1 can also overlap with the channel region of the seventh transistor T7 in the previous row pixel circuit PDCA, and the overlapping portion is multiplexed as the control electrode of the seventh transistor T7 in the previous row pixel circuit PDCA. Thus, the second reset control line RL2 connected to the previous row pixel circuit PDCA and the first scan trace GL1 connected to the next row pixel circuit PDCA are the same trace. Therefore, the electrode reset control signal Re2 of the previous row pixel circuit PDCA and the first scan signal G1 of the next row pixel circuit PDCA can be the same signal.

[0154] The enable signal line EML overlaps sequentially with the channel regions of the fifth transistor T5 and the sixth transistor T6, with the two overlapping portions being multiplexed as the control electrodes of the fifth transistor T5 and the sixth transistor T6, respectively. The enable signal line EML can be used to load the enable signal EM. The first plate CP1 of the storage capacitor C overlaps with the channel region of the third transistor T3, and is multiplexed as the control electrode of the third transistor T3.

[0155] like Figure 14 and Figure 18 As shown, the second gate metal layer LG2 is provided with an initial voltage trace VinitL extending along the row direction H1 and arranged sequentially along the column direction H2, a first reset control line RL1 and a second scan trace GL2, and a second electrode plate CP2 located on the side of the second scan trace GL2 away from the first reset control line RL1 and spaced apart along the row direction H1.

[0156] Among them, the initial voltage trace VinitL is used to load the initial voltage signal Vinit, and it overlaps with the first terminal of the first transistor T1 and the second terminal of the seventh transistor T7; the first reset control line RL1 is used to load the capacitor reset control signal Re1, and the second scan trace GL2 is used to load the second scan signal G2.

[0157] like Figure 14 , Figure 19 and Figure 20 As shown, the second semiconductor layer LOxide is provided with the source, drain, and channel regions of the first transistor T1 and the second transistor T2.

[0158] In this circuit, the second stage of the first transistor T1 is connected to the first stage of the second transistor T2. Along column direction H2, the channel region of the first transistor T1 is located on the side of the channel region of the second transistor T2 away from the channel region of the third transistor T3. The channel regions of the second transistor T2 and the fifth transistor T5 are located on opposite sides of the channel region of the third transistor T3. Along row direction H1, the channel regions of the fourth transistor T4 of the next row pixel circuit PDCA and the first transistor T1 are located on opposite sides of the channel region of the fourth transistor T4 of the previous row pixel circuit PDCA.

[0159] In this configuration, the channel region of the first transistor T1 overlaps with the first reset control line RL1, such that at least a portion of the overlapping area of ​​the first reset control line RL1 and the channel region of the first transistor T1 can be reused as the first control electrode of the first transistor T1. Similarly, the second scan line GL2 overlaps with the channel region of the second transistor T2, such that at least a portion of the overlapping area of ​​the second scan line GL2 and the channel region of the second transistor T2 can be reused as the second control electrode of the second transistor T2.

[0160] like Figure 14 and Figure 21 As shown, the third gate metal layer LG3 is provided with a second reset control line RL2 extending along the row direction H1 and a third scan line GL3 arranged sequentially along the column direction H2.

[0161] In this configuration, the second reset control line RL2 is used to load the electrode reset control signal Re2, and the third scan line GL3 is used to load the second scan signal G2. The second reset control line RL2 overlaps with the channel region of the first transistor T1, and the overlapping portion is multiplexed as the second control electrode of the first transistor T1. Similarly, the third scan line GL3 overlaps with the channel region of the second transistor T2, and the overlapping portion is multiplexed as the second control electrode of the second transistor T2. Thus, the first transistor T1 includes both a first and a second control electrode, and the second transistor T2 includes both a first and a second control electrode.

[0162] like Figure 22 As shown, the initial voltage trace VinitL and the first reset control line RL1 are located on the side of the first scan trace GL1 away from the enable signal line EML. The second scan trace GL2 and the second electrode plate are located between the first scan trace GL1 and the enable signal line EML, and the second electrode plate overlaps with the first electrode LAn1 plate. The second electrode plate has a clearance hole that exposes a portion of the first electrode LAn1 plate. The second reset control line RL2 is located between the initial voltage trace VinitL and the first scan line, and overlaps with the first reset control line RL1. The third scan line is located between the first scan line and the second electrode, and overlaps with the second scan trace GL2.

[0163] like Figure 14 and Figure 23 As shown, the adapter layer TR includes an adapter cable extending along the row direction H1, with adjacent adapter cables of different lengths along the row direction H1. This adapter cable can be either a first adapter cable TR1 or a second adapter cable TR2.

[0164] like Figure 22 As shown, in the pixel circuit island PDCC, the adapter line corresponding to the upper row of pixel circuit PDCA is located on the side of the enable signal line EML closer to the second electrode plate CP2, and there is an overlap with the second electrode plate CP2. The adapter line corresponding to the lower row of pixel circuit PDCA is located on the side of the enable signal line EML away from the second electrode plate CP2.

[0165] In the embodiments of this disclosure, such as Figure 24 As shown, the display area includes a transparent display area AA3 and a normal display area AA4 located around the transparent display area AA3.

[0166] In this context, in conjunction with the main display area AA1 and the secondary display area AA2 described above, the transparent display area AA3 can be located in the main display area AA1, in which case the other areas of the secondary display area AA2 and the main display area AA1 are the normal display area AA4; or the transparent display area AA3 can be located in the secondary display area AA2, in which case the other areas of the main display area AA1 and the secondary display area AA2 are the normal display area AA4.

[0167] The pixel circuit PDCA distribution density of the transparent display area AA3 is less than that of the pixel circuit PDCA distribution density of the normal display area AA4 (for example, the number of pixel circuit PDCA in the transparent display area AA3 is 0, that is, the multiple pixel circuit PDCA included in the display panel are all located in the normal display area AA4), so as to ensure that the transparent display area AA3 has a certain light transmittance, thereby ensuring the effect of under-screen photography.

[0168] In this embodiment of the disclosure, a portion of the multiple light-emitting units EL included in the light-emitting layer EE is located in the normal display area AA4, and the remaining portion is located in the transparent display area AA3. While realizing the under-screen camera function, in order to ensure the normal display of the image in the transparent display area AA3, the multiple pixel circuits PDCA include a third pixel circuit PDCA located in the normal display area AA4. The third pixel circuit PDCA is connected to one light-emitting unit EL in the transparent display area AA3.

[0169] To connect the third pixel circuit PDCA to the light-emitting unit EL of the transparent display area AA3, since there is a misalignment between the third pixel circuit PDCA and the light-emitting unit EL to be connected, the aforementioned adapter layer TR can be reused to achieve the connection between the third pixel circuit PDCA and the light-emitting unit EL of the transparent display area AA3. Specifically, the adapter layer TR also includes a third adapter wire, one end of which is electrically connected to the third pixel circuit PDCA, and the other end of which is connected to one of the light-emitting units EL of the transparent display area AA3.

[0170] The fewer the number of pixel circuits PDCA included in the transparent display area AA3, the more the number of third pixel circuits PDCA, and the more third adapter lines there will be. In order to facilitate the arrangement of a large number of third adapter lines, the adapter layer TR can be a multi-layer structure layer as described above, that is, multiple third adapter lines are set through multiple sub-transfer layers TR.

[0171] This disclosure provides a method for manufacturing a display panel, which can be used to manufacture the display panel described in the above embodiments. Figure 25 As shown, the method includes the following steps 2510 to 2540.

[0172] Step 2510: Fabricate a driving backplane BM, which includes a substrate BP, a pixel circuit layer DR, and a first planarization layer PLN1 stacked sequentially.

[0173] The display panel includes a display area and an outer peripheral area BB located outside the display area. The display area includes a main display area AA1 and a secondary display area AA2 located on one or both sides of the main display area AA1 along the row direction H1. The outer peripheral area BB includes a bonding area B1 located on one side of the display area along the column direction H2. The pixel circuit layer DR includes multiple pixel circuits PDCA, multiple data traces DL, and multiple data transfer lines DL3. A column of pixel circuits PDCA is connected to a data trace DL. At least some of the pixel circuits PDCA located in the main display area AA1 form multiple pixel circuit islands PDCC distributed in an array. The multiple data transfer lines DL3 are located in the main display area AA1 and do not overlap with the pixel circuit islands PDCC. One end of a data transfer line DL3 is connected to a data trace DL in the secondary display area AA2, and the other end extends to the bonding area B1. The first planarization layer PLN1 is provided with multiple first vias PLN11 that are connected one-to-one with the multiple pixel circuits PDCA.

[0174] Step 2520: Fabricate a transition layer TR on the side of the first planarization layer PLN1 away from the substrate BP. The transition layer TR includes a first transition line TR1.

[0175] Step 2530: A second planarization layer PLN2 is fabricated on the side of the transition layer TR away from the substrate BP. The second planarization layer PLN2 has a plurality of second vias PLN21 corresponding to a plurality of first vias PLN11. The plurality of pixel circuit islands PDCC include a first pixel circuit PDCA1. The two ends of the first transition line TR1 are respectively connected to the first vias PLN11 and second vias PLN21 corresponding to the first pixel circuit PDCA1.

[0176] Step 2540: A light-emitting layer EE is fabricated on the side of the second planarization layer PLN2 away from the substrate BP. The light-emitting layer EE includes multiple light-emitting units EL that are connected one-to-one with multiple second vias PLN21. The light-emitting area of ​​the light-emitting unit EL does not overlap with the second via PLN21. The multiple light-emitting units EL include a first light-emitting unit EL1. The light-emitting area of ​​the first light-emitting unit EL1 overlaps with the first via PLN11 corresponding to the first pixel circuit PDCA1.

[0177] In this embodiment, the structure of the display panel manufactured by the above manufacturing method can refer to the display panel described in the above embodiment, and will not be repeated here. Under the conversion function of the data adapter cable DL3, the data trace DL of the sub-display area AA2 is adjusted to extend from the main display area AA1 to the bonding area B1, thereby avoiding the technical problem of increasing the bezel of the display device due to the sub-display area AA2 directly extending to the bonding area B1. Furthermore, after compressing the pixel circuit PDCA, the connection point of the first light-emitting unit EL1 is transferred from the first via PLN11 to the position of the second via PLN21 through the setting of the first adapter cable TR1. This ensures the planarization of the first light-emitting unit EL1 during the subsequent fabrication of the light-emitting layer EE, thereby avoiding color shift problems in the displayed image of the fabricated display panel.

[0178] It should be noted that although the steps of the manufacturing method of the display panel in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0179] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, wherein, The display panel includes a display area and a peripheral area located outside the display area. The peripheral area includes a binding area located on one side of the display area along the column direction. The display panel includes: The driving backplane includes a substrate, a pixel circuit layer and a first planarization layer stacked sequentially. The pixel circuit layer includes multiple pixel circuits, multiple data traces, and multiple data adapters. A column of pixel circuits is connected to a data trace. At least a portion of the pixel circuits located in the display area form multiple pixel circuit islands distributed in an array. The multiple data adapters are located in the display area and do not overlap with the pixel circuit islands. One end of a data adapter is connected to a data trace in the display area, and the other end extends to the bonding area. The first planarization layer is provided with a plurality of first vias that are connected one-to-one with the plurality of pixel circuits; An adapter layer is located on the side of the first planarization layer opposite to the substrate, and includes a first adapter line; The second planarization layer is located on the side of the transition layer away from the substrate, and is provided with a plurality of second vias corresponding one-to-one with the plurality of first vias. The plurality of pixel circuit islands include a first pixel circuit, and the two ends of the first transition line are respectively connected to the first via and the second via corresponding to the first pixel circuit. The light-emitting layer is located on the side of the second planarization layer opposite to the substrate, and includes a plurality of light-emitting units that are connected to a plurality of second vias in a one-to-one correspondence. The light-emitting area of ​​the light-emitting unit does not overlap with the second via. The plurality of light-emitting units includes a first light-emitting unit, and the light-emitting area of ​​the first light-emitting unit overlaps with the first via corresponding to the first pixel circuit.

2. The display panel as claimed in claim 1, wherein, The plurality of pixel circuit islands include a second pixel circuit; The light-emitting areas of the multiple light-emitting units do not overlap with the first vias corresponding to the second pixel circuit, but the first vias corresponding to the second pixel circuit overlap with the corresponding second vias.

3. The display panel as claimed in claim 1, wherein, The plurality of pixel circuit islands include a second pixel circuit, and the adapter layer further includes a second adapter wire; The light-emitting areas of the multiple light-emitting units do not overlap with the first vias corresponding to the second pixel circuit, the first vias corresponding to the second pixel circuit do not overlap with the corresponding second vias, and the two ends of the second adapter wire are respectively connected to the first via and the second via corresponding to the second pixel circuit.

4. The display panel as described in any one of claims 1-3, wherein, The transition layer includes multiple sub-transition layers and an interlayer insulation layer located between any two adjacent sub-transition layers; Each of the multiple sub-transition layers has a first sub-transition line, and each of the interlayer insulating layers has a via. The vias are respectively connected to the first sub-transition lines on both sides of the sub-transition layers. Multiple first sub-transition lines are connected in sequence to form the first transition line.

5. The display panel as described in any one of claims 1-3, wherein, The pixel circuit layer includes a transistor layer, a first source / drain metal layer, a third planarization layer, and a second source / drain metal layer stacked sequentially in a direction away from the substrate. The second source / drain metal layer includes multiple pairs of power traces distributed along the row direction and extending along the column direction. Each pair of power traces encloses multiple clearance areas. The second source / drain metal layer also includes a pair of transition electrodes located in the clearance areas and extending along the column direction. Among the multiple transition electrodes, there is a first transition electrode corresponding to the first pixel circuit. The first transition electrode is connected to the first source / drain metal layer and the first end of the first transition line, respectively. The light-emitting layer further includes a pixel definition layer disposed on the surface of the first planarization layer away from the substrate. The pixel definition layer has pixel openings corresponding to the plurality of light-emitting units. The light-emitting unit includes a first electrode, an organic light-emitting layer, and a second electrode stacked sequentially along one side away from the second planarization layer. The first electrode includes an exposed area exposed at the corresponding pixel opening and a covered area covered by the pixel definition layer. The exposed area of ​​the first electrode forms the light-emitting area of ​​the corresponding light-emitting unit. The second end of the first adapter cable is connected to the covered area of ​​a light-emitting unit.

6. The display panel as claimed in claim 5, wherein, The first adapter wire extends along the row direction, and the first end of the first adapter wire overlaps with at least a portion of the first adapter electrode, the first via corresponding to the first pixel circuit, and the exposed area of ​​the first light-emitting unit. The second end of the first adapter wire overlaps with the second via corresponding to the first pixel circuit and the covered area of ​​the first light-emitting unit.

7. The display panel as claimed in claim 5, wherein, The first adapter line extends along the row direction. The first end of the first adapter line overlaps with at least a portion of the first adapter electrode, the first via corresponding to the first pixel circuit, and the exposed area of ​​the first light-emitting unit. The second end of the first adapter line overlaps with the second via corresponding to the first pixel circuit and the covered area of ​​the second light-emitting unit among the plurality of light-emitting units. The second light-emitting unit is adjacent to the first light-emitting unit.

8. The display panel as claimed in claim 5, wherein, The transition layer further includes a second transition wire, and among the plurality of transition electrodes is a second transition electrode corresponding to the second pixel circuit; At least a portion of the second transfer electrode overlaps with the first via corresponding to the second pixel circuit, but does not overlap with the exposed areas of the plurality of light-emitting units; The second adapter line extends along the row direction. The first end of the second adapter line overlaps with at least a portion of the second adapter electrode. The second end of the second adapter line overlaps with the second via corresponding to the second pixel circuit and the coverage area of ​​the third light-emitting unit among the plurality of light-emitting units.

9. The display panel as claimed in claim 5, wherein, The data transfer cable includes a first section of cable and a second section of cable; The first segment of the trace extends along the row direction, the second segment of the trace extends along the column direction, one end of the first segment of the trace is connected to a data trace, the other end is connected to one end of the second segment of the trace, and the other end of the second segment of the trace extends to the binding area. The first segment of the data adapter cable and part of the second segment of the data adapter cable are located in the first source-drain metal layer, and the remaining second segment of the data adapter cable is located in the second source-drain metal layer.

10. The display panel as described in any one of claims 1-3, wherein, The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a storage capacitor; The control electrode of the first transistor is used to load a capacitor reset control signal, the first electrode of the first transistor is used to load an initial voltage signal, and the second electrode of the first transistor is connected to the first electrode of the second transistor, the control electrode of the third transistor, and one end of the storage capacitor. The control electrode of the second transistor is used to load the first scan signal, and the second electrode of the second transistor is connected to the first electrode of the third transistor and the first electrode of the sixth transistor; The second terminal of the third transistor is connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor. The control terminal of the fourth transistor is used to load the second scan signal, the second terminal of the fourth transistor is used to load the drive data signal, the control terminal of the fifth transistor is used to load the enable signal, and the second terminal of the fifth transistor is connected to the other end of the storage capacitor and is used to load the power supply voltage signal. The control electrode of the sixth transistor is used to load an enable signal. The second electrode of the sixth transistor is connected to the first electrode of the seventh transistor and is used to connect to the corresponding light-emitting unit. The control electrode of the seventh transistor is used to load an electrode reset control signal, and the second electrode of the seventh transistor is used to load an initial voltage signal.

11. The display panel as claimed in claim 10, wherein, The pixel circuit layer includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and a source / drain metal layer; The first semiconductor layer includes the active layers of each of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second semiconductor layer is provided with the active layers of the first transistor and the second transistor. The first gate metal layer is provided with a first scan trace and an enable signal line extending along the row direction and arranged sequentially along the column direction, and a first electrode plate located between the first scan trace and the enable signal line and spaced apart along the row direction. The first scan trace is used to load the first scan signal, and the enable signal line is used to load the enable signal. The second gate metal layer is provided with an initial voltage trace, a first reset control line and a second scan trace extending along the row direction and arranged sequentially along the column direction, and a second electrode plate located on the side of the second scan trace away from the first reset control line and spaced apart along the row direction. The initial voltage trace is used to load the initial voltage signal, the first reset control line is used to load the capacitor reset control signal, and the second scan trace is used to load the second scan signal. The third gate metal layer is provided with a second reset control line and a third scan line extending along the row direction and arranged sequentially along the column direction. The second reset control line is used to load the electrode reset control signal, and the third scan line is used to load the second scan signal. The initial voltage trace and the first reset control line are located on the side of the first scan trace away from the enable signal line. The second scan trace and the second electrode are located between the first scan trace and the enable signal line, and the second electrode overlaps with the first electrode. The second reset control line is located between the initial voltage trace and the first scan trace, and overlaps with the first reset control line. The third scan trace is located between the first scan trace and the second electrode, and overlaps with the second scan trace. The transition layer includes transition lines extending along the row direction. In the pixel circuit island, the transition line corresponding to the upper row of pixel circuits in two adjacent rows is located on the side of the enable signal line closer to the second electrode plate and overlaps with the second electrode plate. The transition line corresponding to the lower row of pixel circuits is located on the side of the enable signal line away from the second electrode plate.

12. The display panel as described in any one of claims 1-3, wherein, The display area includes a transparent display area and a normal display area located around the transparent display area; The pixel circuit distribution density of the transparent display area is less than that of the pixel circuit distribution density of the normal display area. The plurality of pixel circuits include a third pixel circuit located in the normal display area. The adapter layer also includes a third adapter wire, the two ends of which are respectively connected to the third pixel circuit and a light-emitting unit of the transparent display area.

13. The display panel as described in any one of claims 1-3, wherein, The display area includes a main display area and a secondary display area located on one or both sides of the main display area along the row direction; Multiple pixel circuit islands and multiple data adapter cables are located in the main display area, and one end of one of the data adapter cables extends into the sub-display area and connects to a data trace, while the other end extends into the bonding area.

14. The display panel as described in any one of claims 1-3, wherein, The first adapter cable is made of a transparent conductive material.

15. A method for manufacturing a display panel, wherein, include: Fabricate a driving backplane, the driving backplane comprising a substrate, a pixel circuit layer, and a first planarization layer stacked sequentially. The display panel includes a display area and a peripheral area located outside the display area. The peripheral area includes a bonding area located on one side of the display area along the column direction. The pixel circuit layer includes multiple pixel circuits, multiple data traces, and multiple data adapter lines. A column of the pixel circuits is connected to a data trace. At least a portion of the pixel circuits located in the display area form multiple pixel circuit islands distributed in an array. The multiple data adapter lines are located in the display area and do not overlap with the pixel circuit islands. One end of a data adapter line is connected to a data trace in the display area, and the other end extends to the bonding area. The first planarization layer is provided with multiple first vias that are connected to the multiple pixel circuits one by one. An adapter layer is formed on the side of the first planarization layer opposite to the substrate, the adapter layer including a first adapter line; A second planarization layer is formed on the side of the transition layer away from the substrate. The second planarization layer has a plurality of second vias that correspond one-to-one with the plurality of first vias. The plurality of pixel circuit islands include a first pixel circuit. The two ends of the first transition line are respectively connected to the first via and the second via corresponding to the first pixel circuit. A light-emitting layer is formed on the side of the second planarization layer away from the substrate. The light-emitting layer includes a plurality of light-emitting units that are connected one-to-one with a plurality of second vias. The light-emitting area of ​​the light-emitting unit does not overlap with the second via. The plurality of light-emitting units include a first light-emitting unit. The light-emitting area of ​​the first light-emitting unit overlaps with the first via corresponding to the first pixel circuit.

16. A display device, wherein, Includes the display panel described in any one of claims 1-14 above.

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