Current sense circuit with integrated resistor and dual sense amplifier

Abstract

The present disclosure relates to a current sense circuit with integrated resistors and dual sense amplifiers. A first amplifier is considered a constant-on amplifier. The constant-on amplifier provides continuous measurement of current across an integrated polysilicon resistor (Isns) for one or more analog control loops. A second amplifier is considered a switched amplifier. The switched amplifier provides measurement of the current (Isns) for one or more digital control loops. The switched amplifier is switched by one or more switches in order to perform offset measurements with high accuracy.

Description

Technical Field

[0001] This invention generally relates to wireless power, and more specifically, to current sensing. Background Technology

[0002] Current sensing is a component of wireless power systems. The sensed current, along with voltage measurement, provides a measurement of the system's power. This power measurement is crucial for understanding how much power is actually received from the transmitter and delivered to a load (e.g., a battery). Specifically, wireless power systems must measure power very accurately to aid in foreign object detection. It is undesirable for a foreign object to receive power from the transmitter and begin to overheat. The receiver may include current sensing functionality to measure the received power to determine power loss caused by a foreign object. Power loss caused by a foreign object can be predicted by more accurately determining the received current. Therefore, it is desirable to determine the received current with a given level of accuracy. However, the current sensing functionality of a wireless power system may contain inaccuracies introduced by one or more sources.

[0003] In view of the above, one or more embodiments of this disclosure provide an integrated circuit that includes improved current sensing capabilities. Summary of the Invention

[0004] According to one or more illustrative embodiments of this disclosure, an integrated circuit is described. In some embodiments, the integrated circuit includes a first resistor coupled between a first node and a second node. In some embodiments, the first resistor includes a first resistance (Rs). In some embodiments, the first resistor is configured to carry a first current (Isns) across the first resistor when the first node includes a first voltage (Vrect) and the second node includes a second voltage (Vmid). In some embodiments, the integrated circuit includes a first amplifier including a first input coupled to the first node and a second input coupled to the second node. In some embodiments, the first amplifier is configured to output a third voltage (Vo). In some embodiments, the integrated circuit includes a second resistor and a third resistor. In some embodiments, the second resistor and the third resistor each include a second resistance (Rt). In some embodiments, the second resistor is coupled between the first node and a first input of the first amplifier. In some embodiments, the third resistor is coupled between the second node and a second input of the first amplifier. In some embodiments, the integrated circuit includes a plurality of switches for measuring offset. In some embodiments, the integrated circuit includes a second amplifier including a third input coupled to the first node and a fourth input coupled to the second node. In some embodiments, the second amplifier is configured to output a fourth voltage (Van).

[0005] According to one or more illustrative embodiments of this disclosure, a wireless power system is described. In one illustrative embodiment, the wireless power system includes a coil. In some embodiments, the wireless power system includes an integrated circuit. In some embodiments, the integrated circuit includes a rectifier circuit configured to receive alternating current from the coil and generate a first voltage (Vrect). In some embodiments, the integrated circuit includes a current sensing circuit. In some embodiments, the current sensing circuit includes a first resistor coupled between a first node and a second node. In some embodiments, the first resistor includes a first resistance (Rs). In some embodiments, the first resistor is configured to carry a first current (Isns) across the first resistor when the first node contains the first voltage (Vrect) and the second node contains a second voltage (Vmid). In some embodiments, the current sensing circuit includes a first amplifier including a first input coupled to the first node and a second input coupled to the second node. In some embodiments, the first amplifier is configured to output a third voltage (Vo). In some embodiments, the current sensing circuit includes a second resistor and a third resistor. In some embodiments, the second resistor and the third resistor each include a second resistance (Rt). In some embodiments, the second resistor is coupled between the first node and a first input of the first amplifier. In some embodiments, the third resistor is coupled between the second node and a second input of the first amplifier. In some embodiments, the current sensing circuit includes a plurality of switches for measuring offset. In some embodiments, the second amplifier includes a third input coupled to the first node and a fourth input coupled to the second node. In some embodiments, the second amplifier is configured to output a fourth voltage (Van). In some embodiments, the integrated circuit includes a voltage regulator circuit configured to regulate the second voltage (Vmid). In some embodiments, the integrated circuit includes a processor. In some embodiments, the processor is configured to receive one or more digital signals of the third voltage (Vo) and determine the current (Isns) based on the third voltage (Vo). In some embodiments, the wireless power system includes a battery charging system. Attached Figure Description

[0006] The embodiments of the concepts disclosed herein can be better understood from the following details. This description refers to the accompanying drawings, which are not necessarily drawn to scale and, for clarity, some features may be enlarged and some features may be omitted or schematically represented. The same reference numerals in the drawings may indicate and refer to the same or similar elements, features, or functions. In the drawings:

[0007] Figures 1A to 1CA top view depicting the layout of components of a current sensing circuit according to one or more embodiments of the present disclosure.

[0008] Figures 2A to 2B A side view depicting the layout of components of a current sensing circuit according to one or more embodiments of the present disclosure.

[0009] Figure 3 A top view depicting the layout of components of a current sensing circuit according to one or more embodiments of the present disclosure.

[0010] Figure 4 A circuit diagram depicting a current sensing circuit according to one or more embodiments of the present disclosure.

[0011] Figures 5A to 5B A circuit diagram depicting a current sensing circuit according to one or more embodiments of the present disclosure.

[0012] Figure 6 A top view depicting the layout of components of a current sensing circuit according to one or more embodiments of the present disclosure.

[0013] Figure 7 A simplified block diagram depicts an integrated circuit including a current sensing circuit according to one or more embodiments of the present disclosure.

[0014] Figure 8 A simplified schematic diagram of a wireless power system according to one or more embodiments of the present disclosure is shown.

[0015] Figure 9 A simplified communication apparatus comprising one or more components of a wireless power system is described according to one or more embodiments of the present disclosure. Detailed Implementation

[0016] Before explaining one or more embodiments of this disclosure in detail, it should be understood that the application of the embodiments is not limited to the details of the construction and arrangement of the components, steps, or methods set forth in the following description or illustrated in the drawings. In the following detailed description of the embodiments, numerous specific details are set forth to provide a more thorough understanding of this disclosure. However, those skilled in the art to which this disclosure pertains will understand that the embodiments disclosed herein can be practiced without these specific details. In other instances, well-known features may not be described in detail to avoid unnecessarily complicating this disclosure.

[0017] As used herein, the letters following the reference numerals are intended to refer to embodiments of features or elements that are similar to, but not necessarily identical to, the aforementioned elements or features having the same reference numerals (e.g., 1, 1a, 1b). Such shorthand notation is for convenience only and should not be construed as limiting this disclosure in any way unless expressly stated otherwise.

[0018] Furthermore, unless explicitly stated otherwise, "or" refers to "inclusive or" rather than "exclusive or". For example, conditions A or B satisfy any of the following: A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); and both A and B are true (or exist).

[0019] Furthermore, the term "a" may be used to describe the elements and components of the embodiments disclosed herein. This is merely for convenience, and "a" is intended to include "one" or "at least one," and the singular includes the plural, unless it clearly implies otherwise.

[0020] Finally, as used herein, any reference to “one embodiment” or “some embodiments” means that a particular element, feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment disclosed herein. The phrase “in some embodiments” appearing in various places in the specification does not necessarily refer to all the same embodiments, and embodiments may include any combination or sub-combination of one or more, or two or more, of the features expressly described or inherent in this document, as well as any other features not necessarily expressly described or inherent in this disclosure.

[0021] The subject matter of the disclosure will now be described in detail with reference to the accompanying drawings.

[0022] The current sensing circuit may include the functionality to measure the current (Isns) across an integrated resistor. The current sensing circuit may include a digital channel that needs to be offline to perform offset measurements. Offset measurements are expected to ensure high accuracy in wireless power applications. When the digital channel is offline, one or more analog control loops using the measured current (Isns) can be interrupted.

[0023] According to one or more embodiments of this disclosure, a current sensing circuit with a dual amplifier path is described. The first path includes a normally open amplifier for an analog channel. The normally open amplifier provides an analog signal indicating the current (Isns) to one or more analog control loops of the current sensing circuit. The second path includes a switched amplifier for an ADC channel. The switched amplifier is separate from the analog channel and offline for offset measurement.

[0024] General reference Figures 1A to 6This document describes a current sensing circuit 100. The current sensing circuit 100 can be configured to measure current across a wide range of voltages, such as up to 24 volts or higher. The current sensing circuit 100 can be configured to measure currents with a relatively large dynamic range, such as (but not limited to) between 1 mA and up to 2.5 A or greater. Through one or more layout configurations, a switching matrix for determining offset, and a dual-channel approach for analog and digital control loops, the accuracy of the current sensing circuit 100 is expected to be within 0.5% of the actual current dynamic range across the current. Although the current sensing circuit 100 is depicted as including various components contained in the respective arrangements, this is not intended to be a limitation of this disclosure. It is further contemplated that the current sensing circuit 100 may include various additional components not depicted. It should be noted herein that, for the purposes of this disclosure, "coupled" can mean one or more of "communically coupled to," "electrically coupled to," and / or "physically coupled to." As used herein, coupling can refer to direct or indirect coupling. Indirect coupling can refer to a connection via another functional element. Direct coupling can refer to a connection without intermediate elements. It should be noted in this article that “coupled between” can be understood as relative to the movement or flow of a signal between two or more components, which may also include an intermediary component.

[0025] For reference Figures 1A to 1C The layout of one or more components of the current sensing circuit 100 is described according to one or more embodiments of the present disclosure.

[0026] The current sensing circuit 100 may include one or more of resistors 102, 104, and 106. Resistor 102 may also be referred to herein as a sensing resistor having a resistance (Rs). For example, the resistance (Rs) may be 20 milliohms, but this is not intended to be limiting. The value range of resistor 102 is contemplated to be around an exemplary 20 milliohm resistor. In this respect, the resistance value may be selected from about 1 to 100 milliohms or greater. Resistors 104 and 106 may be connected to the input of amplifier 108, such that resistors 104 and 106 may also be referred to herein as upper resistors. Resistors 104 and 106 may each include a resistance (Rt), such that resistors 104 and 106 may also be referred to herein as a pair of matched resistors. For example, the resistance (Rt) may be 1 kilohm (e.g., a 1 kΩ resistor), but this is not intended to be limiting. The current sensing circuit 100 may further include one or more dummy resistors 124. The current sensing circuit 100 may further include one or more switches 122 (e.g., switches (M1), (M2), (M3), and (M4)). Switches (M1 to M4) may be provided to measure the offset of the current sensing circuit, which is caused by resistors 104, 106, 110, 112, and amplifier 108, as will be further described herein.

[0027] like Figure 1A As depicted, resistors 102, 104, 106, and dummy resistor 124 are shown with different shaded lines, which is not intended to be limiting. Specifically, resistors 102, 104, 106, and dummy resistor 124 are shaded to indicate the number of array elements contained in each resistor. The arrangement of resistors 102, 104, and 106 is intended to facilitate the sensing of any number of current sensing circuits in the milliampere to ampere range.

[0028] In an embodiment, resistors 102, 104, and 106 each comprise a polysilicon resistor formed on a substrate. The polysilicon resistor may also be referred to herein as a polysilicon resistor or an internal polysilicon resistor. In an embodiment, the polysilicon resistors are formed as an array of array elements each comprising an array of polysilicon wafers. Figure 1A Resistor 102 is depicted as containing 140 array elements, resistor 104 as containing 7 array elements, resistor 106 as containing 7 array elements, and dummy resistor 124 as containing 6 array elements, but this is not intended to be limiting. Furthermore, although not depicted, the array elements of each of resistors 102, 104, and 106 can be coupled in various series or parallel arrangements to achieve the desired resistance value. As further depicted in Figure 2, each array element may contain several polysilicon wafers. For example, the array element may also be referred to as a 10x resistor, such that each array element contains 10 polysilicon wafers (also called fingers), but this is not intended to be limiting. Therefore, resistor 102 may contain 1400 polysilicon wafers, and resistors 104 and 106 may each contain 70 polysilicon wafers.

[0029] Therefore, resistors 102, 104, and 106 can each be formed from multiple polysilicon wafers. The polysilicon wafers can include any polysilicon material known in the art, such as (but not limited to) doped or undoped polysilicon films. The polysilicon wafers can be disposed on the same layer of the integrated circuit, such as below a metallization layer. The polysilicon wafers can contain resistance that varies with temperature. Using polysilicon wafers can be advantageous for reducing the temperature coefficient compared to implementing resistors 102, 104, and 106 in the metallization layer of the integrated circuit. For example, the polysilicon wafers can contain a temperature coefficient of resistance (TCR) between 150 and 160 parts per million per degree Celsius, but this is not intended to be limiting. Each polysilicon wafer can contain a resistance value. For example, each polysilicon wafer can contain a sheet resistor of 300 ohms per square meter, but this is not intended to be limiting. The polysilicon wafers can be arranged in parallel and / or in series. Parallel and / or series arrangements of polysilicon wafers can be used to form resistor arrays with selected resistance values ​​for polysilicon resistors. The resistance (Rs) of the sensing resistor, the resistance (Rt) of the upper resistor, and the resistance (Rb) of the lower resistor are based on the number and arrangement of the polysilicon wafer array. The number of resistor elements used to form the array of resistor 102 can be substantially greater than the number of resistor elements used to form the upper resistor. Providing substantially more resistor elements 102 than the upper resistor can result in a resistance (Rs) that is substantially smaller than the resistance (Rt). Consider an example where resistor 102 has 140 array elements, where each array element comprises 10 polysilicon wafers. In this example, resistor 102 can be composed of 1400 parallel polysilicon wafers to achieve a resistance value of 20 milliohms (Rs), but this is not intended to be limiting.

[0030] It is desirable to ensure that resistors 104 and 106 are as close as possible to their matched resistance values, for example, to ensure the gain of one or more amplifiers suitable for a current sensing circuit. One challenge in implementing resistors 102, 104, and 106 is due to the piezoresistive nature of polysilicon. In this respect, the resistance (Rs) and the anti-resistance (Rt) can change when the polysilicon wafer is subjected to pressure. Each of resistors 104 and 106 can be subjected to stress due to pressure. In some examples, the stress on resistor 104 may differ from the stress on resistor 106, which may also be referred to herein as stress difference.

[0031] like Figure 1B As depicted, the stress gradient plot 130 of the integrated circuit can decrease away from axis 126 and can be further symmetrical about axis 126. Similarly, the resistance plot (not depicted) varying with distance shows the change in resistance away from the axis. Figure 1CAs further described, the stress gradient plot 131 of the integrated circuit can vary away from the die edge 128. For example, the stress gradient may be highest at the die edge 128 and decrease non-linearly across the die, making the stress gradient across the integrated circuit from the die edge 128 non-linear. Similarly, a resistance plot (not depicted) varying with distance shows the change in resistance away from the die edge 128. It should be understood that plots 130 and 131 are not intended to be limiting. In this respect, plots 130 and 131 may include batch-to-batch and / or portion-to-part variations.

[0032] In an embodiment, resistors 104 and 106 may be arranged symmetrically about the stress gradient to minimize the resistance variation caused by piezoresistive properties.

[0033] In this embodiment, resistors 104 and 106 comprise an array of polysilicon wafers symmetrically arranged about an axis 126. Axis 126 may include a central axis. In this respect, the stress difference between the polysilicon wafers of resistors 104 and 106 can be reduced, thereby causing the matching resistor pair to experience similar stress and similar resistance changes caused by piezoresistive properties. This resulting in similar resistance changes in the matching resistor pair can be particularly advantageous, where each resistor is coupled to the input of a differential amplifier, thereby improving the accuracy of the differential amplifier.

[0034] In an embodiment, resistors 104 and 106 comprise an array of polysilicon wafers arranged at the same distance from the die edge 128 of the integrated circuit. Resistors 104 and 106 may be piezoresistive and their resistance changes due to pressure. The resistance change caused by pressure affects the offset and gain of the downstream amplifier. By arranging resistors 104 and 106 at the same distance from the axis 126 and the die edge 128, the stress difference between the resistors is reduced. Reducing the stress difference can cause the resistors to experience similar resistance changes. Therefore, arranging the resistors at the same distance from the die edge 128 minimizes the impact on the offset and gain of the downstream amplifier (e.g., where resistors 104 and 106 are inputs to the amplifier) ​​compared to arranging resistors 104 and 106 at different distances from the die edge 128.

[0035] Resistors 104 and 106 may also be placed at a distance from the die edge within a portion of the stress gradient that is flatter than the region closer to the die edge. In this respect, the resistance of the matching resistor pair can be changed to a minimum, thereby minimizing the impact on the amplifier gain. For example, one or more array elements of resistor 102 and one or more of the switches (M1 to M4) may be placed between the die edge 128 and resistors 104, 106, thereby spacing resistors 104, 106 from the die edge 128.

[0036] As depicted, the layout may include an array of resistors. The array may be partitioned based on one or more deep n-well (DNW) regions 132 of the integrated circuit, but this is not intended to limit it. In this respect, the resistors may be placed in a layer above the DNW region 132. For example, Figure 1A A 2×4 array of DNW regions 132 is depicted, wherein each of the DNW regions 132 comprises two rows, and each row has 10 array elements. As further depicted, a first 1×4 array of DNW regions 132 is separated from a second 1×4 array of DNW regions 132 by switches (M1 to M4). Although DNW regions 132 are depicted as containing 20 array elements, this is not intended to be a limitation of this disclosure. DNW regions 132 can typically contain any suitable number for implementing the desired resistance. For example, DNW regions 132 may contain 22 array elements per DNW region (i.e., rows of 11 array elements). In this example, the total number of array elements may be 176 elements (i.e., a 2×4 array of DNW regions, each region containing 22 elements). When each element contains 10 fingers or polysilicon wafers, the array may contain 1760 polysilicon wafers. To achieve a 20 milliohm resistance for resistor 102, 1400 of the 1760 polysilicon wafers can be used for a total of 140 array elements. To achieve a 1kΩ resistance for each of resistors 104 and 106, 70 array elements can be used. The remaining layout may contain 12 unused array elements (e.g., dummy resistor 124).

[0037] In this embodiment, resistors 104 and 106 are arranged symmetrically about axis 126 and positioned at the same distance from die edge 128, as depicted. The resistors will still experience stress, resulting in resistance changes. Advantageously, the resistivity of resistors 104 and 106 changes at similar rates. The resistivity can change at similar rates because the two resistors are equidistant from edge 128 and oriented similarly about axis 126. Therefore, the resistance (Rt) of each resistor can be more closely matched. For example, the array elements of resistors 104 and 106 are depicted as being positioned in a separate DNW region 132 closest to axis 126 and separated from die edge 128 by a second group of DNW regions 132.

[0038] Resistor 102 may comprise one or more rows of array elements comprising a polysilicon wafer. One or more rows of resistors 102 are disposed between die edge 128 and the polysilicon wafer of resistor 104. Similarly, one or more rows of resistors 102 are disposed between die edge 128 and the polysilicon wafer of resistor 104. A row can be considered closer to die edge 128 and can also be disposed in an area experiencing higher stress concentration. Therefore, resistor 102 can experience relatively more piezoelectric variation than resistor 104 or resistor 106. For example, resistor 102 is depicted as comprising 14 rows of array elements, with 10 array elements in each row. Resistor 102 is further depicted as comprising 8 rows between die edge 128 and resistor 104 or resistor 124.

[0039] Resistor 102 may additionally comprise one or more rows of array elements arranged at the same distance from die edge 128, similar to resistors 104 or 106. The rows arranged at the same distance may also be symmetrically arranged about axis 126. The polysilicon wafers of resistors 104 and 106 may also be disposed between one or more rows of the first resistor 102. For example, resistors 104 and 106 may be depicted disposed between three rows of resistors 102 arranged symmetrically about axis, the three rows being arranged at the same distance from die edge 128. Therefore, resistor 102 may include a layout that reduces the space between resistors 104 and 106 for better matching.

[0040] Resistors 102, 104, and 106 can be placed in the same layer of the circuit to reduce temperature difference. In an embodiment, resistors 104 and 106 can be interdigitated to reduce the temperature difference between them. Reducing the temperature difference is valuable for minimizing errors caused by temperature-induced changes in resistance.

[0041] A fork can refer to one or more sub-components of a first component interleaving with one or more sub-components of a second component. For example, an array can contain polysilicon wafers of the first component interleaved with polysilicon wafers of the second component. As another example, a switch matrix can contain a first switch interleaved with second switches on a layer to match channel resistance. Channel resistance can refer to the resistance from drain to source.

[0042] The integrated circuit can be further configured to directly measure the offset. The current sensing circuit 100 may further include one or more switches. For example, the switches may include four switches (M1 to M4). Switches (M1 to M4) can be provided to measure the offset. The switches (M1 to M4) may also be arranged symmetrically about the stress gradient. For example, switches (M2) and (M3) may be symmetrical about axis 126 with respect to switches (M1) and (M4).

[0043] Switches (M1 to M4) may be disposed on the same layer as resistors 102, 104, and 106. In an embodiment, switch (M1) may be interlocked with switch (M4). Similarly, switch (M2) may be interlocked with switch (M3). Interlocking switches can be beneficial for matching the channel resistance of switches (M1) and (M4) and similarly for matching the channel resistance of switches (M2) and (M3). Alternative arrangements for the layout of switches (M1 to M4) are anticipated. For example, switches (M1) and (M4) may be separate and may be arranged with switches (M2) and (M3) in any order. Switches (M1) and (M4) may also be arranged symmetrically about an axis relative to switches (M2) and (M3).

[0044] General reference Figures 2A to 2B This describes an array element of polysilicon resistors. The polysilicon resistors may include one or more of resistors 102, 104, or 106. The array element may include one or more polysilicon wafers 134 and one or more metallization layers 136. The array element may further include one or more channels 138 connecting the polysilicon wafers 134 to the metallization layers 136.

[0045] The array element may comprise any number of polysilicon wafers 134. For example, the array element may comprise 12 polysilicon wafers 134 (e.g., two dummy wafers and wafers 1 to 10), but this is not intended to be limiting. As depicted, array elements 201 and 203 each comprise 10 coupled polysilicon wafers (1 to 10) and 2 dummy polysilicon wafers (Dmy). The polysilicon wafers 134 may comprise a suitable range of sizes. For example, the polysilicon wafers 134 may be relatively wide, for example (but not limited to) 50 micrometers wide. The polysilicon wafers 134 may further comprise a length, for example (but not limited to) 4 micrometers long. Thus, the aspect ratio of the polysilicon wafers 134 may be 50 micrometers × 4 micrometers, but this is not intended to be limiting. Polysilicon wafers with an aspect ratio of 50 micrometers × 4 micrometers have been experimentally determined to have a temperature coefficient of 150 PPM / C. Setting the size of polycrystalline silicon wafers to have the same aperture and similar temperature coefficient can help offset the temperature coefficients of resistance (Rs) and resistance (Rt).

[0046] Connections between multiple polysilicon wafers 134 are routed among one or more of the metallization layers 136. In addition to the polysilicon wafers 134, the metallization layers 136 of the integrated circuit may also be resistive. Therefore, the resistance value of the array element can be based on the array itself and the metallization layers used to allow current to flow in and out of the polysilicon wafers 134. The metallization layers can be formed of one or more materials, such as (but not limited to) copper. The layers may contain resistivity inversely proportional to their thickness. As depicted, the array element may contain four metallization layers. Although the array element is depicted as containing four metallization layers, this is not intended to be limiting. For example, each array element may contain six metallization layers (m1 to m6). Layers (m1 to m5) may be relatively thin and contain a sheet resistivity (e.g., 300 milliohms per square). Layers (m1 to m5) may be high-density metal interconnects for various digital signals. In contrast, layer (m6) may be relatively thicker than layers (m1 to m5) and contain a relatively low sheet resistivity (e.g., 4 milliohms per square). Layer (m6) may be provided with an analog path for high current. Layer (m6) may also be described as a top layer or a package layer. Metallization layers (m1 to m6) may be provided as one or more parallel layers. Parallel layers may be disposed on top of polysilicon wafer layers. Polysilicon wafer layers may be disposed on top of one or more deep n-well (DNW) layers.

[0047] When designing a current sensing circuit, parasitic resistance caused by path routing between polysilicon wafers 134 contributes to an error term. Mismatch between upper-layer resistors in the current sensing circuit can lead to significant percentage errors. For example, when resistors 104 and 106 are 1kΩ resistors, a 1-ohm mismatch results in a 0.1% error. The 3 square millimeters of metal in layers (m1 to m5) can contribute to this error. In an embodiment, connections between polysilicon wafers 134 can be routed between metallization layers 136 that contain lower sheet resistivity. Routing through layers with lower sheet resistivity minimizes the impact on the resistance of resistors 102, 104, or 106. For example, layer (m6) can be used to route connections between polysilicon wafers 134 due to its lower sheet resistivity. In this respect, connecting polysilicon wafers 134 through layer (m6) reduces the ohmic resistance caused by the metallization layers.

[0048] Layers (m1 to m5) may be disposed between layer (m6) and polysilicon wafer 134. A pathway 138 may be coupled between polysilicon wafer 134 and metallization layer 136. For example, pathway 138 may be provided to couple polysilicon wafer 134 to layer (m6). Pathway 138 may be perpendicular to layers (m1 to m6) to allow current to be routed laterally through layer (m6). Pathway 138 may also be referred to as a stacked pathway. Pathway 138 may also contain resistivity. The resistance of pathway 138 may cause additional error terms. In an embodiment, the resistance of pathway 138 is matched between array elements 201 and 203. Each of array elements 201 and 203 may have the same number of pathways to match the resistance. Current then flows through the stacked pathways to the polysilicon wafer, flows along the polysilicon wafer, and then reaches layer (m6) through a second set of stacked pathways reaching different portions of the metallization layer 6.

[0049] For reference Figure 2A This describes an array element 201 of resistor 102. The array element 201 of resistor 102 may comprise one or more polysilicon wafers 134 coupled in parallel, for example, ten polysilicon wafers 134 connected through a path 138 and a metallization layer 136. As depicted, the resistance of the array element may be based on the resistance of the polysilicon wafer (Rpoly) and the resistance of the path (Rcontact). In some examples, each of the polysilicon wafers 134 in each array element of resistor 102 is coupled in parallel. By coupling each of the polysilicon wafers 134 in parallel, the resistance (Rs) of resistor 102 can be very low. Providing very low resistance helps to minimize power loss across resistor 102. Each of the polysilicon wafers 1 to 10 may be coupled in parallel. For example, the resistance (Rs) of resistor 102 may be 20 milliohms, but this is not intended to limit it. The resistance can be defined by the following equation:

[0050] R = [Rpoly + (2 * Rcontact)] / 10

[0051] Resistor 102 may further include any number of array elements 201 to achieve the desired resistance, for example Figure 1A The layout depicted in the figure consists of 140 array elements 201.

[0052] For reference Figure 2BThe diagram describes an array element 203 comprising resistors 104 and 106. Array element 203 may comprise one or more polysilicon wafers coupled in series. As depicted, the resistance of the array element may be based on the resistance of the polysilicon wafers (Rpoly) and the resistance of the path (Rcontact). Array element 203 may include a path 138 that rises and passes through resistor 9, rises through the path, and falls. Resistor 8 may then be skipped. The pattern may continue where wafers 1, 3, 5, 7, and 9 are coupled in series and resistors 2, 4, 6, and 8 are skipped. In this respect, array elements 201 and 203 may include matching path resistors. For example, the resistance may be defined by the following equation:

[0053] R = (5 * Rpoly) + (10 * Rcontact)

[0054] =5*[Rpoly+(2*Rcontact)]

[0055] Resistors 104 and 106 may further include any number of array elements 203 to achieve the desired resistance, for example... Figure 1B The layout depicted in the diagram consists of 7 array elements 203.

[0056] For reference Figure 3 The layout of the current sensing circuit 100 is further described according to one or more embodiments of this disclosure. The current sensing circuit 100 may additionally include resistors 110 and 112. Resistors 110 and 112 may be connected to the output of an amplifier, such that resistors 110 and 112 may also be referred to herein as lower-level resistors. Resistors 110 and 112 may each include a resistance (Rb), such that resistors 110 and 112 may also be referred to as a pair of matched resistors. For example, the resistance (Rb) may be 17.5 kΩ (e.g., a 17.5 kΩ resistor), but this is not intended to be limiting.

[0057] Although not depicted, resistors 110 and 112 may each comprise several array elements arranged from polysilicon wafers and configured to form a resistor (Rb). The array elements may be arranged in a checkerboard pattern to improve matching. As depicted, resistors 110 and 112 are arranged in a symmetrical matrix.

[0058] The current sensing circuit 100 may further include one or more of package pins 140 and 142. Package pins 140 and 142 may be centered about axis 126 to reduce the stress gradient of the array elements disposed below, thereby improving the matching between resistors 104 and 106. Package pins may be provided for coupling the integrated circuit package to external components. Package pins may also be referred to as leads or leads.

[0059] The current sensing circuit 100 may further include one or more resistors 144 for the secondary amplifier path (e.g., an analog path), as referenced Figures 5A to 6 Further description. For example, resistor 144 may comprise a pair of integrated 1kΩ resistors and a 17K resistor arranged in a checkerboard pattern.

[0060] For reference Figure 4 A circuit diagram of a current sensing circuit 100 is described according to one or more embodiments of the present disclosure. The current sensing circuit 100 can provide a structure for measuring current across a resistor to select an accuracy level and a wide range of current values. The current sensing circuit 100 can be configured to output a voltage (Vo). The voltage (Vo) can be provided to an analog-to-digital converter, which generates a digital signal that is then used by a processor to determine the current (Isns). The current sensing circuit 100 can include one or more components for generating the voltage (Vo). For example, the current sensing circuit 100 can include resistors 102, 104, 106, amplifier 108, resistor 110, resistor 112, transistor 114, and transistor 116. The current sensing circuit 100 can additionally include one or more switches 122 (i.e., switches (M1), (M2), (M3), and (M4)).

[0061] Resistor 102 may be coupled between a node having a first voltage (Vrect) and a node having a voltage (Vmid). A node may refer to a point connecting one or more components of a circuit and / or one or more branches of a circuit. A node may be represented by a wire connecting various components and / or branches. Resistor 102 may contain a resistance (Rs). The resistance (Rs) may contain a relatively small resistance value. Due to the inverse relationship between resistance and power loss, the resistance (Rs) may be relatively small to reduce the amount of power dissipated across resistor 102. For example, resistor 102 may be a 20 milliohm resistor, but this is not intended to be limiting. Resistor 102 may be configured to carry a current (Isns) across the resistor, which is based on the resistance (Rs) and the voltage difference between the voltage (Vrect) and the voltage (Vmid). Providing a low-resistance resistor presents challenges for circuit design, especially when the resistance (Rs) is reduced and the current is measured across a wide dynamic range (e.g., between milliamps and 2.5 amps). Integrating resistor 102 into an integrated circuit (IC) presents many challenges.

[0062] In this embodiment, the current sensing circuit 100 is designed to output a voltage (Vo) for sensing the current (Isns). In this respect, the ability to detect the current (Isns) is advantageous for sensing received or transmitted power. Since it is desirable to detect the current (Isns) across resistor 102, resistor 102 can also be referred to as a sensing resistor.

[0063] Resistor 104 may be coupled between a node having a voltage (Vrect) and the input of amplifier 108. Similarly, resistor 106 may be coupled between a node having a voltage (Vmid) and the input of amplifier 108. In this respect, resistors 104 and 106 may also be referred to herein as upper resistors or input resistors of amplifier 108. In an embodiment, resistors 104 and 106 each include a matching resistance value (Rt). In this respect, resistors 104 and 106 may also be referred to herein as a pair of matching resistors. The resistance (Rt) may increase as resistors 104 and 106 age.

[0064] Resistor 110 may be coupled between the output of amplifier 108 and ground. Similarly, resistor 112 may be coupled between the output of amplifier 108 and ground. For example, resistor 110 is depicted as coupled between a node of transistor 114 and ground, and resistor 112 is depicted as coupled between a node of transistor 116 and ground. In this respect, resistors 110 and 112 may also be referred to herein as lower-level resistors of amplifier 108. In an embodiment, resistors 110 and 112 each include a matching resistance value (Rb). In this respect, resistors 110 and 112 may also be referred to herein as a pair of matching resistors. Due to the arrangement of resistors 110 and 112, the voltage (Vo) output from current sensing circuit 100 is proportional to the resistance (Rb).

[0065] Amplifier 108 can be configured to output a voltage (Vo). Amplifier 108 outputs a voltage (Vo) by amplifying the voltage drop across resistor 102. Therefore, the voltage (Vo) can be based on the current (Isns). Amplifier 108 can also be referred to as an operational amplifier, differential amplifier, or high-gain amplifier. Amplifier 108 can sense the input voltage across the upper resistor and drive the output such that the voltages from the left and right sides are equal. Providing equal voltages on the left and right sides provides a current proportional to the current (Isns). Amplifier 108 can contain a gain based on the resistance (Rb) of the lower resistor divided by the resistance (Rt) of the upper resistor. For example, the resistance (Rt) of the upper resistor can be 1 kΩ (1 kΩ resistor), but this is not intended to be limiting. Continuing with the example, the resistance (Rb) of the lower resistor can be 17.5 kΩ (17.5 kΩ resistor), but this is not intended to be limiting. When the upper resistor is 1kΩ and the lower resistor is 17.5kΩ, the amplifier gain can be 17.5 times (e.g., a gain of approximately 24.86dB), but this is not intended to be limiting. In some cases, the gain of amplifier 108 can be selected based on the capabilities of the downstream ADC.

[0066] In this embodiment, each of resistors 102, 104, 106, 110, and 112 is included within integrated circuit 700, such that the resistors can be considered "internal". Each of the resistors may be formed from one or more polysilicon elements defining resistance values ​​(Rs), resistance values ​​(Rt), and resistance values ​​(Rb). It is further anticipated that resistors 102, 104, and 106 may have substantially similar temperature coefficients and similar aging coefficients.

[0067] In this embodiment, resistor 102 is an internal resistor. The current sensing circuit can sense the current internally without the use of external components, such as an external sensing resistor. The fact that resistor 102 is part of an integrated circuit, contains a relatively low resistance value, and measures a large dynamic range of current can present challenges in designing the current sensing circuit 100. In this embodiment, resistor 102 is a precision resistor provided within an on-chip integrated circuit and combined with amplifier 108 to form the current sensing circuit 100. The current measured across resistor 102 may be referred to herein as the sensed current (Isns) and may be based on the resistance value of the sensed resistor (Rs) and the voltage drop between the rectified voltage (Vrect) and the intermediate voltage (Vmid).

[0068] The current sensing circuit 100 includes a node 118 between resistors 102 and 104. Node 118 may be provided for routing the voltage (Vrect) through a rectifier, but this is not intended to limit it. The current sensing circuit 100 may also include a node 120 between resistors 102 and 104. Node 120 may be provided for routing the voltage (Vmid) through a voltage regulator, but this is not intended to limit it.

[0069] In this embodiment, resistor 102 is assembled with amplifier 108 into an integrated circuit. Upper-layer resistors (e.g., resistors 104 and 106) and lower-layer resistors (e.g., resistors 110 and 112) may also be part of the integrated circuit. By incorporating the amplifier assembly with resistor 102 onto the integrated circuit, the temperature coefficients of resistor 102 and the upper-layer resistors can be substantially similar. In this embodiment, the integrated circuit includes upper-layer resistors and current-sensing resistors integrated into the layout.

[0070] In embodiments, one or more of resistors 102, 104, 106, 110, or 112 comprise polysilicon resistors formed on the integrated circuit beneath the metallization layer. Polysilicon resistors may also be referred to herein as polysilicon resistors or internal polysilicon resistors. In embodiments, the polysilicon resistors are formed as an array of polysilicon elements. Polysilicon elements may also be referred to herein as polysilicon wafers. Polysilicon elements may comprise any polysilicon material known in the art. Polysilicon materials may contain resistance that varies with temperature. Using polysilicon materials can be advantageous for reducing the temperature coefficient compared to implementing resistors in the metallization layer of the integrated circuit.

[0071] Polysilicon elements can encompass a wide range of dimensions. For example, the polysilicon elements used to form resistors 102, 104, or 106 can be relatively wide. For instance, a polysilicon element can be 50 micrometers wide. The polysilicon element can further include a length, such as (but not limited to) 4 micrometers. Therefore, the aspect ratio of the polysilicon element can be 50 micrometers × 4 micrometers. A polysilicon element with an aspect ratio of 50 micrometers × 4 micrometers has been experimentally determined to have a temperature coefficient of 150 PPM / C. As another example, the polysilicon elements used to form resistors 110 or 112 can be relatively narrow compared to the polysilicon elements of the upper resistor and sensing resistor. For example, the polysilicon element of the lower resistor can be 1 micrometer wide. The polysilicon element of the lower resistor can change over time due to aging. In an embodiment, the resistance change of the lower resistor is further calibrated by a calibration circuit (not depicted).

[0072] One challenge in implementing resistor 102 within an integrated circuit is its temperature coefficient. Integrating upper-layer resistors into an array of resistors 102 allows for the cancellation of the temperature coefficients of resistance (Rs) and resistance (Rt). This temperature coefficient cancellation eliminates inaccuracies associated with the temperature of the upper-layer resistors and the current-sensing resistor. Voltage (Vo) can be proportional to current (Isns), resistance (Rs), and resistance (Rb). Voltage (Vo) can further be inversely proportional to resistance (Rt).

[0073] Transistors 114 and 116 can serve as gain stages from the amplifier. For example, if amplifier 108 begins to detect different voltages on the input, the output from the amplifier can pull up or pull down the gates of transistors 114 and 116, causing transistors 114 and 116 to act as current sources. It should be understood that transistors 114 and 116 can generally comprise any transistor, such as (but not limited to) field-effect transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs or M). As depicted, transistors 114 and 116 can be N-channel MOS (NMOS), but this is not intended to be limiting.

[0074] The current sensing circuit 100 may also include a switching matrix. The switching matrix may include one or more switches 122, such as (but not limited to) switches (M1), (M2), (M3), and (M4). Switches (M1 to M4) can be selectively opened and closed to configure the current sensing circuit in receive mode, transmit mode, and one or more offset calibration modes. The switching matrix allows for inversion of transmit and receive gains. The switching matrix also allows for offset of the input voltage of the measurement amplifier. Advantageously, the current sensing circuit 100 includes current sensing accuracy within 0.5% of the actual current across resistor 102. The switching matrix provides direct offset measurement and introduces minimal parasitic effects that could affect temperature performance.

[0075] Switches (M1 to M4) can be arranged between resistors 102, 104, and 106. Switch (M1) is coupled between node 118 and resistor 104. Switch (M2) is coupled between node 120 and resistor 106. Switch (M3) is coupled between node 120 and resistor 104. Switch (M4) is coupled between node 118 and resistor 106.

[0076] Switches (M1 to M4) allow measurement of current transfer from node 118 with voltage (Vrect) to node 120 with voltage (Vmid), measurement of current transfer from voltage (Vmid) to voltage (Vrect), and measurement of the offset of the current sensing circuit. The processor can receive one or more digital signals of voltage (Vo) and determine the current (Isns) based on the voltage (Vo). Voltage (Vo) can also indicate the offset contributed by resistors 104, 106, 110, 112, and amplifier 108, depending on which of the switches (M1 to M4) are closed.

[0077] When switches (M1) and (M2) are closed and switches (M3) and (M4) are open, the current sensing circuit 100 is configured in a receiving mode. In the receiving mode, the processor can measure the current transfer from voltage (Vrect) to voltage (Vmid). In the receiving mode, the current sensing circuit can measure the current received by the integrated circuit of the wireless power system. For example, the receiving mode may correspond to communication and / or wireless power received from a transmitter. Therefore, the wireless power system can be configured in the receiving mode based on the switch configuration.

[0078] When switches (M3) and (M4) are closed and switches (M1) and (M2) are open, the current sensing circuit 100 is configured in transmission mode. In transmission mode, the processor can measure the current from voltage (Vmid) to voltage (Vrect). In this regard, switches (M1 to M4) provide a way to reverse between transmission (Tx) and reception (Rx). In transmission mode, the current sensing circuit can measure the current transmitted from the integrated circuit of the wireless power system. For example, the transmission mode may correspond to communication transmitted from the wireless power system. Therefore, the wireless power system can be configured in transmission mode based on the configuration of the switches.

[0079] When switches (M1) and (M4) are closed and switches (M2) and the third switch (M3) are open, the current sensing circuit 100 is configured in a first offset mode to measure the offset of the current sensing circuit 100. When switches (M1) and (M4) are on, the input of the current sensing circuit 100 can be shorted at node 118. When switches (M1) and (M4) are closed and switches (M2) and (M3) are open, the processor can be configured to measure the offset of the current sensing circuit 100 (e.g., the offset of various resistors and amplifiers together) based on one or more digital signals of voltage (Vo).

[0080] Alternatively, when switches (M2) and (M3) are closed and switches (M1) and (M4) are open, the current sensing circuit 100 is configured in a second offset mode to measure the offset of the current sensing circuit 100. When switches M2 and M3 are on, the input of the current sensing circuit 100 can be shorted at node 120. When switches (M2) and (M3) are closed and switches (M1) and (M4) are open, the processor can be configured to measure the offset of the current sensing circuit 100 based on one or more digital signals of voltage (Vo).

[0081] Next, the processor can use the offset to calibrate the measured current (Isns). For example, when in offset mode, any voltage received from the ADC is a zero-current reference. During the calibration phase, the zero-current reference can be subtracted from the voltage. By implementing switches in the upper resistor array, the current sensing circuit 100 can have both power transmission and reception modes and also perform direct offset measurements of the resistor structure. Therefore, the processor measures the offset of the current sensing circuit 100 based on the voltage (Vo) and then compensates for the offset when determining the current (Isns).

[0082] Switches (M1 to M4) can be controlled by one or more processors executing program instructions. The processor may contain firmware that causes it to control the switches (M1 to M4). The firmware can cause the processor to control the switches to perform an offset measurement on the current offset. The firmware can perform the offset measurement to detect the current offset of the structure and then use the offset information for calibration purposes.

[0083] It should be understood that the switches (M1 to M4) can typically include any switch, such as a transistor. Transistors can include (but are not limited to) field-effect transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs or M). As depicted, the switches (M1 to M4) can be P-channel MOS (PMOS), but this is not intended to be limiting.

[0084] For reference Figures 5A to 5B A current sensing circuit 100 is described according to one or more embodiments of the present disclosure. In an embodiment, the current sensing circuit 100 includes one or more channels. The current sensing circuit 100 may include digital channels and analog channels. The current sensing circuit 100 may include an amplifier 108 for the digital channel, which is connected in parallel with an amplifier 146 for the analog channel. Amplifiers 108 and 146 may each include inputs coupled to nodes 118 and 120, respectively.

[0085] The digital channel can provide one or more digital control loops using a first current (Isns). The digital channel can output a voltage (Vo) from amplifier 108 to the ADC. The ADC can then provide one or more digital signals of the voltage (Vo) to the processor. The processor can be configured to receive one or more digital signals of a third voltage (Vo) and further configured to determine the current (Isns) based on the voltage (Vo). The processor can also measure the offset of the current sensing circuit contributed by resistors 104, 106, 110, 112, and amplifier 108 by switching one or more switches 122. Then, when determining the current (Isns) of one or more digital control loops, the processor can compensate for the offset. When the processor switches 122, the digital channel can be offline, so that when one or more switches 122 are switched to determine the offset, the processor cannot determine the current (Isns). Undesirable loss of current (Isns) measurement results in periods in which the current (Isns) cannot be measured. However, it is expected that providing offset measurements will improve the accuracy of current (Isns) measurements in digital control loops.

[0086] The analog channel can provide one or more analog control loops using a first current (Isns). The analog channel can output a voltage (Van) from amplifier 146 to one or more circuits. The circuits can use the current (Isns) in one or more analog control loops for wireless power control. For example, the analog control loop of the integrated circuit may include (but is not limited to) a load modulation circuit (ILOAD), a main voltage regulator (MVR), and the like. The voltage regulator can regulate the voltage output of the integrated circuit. Regulating the voltage output can be beneficial in allowing the battery charging system to charge the battery. The voltage regulator circuit can typically include any circuitry for regulating the voltage based on the analog control loop.

[0087] By providing both analog and digital channels, amplifier 146 can remain on when node 118 contains a voltage (Vrect) and node 120 contains a voltage (Vmid), thereby ensuring that the analog channel continuously receives current (Isns). Amplifier 146 remains on regardless of the state of switch 122, allowing the switch to be switched to determine the offset without affecting the analog control loop. Therefore, the analog channel can operate independently of the digital channel, thereby allowing the digital channel to be calibrated while the analog control loop is in operation. In this respect, amplifier 108 may also be referred to herein as a switching amplifier and amplifier 146 may also be referred to herein as a normally open amplifier.

[0088] The current sensing circuit 100 may additionally include any number of elements coupled to the amplifier 146. Although not depicted, the current sensing circuit 100 may include one or more resistors (see, for example, resistor 104, resistor 106) coupled between node 118 or node 120 and the input of the amplifier 146. The current sensing circuit 100 may include one or more elements coupled to the output of the amplifier 146. For example, the current sensing circuit 100 may include transistor 148, transistor 150, resistor 152, and resistor 154. Transistor 148 and transistor 150 may each be coupled to the output of the amplifier 146. Therefore, the voltage (Van) may be based on the input voltage of the amplifier 146 and one or more resistors of the analog channel. For example, the amplifier 146 may be a differential amplifier with a gain set based on the resistance settings of the input and output.

[0089] Transistors 148 and 150 may typically comprise any transistor, such as (but not limited to) field-effect transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs or M). As depicted, transistors 148 and 150 may be P-channel MOS (PMOS), but this is not intended to be limiting.

[0090] Resistor 152 may be coupled between transistor 148 and ground. Similarly, resistor 154 may be coupled between transistor 150 and ground. Resistors 152 and 154 may each contain a resistance (Rt). For example, resistors 152 and 154 may each contain a 17 kΩ resistance, but this is not intended to be limiting. Resistors 152 and 154 may also be referred to as a pair of matching lower-level resistors.

[0091] The current sensing circuit 100 may include one or more components coupled between the output and input of amplifier 146. One or more components may include resistor 156 and resistor 158. Resistors 156 and 158 may each have a matching resistance value. For example, resistors 156 and 158 may each have a 1 kΩ resistance, but this is not intended to be limiting. Resistor 156 may be coupled between transistor 148 and a first input of amplifier 146. Similarly, resistor 158 may be coupled between transistor 150 and a second input of amplifier 148.

[0092] The current sensing circuit 100 may include one or more offset correction features. For example, amplifier 146 may include a chopper switch 151. The chopper switch 151 may also be referred to as chopper clock feedback or the like. The chopper feedback loop may provide chopping for offset correction of amplifier 146. Offset correction of amplifier 146 can improve the accuracy of the analog channel. For example, the chopper feedback loop may include a first chopper switch at the input of amplifier 146. The first chopper switch may be configured to switch the input of the amplifier. As another example, the chopper feedback loop may include a second chopper switch at the output of amplifier 146. The second chopper switch may be configured to switch the output of the amplifier.

[0093] It should be understood that the depiction of switch 122 is not intended to be limiting. For example, the current sensing circuit 100 may include any number of switches for measuring offset, such as (but not limited to) Figure 4 Four-switch configuration or Figure 5A The three-switch configuration.

[0094] For reference Figure 6 According to one or more embodiments of this disclosure, the layout of one or more components of a current sensing circuit 100 is described. As depicted, dummy resistors 124, 152, 154, 156, and 158 are depicted with different shaded lines, which is not intended to be limiting. Rather, the resistors are shaded to indicate the number of array elements included in each resistor. The layout of resistors 152, 154, 156, and 158 is intended to facilitate sensing any number of current sensing circuits in the milliampere to ampere range.

[0095] In an embodiment, resistors 152, 154, and 156 each comprise a polysilicon resistor formed on a substrate. The polysilicon resistor may also be referred to herein as a polysilicon resistor or an internal polysilicon resistor. In an embodiment, the polysilicon resistors are formed as arrays of array elements each comprising an array of polysilicon wafers. The polysilicon wafers may be disposed on a layer of an integrated circuit. As depicted, resistors 152 and 154 each comprise 17 array elements. Similarly, resistors 156 and 158 are each depicted as comprising 9 array elements. Furthermore, although not depicted, the array elements of each of the resistors may be coupled in various series or parallel arrangements to achieve a desired resistance value. Each array element may comprise several polysilicon wafers. (The following is incorporated herein by reference.) Figures 1A to 2B The discussion focuses on polycrystalline silicon wafers. In this regard, array elements can be formed from any number of polycrystalline silicon wafers having any aperture, resistivity, and temperature coefficient.

[0096] It is desirable to ensure that resistors 152 and 154 are as close as possible to their matching resistance values, for example, to ensure the gain of one or more amplifiers suitable for a current sensing circuit. In an embodiment, resistors 152 and 154 comprise an array of polysilicon wafers symmetrically arranged about axis 160. Similarly, resistors 156 and 158 comprise an array of polysilicon wafers symmetrically arranged about axis 160. In this respect, the stress difference between the polysilicon wafers can be reduced. Reducing the stress difference can cause the matching resistor pair to experience similar stress. Experiencing similar stress can cause the resistors to experience similar resistance changes caused by piezoresistive properties. The polysilicon wafer of resistor 152 may interleave with that of resistor 154. Similarly, the polysilicon wafer of resistor 156 may interleave with that of resistor 158. As depicted, the polysilicon wafer of resistor 152 is a mirror image of resistor 154 about axis 160. Additionally, the wafer of resistor 156 is a mirror image of resistor 158 about axis 160. This arrangement can also be called a chessboard pattern, but this is not intended to be limiting.

[0097] For reference Figure 7An exemplary embodiment of integrated circuit 700 is described according to one or more embodiments of this disclosure. Integrated circuit 700 may also be referred to herein as a transceiver unit, mixed-signal chip, wireless power chip, wireless power receiver (Rx), receiver (Rx) integrated circuit, or the like. Integrated circuit 700 may be configured to receive and regulate alternating current and output a regulated DC voltage. For example, alternating current may be received from a coil of a wireless power system and a regulated DC voltage may be provided to a battery for charging, but this is not intended to be limiting. In embodiments, integrated circuit 700 may include one or more of a rectifier 702, a current sensing circuit 704 (e.g., current sensing circuit 100), a processor 706, a power unit 708, a voltage regulator 710, an analog-to-digital converter 712, and the like. It is further contemplated that integrated circuit 700 may include any number of additional components not depicted herein for clarity. For example, integrated circuit 700 may further include various undrawn traces between one or more of rectifier 702, current sensing circuit 704, embedded processor 706, power unit 708, voltage regulator 710 and analog-to-digital converter 712.

[0098] Rectifier 702 can be configured to receive alternating current (AC) with a voltage (Vin). For example, AC power can be received from the coil of a wireless power system, but this is not intended to limit it. Rectifier 702 can be further configured to generate direct current (DC) with a voltage (Vrect). The voltage (Vrect) may not be regulated to the desired power supply. Rectifier 702 can typically include any circuitry suitable for rectifying the current. For example, rectifier 702 may include bridging circuitry, such as an H-bridge circuit.

[0099] When the integrated circuit is configured in receive mode, rectifier 702 converts an AC input voltage to a rectified DC voltage. When the integrated circuit is configured in transmit mode, the rectifier can also convert a DC input voltage to an AC output voltage. For example, the integrated circuit can be configured in receive mode for receiving wireless power. As another example, the integrated circuit can be configured in receive mode and / or transmit mode for wireless communication with a transmitter.

[0100] The current sensing circuit 704 is incorporated herein by reference into the discussion of the current sensing circuit 100. The current sensing circuit 704 may include a voltage (Vrect) from the node and a voltage (Vmid) from the node. Depending on whether the integrated circuit 700 is receiving or transmitting, the voltage (Vrect) may be higher or lower than the voltage (Vmid). The current sensing circuit 704 may further output a voltage (Vo) that can be used to determine the current (Isns).

[0101] Processor 706 may typically include any suitable processor. For example, embedded processor 706 may be a microprocessor, but this is not intended to be limiting. Processor 706 may further include one or more memory blocks through which processor 706 may be configured to perform any of the various methods described herein. For example, processor 706 may include (but is not limited to) read-only memory (ROM) for performing boot operations, one-time programmable (OTP) memory for boot code, and / or random access memory (e.g., static RAM) for storing program instructions, communications (e.g., FSK communication, ASK communication, etc.) and the like.

[0102] Processor 706 can typically be configured to perform various program functions that can be stored in firmware. For example, processor 706 can be configured to receive various bits from analog-to-digital converter 712. Processor 706 can be further configured to determine the current (Isns) across current sensing circuit 704.

[0103] Power unit 708 can be configured to power various components of the integrated circuit, such as (but not limited to) the embedded processor 706 or another component of the integrated circuit 700. Power unit 708 can typically provide any level of power, such as (but not limited to) 1.2 volts, 1.8 volts, 3.3 volts, or 5 volts. Power unit 708 can draw power from any number of sources, such as (but not limited to) the main power rail of a communication device.

[0104] Voltage regulator 710 can be configured to receive voltage (Vmid) from current sensing circuit 704. Voltage regulator 710 can be further configured to regulate the voltage to a desired output. The regulated voltage can then be provided to a battery or battery charging system for charging the battery. The regulated voltage can typically include any suitable output voltage for wireless charging, such as (but not limited to) 15 volts or 30 volts.

[0105] The analog-to-digital converter 712 can be configured to receive various voltages and / or currents from any one or more components of an integrated circuit and generate a bit-digital signal. For example, the analog-to-digital converter 712 can receive a voltage (Vo) from a current sensing circuit 704 and generate a digital signal based on the voltage (Vo). The analog-to-digital converter 712 can then provide the digital signal to a processor 706 for processing. It should be understood that the analog-to-digital converter 712 may typically include any analog-to-digital converter (ADC) and may further include a plurality of various other converters for processing various other signals, which are not depicted herein.

[0106] Although the current sensing circuit 704 is described as a component of integrated circuit 700, this is not intended to be a limitation of this disclosure. It is contemplated that current sensing circuit 100 and / or current sensing circuit 704 can be integrated into any number of integrated circuits. In this regard, reducing pressure variations caused by piezoresistive forces can facilitate accurate current measurement over a wide dynamic range in any number of integrated circuits. Applications can include any type of accurate on-chip current measurement, whether it originates from wireless power or is used for any type of power management integrated circuit.

[0107] In some examples, the integrated circuit 700 can achieve current sensing accuracy of 0.5% or better, which is an improvement over the existing current sensing accuracy of 1.0%. Improving current sensing accuracy can facilitate allowing for higher levels of power transfer while still meeting one or more safety requirements, such as (but not limited to) requirements regarding foreign object detection.

[0108] For reference Figure 8 According to one or more embodiments of this disclosure, a wireless power system 800 is described. The wireless power system 800 may include one or more components, such as (but not limited to) a transmitter unit 802, a transmitter coil 804, a receiver coil 806, an integrated circuit 700, and a battery charger 808. The transmitter unit 802 and the integrated circuit 700 may be inductively coupled via the transmitter coil 804 and the receiver coil 806. In this respect, the integrated circuit 700 may wirelessly receive power from the transmitter unit 802 and provide power to the battery charger 808 for charging one or more batteries. The integrated circuit 700 and the transmitter unit 802 may wirelessly communicate via any number of communication protocols. For example, the integrated circuit 700 may receive and receive transmissions from the transmitter unit 802 to establish a transmission via one or more handshake protocols. A current sensing circuit may be configured to sense current (Isns) in either a transmission mode or a reception mode.

[0109] High-accuracy current measurement provided by the current sensing circuit within integrated circuit 700 is beneficial for foreign object detection. The more accurate the current sensing, the more accurate the power transfer that can be performed in system 800. The power transfer level of the wireless power system 800 increases over time. As power levels increase, accurate current sensing becomes increasingly important. It is also advantageous to sense the current internally without using external resistors within the current sensing circuit.

[0110] For reference Figure 9According to one or more embodiments of this disclosure, a communication device 900 is described. The communication device 900 may typically include one or more components of a wireless power system 800 through which a battery can be wirelessly charged. The peak wireless power transfer level of the communication device 900 may range from 15 to 30 watts or higher and may be further improved with advancements in wireless power transfer protocols and hardware. As the peak wireless power transfer level increases, the ability to accurately sense current within the wireless power system 800 becomes increasingly important. The communication device 900 may typically include any type of device configured to communicate by transmitting or receiving signals (e.g., digital, analog, etc.) via a medium (e.g., wired, wireless, etc.), such as (but not limited to) a cellular phone, modem, network interface, and the like. In some examples, the communication device 900 is configured to communicate via a wireless power system, for example, for communication between a transmitter and a receiver.

[0111] Again, for general reference Figures 1A to 9 For the purposes of this disclosure, the terms "processor" or "processing element" may be broadly defined to encompass any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application-specific integrated circuit (ASIC) devices, one or more field-programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)). In this sense, one or more processors may include any means configured to execute algorithms and / or instructions (e.g., program instructions stored in memory). Furthermore, memory may include any storage medium known in the art suitable for storing program instructions executable by the associated processor. For example, storage medium may include non-transitory memory media. As another example, memory media may include (but is not limited to) read-only memory (ROM), random access memory (RAM), magnetic or optical memory devices (e.g., disks), solid-state drives, and the like. It should be further noted that the memory medium may be housed together with the processor in a common controller housing. In embodiments, the memory medium may be remotely located relative to the physical location of the processor.

[0112] In this disclosure, the disclosed methods, operations, and / or functionalities can be implemented as a set of instructions or software readable by a device. Furthermore, it should be understood that the specific order or hierarchy of steps in the disclosed methods, operations, and / or functionalities is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the methods, operations, and / or functionalities can be rearranged while remaining within the scope of the inventive concept disclosed herein. The appended claims may present the elements of each step in a sample order and are not necessarily intended to be limited to the specific order or hierarchy presented.

[0113] It should be understood that embodiments of the methods according to the inventive concepts disclosed herein may include one or more steps described herein. Furthermore, such steps may be performed in any desired order, and two or more steps may be performed simultaneously with each other. Two or more steps disclosed herein may be combined into a single step, and in some embodiments, one or more steps may be implemented as two or more sub-steps. In addition, other steps or sub-steps may be implemented besides or as alternatives to one or more steps disclosed herein.

[0114] Based on the above description, it is evident that the inventive concepts disclosed herein are well-suited to carrying out the objectives and achieving the advantages mentioned herein, as well as the inherent advantages of the inventive concepts disclosed herein. Although presently preferred embodiments of the inventive concepts disclosed herein have been described for the purposes of this disclosure, it should be understood that many modifications can be made, which will be apparent to those skilled in the art and are within the broad scope and coverage of the inventive concepts disclosed and claimed herein.

Claims

1. An integrated circuit, comprising: A current sensing amplifier, comprising: A first resistor is coupled between a first node and a second node; wherein the first resistor has a first resistance (Rs); wherein the first resistor is configured to carry a first current (Isns) across the first resistor when the first node has a first voltage (Vrect) and the second node has a second voltage (Vmid). A first amplifier includes a first input coupled to the first node and a second input coupled to the second node; the first amplifier is configured to output a third voltage (Vo); A second resistor and a third resistor; wherein each of the second resistor and the third resistor has a second resistance (Rt); wherein the second resistor is coupled between the first node and the first input of the first amplifier; wherein the third resistor is coupled between the second node and the second input of the first amplifier; A plurality of switches, configured to be switched to measure the offset of the current-sensing amplifier, are coupled to the first resistor, the second resistor, and the third resistor; and A second amplifier includes a third input coupled to the first node and a fourth input coupled to the second node; the second amplifier is configured to output a fourth voltage (Van).

2. The integrated circuit of claim 1, wherein the second amplifier uses the first current (Isns) to provide an analog channel for one or more analog control loops.

3. The integrated circuit of claim 2, wherein the first amplifier uses the first current (Isns) to provide a digital channel for one or more digital control loops.

4. The integrated circuit of claim 3, further comprising a processor configured to receive one or more digital signals of the third voltage (Vo) and further configured to determine the first current (Isns) based on the third voltage (Vo); The processor is configured to measure the offset by switching one or more of the plurality of switches; The processor is configured to compensate for the offset when the first current (Isns) is determined.

5. The integrated circuit of claim 4, further comprising at least one analog-to-digital converter configured to provide the third voltage (Vo) to the processor of the one or more digital signals.

6. The integrated circuit of claim 5, wherein the processor cannot determine the first current (Isns) when one or more of the plurality of switches are switched to determine the offset.

7. The integrated circuit of claim 6, wherein the second amplifier is turned on when the first node has the first voltage (Vrect) and the second node has the second voltage (Vmid).

8. The integrated circuit of claim 7, wherein when one or more of the plurality of switches are switched to determine the offset, the second amplifier remains on to ensure that the analog channel continuously receives the first current (Isns).

9. The integrated circuit of claim 2, wherein the one or more analog control loops of the integrated circuit include a voltage regulator coupled to the second amplifier.

10. The integrated circuit of claim 1, further comprising: A first transistor and a second transistor; wherein the first transistor is coupled to a first output of the second amplifier; The second transistor is coupled to the second output of the second amplifier; and The fourth and fifth resistors; The fourth resistor is coupled between the first transistor and ground; the fifth resistor is coupled between the second transistor and ground; and the fourth and fifth resistors each have a third resistance (Rt).

11. The integrated circuit of claim 10, further comprising a sixth resistor and a seventh resistor; The sixth resistor and the seventh resistor each have a matching resistor; The sixth resistor is coupled between the first input of the second amplifier and the first transistor; the seventh resistor is coupled between the second input of the second amplifier and the second transistor.

12. The integrated circuit of claim 11, wherein the fourth resistor is formed of a first plurality of polysilicon wafers; wherein the fifth resistor is formed of a second plurality of polysilicon wafers; wherein the sixth resistor is formed of a third plurality of polysilicon wafers; wherein the seventh resistor is formed of a fourth plurality of polysilicon wafers; wherein the first plurality of polysilicon wafers, the second plurality of polysilicon wafers, the third plurality of polysilicon wafers and the fourth plurality of polysilicon wafers are disposed on a layer of the integrated circuit.

13. The integrated circuit of claim 12, wherein the first plurality of polysilicon wafers are intertwined with the second plurality of polysilicon wafers, the third plurality of polysilicon wafers, and the fourth plurality of polysilicon wafers; wherein the second plurality of polysilicon wafers are intertwined with the third plurality of polysilicon wafers and the fourth plurality of polysilicon wafers; wherein the third plurality of polysilicon wafers are intertwined with the fourth plurality of polysilicon wafers.

14. The integrated circuit of claim 13, wherein the first plurality of polysilicon wafers are mirror images of the second plurality of polysilicon wafers about an axis; wherein the third plurality of polysilicon wafers are mirror images of the fourth plurality of polysilicon wafers about the axis.

15. The integrated circuit of claim 1, wherein the second amplifier includes a chopper feedback loop for offset correction.

16. The integrated circuit of claim 1, wherein the gain of the first amplifier is based on the first resistor (Rs).

17. The integrated circuit of claim 1, further comprising a rectifier and a voltage regulator; wherein the rectifier is configured to receive alternating current from a coil and rectify the alternating current to provide the first voltage (Vrect) to the first node; wherein the voltage regulator is coupled to the second node of the current sensing amplifier and configured to regulate the second voltage (Vmid).

18. The integrated circuit of claim 1, wherein the first amplifier and the second amplifier each comprise a differential amplifier.

19. A system comprising: A coil configured to receive wireless power; Integrated circuits, including: A rectifier configured to receive alternating current from the coil and generate a first voltage (Vrect); A current sensing circuit includes: A first resistor is coupled between a first node and a second node; wherein the first resistor has a first resistance (Rs); wherein the first resistor is configured to carry a first current (Isns) across the first resistor when the first node has a first voltage (Vrect) and the second node has a second voltage (Vmid). A first amplifier includes a first input coupled to the first node and a second input coupled to the second node; the first amplifier is configured to output a third voltage (Vo); A second resistor and a third resistor; wherein each of the second resistor and the third resistor has a second resistance (Rt); wherein the second resistor is coupled between the first node and the first input of the first amplifier; wherein the third resistor is coupled between the second node and the second input of the first amplifier; A plurality of switches, configured to be switched to measure the offset of the current sensing circuit, the plurality of switches being coupled to the first resistor, the second resistor, and the third resistor; and A second amplifier includes a third input coupled to the first node and a fourth input coupled to the second node; the second amplifier is configured to output a fourth voltage (Van); A voltage regulator coupled to the second node of the current sensing circuit and configured to regulate the second voltage (Vmid); and A processor; wherein the processor is configured to receive one or more digital signals of the third voltage (Vo); wherein the processor is configured to determine the first current (Isns) based on the third voltage (Vo); and Battery charging system.

20. The system of claim 19, wherein the system is configurable between a receive mode and a transmit mode; wherein when the system is in the receive mode, the first current (Isns) is provided from the rectifier across the first resistor to the voltage regulator; wherein the processor is configured to determine the first current (Isns) when the system is in the receive mode.

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